Apple-1-HW/verilog-apple-one
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70 Commits 3 Branches 0 Tags 6.9 MiB
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8 Commits

Author SHA1 Message Date
Alan Garfield
4fef9bc10b Initial VGA module, still WIP, just outputs fixed VRAM 2018-01-29 22:53:16 +11:00
Alan Garfield
b2ebc23e3a added license headers and tidied up 2018-01-29 22:15:21 +11:00
Alan Garfield
474cabbab0 Made core neater and trying to get naming better 2018-01-29 21:00:38 +11:00
Alan Garfield
2717184e71 Added yosys support again, yay for FOSS! 2018-01-29 17:45:01 +11:00
Alan Garfield
69f1b53e18 added basic rom and fix uart issue on HX 2018-01-28 15:02:51 +11:00
Alan Garfield
04323a6256 more moving around, added params for hex files 2018-01-27 14:27:10 +11:00
Alan Garfield
149334259d Cleaned up mess, and added HX8K board top file 2018-01-27 13:40:59 +11:00
Alan Garfield
7bdccf3d1a move things around. 2018-01-27 00:21:05 +11:00