Apple-1-HW
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verilog-apple-one
mirror of https://github.com/alangarf/apple-one.git
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Added yosys support again, yay for FOSS!

This commit is contained in:
Alan Garfield 2018-01-29 17:45:01 +11:00
parent 586b006e88
commit 2717184e71
8 changed files with 105 additions and 30 deletions
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1
.gitignore vendored
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@ -7,3 +7,4 @@ synlog.tcl
*.swp
*_tb
*.vcd
build

64
boards/ice40hx8k_yosys/Makefile Normal file
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@ -0,0 +1,64 @@
DEVICE = hx8k
PIN_DEF=ice40hx8k.pcf
SOURCEDIR = ../../rtl
BUILDDIR = build
all:
@echo " To build: make apple1"
@echo " To program: make prog"
@echo "To build report: make report"
@echo " To clean up: make clean"
dir:
mkdir -p $(BUILDDIR)
# ------ TEMPLATES ------
$(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v
yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif $@" $^
$(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif
arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^
$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
icepack $^ $@
%.rpt: $(BUILDDIR)/%.asc
icetime -d $(DEVICE) -mtr $@ $<
%_tb.vvp: %_tb.v %.v
iverilog -o $@ $^
%_tb.vcd: %_tb.vvp
vvp -N $< +vcd=$@
# ------ APPLE 1 ------
apple1: dir $(BUILDDIR)/apple1.bin
report: dir apple1.rpt
$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc
$(BUILDDIR)/apple1.asc: $(BUILDDIR)/apple1.blif
$(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \
$(SOURCEDIR)/ram.v \
$(SOURCEDIR)/rom_wozmon.v \
$(SOURCEDIR)/rom_basic.v \
$(SOURCEDIR)/cpu/arlet_6502.v \
$(SOURCEDIR)/cpu/arlet/ALU.v \
$(SOURCEDIR)/cpu/arlet/cpu.v \
$(SOURCEDIR)/uart/uart.v \
$(SOURCEDIR)/uart/async_tx_rx.v \
$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
$(SOURCEDIR)/boards/ice40hx8k/clock_pll.v \
$(SOURCEDIR)/boards/ice40hx8k/apple1_hx8k.v
apple1.rpt: $(BUILDDIR)/apple1.asc
prog: dir $(BUILDDIR)/apple1.bin
iceprog -S $(filter-out $<,$^)
# ------ HELPERS ------
clean:
rm -rf build apple1.rpt
.SECONDARY:
.PHONY: all clean prog iceprog

1
boards/ice40hx8k_yosys/ice40hx8k.pcf Symbolic link
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@ -0,0 +1 @@
../ice40hx8k/ice40hx8k.pcf

30
rtl/apple1.v
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@ -1,20 +1,17 @@
module apple1(
input clk25, // 25 MHz master clock
input rst_n, // active low synchronous reset (needed for simulation)
input clk25, // 25 MHz master clock
input rst_n, // active low synchronous reset (needed for simulation)
input uart_rx,
output uart_tx,
output uart_cts,
input ps2_clk, // PS/2 keyboard serial clock input
input ps2_din, // PS/2 keyboard serial data input
input ps2_clk, // PS/2 keyboard serial clock input
input ps2_din, // PS/2 keyboard serial data input
output [15:0] pc_monitor // spy for program counter / debugging
output [15:0] pc_monitor, // spy for program counter / debugging
input reset_button // allow a physical reset button
);
parameter RAM_FILENAME = "../../roms/ram.hex";
parameter WOZ_FILENAME = "../../roms/wozmon.hex";
parameter BASIC_FILENAME = "../../roms/basic.hex";
//////////////////////////////////////////////////////////////////////////
// Registers and Wires
@ -89,7 +86,7 @@ module apple1(
end
end
assign reset = ~hard_reset;
assign reset = ~(hard_reset && reset_button);
//////////////////////////////////////////////////////////////////////////
// 6502
@ -120,7 +117,7 @@ module apple1(
// RAM
wire [7:0] ram_dout;
ram #(RAM_FILENAME) my_ram (
ram my_ram(
.clk(clk25),
.address(ab[12:0]),
.w_en(we & ram_cs),
@ -130,7 +127,7 @@ module apple1(
// WozMon ROM
wire [7:0] rom_dout;
rom_wozmon #(WOZ_FILENAME) my_rom_wozmon (
rom_wozmon my_rom_wozmon(
.clk(clk25),
.address(ab[7:0]),
.dout(rom_dout)
@ -138,7 +135,7 @@ module apple1(
// Basic ROM
wire [7:0] basic_dout;
rom_basic #(BASIC_FILENAME) my_rom_basic (
rom_basic my_rom_basic(
.clk(clk25),
.address(ab[11:0]),
.dout(basic_dout)
@ -150,9 +147,9 @@ module apple1(
`ifdef SIM
100, 10, 2 // for simulation don't need real baud rates
`else
25000000, 115200, 8
25000000, 115200, 8 // 25MHz, 115200 baud, 8 times RX oversampling
`endif
)my_uart (
) my_uart(
.clk(clk25),
.reset(reset),
@ -170,8 +167,7 @@ module apple1(
// PS/2 keyboard interface
wire [7:0] ps2_dout;
ps2keyboard keyboard
(
ps2keyboard keyboard(
.clk25(clk25),
.reset(reset),
.key_clk(ps2_clk),

5
rtl/boards/ice40hx8k/apple1_hx8k.v
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@ -5,7 +5,7 @@ module apple1_top(
output uart_tx,
output uart_cts,
output [15:0] led,
output [1:0] button
input [3:0] button
);
wire clk25;
@ -29,7 +29,8 @@ module apple1_top(
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.uart_cts(uart_cts),
.pc_monitor(pc_monitor)
.pc_monitor(pc_monitor),
.reset_button(button[0])
);
endmodule

12
rtl/ram.v
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@ -6,17 +6,21 @@ module ram(
output reg [7:0] dout
);
`ifdef YOSYS
parameter RAM_FILENAME = "../../roms/ram.hex";
`else
parameter RAM_FILENAME = "../roms/ram.hex";
`endif
reg [7:0] ram[0:8191];
reg [7:0] ram_data[0:8191];
initial
$readmemh(RAM_FILENAME, ram, 0, 8191);
$readmemh(RAM_FILENAME, ram_data, 0, 8191);
always @(posedge clk)
begin
dout <= ram[address];
if (w_en) ram[address] <= din;
dout <= ram_data[address];
if (w_en) ram_data[address] <= din;
end
endmodule

12
rtl/rom_basic.v
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@ -4,14 +4,18 @@ module rom_basic(
output reg [7:0] dout
);
parameter ROM_FILENAME = "../roms/basic.hex";
`ifdef YOSYS
parameter BASIC_FILENAME = "../../roms/basic.hex";
`else
parameter BASIC_FILENAME = "../roms/basic.hex";
`endif
reg [11:0] rom[0:4095];
reg [7:0] rom_data[0:4095];
initial
$readmemh(ROM_FILENAME, rom, 0, 4095);
$readmemh(BASIC_FILENAME, rom_data, 0, 4095);
always @(posedge clk)
dout <= rom[address];
dout <= rom_data[address];
endmodule

10
rtl/rom_wozmon.v
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@ -4,15 +4,19 @@ module rom_wozmon(
output reg [7:0] dout
);
`ifdef YOSYS
parameter ROM_FILENAME = "../../roms/wozmon.hex";
`else
parameter ROM_FILENAME = "../roms/wozmon.hex";
`endif
reg [7:0] rom[0:255];
reg [7:0] rom_data[0:255];
initial
$readmemh(ROM_FILENAME, rom, 0, 255);
$readmemh(ROM_FILENAME, rom_data, 0, 255);
always @(posedge clk)
dout <= rom[address];
dout <= rom_data[address];
endmodule