Merge aea51dc240 into 5a969c5f6f

Update README.md
Merge pull request #44 from aslak3/aslak3/ice40updevboard
2024-04-22 08:59:27 +10:00 · 2024-04-22 08:56:44 +10:00 · 2024-04-22 08:55:48 +10:00 · 2024-04-18 10:34:52 +01:00 · 2024-04-09 21:22:14 +10:00 · 2018-10-22 14:13:07 +11:00
15 changed files with 656 additions and 8 deletions
--- a/README.md
+++ b/README.md
@ -16,7 +16,7 @@ Contributor supported boards (YMMV):
 <img src="media/apple-one.png" alt="Apple One Running">
 </p>

-This project borrows heavily from the *awesome* work of Andrew Holme and his ["Pool"](http://www.aholme.co.uk/6502/Main.htm) project and [Arlet Otten's](https://github.com/Arlet/verilog-6502) tiny 6502 core. Also many special thanks to ["sbprojects.com"](https://www.sbprojects.com/projects/apple1/index.php) for the wealth of information I gleaned from there.
+This project borrows heavily from the *awesome* work of Andrew Holme and his ["Pool"](http://www.aholme.co.uk/6502/Main.htm) project and [Arlet Otten's](https://github.com/Arlet/verilog-6502) tiny 6502 core. Also many special thanks to [sbprojects.com](https://www.sbprojects.net/projects/apple1/index.php) for the wealth of information I gleaned from there.

 ## Memory Map
 
--- a/boards/ice40updevboard/README.md
+++ b/boards/ice40updevboard/README.md
@ -0,0 +1,17 @@
+# ICE40UPDev Board support
+
+![ICE40UPDevBoard board render](images/ICE40UPDevBoard.png)
+
+This adds support for building apple one design for [Aslak3's ICE40UP Development Board](http://github.com/aslak3/ICE40UPDevBoard). The board contains a [ADV7123](https://www.analog.com/media/en/technical-documentation/data-sheets/ADV7123-EP.pdf) (PDF) RGB DAC and PS/2 port, and some I2C hardware that this Apple 1 implementation does not yet make use of. The single push button on the board is mapped to the reset line. The PS/2 port on the board is actually wired to two PS/2 connections, but this project makes only use of the first ("default") wiring for the keyboard.
+
+## Building
+Install a recent toolchain and:
+
+```
+$ cd yosys
+$ make
+```
+
+Unlike other boards in this project nextpnr-ice4 is used for routing, since it has been the current tool for some years now and arachne-pnr was deprecated in 2015.
+
+Program the board using any suitable method.
--- a/boards/ice40updevboard/images/ICE40UPDevBoard.png
+++ b/boards/ice40updevboard/images/ICE40UPDevBoard.png
--- a/boards/ice40updevboard/yosys/Makefile
+++ b/boards/ice40updevboard/yosys/Makefile
@ -0,0 +1,67 @@
+DEVICE = up5k
+PIN_DEF = ice40updevboard.pcf
+
+SOURCEDIR = ../../../rtl
+BUILDDIR = build
+
+all: apple1 
+
+info:
+	@echo "       To build: make apple1"
+	@echo "To build report: make report"
+	@echo "    To clean up: make clean"
+
+dir:
+	mkdir -p $(BUILDDIR)
+
+# ------ TEMPLATES ------
+$(BUILDDIR)/%.json: $(SOURCEDIR)/%.v
+	yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -json $@" $^
+
+$(BUILDDIR)/%.asc: $(BUILDDIR)/%.json
+	nextpnr-ice40 --up5k --package sg48 --pcf $(PIN_DEF) --json $^ --asc $@
+
+$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
+	icepack $^ $@
+
+%.rpt: $(BUILDDIR)/%.asc
+	icetime -d $(DEVICE) -mtr $@ $<
+
+%_tb.vvp: %_tb.v %.v
+	iverilog -o $@ $^
+
+%_tb.vcd: %_tb.vvp
+	vvp -N $< +vcd=$@
+
+# ------ APPLE 1 ------
+apple1: dir $(BUILDDIR)/apple1.bin
+report: dir apple1.rpt
+
+$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc
+$(BUILDDIR)/apple1.asc: $(BUILDDIR)/apple1.json
+$(BUILDDIR)/apple1.json: $(SOURCEDIR)/apple1.v \
+	$(SOURCEDIR)/clock.v \
+	$(SOURCEDIR)/pwr_reset.v \
+	$(SOURCEDIR)/ram.v \
+	$(SOURCEDIR)/rom_wozmon.v \
+	$(SOURCEDIR)/rom_basic.v \
+	$(SOURCEDIR)/cpu/arlet_6502.v \
+	$(SOURCEDIR)/cpu/arlet/ALU.v \
+	$(SOURCEDIR)/cpu/arlet/cpu.v \
+	$(SOURCEDIR)/uart/uart.v \
+	$(SOURCEDIR)/uart/async_tx_rx.v \
+	$(SOURCEDIR)/vga/vga.v \
+	$(SOURCEDIR)/vga/vram.v \
+	$(SOURCEDIR)/vga/font_rom.v \
+	$(SOURCEDIR)/ps2keyboard/debounce.v \
+	$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
+	$(SOURCEDIR)/boards/ice40updevboard/apple1_ice40updevboard.v
+
+apple1.rpt: $(BUILDDIR)/apple1.asc
+
+# ------ HELPERS ------
+clean:
+	rm -rf build apple1.rpt
+
+.SECONDARY:
+.PHONY: all info clean
--- a/boards/ice40updevboard/yosys/ice40updevboard.pcf
+++ b/boards/ice40updevboard/yosys/ice40updevboard.pcf
@ -0,0 +1,35 @@
+### UART - This is the first 3 userheader pins, USER0 through 2 on the board
+set_io uart_rx   45
+set_io uart_tx   46 
+set_io uart_cts  47
+
+### LEDs
+set_io led[0]   38
+set_io led[1]   39
+set_io led[2]   40
+
+set_io vga_h_sync 9
+set_io vga_v_sync 10
+set_io vga_clk 11      # DAC clock
+set_io vga_blank_n 20  # Blanking pin
+
+set_io vga_r[3] 27
+set_io vga_r[2] 28
+set_io vga_r[1] 31
+set_io vga_r[0] 32
+set_io vga_g[3] 21
+set_io vga_g[2] 23
+set_io vga_g[1] 25
+set_io vga_g[0] 26
+set_io vga_b[3] 12
+set_io vga_b[2] 13
+set_io vga_b[1] 18
+set_io vga_b[0] 19
+
+set_io clk 44
+
+set_io ps2_din 36
+set_io ps2_clk 37
+
+set_io button 41
+
--- a/boards/tinyfpga_bx/icecube2/icecube2_sbt.project
+++ b/boards/tinyfpga_bx/icecube2/icecube2_sbt.project
@ -0,0 +1,88 @@
+[Project]
+ProjectVersion=2.0
+Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Build Date: Sep 11 2017 17:40:01
+ProjectName=icecube2
+Vendor=SiliconBlue
+Synthesis=synplify
+ProjectVFiles=../../../../rtl/apple1.v,../../../../rtl/clock.v,../../../../rtl/pwr_reset.v,../../../../rtl/ram.v,../../../../rtl/rom_basic.v,../../../../rtl/rom_wozmon.v,../../../../rtl/boards/tinyfpga_bx/apple1_hx8k.v,../../../../rtl/boards/tinyfpga_bx/clock_pll.v,../../../../rtl/cpu/arlet_6502.v,../../../../rtl/cpu/arlet/ALU.v,../../../../rtl/cpu/arlet/cpu.v,../../../../rtl/ps2keyboard/debounce.v,../../../../rtl/ps2keyboard/ps2keyboard.v,../../../../rtl/uart/async_tx_rx.v,../../../../rtl/uart/uart.v,../../../../rtl/vga/font_rom.v,../../../../rtl/vga/vga.v,../../../../rtl/vga/vram.v
+ProjectCFiles=
+CurImplementation=icecube2_Implmnt
+Implementations=icecube2_Implmnt
+StartFromSynthesis=yes
+IPGeneration=false
+
+[icecube2_Implmnt]
+DeviceFamily=iCE40
+Device=LP8K
+DevicePackage=CM81
+DevicePower=
+NetlistFile=icecube2_Implmnt/icecube2.edf
+AdditionalEDIFFile=
+IPEDIFFile=
+DesignLib=icecube2_Implmnt/sbt/netlist/oadb-apple1_top
+DesignView=_rt
+DesignCell=apple1_top
+SynthesisSDCFile=icecube2_Implmnt/icecube2.scf
+UserPinConstraintFile=
+UserSDCFile=
+PhysicalConstraintFile=../tinyfpga_bx.pcf
+BackendImplPathName=
+Devicevoltage=1.14
+DevicevoltagePerformance=+/-5%(datasheet default)
+DeviceTemperature=85
+TimingAnalysisBasedOn=Worst
+OperationRange=Commercial
+TypicalCustomTemperature=25
+WorstCustomTemperature=85
+BestCustomTemperature=0
+IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3
+derValue=1.03369
+TimingPathNumberStick=0
+
+[lse options]
+CarryChain=True
+CarryChainLength=0
+CommandLineOptions=
+EBRUtilization=100.00
+FSMEncodingStyle=Auto
+FixGatedClocks=True
+I/OInsertion=True
+IntermediateFileDump=False
+LoopLimit=1950
+MaximalFanout=10000
+MemoryInitialValueFileSearchPath=
+NumberOfCriticalPaths=3
+OptimizationGoal=Area
+PropagateConstants=True
+RAMStyle=Auto
+ROMStyle=Auto
+RWCheckOnRam=False
+RemoveDuplicateRegisters=True
+ResolvedMixedDrivers=False
+ResourceSharing=True
+TargetFrequency=
+TopLevelUnit=
+UseIORegister=Auto
+VHDL2008=False
+VerilogIncludeSearchPath=
+
+[tool options]
+PlacerEffortLevel=std
+PlacerAutoLutCascade=yes
+PlacerAutoRamCascade=yes
+PlacerPowerDriven=no
+PlacerAreaDriven=no
+RouteWithTimingDriven=yes
+RouteWithPinPermutation=yes
+BitmapSPIFlashMode=yes
+BitmapRAM4KInit=yes
+BitmapInitRamBank=1111
+BitmapOscillatorFR=low
+BitmapEnableWarmBoot=yes
+BitmapDisableHeader=no
+BitmapSetSecurity=no
+BitmapSetNoUsedIONoPullup=no
+FloorPlannerShowFanInNets=yes
+FloorPlannerShowFanOutNets=yes
+HookTo3rdPartyTextEditor=
+
--- a/boards/tinyfpga_bx/icecube2/icecube2_syn.prj
+++ b/boards/tinyfpga_bx/icecube2/icecube2_syn.prj
@ -0,0 +1,73 @@
+#-- Synopsys, Inc.
+#-- Project file Z:\boards\tinyfpga_bx\\icecube2\icecube2_syn.prj
+#project files
+add_file -verilog -lib work "../../../../rtl/apple1.v"
+add_file -verilog -lib work "../../../../rtl/clock.v"
+add_file -verilog -lib work "../../../../rtl/pwr_reset.v"
+add_file -verilog -lib work "../../../../rtl/ram.v"
+add_file -verilog -lib work "../../../../rtl/rom_basic.v"
+add_file -verilog -lib work "../../../../rtl/rom_wozmon.v"
+add_file -verilog -lib work "../../../../rtl/boards/tinyfpga_bx/apple1_hx8k.v"
+add_file -verilog -lib work "../../../../rtl/boards/tinyfpga_bx/clock_pll.v"
+add_file -verilog -lib work "../../../../rtl/cpu/arlet_6502.v"
+add_file -verilog -lib work "../../../../rtl/cpu/arlet/ALU.v"
+add_file -verilog -lib work "../../../../rtl/cpu/arlet/cpu.v"
+add_file -verilog -lib work "../../../../rtl/ps2keyboard/debounce.v"
+add_file -verilog -lib work "../../../../rtl/ps2keyboard/ps2keyboard.v"
+add_file -verilog -lib work "../../../../rtl/uart/async_tx_rx.v"
+add_file -verilog -lib work "../../../../rtl/uart/uart.v"
+add_file -verilog -lib work "../../../../rtl/vga/font_rom.v"
+add_file -verilog -lib work "../../../../rtl/vga/vga.v"
+add_file -verilog -lib work "../../../../rtl/vga/vram.v"
+
+#implementation: "icecube2_Implmnt"
+impl -add icecube2_Implmnt -type fpga
+
+#implementation attributes
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+
+#device options
+set_option -technology SBTiCE40
+set_option -part iCE40LP8K
+set_option -package CM81
+set_option -speed_grade 
+set_option -part_companion ""
+
+#compilation/mapping options
+
+# mapper_options
+set_option -frequency auto
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+# Silicon Blue iCE40
+set_option -maxfan 10000
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -retiming 0
+set_option -update_models_cp 0
+set_option -fixgatedclocks 2
+set_option -fixgeneratedclocks 0
+
+# NFilter
+set_option -popfeed 0
+set_option -constprop 0
+set_option -createhierarchy 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_format "edif"
+project -result_file ./icecube2_Implmnt/icecube2.edf
+project -log_file "./icecube2_Implmnt/icecube2.srr"
+impl -active "icecube2_Implmnt"
+project -run synthesis -clean
--- a/boards/tinyfpga_bx/tinyfpga_bx.pcf
+++ b/boards/tinyfpga_bx/tinyfpga_bx.pcf
@ -0,0 +1,17 @@
+## System Clock
+set_io clk B2
+
+## VGA Display
+set_io vga_red A6
+set_io vga_grn B6
+set_io vga_blu A7
+set_io vga_h_sync B7
+set_io vga_v_sync A8
+
+## UART
+set_io uart_rx B1
+set_io uart_tx C2
+
+## Lighthouse
+set_io lt_dat H1
+set_io lt_env J1
--- a/boards/tinyfpga_bx/yosys/Makefile
+++ b/boards/tinyfpga_bx/yosys/Makefile
@ -0,0 +1,82 @@
+DEVICE = 8k
+PACKAGE = cm81
+FREQ_OSC = 16
+FREQ_PLL = 25
+
+PIN_DEF=tinyfpga_bx.pcf
+
+SOURCEDIR = ../../../rtl
+BUILDDIR = build
+
+PLL = $(BUILDDIR)/pll.sv
+
+all: apple1 prog
+
+info:
+	@echo "       To build: make apple1"
+	@echo "     To program: make prog"
+	@echo "To build report: make report"
+	@echo "    To clean up: make clean"
+
+dir:
+	mkdir -p $(BUILDDIR)
+
+# ------ TEMPLATES ------
+$(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v
+	yosys -q -p "synth_ice40 -top apple1_top -blif $@" $^
+
+$(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif
+	arachne-pnr -d $(DEVICE) -P $(PACKAGE) -o $@ -p $^
+
+$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
+	icepack $^ $@
+
+%.rpt: $(BUILDDIR)/%.asc
+	icetime -d $(DEVICE) -mtr $@ $<
+
+%_tb.vvp: %_tb.v %.v
+	iverilog -o $@ $^
+
+%_tb.vcd: %_tb.vvp
+	vvp -N $< +vcd=$@
+
+$(PLL):
+	icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@
+
+# ------ APPLE 1 ------
+apple1: dir $(BUILDDIR)/apple1.bin
+report: dir apple1.rpt
+
+$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc
+$(BUILDDIR)/apple1.asc: $(BUILDDIR)/apple1.blif
+$(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \
+	$(SOURCEDIR)/clock.v \
+	$(SOURCEDIR)/pwr_reset.v \
+	$(SOURCEDIR)/ram.v \
+	$(SOURCEDIR)/rom_wozmon.v \
+	$(SOURCEDIR)/rom_basic.v \
+	$(SOURCEDIR)/cpu/arlet_6502.v \
+	$(SOURCEDIR)/cpu/arlet/ALU.v \
+	$(SOURCEDIR)/cpu/arlet/cpu.v \
+	$(SOURCEDIR)/uart/uart.v \
+	$(SOURCEDIR)/uart/async_tx_rx.v \
+	$(SOURCEDIR)/vga/vga.v \
+	$(SOURCEDIR)/vga/vram.v \
+	$(SOURCEDIR)/vga/font_rom.v \
+	$(SOURCEDIR)/ps2keyboard/debounce.v \
+	$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
+	$(SOURCEDIR)/boards/tinyfpga_bx/clock_pll.v \
+	$(SOURCEDIR)/boards/tinyfpga_bx/apple1_hx8k.v \
+	$(BUILDDIR)/pll.sv
+
+apple1.rpt: $(BUILDDIR)/apple1.asc
+
+prog: dir $(BUILDDIR)/apple1.bin
+	tinyprog -p $(filter-out $<,$^)
+
+# ------ HELPERS ------
+clean:
+	rm -rf build apple1.rpt
+
+.SECONDARY:
+.PHONY: all info clean prog iceprog
--- a/boards/tinyfpga_bx/yosys/tinyfpga_bx.pcf
+++ b/boards/tinyfpga_bx/yosys/tinyfpga_bx.pcf
@ -0,0 +1 @@
+../tinyfpga_bx.pcf
--- a/rtl/apple1.v
+++ b/rtl/apple1.v
@ -35,7 +35,6 @@ module apple1 #(
    // I/O interface to computer
    input  uart_rx,             // asynchronous serial data input from computer
    output uart_tx,             // asynchronous serial data output to computer
-    output uart_cts,            // clear to send flag to computer

    // I/O interface to keyboard
    input ps2_clk,              // PS/2 keyboard serial clock input
@ -177,9 +176,8 @@ module apple1 #(

        .uart_rx(uart_rx),
        .uart_tx(uart_tx),
-        .uart_cts(uart_cts),

-        .address(ab[1:0]),        // for uart
+        .address(ab[1:0]),
        .w_en(we & uart_cs),
        .din(dbo),
        .dout(uart_dout)
--- a/rtl/boards/ice40updevboard/apple1_ice40updevboard.v
+++ b/rtl/boards/ice40updevboard/apple1_ice40updevboard.v
@ -0,0 +1,120 @@
+// Licensed to the Apache Software Foundation (ASF) under one
+// or more contributor license agreements.  See the NOTICE file
+// distributed with this work for additional information
+// regarding copyright ownership.  The ASF licenses this file
+// to you under the Apache License, Version 2.0 (the
+// "License"); you may not use this file except in compliance
+// with the License.  You may obtain a copy of the License at
+//
+//   http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing,
+// software distributed under the License is distributed on an
+// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+// KIND, either express or implied.  See the License for the
+// specific language governing permissions and limitations
+// under the License.
+//
+// Description: Apple 1 implementation for the Blackeice II ICE40HX8K +
+//
+// Author.....: Lawrence Manning
+// Date.......: 18-04-2024 (inspired by blackice2/apple1_hx8k.v)
+//
+
+module apple1_top #(
+    parameter BASIC_FILENAME      = "../../../roms/basic.hex",
+    parameter FONT_ROM_FILENAME   = "../../../roms/vga_font_bitreversed.hex",
+    parameter RAM_FILENAME        = "../../../roms/ram.hex",
+    parameter VRAM_FILENAME       = "../../../roms/vga_vram.bin",
+    parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
+) (
+    input  clk,             // 50 MHz board clock
+
+    // I/O interface to computer
+    input  uart_rx,         // asynchronous serial data input from computer
+    output uart_tx,         // asynchronous serial data output to computer
+    output uart_cts,        // clear to send flag to computer - not used
+
+    // I/O interface to keyboard
+    input ps2_clk,          // PS/2 keyboard serial clock input
+    input ps2_din,          // PS/2 keyboard serial data input
+
+    // Outputs to VGA display
+    output vga_h_sync,      // hozizontal VGA sync pulse
+    output vga_v_sync,      // vertical VGA sync pulse
+
+    // Outputs to the ADV7123 RGB DAC IC
+    output vga_clk,
+    output vga_blank_n,
+
+    output [3:0] vga_r,     // red VGA signal
+    output [3:0] vga_g,     // green VGA signal
+    output [3:0] vga_b,     // blue VGA signal
+
+    // Debugging ports
+    output [2:0] led,
+    input button,            // 1 button on board
+);
+
+    assign vga_clk = clk25;
+    assign vga_blank_n = 1;
+
+    // Active low
+    assign led[0] = reset_n;
+    assign led[1] = 1;
+    assign led[2] = 1;
+
+    // ===============================================================
+    // System Clock generation (25MHz)
+    // ===============================================================
+
+    reg clk25 = 1;
+
+    // generate 25MHz clock from 50MHz master clock
+    always @(posedge clk)
+    begin
+        clk25 <= ~clk25;
+    end
+
+    wire vga_bit;
+
+    // set the monochrome base colour here..
+    assign vga_r[3:0] = vga_bit ? 4'b1000 : 4'b0000;
+    assign vga_g[3:0] = vga_bit ? 4'b1111 : 4'b0000;
+    assign vga_b[3:0] = vga_bit ? 4'b1000 : 4'b0000;
+
+    // debounce reset button
+    wire reset_n;
+    debounce reset_button (
+        .clk25(clk25),
+        .rst(1'b0),
+        .sig_in(button),
+        .sig_out(reset_n)
+    );
+
+    // apple one main system
+    apple1 #(
+        .BASIC_FILENAME (BASIC_FILENAME),
+        .FONT_ROM_FILENAME (FONT_ROM_FILENAME),
+        .RAM_FILENAME (RAM_FILENAME),
+        .VRAM_FILENAME (VRAM_FILENAME),
+        .WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
+    ) my_apple1(
+        .clk25(clk25),
+        .rst_n(reset_n),
+
+        .uart_rx(uart_rx),
+        .uart_tx(uart_tx),
+        .uart_cts(uart_cts),
+
+        .ps2_clk(ps2_clk),
+        .ps2_din(ps2_din),
+        .ps2_select(1'b1),       // PS/2 enabled, UART TX disabled
+        // .ps2_select(1'b0),    // PS/2 disabled, UART TX enabled
+
+        .vga_h_sync(vga_h_sync),
+        .vga_v_sync(vga_v_sync),
+        .vga_red(vga_bit),
+        .vga_cls(~reset_n),
+    );
+endmodule
--- a/rtl/boards/tinyfpga_bx/apple1_hx8k.v
+++ b/rtl/boards/tinyfpga_bx/apple1_hx8k.v
@ -0,0 +1,115 @@
+// Licensed to the Apache Software Foundation (ASF) under one
+// or more contributor license agreements.  See the NOTICE file
+// distributed with this work for additional information
+// regarding copyright ownership.  The ASF licenses this file
+// to you under the Apache License, Version 2.0 (the
+// "License"); you may not use this file except in compliance
+// with the License.  You may obtain a copy of the License at
+//
+//   http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing,
+// software distributed under the License is distributed on an
+// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+// KIND, either express or implied.  See the License for the
+// specific language governing permissions and limitations
+// under the License.
+//
+// Description: Apple 1 implementation for the iCE40HX8K dev
+//              board.
+//
+// Author.....: Alan Garfield
+// Date.......: 21-10-2018
+//
+
+module apple1_top #(
+    parameter BASIC_FILENAME      = "../../../roms/basic.hex",
+    parameter FONT_ROM_FILENAME   = "../../../roms/vga_font_bitreversed.hex",
+    parameter RAM_FILENAME        = "../../../roms/ram.hex",
+    parameter VRAM_FILENAME       = "../../../roms/vga_vram.bin",
+    parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
+) (
+    input clk,          // 16 MHz board clock
+
+    // I/O interface to computer
+    input  uart_rx,         // asynchronous serial data input from computer
+    output uart_tx,         // asynchronous serial data output to computer
+
+    // Outputs to VGA display
+    output vga_h_sync,      // hozizontal VGA sync pulse
+    output vga_v_sync,      // vertical VGA sync pulse
+    output vga_red,         // red VGA signal
+    output vga_grn,         // green VGA signal
+    output vga_blu,         // blue VGA signal
+
+    inout lt_dat,
+    inout lt_env
+);
+
+    wire clk25;
+
+    // 16MHz up to 25MHz
+    clock_pll clock_pll_inst(
+            .REFERENCECLK(clk),
+            .PLLOUTGLOBAL(clk25),
+            .RESET(1'b1)
+            );
+
+    // lighthouse sensor
+    wire lt_data_rw;
+    wire lt_data_in, lt_data_out;
+    SB_IO #(
+        .PIN_TYPE(6'b101001),
+        .PULLUP(1'b1)
+    ) lt_dat_io (
+        .PACKAGE_PIN(lt_dat),
+        .OUTPUT_ENABLE(lt_data_rw),
+        .D_IN_0(lt_data_in),
+        .D_OUT_0(lt_data_out)
+    );
+
+    wire lt_env_rw;
+    wire lt_env_in, lt_env_out;
+    SB_IO #(
+        .PIN_TYPE(6'b101001),
+        .PULLUP(1'b1)
+    ) lt_env_io (
+        .PACKAGE_PIN(lt_env),
+        .OUTPUT_ENABLE(lt_env_rw),
+        .D_IN_0(lt_env_in),
+        .D_OUT_0(lt_env_out)
+    );
+
+    assign lt_data_rw = 1'b0;
+    assign lt_data_out = 1'b0;
+    assign lt_env_rw = 1'b0;
+    assign lt_env_out = 1'b0;
+
+    // program counter
+    wire pc_monitor;
+
+    // apple one main system
+    apple1 #(
+        .BASIC_FILENAME (BASIC_FILENAME),
+        .FONT_ROM_FILENAME (FONT_ROM_FILENAME),
+        .RAM_FILENAME (RAM_FILENAME),
+        .VRAM_FILENAME (VRAM_FILENAME),
+        .WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
+    ) my_apple1(
+        .clk25(clk25),
+        .rst_n(1'b1),
+        .uart_rx(uart_rx),
+        .uart_tx(uart_tx),
+        .ps2_clk(1'b0),
+        .ps2_din(1'b0),
+        .ps2_select(1'b1),
+        .vga_h_sync(vga_h_sync),
+        .vga_v_sync(vga_v_sync),
+        .vga_red(vga_red),
+        .vga_grn(vga_grn),
+        .vga_blu(vga_blu),
+        .vga_cls(1'b0),
+        .pc_monitor(pc_monitor)
+    );
+
+endmodule
--- a/rtl/boards/tinyfpga_bx/clock_pll.v
+++ b/rtl/boards/tinyfpga_bx/clock_pll.v
@ -0,0 +1,38 @@
+module clock_pll(REFERENCECLK,
+                 PLLOUTCORE,
+                 PLLOUTGLOBAL,
+                 RESET);
+
+input REFERENCECLK;
+input RESET;    /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */ 
+output PLLOUTCORE;
+output PLLOUTGLOBAL;
+
+SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK),
+                             .PLLOUTCORE(PLLOUTCORE),
+                             .PLLOUTGLOBAL(PLLOUTGLOBAL),
+                             .EXTFEEDBACK(1'd0),
+                             .DYNAMICDELAY(8'd0),
+                             .RESETB(RESET),
+                             .BYPASS(1'b0),
+                             .LATCHINPUTVALUE(1'd0),
+                             .LOCK(),
+                             .SDI(1'd0),
+                             .SDO(),
+                             .SCLK(1'd0));
+
+//\\ Fin=16, Fout=25;
+defparam clock_pll_inst.DIVR = 4'b0000;
+defparam clock_pll_inst.DIVF = 7'b0110001;
+defparam clock_pll_inst.DIVQ = 3'b101;
+defparam clock_pll_inst.FILTER_RANGE = 3'b001;
+defparam clock_pll_inst.FEEDBACK_PATH = "SIMPLE";
+defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
+defparam clock_pll_inst.FDA_FEEDBACK = 4'b0000;
+defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
+defparam clock_pll_inst.FDA_RELATIVE = 4'b0000;
+defparam clock_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
+defparam clock_pll_inst.PLLOUT_SELECT = "GENCLK";
+defparam clock_pll_inst.ENABLE_ICEGATE = 1'b0;
+
+endmodule
--- a/rtl/uart/uart.v
+++ b/rtl/uart/uart.v
@ -32,8 +32,7 @@ module uart(
    output reg [7:0] dout,  // 8-bit data bus (output)

    input uart_rx,          // asynchronous serial data input from computer
-    output uart_tx,         // asynchronous serial data output to computer
-    output uart_cts         // clear to send flag to computer
+    output uart_tx          // asynchronous serial data output to computer
    );

    parameter ClkFrequency = 25000000;	// 25MHz
@ -91,8 +90,6 @@ module uart(
        end
    end

-    assign uart_cts = ~rx_idle || uart_rx_status;
-
    localparam UART_RX   = 2'b00;
    localparam UART_RXCR = 2'b01;
    localparam UART_TX   = 2'b10;
Author	SHA1	Message	Date
Alan Garfield	2b63b396ec	Merge `aea51dc240` into `5a969c5f6f`	2024-04-22 08:59:27 +10:00
Alan Garfield	5a969c5f6f	Update README.md	2024-04-22 08:56:44 +10:00
Alan Garfield	51fda1c41b	Merge pull request #44 from aslak3/aslak3/ice40updevboard Added support for ICE40UPDevBoard	2024-04-22 08:55:48 +10:00
Lawrence Manning	09c2181820	Added support for ICE40UPDevBoard My board features an ICE40UP5K in QFN and the usual flash, PS/2 port etc. Thought it would be fun to port this Apple One implementation, and it was super easy considering I'm quite new to Verilog.	2024-04-18 10:34:52 +01:00
Alan Garfield	f1abc56bb1	Update README.md	2024-04-09 21:22:14 +10:00
Alan Garfield	aea51dc240	more tidy up on bx	2018-10-22 14:13:07 +11:00
Alan Garfield	d6a31cfd0e	fixed a few errors yosys didn't care about but icecube2 does	2018-10-22 00:08:54 +11:00
Alan Garfield	7ce76a224d	fixed dumb error with uart setup	2018-10-21 22:23:23 +11:00
Alan Garfield	99fc3e6ef5	added initial test of tinyfpga bx	2018-10-21 21:06:21 +11:00