Apple-1-HW
/
verilog-apple-one
mirror of https://github.com/alangarf/apple-one.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
142 Commits 3 Branches 0 Tags 6.9 MiB
Verilog 52.8%
IGOR Pro 17.1%
Pawn 16%
Tcl 7.1%
Makefile 4.1%
Other 2.8%
Go to file
Olof Kindgren 4cb800f368 Add FuseSoC support for s3e-starterkit 2018-02-12 21:32:40 +01:00
boards S3E updates. 2018-02-12 16:47:52 +01:00
doc Added fusesoc doc. 2018-02-12 16:15:26 +01:00
media added apple-one standalone image 2018-02-12 09:40:11 +11:00
roms Update basic.hex and ram.hex to be ISE compliant. 2018-02-12 16:27:01 +01:00
rtl S3E updates. 2018-02-12 16:47:52 +01:00
tools Merge pull request #14 from olofk/fusesoc 2018-02-12 15:56:44 +01:00
.gitignore Added yosys support again, yay for FOSS! 2018-01-29 17:45:01 +11:00
CODE_OF_CONDUCT.md Create CODE_OF_CONDUCT.md 2018-01-28 12:46:48 +11:00
CONTRIBUTING.md Create CONTRIBUTING.md 2018-01-28 12:48:43 +11:00
LICENSE Initial commit 2018-01-02 00:23:13 +11:00
README.md Centered main image in readme 2018-02-12 09:46:53 +11:00
apple-one.core Add FuseSoC support for s3e-starterkit 2018-02-12 21:32:40 +01:00

README.md

Apple One

This is a basic implementation of the original Apple 1 in Verilog. It can run the Apple 1 WozMon and Integer Basic via the serial or VGA 640x480 video with PS/2 keyboard standalone. This makes this a very compact little set up. So far fully tested and supported boards are:

  • iCE40HX8K-B-EVN breakout
  • Terasic DE0

Apple One Running

This project borrows heavily from the awesome work of Andrew Holme and his "Pool" project where he built a 6502 CPU core in Verilog using the netlist from the Visual 6502 project. Amazing stuff, and so far seems to work perfectly. Also many special thanks to "sbprojects.com" for the wealth of information I gleaned from there.

Memory Map

The memory map is currently set up to have:

Start End Description
0x0000 0x1FFF 8KB of block RAM for system
0xE000 0xEFFF 4KB of block RAM for basic ROM
0xFF00 0xFFFF 512B of block RAM for WozMon ROM

Building

Each supported board has a directory in boards. This directory has a structure where each board can have multiple build environments (eg. yosys, icecube2, quartus etc).

To build for your board you just need to open the project or use the Makefile that's compatible with your board.

eg.

$ cd boards/ice40hx8k-b-evn/yosys/
$ make

Serial Setup

To communicate with the Apple 1 you need to use the second channel serial interface for the iCE40HX8K-B-EVN board. This should appear as a COM port on you PC. This project is configured to use the 12MHz onboard clock to generate the baud rate, and as such I've selected 19200 baud (8/N/1).

A very very basic hardware flow control is implemented too. You should turn on CTS support as this will allow you to cut and paste code into the Woz Mon without the Apple 1 missing any bytes.

Helping

All PRs and suggestions happily accepted! Please any support us most welcome, and it would be good to have this as feature complete as possible with the real Apple1. I'd like to implement the cassette interface next with the basic electronics to talk to the headphone/mic jack of a mobile phone to upload and download recordings as a means to save programs.

But yes, help happily accepted!