mirror of
https://github.com/alangarf/apple-one.git
synced 2024-07-03 14:29:30 +00:00
f4a450f022
yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif build/apple1.blif" ../../../rtl/apple1.v build/pll.sv ../../../rtl/clock.v ../../../rtl/pwr_reset.v ../../../rtl/ram.v ../../../rtl/rom_wozmon.v ../../../rtl/rom_basic.v ../../../rtl/cpu/arlet_6502.v ../../../rtl/cpu/arlet/ALU.v ../../../rtl/cpu/arlet/cpu.v ../../../rtl/uart/uart.v ../../../rtl/uart/async_tx_rx.v ../../../rtl/vga/vga.v ../../../rtl/vga/vram.v ../../../rtl/vga/font_rom.v ../../../rtl/ps2keyboard/debounce.v ../../../rtl/ps2keyboard/ps2keyboard.v ../../../rtl/boards/upduino/apple1_up5k.v Warning: Replacing memory \AXYS with list of registers. See ../../../rtl/cpu/arlet/cpu.v:541 ERROR: Module `$paramod$e7b6f8008bbd43376eeb102f607da77667371076\apple1' referenced in module `apple1_top' in cell `my_apple1' does not have a port named 'clr_screen_btn'. Makefile:26: recipe for target 'build/apple1.blif' failed make: *** [build/apple1.blif] Error 1 |
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|---|---|---|
| .. | ||
| boards | ||
| cpu | ||
| led_and_key | ||
| ps2keyboard | ||
| uart | ||
| vga | ||
| apple1.v | ||
| clock.v | ||
| pwr_reset.v | ||
| ram.v | ||
| rom_basic.v | ||
| rom_wozmon.v | ||