Apple-1-HW/verilog-apple-one
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f4a450f022
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78 Commits

Author SHA1 Message Date
Steve White
f4a450f022 Remove invalid port clr_screen_btn (as I don't see any other references to it in the repo) 
yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif build/apple1.blif" ../../../rtl/apple1.v build/pll.sv ../../../rtl/clock.v ../../../rtl/pwr_reset.v ../../../rtl/ram.v ../../../rtl/rom_wozmon.v ../../../rtl/rom_basic.v ../../../rtl/cpu/arlet_6502.v ../../../rtl/cpu/arlet/ALU.v ../../../rtl/cpu/arlet/cpu.v ../../../rtl/uart/uart.v ../../../rtl/uart/async_tx_rx.v ../../../rtl/vga/vga.v ../../../rtl/vga/vram.v ../../../rtl/vga/font_rom.v ../../../rtl/ps2keyboard/debounce.v ../../../rtl/ps2keyboard/ps2keyboard.v ../../../rtl/boards/upduino/apple1_up5k.v
Warning: Replacing memory \AXYS with list of registers. See ../../../rtl/cpu/arlet/cpu.v:541
ERROR: Module `$paramod$e7b6f8008bbd43376eeb102f607da77667371076\apple1' referenced in module `apple1_top' in cell `my_apple1' does not have a port named 'clr_screen_btn'.
Makefile:26: recipe for target 'build/apple1.blif' failed
make: *** [build/apple1.blif] Error 1
 2018-05-05 12:59:52 -07:00
Steve White
59bbb91a8d Fix syntax error on apple1 declaration by adding missing closing parentheses 
yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif build/apple1.blif" ../../../rtl/apple1.v build/pll.sv ../../../rtl/clock.v ../../../rtl/pwr_reset.v ../../../rtl/ram.v ../../../rtl/rom_wozmon.v ../../../rtl/rom_basic.v ../../../rtl/cpu/arlet_6502.v ../../../rtl/cpu/arlet/ALU.v ../../../rtl/cpu/arlet/cpu.v ../../../rtl/uart/uart.v ../../../rtl/uart/async_tx_rx.v ../../../rtl/vga/vga.v ../../../rtl/vga/vram.v ../../../rtl/vga/font_rom.v ../../../rtl/ps2keyboard/debounce.v ../../../rtl/ps2keyboard/ps2keyboard.v ../../../rtl/boards/upduino/apple1_up5k.v
Warning: Replacing memory \AXYS with list of registers. See ../../../rtl/cpu/arlet/cpu.v:541
ERROR: Parser error in line ../../../rtl/boards/upduino/apple1_up5k.v:76: syntax error, unexpected TOK_ID, expecting ',' or ')'
Makefile:26: recipe for target 'build/apple1.blif' failed
make: *** [build/apple1.blif] Error 1
 2018-05-05 12:59:16 -07:00
Alan Garfield
86b75a0f2c Fixed new line and nul characters outside of WozMon 2018-04-03 22:14:47 +10:00
lawrie
bad3b601cc Added support for Blackice II 2018-03-31 10:14:15 +01:00
Niels Moseley
03ab2cc86e Fixed VGA scrolling bug 2018-02-19 00:46:34 +01:00
Niels Moseley
a0dae6f9a7 Fixed DE0 compilation problems 2018-02-19 00:29:30 +01:00
Alan Garfield
37c3898d9f added font and colour support at 0xC000-0xC002 2018-02-18 17:52:19 +11:00
Alan Garfield
48f6f7b78d removed vga font mode switch from software control 2018-02-16 14:38:18 +11:00
Alan Garfield
11bef736b4 Added toggle button on ice40hx8k breakout to switch from PS2 to Uart 2018-02-16 14:02:02 +11:00
Alan Garfield
b7f3f186f7 Added clear screen button 2018-02-16 13:43:43 +11:00
Alan Garfield
ae59891f2e fixed condition where uart_cts failed 2018-02-16 13:42:21 +11:00
Alan Garfield
526538a685 fixed param paths for yosys, may need more work 2018-02-14 15:27:36 +11:00
Alan Garfield
78b3c6f5c6 Updated the omilex board support 2018-02-14 11:38:26 +11:00
Alan Garfield
7ef0df07da
Merge pull request #11 from ironsteel/master 
Support for Olimex iCE40HX8K-EVB fpga board
 2018-02-14 11:14:12 +11:00
Niels Moseley
f525631760 S3E updates. 2018-02-12 16:47:52 +01:00
Niels Moseley
7a260619a5 * Added missing S3E top level verilog file. 
* Updated wozmon.hex to be ISE compliant.
 2018-02-12 16:24:16 +01:00
Olof Kindgren
3a330aeccb Remove non-existing port assignments 2018-02-12 15:19:40 +01:00
Olof Kindgren
2226afe669 Expose ROM/RAM files as top-level parameters 
This allows file names to be overridden at compile-time.

It also gets rid of the ifdef SIM in the verilog components
 2018-02-12 14:04:00 +01:00
Niels Moseley
9bf7d101cc Light maintenance. 2018-02-12 01:57:15 +01:00
Alan Garfield
b0d0d778f0 Fixed paths on upduino build 2018-02-12 09:35:44 +11:00
Alan Garfield
ffad5968b6 moved tinyfpga rtl to rtl/boards 2018-02-12 08:43:29 +11:00
Alan Garfield
a4f13a87fe updated ROM paths to handle new board/buildenv structure 2018-02-12 08:26:57 +11:00
Alan Garfield
3505ff20fc
Merge pull request #10 from al177/master 
Add UPDuino  (iCE40UP5K) support to apple-one
 2018-02-12 07:40:55 +11:00
Alan Garfield
585391414c Added PS2 interface to ice40hx8k board 2018-02-12 07:12:38 +11:00
Rangel Ivanov
3987dc22cb Initial port to olimex ice40hx8k with ice-40io 
ps2 will be added when someone donates a ps2 keyboard
 2018-02-11 13:28:37 +02:00
al177
ca44652a69 Add iCE40UP5K (UPDuino) support 2018-02-10 00:01:39 -06:00
Niels Moseley
7d36183103 some more ps/2 code cleanup 2018-02-09 00:57:45 +01:00
Niels Moseley
88bb7167f8 PS/2 code cleanup 2018-02-09 00:01:30 +01:00
Niels Moseley
894c50ff4e Added debounced PS/2 keyboard interface and A1 top-level selection between keyboard and UART RX 2018-02-08 23:47:09 +01:00
Niels Moseley
14743ed0de Updated PS/2 keyboard processing in an attempt to make it more stable -- still needs work 2018-02-08 19:02:46 +01:00
Niels Moseley
237d35491a Fixed Quartus VGA reversal bug/feature. Removed bit reversing logic and created bit-reversed font rom hex file 2018-02-08 17:51:30 +01:00
Niels Moseley
f76134bcf1 Added VGA font rom in hex to (hopefully) solve the endianess problems between Yosys/Quartus 2018-02-07 19:22:00 +01:00
Niels Moseley
dd2c480675 Fixed reg/wire problems for Quartus. 2018-02-07 17:12:27 +01:00
Niels Moseley
3ae84f6bc0 Merge branch 'master' of https://github.com/alangarf/apple-one 2018-02-07 17:05:24 +01:00
Niels Moseley
2ae6d8a867 DE0 2018-02-07 17:04:40 +01:00
Alan Garfield
9371303789 Fixed minor verilator complaint 2018-02-08 01:06:35 +11:00
Alan Garfield
fdc93fb0d2 Hardware scrolling seems to be working! 2018-02-08 00:40:43 +11:00
Niels Moseley
c1942d5d14 new VGA 2018-02-05 14:43:46 +01:00
Alan Garfield
6f7812f51d Added defines to choose display mode of fonts 2018-02-06 00:35:30 +11:00
Alan Garfield
25aff9cdc3 VGA module works. Still no hardware scrolling though 2018-02-06 00:29:56 +11:00
Alan Garfield
7b3c65b8d9 Fixed issue with yosys compile 2018-02-05 00:24:12 +11:00
Alan Garfield
20919fa726 wip of the pipeline VGA module. stupid yosys bug, but testbench looks ok 2018-02-05 00:12:06 +11:00
Alan Garfield
2432225d01 Initial VGA working with the apple one output. YAY! 2018-01-31 00:48:47 +11:00
Alan Garfield
451bff1592 fiddled the vga module a little 2018-01-30 00:19:21 +11:00
Alan Garfield
4fef9bc10b Initial VGA module, still WIP, just outputs fixed VRAM 2018-01-29 22:53:16 +11:00
Alan Garfield
b2ebc23e3a added license headers and tidied up 2018-01-29 22:15:21 +11:00
Alan Garfield
119d077e1a Fixed differences for iceube2 and yosys 2018-01-29 21:36:32 +11:00
Alan Garfield
474cabbab0 Made core neater and trying to get naming better 2018-01-29 21:00:38 +11:00
Alan Garfield
2717184e71 Added yosys support again, yay for FOSS! 2018-01-29 17:45:01 +11:00
Niels Moseley
586b006e88 PS/2 keyboard seems to be working including the shift key. It needs debouncing, however 2018-01-29 00:39:24 +01:00