Apple-2-HW
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GR8RAM
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This commit is contained in:
Zane Kaminski 2021-04-03 03:44:42 -04:00
parent 763861e444
commit fc2e875ac2
71 changed files with 3880 additions and 28921 deletions
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0
Documentation/Flash Map → Documentation/
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187
GR8RAM-cache.lib
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@ -1,59 +1,6 @@
EESchema-LIBRARY Version 2.4 EESchema-LIBRARY Version 2.4
#encoding utf-8 #encoding utf-8
# #
# Comparator_LM393
#
DEF Comparator_LM393 U 0 5 Y Y 3 L N
F0 "U" 150 150 50 H V C CNN
F1 "Comparator_LM393" 250 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS LM393 LMV393 MCP6562 MCP6567
$FPLIST
SOIC*3.9x4.9mm*P1.27mm*
DIP*W7.62mm*
MSOP*3x3mm*P0.65mm*
VSSOP*2.3x2mm*P0.5mm*
$ENDFPLIST
DRAW
P 4 1 1 10 -200 200 200 0 -200 -200 -200 200 f
P 4 2 1 10 -200 200 200 0 -200 -200 -200 200 f
X ~ 1 300 0 100 L 50 50 1 1 C
X - 2 -300 -100 100 R 50 50 1 1 I
X + 3 -300 100 100 R 50 50 1 1 I
X + 5 -300 100 100 R 50 50 2 1 I
X - 6 -300 -100 100 R 50 50 2 1 I
X ~ 7 300 0 100 L 50 50 2 1 C
X V- 4 -100 -300 150 U 50 50 3 1 W
X V+ 8 -100 300 150 D 50 50 3 1 W
ENDDRAW
ENDDEF
#
# Connector_Barrel_Jack_Switch
#
DEF Connector_Barrel_Jack_Switch J 0 20 Y N 1 F N
F0 "J" 0 210 50 H V C CNN
F1 "Connector_Barrel_Jack_Switch" 0 -200 50 H V C CNN
F2 "" 50 -40 50 H I C CNN
F3 "" 50 -40 50 H I C CNN
$FPLIST
BarrelJack*
$ENDFPLIST
DRAW
A -130 100 25 901 -901 0 1 10 F -130 125 -130 75
A -130 100 25 901 -901 0 1 10 N -130 125 -130 75
S -200 150 200 -150 0 1 10 f
S 145 125 -130 75 0 1 10 F
P 2 0 1 10 50 -90 75 -65 N
P 2 0 1 10 200 100 150 100 N
P 4 0 1 10 200 0 50 0 50 -90 25 -65 N
P 6 0 1 10 -150 -100 -100 -100 -50 -50 0 -100 100 -100 200 -100 N
X ~ 1 300 100 100 L 50 50 1 1 P
X ~ 2 300 -100 100 L 50 50 1 1 P
X ~ 3 300 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x05_Odd_Even # Connector_Generic_Conn_02x05_Odd_Even
# #
DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N
@ -222,93 +169,6 @@ X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# Device_D_Schottky_Small_ALT
#
DEF Device_D_Schottky_Small_ALT D 0 10 N N 1 F N
F0 "D" -50 80 50 H V L CNN
F1 "Device_D_Schottky_Small_ALT" -280 -80 50 H V L CNN
F2 "" 0 0 50 V I C CNN
F3 "" 0 0 50 V I C CNN
$FPLIST
TO-???*
*_Diode_*
*SingleDiode*
D_*
$ENDFPLIST
DRAW
P 2 0 1 0 -30 -40 -30 40 N
P 2 0 1 0 -30 0 30 0 N
P 3 0 1 0 -30 -40 -20 -40 -20 -30 N
P 3 0 1 0 -30 40 -40 40 -40 30 N
P 4 0 1 0 30 -40 -30 0 30 40 30 -40 F
X K 1 -100 0 70 R 50 50 1 1 P
X A 2 100 0 70 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_D_Zener_Small_ALT
#
DEF Device_D_Zener_Small_ALT D 0 10 N N 1 F N
F0 "D" 0 90 50 H V C CNN
F1 "Device_D_Zener_Small_ALT" 0 -90 50 H V C CNN
F2 "" 0 0 50 V I C CNN
F3 "" 0 0 50 V I C CNN
$FPLIST
TO-???*
*_Diode_*
*SingleDiode*
D_*
$ENDFPLIST
DRAW
P 2 0 1 0 30 0 -30 0 N
P 3 0 1 0 -10 40 -30 40 -30 -40 N
P 4 0 1 0 30 40 -30 0 30 -40 30 40 F
X K 1 -100 0 70 R 50 50 1 1 P
X A 2 100 0 70 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Ferrite_Bead_Small
#
DEF Device_Ferrite_Bead_Small FB 0 0 N Y 1 F N
F0 "FB" 75 50 50 H V L CNN
F1 "Device_Ferrite_Bead_Small" 75 -50 50 H V L CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Inductor_*
L_*
*Ferrite*
$ENDFPLIST
DRAW
P 2 0 1 0 0 -50 0 -31 N
P 2 0 1 0 0 35 0 51 N
P 5 0 1 0 -72 11 -44 59 72 -8 44 -56 -72 11 N
X ~ 1 0 100 50 D 50 50 1 1 P
X ~ 2 0 -100 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Polyfuse_Small
#
DEF Device_Polyfuse_Small F 0 0 N Y 1 F N
F0 "F" -75 0 50 V V C CNN
F1 "Device_Polyfuse_Small" 75 0 50 V V C CNN
F2 "" 50 -200 50 H I L CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
*polyfuse*
*PTC*
$ENDFPLIST
DRAW
S -20 50 20 -50 0 1 0 N
P 2 0 1 0 0 100 0 -100 N
P 4 0 1 0 -40 50 -40 30 40 -30 40 -50 N
X ~ 1 0 100 25 D 50 50 1 1 P
X ~ 2 0 -100 25 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Pack04 # Device_R_Pack04
# #
DEF Device_R_Pack04 RN 0 0 Y N 1 F N DEF Device_R_Pack04 RN 0 0 Y N 1 F N
@ -688,38 +548,6 @@ X 1 1 0 -100 100 U 50 50 1 1 I
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# Transistor_FET_AO3401A
#
DEF Transistor_FET_AO3401A Q 0 20 Y N 1 F N
F0 "Q" 200 75 50 H V L CNN
F1 "Transistor_FET_AO3401A" 200 0 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23" 200 -75 50 H I L CIN
F3 "" 0 0 50 H I L CNN
ALIAS VP0610T BSS84 NTR2101P BSS83P Si2319CDS IRLML6402 DMG2301L AO3401A IRLML9301 IRLML5203 Si2371EDS
$FPLIST
SOT?23*
$ENDFPLIST
DRAW
C 65 0 110 0 1 10 N
C 100 -70 10 0 1 0 F
C 100 70 10 0 1 0 F
P 2 0 1 0 10 0 -100 0 N
P 2 0 1 10 10 75 10 -75 N
P 2 0 1 10 30 -50 30 -90 N
P 2 0 1 10 30 20 30 -20 N
P 2 0 1 10 30 90 30 50 N
P 2 0 1 0 100 100 100 70 N
P 3 0 1 0 100 -100 100 0 30 0 N
P 4 0 1 0 30 70 130 70 130 -70 30 -70 N
P 4 0 1 0 90 0 50 15 50 -15 90 0 F
P 4 0 1 0 110 -20 115 -15 145 -15 150 -10 N
P 4 0 1 0 130 -15 115 10 145 10 130 -15 N
X G 1 -200 0 100 R 50 50 1 1 I
X S 2 100 -200 100 U 50 50 1 1 P
X D 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+12V # power_+12V
# #
DEF power_+12V #PWR 0 0 Y Y 1 F P DEF power_+12V #PWR 0 0 Y Y 1 F P
@ -805,19 +633,4 @@ X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# power_VBUS
#
DEF power_VBUS #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_VBUS" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VBUS 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library #End Library

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GR8RAM.kicad_pcb
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GR8RAM.sch
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12
cpld/GR8RAM.qsf
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@ -51,18 +51,24 @@ set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name QIP_FILE UFM.qip
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name SAFE_STATE_MACHINE ON set_global_assignment -name SAFE_STATE_MACHINE OFF
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS
set_global_assignment -name AUTO_RESOURCE_SHARING ON set_global_assignment -name AUTO_RESOURCE_SHARING ON
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0 set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0 set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS"
set_global_assignment -name SYNTHESIS_SEED 123
set_global_assignment -name SEED 235
set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII "MINIMIZE AREA"
set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF
set_global_assignment -name VERILOG_FILE GR8RAM.v

BIN
cpld/GR8RAM.qws
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840
cpld/GR8RAM.v
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@ -1,126 +1,132 @@
module GR8RAM(C25M, PHI0, nRES, nRESout, module GR8RAM(C25M, PHI0, nRES, nRESout,
nIOSEL, nDEVSEL, nIOSTRB, nIOSEL, nDEVSEL, nIOSTRB,
RA, nWE, RAdir, RD, RDdir, SetRF, SetLim8M,
RA, nWE, RD, RDdir,
SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD, SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
nFCS, FCK, MISO, MOSI); nFCS, FCK, MISO, MOSI);
/* Clock signals */ /* Clock signals */
/* Outputs: C25M, PHI0r1, PHI0r2, */
input C25M, PHI0; input C25M, PHI0;
reg PHI0r0, PHI0r1, PHI0r2; reg PHI0r1, PHI0r2;
always @(negedge C25M) begin PHI0r0 <= PHI0; end always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
always @(posedge C25M) begin PHI0r1 <= PHI0r0; PHI0r2 <= PHI0r1; end
/* Reset/brown-out detect synchronized inputs */ /* Reset/brown-out detect synchronized inputs */
/* Outputs: nRESr */
input nRES; input nRES;
reg nRESr0, nRESr; reg nRESr0, nRESr;
always @(negedge C25M) begin nRESr0 <= nRES; end always @(posedge C25M) begin nRESr0 <= nRES; nRESr <= nRESr0; end
always @(posedge C25M) begin nRESr <= nRESr0; end
/* Long state counter: counts from 0 to $3FFFF */ /* Long state counter: counts from 0 to $3FFF */
/* Outputs: LS */ reg [13:0] LS = 0;
reg [17:0] LS = 0; always @(posedge C25M) begin if (PS==15) LS <= LS+1; end
always @(posedge C25M) begin LS <= LS+1; end
/* Init state */ /* Init state */
output reg nRESout = 0; output reg nRESout = 0;
reg [2:0] IS = 0;
always @(posedge C25M) begin always @(posedge C25M) begin
if (LS[17:0]==18'h30002) begin if (IS==7) nRESout <= 1;
nRESout <= 1'b1; else if (PS==15) begin
if (LS==14'h1FCE) IS <= 1; // PC all + load mode
else if (LS==14'h1FCF) IS <= 4; // AREF pause, SPI select
else if (LS==14'h1FFA) IS <= 5; // SPI flash command
else if (LS==14'h1FFF) IS <= 6; // Flash load driver
else if (LS==14'h3FFF) IS <= 7; // Operating mode
end end
end end
/* Apple IO area select signals */ /* Apple IO area select signals */
/* Outputs: DEVSELr */
input nIOSEL, nDEVSEL, nIOSTRB; input nIOSEL, nDEVSEL, nIOSTRB;
reg DEVSELr0, DEVSELr;
reg IOSELr0, IOSELr;
reg IOSTRBr0, IOSTRBr;
always @(negedge C25M) begin
DEVSELr0 <= ~nDEVSEL; IOSELr0 <= ~nIOSEL; IOSTRBr0 <= ~nIOSTRB;
end
always @(posedge C25M) begin
DEVSELr <= DEVSELr0; IOSELr <= IOSELr0; IOSTRBr <= IOSTRBr0;
end
/* Apple address bus */ /* Apple address bus */
/* Outputs: RACr, RAcur, nWEcur, RAdir */ input [15:0] RA; input nWE;
input [15:0] RA;
input nWE;
reg RACr;
reg [11:0] RAcur; reg nWEcur;
output RAdir = 1;
always @(posedge C25M) begin
if (PSStart) begin
RACr <= RA[15:12]==4'hC;
RAcur[11:0] <= RA[11:0];
nWEcur <= nWE;
end
end
/* Apple select signals */ /* Apple select signals */
/* Outputs: ROMSpecRD, RAMSpecSEL, RAMSpecRD, RAMSpecWR */ wire ROMSpecSEL = RA[15:12]==4'hC && RA[11:8]!=4'h0;
wire ROMSpecRD = RACr && RAcur[11:8]!=4'h0 && nWEcur; wire BankSpecSEL = RA[3:0]==4'hF;
wire RAMSpecSEL = RACr && RAcur[11:8]==4'h0 && RAcur[7] && RAcur[3:0]==4'h3; wire RAMSpecSEL = RA[15:12]==4'hC && RA[11:8]==4'h0 && RA[7] && RA[3:0]==4'h3 && REGEN;
wire RAMSpecRD = RAMSpecSEL && nWEcur; wire AddrHSpecSEL = RA[3:0]==4'h2;
wire RAMSpecWR = RAMSpecSEL && ~nWEcur; wire AddrMSpecSEL = RA[3:0]==4'h1;
wire AddrLSpecSEL = RA[3:0]==4'h0;
reg ROMSpecSELr, RAMSpecSELr, nWEr;
wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL;
wire RAMSEL = ~nDEVSEL && RAMSpecSELr;
wire RAMWR = RAMSEL && ~nWEr;
wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL;
wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL;
wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL;
always @(posedge C25M) begin
if (PSStart) begin
ROMSpecSELr <= ROMSpecSEL;
RAMSpecSELr <= RAMSpecSEL;
nWEr <= nWE;
end
end
/* IOROMEN and REGEN control */ /* IOROMEN and REGEN control */
reg IOROMEN = 0; reg IOROMEN = 0;
reg REGEN = 0; reg REGEN = 0;
always @(posedge C25M) begin always @(posedge C25M, negedge nRESr) begin
if (~nRESr) begin if (~nRESr) begin
IOROMEN <= 0; IOROMEN <= 0;
REGEN <= 0; REGEN <= 0;
end else if (PS==7 && IOSTRBr && RAcur[10:0]==11'h7FF) begin end else if (PS==8 && ~nIOSTRB && RA[10:0]==11'h7FF) begin
IOROMEN <= 0; IOROMEN <= 0;
end else if (PS==7 && IOSELr) begin end else if (PS==8 && ~nIOSEL) begin
IOROMEN <= 1; IOROMEN <= 1;
REGEN <= 1; REGEN <= 1;
end end
end end
/* Apple data bus */ /* Apple data bus */
inout [7:0] RD = RDdir ? 8'bZ : RDout[7:0]; inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
reg [7:0] RDout; reg [7:0] RDD;
output RDdir = ~(PHI0 && PHI0r2 && nWE && output RDdir = ~(PHI0r2 && nWE && PHI0 &&
((~nDEVSEL && REGEN) || ~nIOSEL || (~nIOSTRB && IOROMEN))); (~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN)));
/* Slinky address registers */ /* Slinky address registers */
reg [23:0] Addr = 0; reg [23:0] Addr = 0;
wire AddrHSpecSEL = RAcur[3:0]==4'h2; reg AddrIncL = 0;
wire AddrMSpecSEL = RAcur[3:0]==4'h1; reg AddrIncM = 0;
wire AddrLSpecSEL = RAcur[3:0]==4'h0; reg AddrIncH = 0;
always @(posedge C25M) begin always @(posedge C25M, negedge nRESr) begin
if (~nRESr) begin if (~nRESr) begin
Addr[23:0] <= 24'h000000; Addr[23:0] <= 24'h000000;
end else if (PS==7 && REGEN && DEVSELr) begin AddrIncL <= 0;
if (RAMSpecSEL) begin AddrIncM <= 0;
Addr[23:0] <= Addr[23:0]+1; AddrIncH <= 0;
end else if (AddrLSpecSEL && ~nWEcur) begin end else begin
if (PS==8 && RAMSEL) AddrIncL <= 1;
else AddrIncL <= 0;
if (PS==8 && AddrLSEL && ~nWEr) begin
Addr[7:0] <= RD[7:0]; Addr[7:0] <= RD[7:0];
if (~RD[7] && Addr[7]) begin AddrIncM <= Addr[7] && ~RD[7];
Addr[23:8] <= Addr[23:8]+1; end else if (AddrIncL) begin
end Addr[7:0] <= Addr[7:0]+1;
end else if (AddrMSpecSEL && ~nWEcur) begin AddrIncM <= Addr[7:0]==8'hFF;
end else AddrIncM <= 0;
if (PS==8 && AddrMSEL && ~nWEr) begin
Addr[15:8] <= RD[7:0]; Addr[15:8] <= RD[7:0];
if (~RD[7] && Addr[15]) begin AddrIncH <= Addr[15] && ~RD[7];
Addr[23:16] <= Addr[23:16]+1; end else if (AddrIncM) begin
end Addr[15:8] <= Addr[15:8]+1;
end else if (AddrHSpecSEL && ~nWEcur) begin AddrIncH <= Addr[15:8]==8'hFF;
end else AddrIncH <= 0;
if (PS==8 && AddrHSEL && ~nWEr) begin
Addr[23:16] <= RD[7:0]; Addr[23:16] <= RD[7:0];
end else if (AddrIncH) begin
Addr[23:16] <= Addr[23:16]+1;
end end
end end
end end
/* ROM bank register */ /* ROM bank register */
reg [1:0] Bank = 0; reg Bank = 0;
wire BankSpecSEL = RAcur[3:0]==4'hF; always @(posedge C25M, negedge nRESr) begin
always @(posedge C25M) begin
if (~nRESr) Bank <= 0; if (~nRESr) Bank <= 0;
else if (PS==7 && DEVSELr && BankSpecSEL && ~nWEcur) begin else if (PS==8 && BankSEL && ~nWEr) begin
Bank[1:0] <= RD[1:0]; Bank <= RD[0];
end end
end end
@ -128,384 +134,414 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
output nFCS = ~FCS; output nFCS = ~FCS;
reg FCS = 0; reg FCS = 0;
output reg FCK = 0; output reg FCK = 0;
reg FCKEN = 0; inout MOSI = MOSIOE ? MOSIout : 1'bZ;
output MOSI = MOSIOE ? MOSIout : 1'bZ;
reg MOSIOE = 0; reg MOSIOE = 0;
reg MOSIout; reg MOSIout;
input MISO; input MISO;
/* SPI flash control */
always @(posedge C25M) begin always @(posedge C25M) begin
FCK <= ~nRESout && FCKEN && LS[0]; case (PS[3:0])
end 0: begin // NOP CKE
always @(posedge C25M) begin FCK <= 1'b1;
if (~nRESout) begin end 1: begin // ACT
// Flash /CS enabled from init states $0FFB0 to $2FFFF FCK <= ~(IS==5 || IS==6);
if (LS[17:0]==18'h0FF90) FCS <= 1'b0; end 2: begin // RD
else if (LS[17:0]==18'h0FFA0) FCS <= 1'b1; FCK <= 1'b1;
else if (LS[17:0]==18'h30000) FCS <= 1'b0; end 3: begin // NOP CKE
FCK <= ~(IS==5 || IS==6);
// Pulse clock from init states $0FFC0 to $2FFFF end 4: begin // NOP CKE
if (LS[17:0]==18'h0FF90) FCKEN <= 1'b0; FCK <= 1'b1;
else if (LS[17:0]==18'h0FFB0) FCKEN <= 1'b1; end 5: begin // NOP CKE
else if (LS[17:0]==18'h30000) FCKEN <= 1'b0; FCK <= ~(IS==5 || IS==6);
end 6: begin // NOP CKE
// Send command $3B (read) (MSB first) FCK <= 1'b1;
if (LS[17:0]==18'h0FFB0 || LS[17:0]==18'h0FFB1) MOSIout <= 0; end 7: begin // NOP CKE
else if (LS[17:0]==18'h0FFB2 || LS[17:0]==18'h0FFB3) MOSIout <= 0; FCK <= ~(IS==5 || IS==6);
else if (LS[17:0]==18'h0FFB4 || LS[17:0]==18'h0FFB5) MOSIout <= 1; end 8: begin // WR AP
else if (LS[17:0]==18'h0FFB6 || LS[17:0]==18'h0FFB7) MOSIout <= 1; FCK <= 1'b1;
else if (LS[17:0]==18'h0FFB8 || LS[17:0]==18'h0FFB9) MOSIout <= 1; end 9: begin // NOP CKE
else if (LS[17:0]==18'h0FFBA || LS[17:0]==18'h0FFBB) MOSIout <= 0; FCK <= ~(IS==5);
else if (LS[17:0]==18'h0FFBC || LS[17:0]==18'h0FFBD) MOSIout <= 1; end 10: begin // PC all
else if (LS[17:0]==18'h0FFBE || LS[17:0]==18'h0FFBF) MOSIout <= 1; FCK <= 1'b1;
// Send 24-bit address (MSB first) end 11: begin // AREF
else if (LS[17:0]==18'h0FFC0 || LS[17:0]==18'h0FFC1) MOSIout <= 0; FCK <= ~(IS==5);
else if (LS[17:0]==18'h0FFC2 || LS[17:0]==18'h0FFC3) MOSIout <= 0; end 12: begin // NOP CKE
else if (LS[17:0]==18'h0FFC4 || LS[17:0]==18'h0FFC5) MOSIout <= 0; FCK <= 1'b1;
else if (LS[17:0]==18'h0FFC6 || LS[17:0]==18'h0FFC7) MOSIout <= SetFW; end 13: begin // NOP CKE
else if (LS[17:0]==18'h0FFC8 || LS[17:0]==18'h0FFC9) MOSIout <= 0; FCK <= ~(IS==5);
else if (LS[17:0]==18'h0FFCA || LS[17:0]==18'h0FFCB) MOSIout <= 0; end 14: begin // NOP CKE
else if (LS[17:0]==18'h0FFCC || LS[17:0]==18'h0FFCD) MOSIout <= 0; FCK <= 1'b1;
else if (LS[17:0]==18'h0FFCE || LS[17:0]==18'h0FFCF) MOSIout <= 0; end 15: begin // NOP CKE
else if (LS[17:0]==18'h0FFD0 || LS[17:0]==18'h0FFD1) MOSIout <= 0; FCK <= ~(IS==5);
else if (LS[17:0]==18'h0FFD2 || LS[17:0]==18'h0FFD3) MOSIout <= 0; end
else if (LS[17:0]==18'h0FFD4 || LS[17:0]==18'h0FFD5) MOSIout <= 0; endcase
else if (LS[17:0]==18'h0FFD6 || LS[17:0]==18'h0FFD7) MOSIout <= 0; FCS <= IS==5 || IS==6;
else if (LS[17:0]==18'h0FFD8 || LS[17:0]==18'h0FFD9) MOSIout <= 0; MOSIOE <= IS==5;
else if (LS[17:0]==18'h0FFDA || LS[17:0]==18'h0FFDB) MOSIout <= 0;
else if (LS[17:0]==18'h0FFDC || LS[17:0]==18'h0FFDD) MOSIout <= 0;
else if (LS[17:0]==18'h0FFDE || LS[17:0]==18'h0FFDF) MOSIout <= 0;
else if (LS[17:0]==18'h0FFE0 || LS[17:0]==18'h0FFE1) MOSIout <= 0;
else if (LS[17:0]==18'h0FFE2 || LS[17:0]==18'h0FFE3) MOSIout <= 0;
else if (LS[17:0]==18'h0FFE4 || LS[17:0]==18'h0FFE5) MOSIout <= 0;
else if (LS[17:0]==18'h0FFE6 || LS[17:0]==18'h0FFE7) MOSIout <= 0;
else if (LS[17:0]==18'h0FFE8 || LS[17:0]==18'h0FFE9) MOSIout <= 0;
else if (LS[17:0]==18'h0FFEA || LS[17:0]==18'h0FFEB) MOSIout <= 0;
else if (LS[17:0]==18'h0FFEC || LS[17:0]==18'h0FFED) MOSIout <= 0;
else if (LS[17:0]==18'h0FFEE || LS[17:0]==18'h0FFEF) MOSIout <= 0;
else MOSIout <= 0;
if (LS[17:0]==18'h0FF90) MOSIOE <= 1'b1;
else if (LS[17:0]==18'h0FFF0) MOSIOE <= 1'b0;
end else begin
//TODO: control these with Apple II
FCS <= 0;
FCKEN <= 0;
MOSIout <= 0;
MOSIOE <= 0;
end
end end
/* UFM control */
reg ARCLK = 0; // UFM address register clock
reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
reg DRCLK = 0; // UFM data register clock
reg DRDIn = 0; // UFM data register input
reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
wire DRDOut; // UFM data output
// UFM oscillator always enabled
wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
.arclk (ARCLK),
.ardin (1'b0),
.arshft (ARShift),
.drclk (DRCLK),
.drdin (DRDIn),
.drshft (DRShift),
.erase (UFMErase),
.oscena (1'b1),
.program (UFMProgram),
.busy (UFMB),
.drdout (DRDOut),
.osc (UFMOsc),
.rtpbusy (RTPB));
reg UFMBr0 = 0; // UFMBusy registered to sync with C25M
reg UFMBr = 0; // UFMBusy registered to sync with C25M
reg RTPBr0 = 0; // RTPBusy registered to sync with C25M
reg RTPBr = 0; // RTPBusy registered to sync with C25M
always @(negedge C25M) begin UFMBr0 <= UFMB; RTPBr0 <= RTPB; end
always @(posedge C25M) begin UFMBr <= UFMBr0; RTPBr <= RTPBr0; end
reg [1:0] SS = 0;
reg SetFW;
reg SetLim8M;
always @(posedge C25M) begin always @(posedge C25M) begin
if (SS[1:0]!=2'b11) begin case (PS[3:0])
if (SS[1:0]==2'b10 && LS[3:0]==4'h2 && DRDOut) SS[1:0] <= 2'b11; 1, 2: begin
else if (LS[15:0]==16'h0FB0) SS[1:0] <= 2'b01; case (LS[2:0])
else if (LS[15:0]==16'h0FFF) SS[1:0] <= 2'b10; 3'h3: MOSIout <= 1'b0; // Command bit 7
else if (LS[15:0]==16'h1FFF) SS[1:0] <= 2'b11; 3'h4: MOSIout <= SetRF; // Address bit 23
end 3'h5: MOSIout <= 1'b0; // Address bit 15
end 3'h6: MOSIout <= 1'b0; // Address bit 7
always @(posedge C25M) begin default MOSIout <= 1'b0;
if (SS[1:0]==2'b00 /* LS[15:0]<=16'h0FB0 */) begin endcase
ARCLK <= 0; end 3, 4: begin
ARShift <= 1; case (LS[2:0])
DRCLK <= 0; 3'h3: MOSIout <= 1'b1; // Command bit 6
DRShift <= 0; 3'h4: MOSIout <= 1'b0; // Address bit 22
end else if (SS[1:0]==2'b01 /* LS[15:0]<=16'h0FFF */) begin 3'h5: MOSIout <= 1'b0; // Address bit 14
ARCLK <= ~LS[1]; 3'h6: MOSIout <= 1'b0; // Address bit 6
ARShift <= 1; default MOSIout <= 1'b0;
DRCLK <= 0; endcase
DRShift <= 0; end 5, 6: begin
SetFW <= 1'b1; case (LS[2:0])
SetLim8M <= 1'b1; 3'h3: MOSIout <= 1'b1; // Command bit 5
end else if (SS[1:0]==2'b10 /* LS[15:0]<=16'h1FFF */) begin 3'h4: MOSIout <= 1'b0; // Address bit 21
case (LS[3:1]) 3'h5: MOSIout <= 1'b0; // Address bit 13
3'h0: begin 3'h6: MOSIout <= 1'b0; // Address bit 5
ARCLK <= 0; default MOSIout <= 1'b0;
ARShift <= 0; endcase
DRCLK <= 1; end 7, 8: begin
DRShift <= 0; case (LS[2:0])
end 3'h1: begin 3'h3: MOSIout <= 1'b0; // Command bit 4
ARCLK <= 0; 3'h4: MOSIout <= 1'b0; // Address bit 20
ARShift <= 0; 3'h5: MOSIout <= 1'b0; // Address bit 12
DRCLK <= 0; 3'h6: MOSIout <= 1'b0; // Address bit 4
DRShift <= 1; default MOSIout <= 1'b0;
end 3'h2: begin endcase
ARCLK <= 0; end 9, 10: begin
ARShift <= 0; case (LS[2:0])
DRCLK <= 1; 3'h3: MOSIout <= 1'b1; // Command bit 3
DRShift <= 1; 3'h4: MOSIout <= 1'b0; // Address bit 19
end 3'h3: begin 3'h5: MOSIout <= 1'b0; // Address bit 11
ARCLK <= 0; 3'h6: MOSIout <= 1'b0; // Address bit 3
ARShift <= 0; default MOSIout <= 1'b0;
DRCLK <= 0; endcase
DRShift <= 1; end 11, 12: begin
end 3'h4: begin case (LS[2:0])
ARCLK <= 0; 3'h3: MOSIout <= 1'b0; // Command bit 2
ARShift <= 0; 3'h4: MOSIout <= 1'b0; // Address bit 18
DRCLK <= 1; 3'h5: MOSIout <= 1'b0; // Address bit 10
DRShift <= 1; 3'h6: MOSIout <= 1'b0; // Address bit 2
if (LS[3:0]==4'h4) SetFW <= DRDOut; default MOSIout <= 1'b0;
end 3'h5: begin endcase
ARCLK <= 0; end 13, 14: begin
ARShift <= 0; case (LS[2:0])
DRCLK <= 0; 3'h3: MOSIout <= 1'b1; // Command bit 1
DRShift <= 1; 3'h4: MOSIout <= 1'b0; // Address bit 16
end 3'h6: begin 3'h5: MOSIout <= 1'b0; // Address bit 9
ARCLK <= 1; 3'h6: MOSIout <= 1'b0; // Address bit 1
ARShift <= 0; default MOSIout <= 1'b0;
DRCLK <= 0; endcase
DRShift <= 1; end 15, 0: begin
if (LS[3:0]==4'h6) SetLim8M <= DRDOut; case (LS[2:0])
end 3'h7: begin 3'h3: MOSIout <= 1'b1; // Command bit 0
ARCLK <= 0; 3'h4: MOSIout <= 1'b0; // Address bit 15
ARShift <= 0; 3'h5: MOSIout <= 1'b0; // Address bit 7
DRCLK <= 0; 3'h6: MOSIout <= 1'b0; // Address bit 0
DRShift <= 0; default MOSIout <= 1'b0;
end endcase
endcase end
DRDIn <= 0; endcase
end else begin
ARCLK <= 0;
ARShift <= 0;
DRShift <= 1;
DRCLK <= 0;
DRDIn <= 0;
end
end end
input SetRF;
input SetLim8M;
/* SDRAM data bus */ /* SDRAM data bus */
inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ; inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
reg [7:0] WRD; reg [7:0] WRD;
reg SDOE = 0; reg SDOE = 0;
always @(posedge C25M) begin always @(posedge C25M) begin
// Shift { MISO, MOSI } in when InitActv. When ready, synchronize RD case (PS[3:0])
if (~nRESout && LS[1]) WRD[7:0] <= { MISO, MOSI, WRD[5:0] }; 0: begin // NOP CKE
else if (PS==8) WRD[7:0] <= RD[7:0]; if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
// Output data on SDRAM data bus only during init and when writing else WRD[7:0] <= RD[7:0];
SDOE <= ~nRESout || (RAMSpecWR && PS==8); end 1: begin // ACT
end 2: begin // RD
if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
else WRD[7:0] <= RD[7:0];
end 3: begin // NOP CKE
end 4: begin // NOP CKE
if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
else if (AddrHSpecSEL && SetRF) RDD[7:0] <= Addr[23:16];
else if (AddrHSpecSEL && ~SetRF) RDD[7:0] <= {4'hF, Addr[19:16]};
else RDD[7:0] <= SD[7:0];
if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
else WRD[7:0] <= RD[7:0];
end 5: begin // NOP CKE
end 6: begin // NOP CKE
if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
else WRD[7:0] <= RD[7:0];
end 7: begin // NOP CKE
end 8: begin // WR AP
if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
else WRD[7:0] <= RD[7:0];
end 9: begin // NOP CKE
end 10: begin // PC all
if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
else WRD[7:0] <= RD[7:0];
end 11: begin // AREF
end 12: begin // NOP CKE
if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
else WRD[7:0] <= RD[7:0];
end 13: begin // NOP CKE
end 14: begin // NOP CKE
if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
else WRD[7:0] <= RD[7:0];
end 15: begin // NOP CKE
end
endcase
end end
reg [2:0] PS = 0; reg [3:0] PS = 0;
wire PSStart = nRESr && PS==0 && PHI0r1 && ~PHI0r2; wire PSStart = PS==0 && PHI0r1 && ~PHI0r2;
always @(posedge C25M) begin always @(posedge C25M) begin
if (PSStart) PS <= 1; if (PSStart) PS <= 1;
else if (PS==0) PS <= 0; else if (PS==0) PS <= 0;
else PS <= PS+1; else PS <= PS+1;
end end
/* Refresh state */
reg RefReqd = 0;
reg RefReady = 0;
always @(posedge C25M) begin
if (LS[6:0]==7'h00) RefReqd <= 1; // Reset RefDone every 128 C25M cycles (5.12 us)
else if (PS==0 && ~RefReqd) RefReqd <= 0;
end
/* SDRAM address/command */ /* SDRAM address/command */
output [1:0] SBA; assign SBA[1:0] =
Amux[2:1]==2'h0 ? 2'b00 : // mode register / "all"
Amux[2:1]==2'h1 ? 2'b00 : // FIXME: init row / col
Amux[2:1]==2'h2 ? 2'b10 : // ROM row / col
/* 2'h3 */ { 1'b0, Addr[23] & SetFW & ~SetLim8M }; // RAM row/col
output [12:0] SA;
assign SA[12] = Amux[2:0]==3'h6 && Addr[22] && SetFW;
/*assign SA[12:0] =
Amux[2:0]==3'h0 ? 13'b0001000100000 : // mode register
Amux[2:0]==3'h1 ? 13'b0011000100000 : // "all"
Amux[2:0]==3'h2 ? { 9'b001100010, LS[16:13] } : // init row
Amux[2:0]==3'h3 ? { 4'b0011, LS[12:4] } : // init col
Amux[2:0]==3'h4 ? { 9'b000000000, Bank[1:0], RAcur[11:10] } : // ROM row
Amux[2:0]==3'h5 ? { 4'b0000, RAcur[9:1]} : // ROM col
Amux[2:0]==3'h6 ? { Addr[22] & SetFW,
Addr[21] & SetFW,
Addr[20] & SetFW,
Addr[19:10] } : // RAM row
{ 4'b0000, Addr[9:1] }; // RAM col
*/
output DQML; assign DQML =
Amux[2:0]==3'h0 ? 1'b1 : // mode register
Amux[2:0]==3'h1 ? 1'b1 : // "all"
Amux[2:0]==3'h2 ? 1'b1 : // FIXME: init row
Amux[2:0]==3'h3 ? LS[3] : // FIXME: init col
Amux[2:0]==3'h4 ? 1'b1 : // ROM row
Amux[2:0]==3'h5 ? RAcur[0]: // ROM col
Amux[2:0]==3'h6 ? 1'b1 : // RAM row
/* 3'h7 */ Addr[0]; // RAM col
output DQMH; assign DQMH =
Amux[2:0]==3'h0 ? 1'b1 : // mode register
Amux[2:0]==3'h1 ? 1'b1 : // "all"
Amux[2:0]==3'h2 ? 1'b1 : // FIXME: init row
Amux[2:0]==3'h3 ? ~LS[3] : // FIXME: init col
Amux[2:0]==3'h4 ? 1'b1 : // ROM row
Amux[2:0]==3'h5 ? ~RAcur[0]: // ROM col
Amux[2:0]==3'h6 ? 1'b1 : // RAM row
/* 3'h7 */ ~Addr[0]; // RAM col
reg [2:0] Amux = 0;
output reg RCKE = 1; output reg RCKE = 1;
output reg nRCS = 1; output reg nRCS = 1;
output reg nRAS = 1; output reg nRAS = 1;
output reg nCAS = 1; output reg nCAS = 1;
output reg nSWE = 1; output reg nSWE = 1;
wire RefReqd = LS[1:0] == 2'b11;
always @(posedge C25M) begin always @(posedge C25M) begin
case (PS[2:0]) case (PS[3:0])
0: begin 0: begin // NOP CKE / CKD
if (PSStart) begin RCKE <= PSStart;
// NOP CKE nRCS <= 1'b1;
RCKE <= 1'b1; nRAS <= 1'b1;
nRCS <= 1'b1; nCAS <= 1'b1;
nRAS <= 1'b1; nSWE <= 1'b1;
nCAS <= 1'b1; SDOE <= 0;
nSWE <= 1'b1; end 1: begin // ACT CKE / NOP CKD
Amux <= 3'b001; RCKE <= IS==6 || (((ROMSpecSELr && nWEr) || RAMSpecSELr) && IS==7);
end else if (RefReqd) begin nRCS <= ~(IS==6 || (((ROMSpecSELr && nWEr) || RAMSpecSELr) && IS==7));
if (RCKE) begin nRAS <= 1'b0;
// AREF nCAS <= 1'b1;
RCKE <= 1'b1; nSWE <= 1'b1;
nRCS <= 1'b0; SDOE <= 0;
nRAS <= 1'b0; end 2: begin // RD CKE / NOP CKD
nCAS <= 1'b0; RCKE <= (ROMSpecSELr || RAMSpecSELr) && nWEr && IS==7;
nSWE <= 1'b1; nRCS <= ~((ROMSpecSELr || RAMSpecSELr) && nWEr && IS==7);
Amux <= 3'b001; nRAS <= 1'b1;
end else begin nCAS <= 1'b0;
// NOP CKE nSWE <= 1'b1;
RCKE <= 1'b1; SDOE <= 0;
nRCS <= 1'b1; end 3: begin // NOP CKE / CKD
nRAS <= 1'b1; RCKE <= (ROMSpecSELr || RAMSpecSELr) && nWEr && IS==7;
nCAS <= 1'b1; nRCS <= 1'b1;
nSWE <= 1'b1; nRAS <= 1'b1;
Amux <= 3'b001; nCAS <= 1'b1;
end nSWE <= 1'b1;
end else begin SDOE <= 0;
// NOP CKE end 4: begin // NOP CKD
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
Amux <= 3'b001;
end
end 1: begin
if (ROMSpecRD || RAMSpecSEL) begin
// ACT
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nSWE <= 1'b1;
end else begin
// NOP CKE
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
end
if (ROMSpecRD) Amux <= 3'b100;
else Amux <= 3'b110;
end 2: begin
if (ROMSpecRD || RAMSpecRD) begin
// RD
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nSWE <= 1'b1;
end else begin
// NOP CKE
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
end
if (ROMSpecRD) Amux <= 3'b101;
else Amux <= 3'b111;
end 3: begin
// NOP CKE
RCKE <= 1'b0; RCKE <= 1'b0;
nRCS <= 1'b1; nRCS <= 1'b1;
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
Amux <= 3'b001; SDOE <= 0;
end 4: begin end 5: begin // NOP CKD
// NOP CKE
RCKE <= 1'b0; RCKE <= 1'b0;
nRCS <= 1'b1; nRCS <= 1'b1;
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
Amux <= 3'b001; SDOE <= 0;
end 5: begin end 6: begin // NOP CKD
if (RAMSpecWR && DEVSELr) begin RCKE <= 1'b0;
// WR AP
RCKE <= 1'b1;
nRCS <= 1'b0;
nRAS <= 1'b1;
nCAS <= 1'b0;
nSWE <= 1'b0;
end else begin
// NOP CKE
RCKE <= 1'b1;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
end
Amux <= 3'b111;
end 6: begin
RCKE <= 1'b1;
nRCS <= 1'b1; nRCS <= 1'b1;
nRAS <= 1'b1; nRAS <= 1'b1;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b1; nSWE <= 1'b1;
Amux <= 3'b001; SDOE <= 0;
end 7: begin end 7: begin // NOP CKE / CKD
// PC all RCKE <= IS==6 || (RAMWR && IS==7);
RCKE <= 1'b1; nRCS <= 1'b1;
nRCS <= 1'b0; nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
SDOE <= 0;
end 8: begin // WR AP / NOP CKE (WR AP)
// NOP CKD / WR AP
RCKE <= IS==6 || (RAMWR && IS==7);
nRCS <= ~(IS==6 || (RAMWR && IS==7));
nRAS <= 1'b1;
nCAS <= 1'b0;
nSWE <= 1'b0;
SDOE <= IS==6 || (RAMWR && IS==7);
end 9: begin // NOP CKE / NOP CKD
RCKE <= (IS==6) || ((ROMSpecSELr || RAMSpecSELr) && IS==7) ||
(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7));
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
SDOE <= 0;
end 10: begin // PC all / NOP CKD (PC all)
RCKE <= (IS==6) || ((ROMSpecSELr || RAMSpecSELr) && IS==7) ||
(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7));
nRCS <= ~((IS==6) || ((ROMSpecSELr || RAMSpecSELr) && IS==7) ||
(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7)));
nRAS <= 1'b0; nRAS <= 1'b0;
nCAS <= 1'b1; nCAS <= 1'b1;
nSWE <= 1'b0; nSWE <= 1'b0;
Amux <= 3'b001; SDOE <= 0;
end 11: begin // AREF / NOP CKD (AREF)
RCKE <= RefReqd && (IS==4 || IS==5 || IS==6 || IS==7);
nRCS <= ~(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7));
nRAS <= 1'b0;
nCAS <= 1'b0;
nSWE <= 1'b1;
SDOE <= 0;
end 12: begin // NOP CKD
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
SDOE <= 0;
end 13: begin // NOP CKD
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
SDOE <= 0;
end 14: begin // NOP CKD
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
SDOE <= 0;
end 15: begin // NOP CKD
RCKE <= 1'b0;
nRCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nSWE <= 1'b1;
SDOE <= 0;
end
endcase
end
output reg DQML = 1;
output reg DQMH = 1;
output reg [1:0] SBA;
output reg [12:0] SA;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 1: begin // ACT
DQML <= 1'b1;
DQMH <= 1'b1;
if (IS==6) begin
SBA[1:0] <= { 2'b10 };
SA[12:0] <= { 10'b0011000100, LS[12:10] };
end else if (RAMSpecSELr) begin
SBA[1:0] <= { 1'b0, Addr[23] && SetLim8M && SetRF };
SA[12:0] <= { SetRF ? Addr [22:20] : 3'b000, Addr[19:10]};
end else begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 10'b0011000100, Bank, RA[11:10] };
end
end 2: begin // RD
if (RAMSpecSELr) begin
SBA[1:0] <= { 1'b0, Addr[23] && SetLim8M && SetRF };
SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0];
DQMH <= ~Addr[0];
end else begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, RA[9:1]};
DQML <= RA[0];
DQMH <= ~RA[0];
end
end 3: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 4: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 5: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 6: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 7: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 8: begin // WR AP
if (IS==6) begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, LS[9:1] };
DQML <= LS[0];
DQMH <= ~LS[0];
end else begin
SBA[1:0] <= { 1'b0, Addr[23] && SetLim8M && SetRF };
SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0];
DQMH <= ~Addr[0];
end
end 9: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 10: begin // PC all
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 11: begin // AREF / load mode
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0001000100000;
end 12: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 13: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 14: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 15: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end end
endcase endcase
end end

268
cpld/UFM.v
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// megafunction wizard: %ALTUFM_NONE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTUFM_NONE
// ============================================================
// File Name: UFM.v
// Megafunction Name(s):
// ALTUFM_NONE
//
// Simulation Library Files(s):
// maxii
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:39:SJ cbx_a_graycounter 2013:06:12:18:03:39:SJ cbx_altufm_none 2013:06:12:18:03:40:SJ cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_lpm_compare 2013:06:12:18:03:40:SJ cbx_lpm_counter 2013:06:12:18:03:40:SJ cbx_lpm_decode 2013:06:12:18:03:40:SJ cbx_lpm_mux 2013:06:12:18:03:40:SJ cbx_maxii 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ cbx_util_mgl 2013:06:12:18:03:40:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = maxii_ufm 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module UFM_altufm_none_0ep
(
arclk,
ardin,
arshft,
busy,
drclk,
drdin,
drdout,
drshft,
erase,
osc,
oscena,
program,
rtpbusy) ;
input arclk;
input ardin;
input arshft;
output busy;
input drclk;
input drdin;
output drdout;
input drshft;
input erase;
output osc;
input oscena;
input program;
output rtpbusy;
wire wire_maxii_ufm_block1_bgpbusy;
wire wire_maxii_ufm_block1_busy;
wire wire_maxii_ufm_block1_drdout;
wire wire_maxii_ufm_block1_osc;
wire ufm_arclk;
wire ufm_ardin;
wire ufm_arshft;
wire ufm_bgpbusy;
wire ufm_busy;
wire ufm_drclk;
wire ufm_drdin;
wire ufm_drdout;
wire ufm_drshft;
wire ufm_erase;
wire ufm_osc;
wire ufm_oscena;
wire ufm_program;
maxii_ufm maxii_ufm_block1
(
.arclk(ufm_arclk),
.ardin(ufm_ardin),
.arshft(ufm_arshft),
.bgpbusy(wire_maxii_ufm_block1_bgpbusy),
.busy(wire_maxii_ufm_block1_busy),
.drclk(ufm_drclk),
.drdin(ufm_drdin),
.drdout(wire_maxii_ufm_block1_drdout),
.drshft(ufm_drshft),
.erase(ufm_erase),
.osc(wire_maxii_ufm_block1_osc),
.oscena(ufm_oscena),
.program(ufm_program)
// synopsys translate_off
,
.ctrl_bgpbusy(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.sbdin(1'b0),
.sbdout()
// synopsys translate_on
);
defparam
maxii_ufm_block1.address_width = 9,
maxii_ufm_block1.erase_time = 500000000,
maxii_ufm_block1.init_file = "none",
maxii_ufm_block1.mem1 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem2 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem3 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem4 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem5 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem6 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem7 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem8 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.osc_sim_setting = 180000,
maxii_ufm_block1.program_time = 1600000,
maxii_ufm_block1.lpm_type = "maxii_ufm";
assign
busy = ufm_busy,
drdout = ufm_drdout,
osc = ufm_osc,
rtpbusy = ufm_bgpbusy,
ufm_arclk = arclk,
ufm_ardin = ardin,
ufm_arshft = arshft,
ufm_bgpbusy = wire_maxii_ufm_block1_bgpbusy,
ufm_busy = wire_maxii_ufm_block1_busy,
ufm_drclk = drclk,
ufm_drdin = drdin,
ufm_drdout = wire_maxii_ufm_block1_drdout,
ufm_drshft = drshft,
ufm_erase = erase,
ufm_osc = wire_maxii_ufm_block1_osc,
ufm_oscena = oscena,
ufm_program = program;
endmodule //UFM_altufm_none_0ep
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module UFM (
arclk,
ardin,
arshft,
drclk,
drdin,
drshft,
erase,
oscena,
program,
busy,
drdout,
osc,
rtpbusy);
input arclk;
input ardin;
input arshft;
input drclk;
input drdin;
input drshft;
input erase;
input oscena;
input program;
output busy;
output drdout;
output osc;
output rtpbusy;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire osc = sub_wire0;
wire rtpbusy = sub_wire1;
wire drdout = sub_wire2;
wire busy = sub_wire3;
UFM_altufm_none_0ep UFM_altufm_none_0ep_component (
.arshft (arshft),
.drclk (drclk),
.erase (erase),
.program (program),
.arclk (arclk),
.drdin (drdin),
.oscena (oscena),
.ardin (ardin),
.drshft (drshft),
.osc (sub_wire0),
.rtpbusy (sub_wire1),
.drdout (sub_wire2),
.busy (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: LPM_FILE STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
// Retrieval info: CONSTANT: PORT_ARCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_DRCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PROGRAM_TIME NUMERIC "1600000"
// Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9"
// Retrieval info: USED_PORT: arclk 0 0 0 0 INPUT NODEFVAL "arclk"
// Retrieval info: CONNECT: @arclk 0 0 0 0 arclk 0 0 0 0
// Retrieval info: USED_PORT: ardin 0 0 0 0 INPUT NODEFVAL "ardin"
// Retrieval info: CONNECT: @ardin 0 0 0 0 ardin 0 0 0 0
// Retrieval info: USED_PORT: arshft 0 0 0 0 INPUT NODEFVAL "arshft"
// Retrieval info: CONNECT: @arshft 0 0 0 0 arshft 0 0 0 0
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
// Retrieval info: USED_PORT: drclk 0 0 0 0 INPUT NODEFVAL "drclk"
// Retrieval info: CONNECT: @drclk 0 0 0 0 drclk 0 0 0 0
// Retrieval info: USED_PORT: drdin 0 0 0 0 INPUT NODEFVAL "drdin"
// Retrieval info: CONNECT: @drdin 0 0 0 0 drdin 0 0 0 0
// Retrieval info: USED_PORT: drdout 0 0 0 0 OUTPUT NODEFVAL "drdout"
// Retrieval info: CONNECT: drdout 0 0 0 0 @drdout 0 0 0 0
// Retrieval info: USED_PORT: drshft 0 0 0 0 INPUT NODEFVAL "drshft"
// Retrieval info: CONNECT: @drshft 0 0 0 0 drshft 0 0 0 0
// Retrieval info: USED_PORT: erase 0 0 0 0 INPUT NODEFVAL "erase"
// Retrieval info: CONNECT: @erase 0 0 0 0 erase 0 0 0 0
// Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL "osc"
// Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0
// Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL "oscena"
// Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0
// Retrieval info: USED_PORT: program 0 0 0 0 INPUT NODEFVAL "program"
// Retrieval info: CONNECT: @program 0 0 0 0 program 0 0 0 0
// Retrieval info: USED_PORT: rtpbusy 0 0 0 0 OUTPUT NODEFVAL "rtpbusy"
// Retrieval info: CONNECT: rtpbusy 0 0 0 0 @rtpbusy 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE
// Retrieval info: LIB_FILE: maxii

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616186128983 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616429543853 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616186128983 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 16:35:28 2021 " "Processing started: Fri Mar 19 16:35:28 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616186128983 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616186128983 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616429543868 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 22 12:12:23 2021 " "Processing started: Mon Mar 22 12:12:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616429543868 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616429543868 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616186128983 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616429543868 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616186130343 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616429545103 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616186130390 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616429545134 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616186131124 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 16:35:31 2021 " "Processing ended: Fri Mar 19 16:35:31 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616186131124 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616186131124 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616186131124 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616186131124 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616429545696 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 22 12:12:25 2021 " "Processing ended: Mon Mar 22 12:12:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616429545696 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616429545696 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616429545696 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616429545696 ""}

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Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280 Version_Index = 302049280
Creation_Time = Mon Mar 15 13:41:40 2021 Creation_Time = Mon Mar 22 01:13:17 2021

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|GR8RAM |GR8RAM
C25M => Amux[0].CLK C25M => SA[0]~reg0.CLK
C25M => Amux[1].CLK C25M => SA[1]~reg0.CLK
C25M => Amux[2].CLK C25M => SA[2]~reg0.CLK
C25M => SA[3]~reg0.CLK
C25M => SA[4]~reg0.CLK
C25M => SA[5]~reg0.CLK
C25M => SA[6]~reg0.CLK
C25M => SA[7]~reg0.CLK
C25M => SA[8]~reg0.CLK
C25M => SA[9]~reg0.CLK
C25M => SA[10]~reg0.CLK
C25M => SA[11]~reg0.CLK
C25M => SA[12]~reg0.CLK
C25M => SBA[0]~reg0.CLK
C25M => SBA[1]~reg0.CLK
C25M => DQMH~reg0.CLK
C25M => DQML~reg0.CLK
C25M => SDOE.CLK
C25M => nSWE~reg0.CLK C25M => nSWE~reg0.CLK
C25M => nCAS~reg0.CLK C25M => nCAS~reg0.CLK
C25M => nRAS~reg0.CLK C25M => nRAS~reg0.CLK
C25M => nRCS~reg0.CLK C25M => nRCS~reg0.CLK
C25M => RCKE~reg0.CLK C25M => RCKE~reg0.CLK
C25M => RefReqd.CLK
C25M => PS[0].CLK C25M => PS[0].CLK
C25M => PS[1].CLK C25M => PS[1].CLK
C25M => PS[2].CLK C25M => PS[2].CLK
C25M => SDOE.CLK C25M => PS[3].CLK
C25M => RDD[0].CLK
C25M => RDD[1].CLK
C25M => RDD[2].CLK
C25M => RDD[3].CLK
C25M => RDD[4].CLK
C25M => RDD[5].CLK
C25M => RDD[6].CLK
C25M => RDD[7].CLK
C25M => WRD[0].CLK
C25M => WRD[1].CLK
C25M => WRD[2].CLK
C25M => WRD[3].CLK
C25M => WRD[4].CLK
C25M => WRD[5].CLK
C25M => WRD[6].CLK C25M => WRD[6].CLK
C25M => WRD[7].CLK C25M => WRD[7].CLK
C25M => DRDIn.CLK
C25M => SetLim8M.CLK
C25M => SetFW.CLK
C25M => DRShift.CLK
C25M => DRCLK.CLK
C25M => ARShift.CLK
C25M => ARCLK.CLK
C25M => SS[0].CLK
C25M => SS[1].CLK
C25M => MOSIOE.CLK
C25M => MOSIout.CLK C25M => MOSIout.CLK
C25M => FCKEN.CLK C25M => MOSIOE.CLK
C25M => FCS.CLK C25M => FCS.CLK
C25M => FCK~reg0.CLK C25M => FCK~reg0.CLK
C25M => Bank.CLK
C25M => AddrIncH.CLK
C25M => AddrIncM.CLK
C25M => AddrIncL.CLK
C25M => Addr[0].CLK C25M => Addr[0].CLK
C25M => Addr[1].CLK C25M => Addr[1].CLK
C25M => Addr[2].CLK C25M => Addr[2].CLK
@ -54,23 +76,9 @@ C25M => Addr[22].CLK
C25M => Addr[23].CLK C25M => Addr[23].CLK
C25M => REGEN.CLK C25M => REGEN.CLK
C25M => IOROMEN.CLK C25M => IOROMEN.CLK
C25M => nWEcur.CLK C25M => nWEr.CLK
C25M => RAcur[0].CLK C25M => RAMSpecSELr.CLK
C25M => RAcur[1].CLK C25M => ROMSpecSELr.CLK
C25M => RAcur[2].CLK
C25M => RAcur[3].CLK
C25M => RAcur[4].CLK
C25M => RAcur[5].CLK
C25M => RAcur[6].CLK
C25M => RAcur[7].CLK
C25M => RAcur[8].CLK
C25M => RAcur[9].CLK
C25M => RAcur[10].CLK
C25M => RAcur[11].CLK
C25M => RACr.CLK
C25M => IOSTRBr.CLK
C25M => IOSELr.CLK
C25M => DEVSELr.CLK
C25M => nRESout~reg0.CLK C25M => nRESout~reg0.CLK
C25M => LS[0].CLK C25M => LS[0].CLK
C25M => LS[1].CLK C25M => LS[1].CLK
@ -86,47 +94,85 @@ C25M => LS[10].CLK
C25M => LS[11].CLK C25M => LS[11].CLK
C25M => LS[12].CLK C25M => LS[12].CLK
C25M => LS[13].CLK C25M => LS[13].CLK
C25M => LS[14].CLK
C25M => LS[15].CLK
C25M => LS[16].CLK
C25M => LS[17].CLK
C25M => nRESr.CLK C25M => nRESr.CLK
C25M => nRESr0.CLK
C25M => PHI0r2.CLK C25M => PHI0r2.CLK
C25M => PHI0r1.CLK C25M => PHI0r1.CLK
C25M => PHI0r0.CLK C25M => IS~7.DATAIN
C25M => nRESr0.CLK
C25M => IOSTRBr0.CLK
C25M => IOSELr0.CLK
C25M => DEVSELr0.CLK
PHI0 => comb.IN1 PHI0 => comb.IN1
PHI0 => PHI0r0.DATAIN PHI0 => PHI0r1.DATAIN
nRES => nRESr0.DATAIN nRES => nRESr0.DATAIN
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
nIOSEL => comb.IN1 nIOSEL => comb.IN0
nIOSEL => IOSELr0.DATAIN nIOSEL => always5.IN1
nDEVSEL => comb.IN1
nDEVSEL => RAMSEL.IN1
nDEVSEL => comb.IN1 nDEVSEL => comb.IN1
nDEVSEL => DEVSELr0.DATAIN
nIOSTRB => comb.IN1 nIOSTRB => comb.IN1
nIOSTRB => IOSTRBr0.DATAIN nIOSTRB => always5.IN1
RA[0] => RAcur[0].DATAIN SetRF => MOSIout.DATAB
RA[1] => RAcur[1].DATAIN SetRF => always10.IN1
RA[2] => RAcur[2].DATAIN SetRF => SA.OUTPUTSELECT
RA[3] => RAcur[3].DATAIN SetRF => SA.OUTPUTSELECT
RA[4] => RAcur[4].DATAIN SetRF => SA.OUTPUTSELECT
RA[5] => RAcur[5].DATAIN SetRF => SBA.IN1
RA[6] => RAcur[6].DATAIN SetRF => always10.IN1
RA[7] => RAcur[7].DATAIN SetLim8M => SBA.IN1
RA[8] => RAcur[8].DATAIN RA[0] => DQML.DATAA
RA[9] => RAcur[9].DATAIN RA[0] => Equal6.IN3
RA[10] => RAcur[10].DATAIN RA[0] => Equal9.IN1
RA[11] => RAcur[11].DATAIN RA[0] => Equal10.IN3
RA[12] => Equal1.IN3 RA[0] => Equal11.IN0
RA[13] => Equal1.IN2 RA[0] => Equal12.IN3
RA[14] => Equal1.IN1 RA[0] => Equal13.IN10
RA[15] => Equal1.IN0 RA[0] => DQMH.DATAA
RA[1] => SA.DATAA
RA[1] => Equal6.IN2
RA[1] => Equal9.IN0
RA[1] => Equal10.IN0
RA[1] => Equal11.IN3
RA[1] => Equal12.IN2
RA[1] => Equal13.IN9
RA[2] => SA.DATAA
RA[2] => Equal6.IN1
RA[2] => Equal9.IN3
RA[2] => Equal10.IN2
RA[2] => Equal11.IN2
RA[2] => Equal12.IN1
RA[2] => Equal13.IN8
RA[3] => SA.DATAA
RA[3] => Equal6.IN0
RA[3] => Equal9.IN2
RA[3] => Equal10.IN1
RA[3] => Equal11.IN1
RA[3] => Equal12.IN0
RA[3] => Equal13.IN7
RA[4] => SA.DATAA
RA[4] => Equal13.IN6
RA[5] => SA.DATAA
RA[5] => Equal13.IN5
RA[6] => SA.DATAA
RA[6] => Equal13.IN4
RA[7] => comb.IN1
RA[7] => SA.DATAA
RA[7] => Equal13.IN3
RA[8] => SA.DATAA
RA[8] => Equal8.IN3
RA[8] => Equal13.IN2
RA[9] => SA.DATAA
RA[9] => Equal8.IN2
RA[9] => Equal13.IN1
RA[10] => SA.DATAA
RA[10] => Equal8.IN1
RA[10] => Equal13.IN0
RA[11] => SA.DATAA
RA[11] => Equal8.IN0
RA[12] => Equal7.IN3
RA[13] => Equal7.IN2
RA[14] => Equal7.IN1
RA[15] => Equal7.IN0
nWE => comb.IN1 nWE => comb.IN1
nWE => nWEcur.DATAIN nWE => nWEr.DATAIN
RAdir <= <VCC>
RD[0] <> RD[0] RD[0] <> RD[0]
RD[1] <> RD[1] RD[1] <> RD[1]
RD[2] <> RD[2] RD[2] <> RD[2]
@ -136,27 +182,27 @@ RD[5] <> RD[5]
RD[6] <> RD[6] RD[6] <> RD[6]
RD[7] <> RD[7] RD[7] <> RD[7]
RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
SBA[0] <= SBA.DB_MAX_OUTPUT_PORT_TYPE SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SBA[1] <= SBA.DB_MAX_OUTPUT_PORT_TYPE SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[0] <= <GND> SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[1] <= <GND> SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[2] <= <GND> SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[3] <= <GND> SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[4] <= <GND> SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[5] <= <GND> SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[6] <= <GND> SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[7] <= <GND> SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[8] <= <GND> SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[9] <= <GND> SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[10] <= <GND> SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[11] <= <GND> SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SA[12] <= SA.DB_MAX_OUTPUT_PORT_TYPE SA[12] <= SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
DQML <= DQML.DB_MAX_OUTPUT_PORT_TYPE DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE
DQMH <= DQMH.DB_MAX_OUTPUT_PORT_TYPE DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE
RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
SD[0] <> SD[0] SD[0] <> SD[0]
SD[1] <> SD[1] SD[1] <> SD[1]
@ -168,39 +214,7 @@ SD[6] <> SD[6]
SD[7] <> SD[7] SD[7] <> SD[7]
nFCS <= FCS.DB_MAX_OUTPUT_PORT_TYPE nFCS <= FCS.DB_MAX_OUTPUT_PORT_TYPE
FCK <= FCK~reg0.DB_MAX_OUTPUT_PORT_TYPE FCK <= FCK~reg0.DB_MAX_OUTPUT_PORT_TYPE
MISO => WRD[7].DATAIN MISO => WRD.DATAB
MOSI <= MOSI.DB_MAX_OUTPUT_PORT_TYPE MOSI <> MOSI
|GR8RAM|UFM:UFM_inst
arclk => arclk.IN1
ardin => ardin.IN1
arshft => arshft.IN1
drclk => drclk.IN1
drdin => drdin.IN1
drshft => drshft.IN1
erase => erase.IN1
oscena => oscena.IN1
program => program.IN1
busy <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.busy
drdout <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.drdout
osc <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.osc
rtpbusy <= UFM_altufm_none_0ep:UFM_altufm_none_0ep_component.rtpbusy
|GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component
arclk => maxii_ufm_block1.ARCLK
ardin => maxii_ufm_block1.ARDIN
arshft => maxii_ufm_block1.ARSHFT
busy <= maxii_ufm_block1.BUSY
drclk => maxii_ufm_block1.DRCLK
drdin => maxii_ufm_block1.DRDIN
drdout <= maxii_ufm_block1.DRDOUT
drshft => maxii_ufm_block1.DRSHFT
erase => maxii_ufm_block1.ERASE
osc <= maxii_ufm_block1.OSC
oscena => maxii_ufm_block1.OSCENA
program => maxii_ufm_block1.PROGRAM
rtpbusy <= maxii_ufm_block1.BGPBUSY

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32
cpld/db/GR8RAM.lpc.html
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@ -15,36 +15,4 @@
<TH>Input only Bidir</TH> <TH>Input only Bidir</TH>
<TH>Output only Bidir</TH> <TH>Output only Bidir</TH>
</TR> </TR>
<TR >
<TD >UFM_inst|UFM_altufm_none_0ep_component</TD>
<TD >9</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >UFM_inst</TD>
<TD >9</TD>
<TD >2</TD>
<TD >0</TD>
<TD >2</TD>
<TD >4</TD>
<TD >2</TD>
<TD >2</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE> </TABLE>

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13
cpld/db/GR8RAM.lpc.txt
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@ -1,8 +1,5 @@
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ; ; Legal Partition Candidates ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; UFM_inst|UFM_altufm_none_0ep_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; UFM_inst ; 9 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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cpld/db/GR8RAM.map.qmsg
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@ -1,34 +1,18 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616186109748 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616429527039 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616186109764 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 16:35:09 2021 " "Processing started: Fri Mar 19 16:35:09 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616186109764 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616186109764 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616429527039 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 22 12:12:06 2021 " "Processing started: Mon Mar 22 12:12:06 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616429527039 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616429527039 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616186109764 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616429527039 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616186111186 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616429528633 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616186111498 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(80) " "Verilog HDL warning at GR8RAM.v(80): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 80 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616429528805 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616186111498 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(255) " "Verilog HDL warning at GR8RAM.v(255): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 255 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616429528805 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616186111498 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616186111498 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616186111498 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616429528805 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616429528805 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(85) " "Verilog HDL warning at gr8ram.v(85): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616186111717 ""} { "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616429528914 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(314) " "Verilog HDL warning at gr8ram.v(314): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 314 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616186111733 ""} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(20) " "Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528914 "|GR8RAM"}
{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616186111733 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616186111733 ""} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(104) " "Verilog HDL assignment warning at GR8RAM.v(104): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528914 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(223) " "Verilog HDL Implicit Net warning at gr8ram.v(223): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 223 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616186111733 ""} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(112) " "Verilog HDL assignment warning at GR8RAM.v(112): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 112 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528914 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(226) " "Verilog HDL Implicit Net warning at gr8ram.v(226): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616186111733 ""} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(119) " "Verilog HDL assignment warning at GR8RAM.v(119): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 119 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528914 "|GR8RAM"}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616186111764 ""} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(306) " "Verilog HDL assignment warning at GR8RAM.v(306): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 306 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616429528930 "|GR8RAM"}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(86) " "Verilog HDL warning at gr8ram.v(86): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"} { "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1616429530336 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "Bank gr8ram.v(118) " "Verilog HDL or VHDL warning at gr8ram.v(118): object \"Bank\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 118 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1616429531165 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(228) " "Verilog HDL or VHDL warning at gr8ram.v(228): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 228 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"} { "Info" "ICUT_CUT_TM_SUMMARY" "304 " "Implemented 304 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616429531211 ""} { "Info" "ICUT_CUT_TM_OPINS" "26 " "Implemented 26 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616429531211 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616429531211 ""} { "Info" "ICUT_CUT_TM_LCELLS" "235 " "Implemented 235 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616429531211 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616429531211 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(230) " "Verilog HDL or VHDL warning at gr8ram.v(230): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616429531352 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RefReady gr8ram.v(335) " "Verilog HDL or VHDL warning at gr8ram.v(335): object \"RefReady\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 335 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616429531524 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 22 12:12:11 2021 " "Processing ended: Mon Mar 22 12:12:11 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616429531524 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616429531524 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616429531524 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616429531524 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(24) " "Verilog HDL assignment warning at gr8ram.v(24): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 gr8ram.v(100) " "Verilog HDL assignment warning at gr8ram.v(100): truncated value with size 32 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 gr8ram.v(104) " "Verilog HDL assignment warning at gr8ram.v(104): truncated value with size 32 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(109) " "Verilog HDL assignment warning at gr8ram.v(109): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 gr8ram.v(330) " "Verilog HDL assignment warning at gr8ram.v(330): truncated value with size 32 to match size of target (3)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 330 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111780 "|GR8RAM"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(86) " "Net \"RDout\" at gr8ram.v(86) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616186111780 "|GR8RAM"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "WRD\[5..0\] 0 gr8ram.v(315) " "Net \"WRD\[5..0\]\" at gr8ram.v(315) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 315 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616186111780 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "SA\[11..0\] gr8ram.v(347) " "Output port \"SA\[11..0\]\" at gr8ram.v(347) has no driver" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1616186111795 "|GR8RAM"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616186111967 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616186112030 ""}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1616186113280 ""}
{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD\[6\] " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\[6\]\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 132 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616186113327 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616186113327 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SBA\[0\] GND " "Pin \"SBA\[0\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 342 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SBA[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[0\] GND " "Pin \"SA\[0\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[1\] GND " "Pin \"SA\[1\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[2\] GND " "Pin \"SA\[2\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[3\] GND " "Pin \"SA\[3\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[4\] GND " "Pin \"SA\[4\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[5\] GND " "Pin \"SA\[5\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[6\] GND " "Pin \"SA\[6\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[7\] GND " "Pin \"SA\[7\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[8\] GND " "Pin \"SA\[8\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[9\] GND " "Pin \"SA\[9\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[10\] GND " "Pin \"SA\[10\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[10]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[11\] GND " "Pin \"SA\[11\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[11]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616186113608 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "306 " "Implemented 306 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "24 " "Implemented 24 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616186113983 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616186113983 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616186113983 ""} { "Info" "ICUT_CUT_TM_LCELLS" "237 " "Implemented 237 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616186113983 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616186113983 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616186113983 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616186114420 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 33 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 33 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616186114655 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 16:35:14 2021 " "Processing ended: Fri Mar 19 16:35:14 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616186114655 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616186114655 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616186114655 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616186114655 ""}

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cpld/db/GR8RAM.rpp.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616136540772 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616386555172 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 32-bit " "Running Quartus II 32-bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616136540788 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 02:49:00 2021 " "Processing started: Fri Mar 19 02:49:00 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616136540788 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616136540788 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus II 32-bit " "Running Quartus II 32-bit Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616386555172 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 22 00:15:54 2021 " "Processing started: Mon Mar 22 00:15:54 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616386555172 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616386555172 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp GR8RAM -c GR8RAM --netlist_type=sgate " "Command: quartus_rpp GR8RAM -c GR8RAM --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616136540788 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_rpp GR8RAM -c GR8RAM --netlist_type=atom " "Command: quartus_rpp GR8RAM -c GR8RAM --netlist_type=atom" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616386555172 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "202 " "Peak virtual memory: 202 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616136541319 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 02:49:01 2021 " "Processing ended: Fri Mar 19 02:49:01 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616136541319 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616136541319 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616136541319 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616136541319 ""} { "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "207 " "Peak virtual memory: 207 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616386555922 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 22 00:15:55 2021 " "Processing ended: Mon Mar 22 00:15:55 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616386555922 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616386555922 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616386555922 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1616386555922 ""}

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cpld/db/GR8RAM.smp_dump.txt Executable file
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State Machine - |GR8RAM|IS
Name IS.state_bit_2 IS.state_bit_1 IS.state_bit_0
IS.000 0 0 0
IS.001 0 0 1
IS.100 1 0 0
IS.101 1 0 1
IS.110 0 1 0
IS.111 0 1 1

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cpld/db/GR8RAM.sta.qmsg
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@ -1,23 +1,23 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616186134749 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616429549056 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616186134780 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 16:35:33 2021 " "Processing started: Fri Mar 19 16:35:33 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616186134780 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616186134780 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616429549071 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 22 12:12:27 2021 " "Processing started: Mon Mar 22 12:12:27 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616429549071 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616429549071 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616186134780 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616429549087 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616186134968 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616429549337 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616186135733 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616429550197 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616186135937 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616429550353 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616186135937 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616429550353 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616186136155 ""} { "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616429550525 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616186136718 ""} { "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616429550962 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616186136905 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616429551103 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616186136905 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616429551103 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616186136921 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616186136921 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616186136921 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616186136921 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551103 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551103 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616186136952 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616429551118 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616186137124 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616429551243 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.555 -547.115 C25M " " -9.555 -547.115 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -9.843 " "Worst-case setup slack is -9.843" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551243 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551243 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.843 -651.483 C25M " " -9.843 -651.483 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551243 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551243 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.276 " "Worst-case hold slack is -16.276" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.276 -16.276 ARCLK " " -16.276 -16.276 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.256 -16.256 DRCLK " " -16.256 -16.256 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.377 0.000 C25M " " 1.377 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 1.395 " "Worst-case hold slack is 1.395" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551259 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551259 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.395 0.000 C25M " " 1.395 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551259 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551259 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616186137312 ""} { "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.404 " "Worst-case recovery slack is -4.404" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.404 -132.120 C25M " " -4.404 -132.120 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616186137343 ""} { "Info" "ISTA_WORST_CASE_SLACK" "removal 4.850 " "Worst-case removal slack is 4.850" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.850 0.000 C25M " " 4.850 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551275 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551290 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551290 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616429551290 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616429551290 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616186137671 ""} { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616429551415 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616186137827 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616429551525 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616186137843 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616429551525 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "275 " "Peak virtual memory: 275 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616186138155 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 16:35:38 2021 " "Processing ended: Fri Mar 19 16:35:38 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616186138155 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616186138155 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616186138155 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616186138155 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "286 " "Peak virtual memory: 286 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616429551712 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 22 12:12:31 2021 " "Processing ended: Mon Mar 22 12:12:31 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616429551712 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616429551712 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616429551712 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616429551712 ""}

BIN
cpld/db/GR8RAM.sta.rdb
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cpld/db/GR8RAM.sta_cmp.5_slow.tdb
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10
cpld/db/GR8RAM.tmw_info
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@ -1,6 +1,6 @@
start_full_compilation:s:00:00:32 start_full_compilation:s:00:00:27
start_analysis_synthesis:s:00:00:08-start_full_compilation start_analysis_synthesis:s:00:00:07-start_full_compilation
start_analysis_elaboration:s-start_full_compilation start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:11-start_full_compilation start_fitter:s:00:00:10-start_full_compilation
start_assembler:s:00:00:05-start_full_compilation start_assembler:s:00:00:04-start_full_compilation
start_timing_analyzer:s:00:00:08-start_full_compilation start_timing_analyzer:s:00:00:06-start_full_compilation

BIN
cpld/db/GR8RAM.vpr.ammdb
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cpld/db/logic_util_heursitic.dat
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111
cpld/db/prev_cmp_GR8RAM.qmsg
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cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt
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14
cpld/output_files/GR8RAM.asm.rpt
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@ -1,5 +1,5 @@
Assembler report for GR8RAM Assembler report for GR8RAM
Fri Mar 19 16:35:30 2021 Mon Mar 22 12:12:25 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+ +---------------------------------------------------------------+
; Assembler Summary ; ; Assembler Summary ;
+-----------------------+---------------------------------------+ +-----------------------+---------------------------------------+
; Assembler Status ; Successful - Fri Mar 19 16:35:30 2021 ; ; Assembler Status ; Successful - Mon Mar 22 12:12:25 2021 ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
@ -90,8 +90,8 @@ applicable agreement for further details.
; Option ; Setting ; ; Option ; Setting ;
+----------------+-------------------------------------------------------+ +----------------+-------------------------------------------------------+
; Device ; EPM240T100C5 ; ; Device ; EPM240T100C5 ;
; JTAG usercode ; 0x0016B2B7 ; ; JTAG usercode ; 0x00166EAF ;
; Checksum ; 0x0016B52F ; ; Checksum ; 0x0016711F ;
+----------------+-------------------------------------------------------+ +----------------+-------------------------------------------------------+
@ -101,14 +101,14 @@ applicable agreement for further details.
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler Info: Running Quartus II 32-bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Fri Mar 19 16:35:28 2021 Info: Processing started: Mon Mar 22 12:12:23 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
Info (115031): Writing out detailed assembly data for power analysis Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 293 megabytes Info: Peak virtual memory: 293 megabytes
Info: Processing ended: Fri Mar 19 16:35:31 2021 Info: Processing ended: Mon Mar 22 12:12:25 2021
Info: Elapsed time: 00:00:03 Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02 Info: Total CPU time (on all processors): 00:00:02

2
cpld/output_files/GR8RAM.done
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@ -1 +1 @@
Fri Mar 19 16:35:39 2021 Mon Mar 22 12:12:32 2021

1446
cpld/output_files/GR8RAM.fit.rpt
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8
cpld/output_files/GR8RAM.fit.summary
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@ -1,11 +1,11 @@
Fitter Status : Successful - Fri Mar 19 16:35:25 2021 Fitter Status : Successful - Mon Mar 22 12:12:21 2021
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM Revision Name : GR8RAM
Top-level Entity Name : GR8RAM Top-level Entity Name : GR8RAM
Family : MAX II Family : MAX II
Device : EPM240T100C5 Device : EPM240T100C5
Timing Models : Final Timing Models : Final
Total logic elements : 217 / 240 ( 90 % ) Total logic elements : 223 / 240 ( 93 % )
Total pins : 68 / 80 ( 85 % ) Total pins : 69 / 80 ( 86 % )
Total virtual pins : 0 Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % ) UFM blocks : 0 / 1 ( 0 % )

31
cpld/output_files/GR8RAM.flow.rpt
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@ -1,5 +1,5 @@
Flow report for GR8RAM Flow report for GR8RAM
Fri Mar 19 16:35:37 2021 Mon Mar 22 12:12:31 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -40,17 +40,17 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+ +-----------------------------------------------------------------------------+
; Flow Summary ; ; Flow Summary ;
+---------------------------+-------------------------------------------------+ +---------------------------+-------------------------------------------------+
; Flow Status ; Successful - Fri Mar 19 16:35:30 2021 ; ; Flow Status ; Successful - Mon Mar 22 12:12:25 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
; Device ; EPM240T100C5 ; ; Device ; EPM240T100C5 ;
; Timing Models ; Final ; ; Timing Models ; Final ;
; Total logic elements ; 217 / 240 ( 90 % ) ; ; Total logic elements ; 223 / 240 ( 93 % ) ;
; Total pins ; 68 / 80 ( 85 % ) ; ; Total pins ; 69 / 80 ( 86 % ) ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ; ; UFM blocks ; 0 / 1 ( 0 % ) ;
+---------------------------+-------------------------------------------------+ +---------------------------+-------------------------------------------------+
@ -59,7 +59,7 @@ applicable agreement for further details.
+-------------------+---------------------+ +-------------------+---------------------+
; Option ; Setting ; ; Option ; Setting ;
+-------------------+---------------------+ +-------------------+---------------------+
; Start date & time ; 03/19/2021 16:35:10 ; ; Start date & time ; 03/22/2021 12:12:08 ;
; Main task ; Compilation ; ; Main task ; Compilation ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
+-------------------+---------------------+ +-------------------+---------------------+
@ -73,21 +73,24 @@ applicable agreement for further details.
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; On ; Off ; -- ; -- ; ; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; On ; Off ; -- ; -- ;
; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always ; Auto ; -- ; -- ; ; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always ; Auto ; -- ; -- ;
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; ; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ;
; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ; ; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 44085571633675.161618611002356 ; -- ; -- ; -- ; ; COMPILER_SIGNATURE_ID ; 44085571633675.161642952802820 ; -- ; -- ; -- ;
; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ; ; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ;
; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ; ; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MUX_RESTRUCTURE ; On ; Auto ; -- ; -- ;
; PLACEMENT_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ; ; PLACEMENT_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; ; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; On ; Off ; -- ; -- ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; On ; Off ; -- ; -- ;
; ROUTER_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ; ; ROUTER_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ;
; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ; ; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ;
; SEED ; 235 ; 1 ; -- ; -- ;
; STATE_MACHINE_PROCESSING ; Minimal Bits ; Auto ; -- ; -- ;
; SYNTHESIS_SEED ; 123 ; 1 ; -- ; -- ;
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; ; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
+-------------------------------------------------+--------------------------------+---------------+-------------+------------+ +-------------------------------------------------+--------------------------------+---------------+-------------+------------+
@ -97,11 +100,11 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:04 ; ; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:05 ;
; Fitter ; 00:00:09 ; 1.5 ; 376 MB ; 00:00:08 ; ; Fitter ; 00:00:08 ; 1.5 ; 373 MB ; 00:00:08 ;
; Assembler ; 00:00:02 ; 1.0 ; 292 MB ; 00:00:02 ; ; Assembler ; 00:00:02 ; 1.0 ; 292 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 275 MB ; 00:00:04 ; ; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 286 MB ; 00:00:04 ;
; Total ; 00:00:20 ; -- ; -- ; 00:00:18 ; ; Total ; 00:00:19 ; -- ; -- ; 00:00:19 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+

2
cpld/output_files/GR8RAM.jdi
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@ -1,6 +1,6 @@
<sld_project_info> <sld_project_info>
<project> <project>
<hash md5_digest_80b="4e85f6d7379987575f53"/> <hash md5_digest_80b="73ef203dd7199fdf781e"/>
</project> </project>
<file_info> <file_info>
<file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/> <file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>

257
cpld/output_files/GR8RAM.map.rpt
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@ -1,5 +1,5 @@
Analysis & Synthesis report for GR8RAM Analysis & Synthesis report for GR8RAM
Fri Mar 19 16:35:14 2021 Mon Mar 22 12:12:11 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -13,15 +13,13 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
5. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary 6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity 7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis IP Cores Summary 8. State Machine - |GR8RAM|IS
9. Registers Removed During Synthesis 9. Registers Removed During Synthesis
10. Removed Registers Triggering Further Register Optimizations 10. General Register Statistics
11. General Register Statistics 11. Inverted Register Statistics
12. Inverted Register Statistics 12. Multiplexer Restructuring Statistics (Restructuring Performed)
13. Multiplexer Restructuring Statistics (Restructuring Performed) 13. Analysis & Synthesis Messages
14. Port Connectivity Checks: "UFM:UFM_inst" 14. Analysis & Synthesis Suppressed Messages
15. Analysis & Synthesis Messages
16. Analysis & Synthesis Suppressed Messages
@ -47,15 +45,15 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ; ; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+ +-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Mar 19 16:35:14 2021 ; ; Analysis & Synthesis Status ; Successful - Mon Mar 22 12:12:11 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
; Total logic elements ; 237 ; ; Total logic elements ; 235 ;
; Total pins ; 68 ; ; Total pins ; 69 ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ; ; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------------+-------------------------------------------------+ +-----------------------------+-------------------------------------------------+
@ -67,22 +65,23 @@ applicable agreement for further details.
; Device ; EPM240T100C5 ; ; ; Device ; EPM240T100C5 ; ;
; Top-level entity name ; GR8RAM ; GR8RAM ; ; Top-level entity name ; GR8RAM ; GR8RAM ;
; Family name ; MAX II ; Cyclone IV GX ; ; Family name ; MAX II ; Cyclone IV GX ;
; Safe State Machine ; On ; Off ; ; Restructure Multiplexers ; On ; Auto ;
; State Machine Processing ; Minimal Bits ; Auto ;
; Remove Redundant Logic Cells ; On ; Off ; ; Remove Redundant Logic Cells ; On ; Off ;
; Optimization Technique ; Area ; Balanced ; ; Optimization Technique ; Area ; Balanced ;
; Perform WYSIWYG Primitive Resynthesis ; On ; Off ; ; Perform WYSIWYG Primitive Resynthesis ; On ; Off ;
; Allow Shift Register Merging across Hierarchies ; Always ; Auto ; ; Allow Shift Register Merging across Hierarchies ; Always ; Auto ;
; Auto Resource Sharing ; On ; Off ; ; Auto Resource Sharing ; On ; Off ;
; Synthesis Seed ; 123 ; 1 ;
; Use smart compilation ; Off ; Off ; ; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ; ; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ; ; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ; ; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ; ; Ignore Verilog initial constructs ; Off ; Off ;
@ -128,7 +127,6 @@ applicable agreement for further details.
; Pre-Mapping Resynthesis Optimization ; Off ; Off ; ; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ; ; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+ +----------------------------------------------------------------------------+--------------------+--------------------+
@ -149,14 +147,13 @@ applicable agreement for further details.
+----------------------------+-------------+ +----------------------------+-------------+
+-----------------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ; ; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+-------------------------------+---------+ +----------------------------------+-----------------+------------------------+-------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------+-------------------------------+---------+ +----------------------------------+-----------------+------------------------+-------------------------------+---------+
; UFM.v ; yes ; User Wizard-Generated File ; Z:/Repos/GR8RAM/cpld/UFM.v ; ; ; GR8RAM.v ; yes ; User Verilog HDL File ; Z:/Repos/GR8RAM/cpld/GR8RAM.v ; ;
; gr8ram.v ; yes ; Auto-Found Verilog HDL File ; Z:/Repos/GR8RAM/cpld/gr8ram.v ; ; +----------------------------------+-----------------+------------------------+-------------------------------+---------+
+----------------------------------+-----------------+------------------------------+-------------------------------+---------+
+-----------------------------------------------------+ +-----------------------------------------------------+
@ -164,78 +161,69 @@ applicable agreement for further details.
+---------------------------------------------+-------+ +---------------------------------------------+-------+
; Resource ; Usage ; ; Resource ; Usage ;
+---------------------------------------------+-------+ +---------------------------------------------+-------+
; Total logic elements ; 237 ; ; Total logic elements ; 235 ;
; -- Combinational with no register ; 142 ; ; -- Combinational with no register ; 133 ;
; -- Register only ; 29 ; ; -- Register only ; 13 ;
; -- Combinational with a register ; 66 ; ; -- Combinational with a register ; 89 ;
; ; ; ; ; ;
; Logic element usage by number of LUT inputs ; ; ; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 80 ; ; -- 4 input functions ; 122 ;
; -- 3 input functions ; 45 ; ; -- 3 input functions ; 36 ;
; -- 2 input functions ; 71 ; ; -- 2 input functions ; 64 ;
; -- 1 input functions ; 11 ; ; -- 1 input functions ; 0 ;
; -- 0 input functions ; 1 ; ; -- 0 input functions ; 0 ;
; ; ; ; ; ;
; Logic elements by mode ; ; ; Logic elements by mode ; ;
; -- normal mode ; 179 ; ; -- normal mode ; 202 ;
; -- arithmetic mode ; 58 ; ; -- arithmetic mode ; 33 ;
; -- qfbk mode ; 0 ; ; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ; ; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 25 ; ; -- synchronous clear/load mode ; 35 ;
; -- asynchronous clear/load mode ; 0 ; ; -- asynchronous clear/load mode ; 30 ;
; ; ; ; ; ;
; Total registers ; 95 ; ; Total registers ; 102 ;
; Total logic cells in carry chains ; 62 ; ; Total logic cells in carry chains ; 37 ;
; I/O pins ; 68 ; ; I/O pins ; 69 ;
; UFM blocks ; 1 ;
; Maximum fan-out node ; C25M ; ; Maximum fan-out node ; C25M ;
; Maximum fan-out ; 95 ; ; Maximum fan-out ; 102 ;
; Total fan-out ; 836 ; ; Total fan-out ; 1020 ;
; Average fan-out ; 2.73 ; ; Average fan-out ; 3.36 ;
+---------------------------------------------+-------+ +---------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ; ; Analysis & Synthesis Resource Utilization by Entity ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |GR8RAM ; 237 (237) ; 95 ; 1 ; 68 ; 0 ; 142 (142) ; 29 (29) ; 66 (66) ; 62 (62) ; 0 (0) ; |GR8RAM ; work ; ; |GR8RAM ; 235 (235) ; 102 ; 0 ; 69 ; 0 ; 133 (133) ; 13 (13) ; 89 (89) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst ; work ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |UFM_altufm_none_0ep:UFM_altufm_none_0ep_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------------+ Encoding Type: Minimal Bits
; Analysis & Synthesis IP Cores Summary ; +-----------------------------------------------------------+
+--------+--------------+---------+--------------+--------------+----------------------+----------------------------+ ; State Machine - |GR8RAM|IS ;
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; +--------+----------------+----------------+----------------+
+--------+--------------+---------+--------------+--------------+----------------------+----------------------------+ ; Name ; IS.state_bit_2 ; IS.state_bit_1 ; IS.state_bit_0 ;
; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |GR8RAM|UFM:UFM_inst ; Z:/Repos/GR8RAM/cpld/UFM.v ; +--------+----------------+----------------+----------------+
+--------+--------------+---------+--------------+--------------+----------------------+----------------------------+ ; IS.000 ; 0 ; 0 ; 0 ;
; IS.001 ; 0 ; 0 ; 1 ;
; IS.100 ; 1 ; 0 ; 0 ;
; IS.101 ; 1 ; 0 ; 1 ;
; IS.110 ; 0 ; 1 ; 0 ;
; IS.111 ; 0 ; 1 ; 1 ;
+--------+----------------+----------------+----------------+
+--------------------------------------------------------------------------------+ +------------------------------------------------------------+
; Registers Removed During Synthesis ; ; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+ +---------------------------------------+--------------------+
; Register name ; Reason for Removal ; ; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+ +---------------------------------------+--------------------+
; DRDIn ; Stuck at GND due to stuck port data_in ; ; IS~10 ; Lost fanout ;
; SetFW ; Stuck at VCC due to stuck port data_in ; ; Total Number of Removed Registers = 1 ; ;
; SetLim8M ; Stuck at VCC due to stuck port data_in ; +---------------------------------------+--------------------+
; Total Number of Removed Registers = 3 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+---------------+---------------------------+----------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+---------------+---------------------------+----------------------------------------+
; DRDIn ; Stuck at GND ; SetFW, SetLim8M ;
; ; due to stuck port data_in ; ;
+---------------+---------------------------+----------------------------------------+
+------------------------------------------------------+ +------------------------------------------------------+
@ -243,12 +231,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+ +----------------------------------------------+-------+
; Statistic ; Value ; ; Statistic ; Value ;
+----------------------------------------------+-------+ +----------------------------------------------+-------+
; Total registers ; 95 ; ; Total registers ; 102 ;
; Number of registers using Synchronous Clear ; 25 ; ; Number of registers using Synchronous Clear ; 10 ;
; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Synchronous Load ; 25 ;
; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Clear ; 30 ;
; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 41 ; ; Number of registers using Clock Enable ; 32 ;
; Number of registers using Preset ; 0 ; ; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+ +----------------------------------------------+-------+
@ -262,8 +250,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; nRAS~reg0 ; 1 ; ; nRAS~reg0 ; 1 ;
; nCAS~reg0 ; 1 ; ; nCAS~reg0 ; 1 ;
; nSWE~reg0 ; 1 ; ; nSWE~reg0 ; 1 ;
; RCKE~reg0 ; 2 ; ; DQML~reg0 ; 1 ;
; Total number of inverted registers = 5 ; ; ; DQMH~reg0 ; 1 ;
; RCKE~reg0 ; 1 ;
; Total number of inverted registers = 7 ; ;
+----------------------------------------+---------+ +----------------------------------------+---------+
@ -272,88 +262,47 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[0] ; ; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[1] ;
; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[0] ; ; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[12]~reg0 ;
; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |GR8RAM|SS[0] ; ; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[3]~reg0 ;
; 7:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |GR8RAM|Addr[13] ; ; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[1]~reg0 ;
; 9:1 ; 8 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |GR8RAM|Addr[17] ; ; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |GR8RAM|WRD[0] ;
; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; No ; |GR8RAM|DQML ; ; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[7] ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[1] ;
; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|RDD[4] ;
; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ;
; 8:1 ; 5 bits ; 25 LEs ; 20 LEs ; 5 LEs ; No ; |GR8RAM|IS ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFM:UFM_inst" ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; ardin ; Input ; Info ; Stuck at GND ;
; oscena ; Input ; Info ; Stuck at VCC ;
; busy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; rtpbusy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
+-------------------------------+ +-------------------------------+
; Analysis & Synthesis Messages ; ; Analysis & Synthesis Messages ;
+-------------------------------+ +-------------------------------+
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Fri Mar 19 16:35:09 2021 Info: Processing started: Mon Mar 22 12:12:06 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
Info (12023): Found entity 1: UFM_altufm_none_0ep
Info (12023): Found entity 2: UFM
Warning (12125): Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: GR8RAM Info (12023): Found entity 1: GR8RAM
Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(223): created implicit net for "UFMB"
Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(226): created implicit net for "RTPB"
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
Warning (10858): Verilog HDL warning at gr8ram.v(86): object RDout used but never assigned Warning (10230): Verilog HDL assignment warning at GR8RAM.v(20): truncated value with size 32 to match size of target (14)
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(118): object "Bank" assigned a value but never read Warning (10230): Verilog HDL assignment warning at GR8RAM.v(104): truncated value with size 32 to match size of target (8)
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(228): object "UFMBr" assigned a value but never read Warning (10230): Verilog HDL assignment warning at GR8RAM.v(112): truncated value with size 32 to match size of target (8)
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(230): object "RTPBr" assigned a value but never read Warning (10230): Verilog HDL assignment warning at GR8RAM.v(119): truncated value with size 32 to match size of target (8)
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(335): object "RefReady" assigned a value but never read Warning (10230): Verilog HDL assignment warning at GR8RAM.v(306): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(24): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(100): truncated value with size 32 to match size of target (24)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(104): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(109): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(330): truncated value with size 32 to match size of target (3)
Warning (10030): Net "RDout" at gr8ram.v(86) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "WRD[5..0]" at gr8ram.v(315) has no driver or initial value, using a default initial value '0'
Warning (10034): Output port "SA[11..0]" at gr8ram.v(347) has no driver
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst"
Info (12128): Elaborating entity "UFM_altufm_none_0ep" for hierarchy "UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component"
Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Info (17049): 1 registers lost all their fanouts during netlist optimizations.
Warning (13047): Converted the fan-out from the tri-state buffer "MOSI" to the node "WRD[6]" into an OR gate Info (21057): Implemented 304 device resources after synthesis - the final resource count might be different
Warning (13024): Output pins are stuck at VCC or GND Info (21058): Implemented 26 input pins
Warning (13410): Pin "RAdir" is stuck at VCC Info (21059): Implemented 26 output pins
Warning (13410): Pin "SBA[0]" is stuck at GND Info (21060): Implemented 17 bidirectional pins
Warning (13410): Pin "SA[0]" is stuck at GND Info (21061): Implemented 235 logic cells
Warning (13410): Pin "SA[1]" is stuck at GND
Warning (13410): Pin "SA[2]" is stuck at GND
Warning (13410): Pin "SA[3]" is stuck at GND
Warning (13410): Pin "SA[4]" is stuck at GND
Warning (13410): Pin "SA[5]" is stuck at GND
Warning (13410): Pin "SA[6]" is stuck at GND
Warning (13410): Pin "SA[7]" is stuck at GND
Warning (13410): Pin "SA[8]" is stuck at GND
Warning (13410): Pin "SA[9]" is stuck at GND
Warning (13410): Pin "SA[10]" is stuck at GND
Warning (13410): Pin "SA[11]" is stuck at GND
Info (21057): Implemented 306 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 24 input pins
Info (21059): Implemented 28 output pins
Info (21060): Implemented 16 bidirectional pins
Info (21061): Implemented 237 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 33 warnings Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 301 megabytes Info: Peak virtual memory: 301 megabytes
Info: Processing ended: Fri Mar 19 16:35:14 2021 Info: Processing ended: Mon Mar 22 12:12:11 2021
Info: Elapsed time: 00:00:05 Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05 Info: Total CPU time (on all processors): 00:00:05

6
cpld/output_files/GR8RAM.map.smsg
View File

@ -1,4 +1,2 @@
Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword Warning (10273): Verilog HDL warning at GR8RAM.v(80): extended using "x" or "z"
Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword Warning (10273): Verilog HDL warning at GR8RAM.v(255): extended using "x" or "z"
Warning (10273): Verilog HDL warning at gr8ram.v(85): extended using "x" or "z"
Warning (10273): Verilog HDL warning at gr8ram.v(314): extended using "x" or "z"

8
cpld/output_files/GR8RAM.map.summary
View File

@ -1,9 +1,9 @@
Analysis & Synthesis Status : Successful - Fri Mar 19 16:35:14 2021 Analysis & Synthesis Status : Successful - Mon Mar 22 12:12:11 2021
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM Revision Name : GR8RAM
Top-level Entity Name : GR8RAM Top-level Entity Name : GR8RAM
Family : MAX II Family : MAX II
Total logic elements : 237 Total logic elements : 235
Total pins : 68 Total pins : 69
Total virtual pins : 0 Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % ) UFM blocks : 0 / 1 ( 0 % )

148
cpld/output_files/GR8RAM.pin
View File

@ -62,103 +62,103 @@ CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------
SA[0] : 1 : output : 3.3-V LVTTL : : 2 : N SBA[0] : 1 : output : 3.3-V LVTTL : : 2 : N
GND* : 2 : : : : 1 : nCAS : 2 : output : 3.3-V LVTTL : : 1 : N
SA[8] : 3 : output : 3.3-V LVTTL : : 1 : N MOSI : 3 : bidir : 3.3-V LVTTL : : 1 : N
SA[2] : 4 : output : 3.3-V LVTTL : : 1 : N nRAS : 4 : output : 3.3-V LVTTL : : 1 : N
RAdir : 5 : output : 3.3-V LVTTL : : 1 : N nRCS : 5 : output : 3.3-V LVTTL : : 1 : N
SD[5] : 6 : bidir : 3.3-V LVTTL : : 1 : N nRES : 6 : input : 3.3-V LVTTL : : 1 : N
SD[4] : 7 : bidir : 3.3-V LVTTL : : 1 : N RCKE : 7 : output : 3.3-V LVTTL : : 1 : N
SD[1] : 8 : bidir : 3.3-V LVTTL : : 1 : N SetLim8M : 8 : input : 3.3-V LVTTL : : 1 : N
VCCIO1 : 9 : power : : 3.3V : 1 : VCCIO1 : 9 : power : : 3.3V : 1 :
GNDIO : 10 : gnd : : : : GNDIO : 10 : gnd : : : :
GNDINT : 11 : gnd : : : : GNDINT : 11 : gnd : : : :
RA[3] : 12 : input : 3.3-V LVTTL : : 1 : N nDEVSEL : 12 : input : 3.3-V LVTTL : : 1 : N
VCCINT : 13 : power : : 2.5V/3.3V : : VCCINT : 13 : power : : 2.5V/3.3V : :
C25M : 14 : input : 3.3-V LVTTL : : 1 : N C25M : 14 : input : 3.3-V LVTTL : : 1 : N
RA[5] : 15 : input : 3.3-V LVTTL : : 1 : N SD[2] : 15 : bidir : 3.3-V LVTTL : : 1 : N
RA[2] : 16 : input : 3.3-V LVTTL : : 1 : N RA[10] : 16 : input : 3.3-V LVTTL : : 1 : N
RA[0] : 17 : input : 3.3-V LVTTL : : 1 : N SD[1] : 17 : bidir : 3.3-V LVTTL : : 1 : N
SD[6] : 18 : bidir : 3.3-V LVTTL : : 1 : N RA[8] : 18 : input : 3.3-V LVTTL : : 1 : N
nRESout : 19 : output : 3.3-V LVTTL : : 1 : N RA[7] : 19 : input : 3.3-V LVTTL : : 1 : N
SD[7] : 20 : bidir : 3.3-V LVTTL : : 1 : N RA[11] : 20 : input : 3.3-V LVTTL : : 1 : N
MOSI : 21 : output : 3.3-V LVTTL : : 1 : N RA[9] : 21 : input : 3.3-V LVTTL : : 1 : N
TMS : 22 : input : : : 1 : TMS : 22 : input : : : 1 :
TDI : 23 : input : : : 1 : TDI : 23 : input : : : 1 :
TCK : 24 : input : : : 1 : TCK : 24 : input : : : 1 :
TDO : 25 : output : : : 1 : TDO : 25 : output : : : 1 :
SD[3] : 26 : bidir : 3.3-V LVTTL : : 1 : N GND* : 26 : : : : 1 :
SD[2] : 27 : bidir : 3.3-V LVTTL : : 1 : N nFCS : 27 : output : 3.3-V LVTTL : : 1 : N
MISO : 28 : input : 3.3-V LVTTL : : 1 : N GND* : 28 : : : : 1 :
SD[0] : 29 : bidir : 3.3-V LVTTL : : 1 : N GND* : 29 : : : : 1 :
FCK : 30 : output : 3.3-V LVTTL : : 1 : N SBA[1] : 30 : output : 3.3-V LVTTL : : 1 : N
VCCIO1 : 31 : power : : 3.3V : 1 : VCCIO1 : 31 : power : : 3.3V : 1 :
GNDIO : 32 : gnd : : : : GNDIO : 32 : gnd : : : :
RA[8] : 33 : input : 3.3-V LVTTL : : 1 : N SD[3] : 33 : bidir : 3.3-V LVTTL : : 1 : N
RA[10] : 34 : input : 3.3-V LVTTL : : 1 : N SD[0] : 34 : bidir : 3.3-V LVTTL : : 1 : N
RA[7] : 35 : input : 3.3-V LVTTL : : 1 : N SA[2] : 35 : output : 3.3-V LVTTL : : 1 : N
RA[4] : 36 : input : 3.3-V LVTTL : : 1 : N FCK : 36 : output : 3.3-V LVTTL : : 1 : N
RA[9] : 37 : input : 3.3-V LVTTL : : 1 : N SA[1] : 37 : output : 3.3-V LVTTL : : 1 : N
RA[1] : 38 : input : 3.3-V LVTTL : : 1 : N SA[0] : 38 : output : 3.3-V LVTTL : : 1 : N
RA[11] : 39 : input : 3.3-V LVTTL : : 1 : N SA[5] : 39 : output : 3.3-V LVTTL : : 1 : N
GND* : 40 : : : : 1 : RA[6] : 40 : input : 3.3-V LVTTL : : 1 : N
GND* : 41 : : : : 1 : RA[4] : 41 : input : 3.3-V LVTTL : : 1 : N
SA[11] : 42 : output : 3.3-V LVTTL : : 1 : N nIOSTRB : 42 : input : 3.3-V LVTTL : : 1 : N
nFCS : 43 : output : 3.3-V LVTTL : : 1 : N SA[3] : 43 : output : 3.3-V LVTTL : : 1 : N
SA[12] : 44 : output : 3.3-V LVTTL : : 1 : N SA[6] : 44 : output : 3.3-V LVTTL : : 1 : N
VCCIO1 : 45 : power : : 3.3V : 1 : VCCIO1 : 45 : power : : 3.3V : 1 :
GNDIO : 46 : gnd : : : : GNDIO : 46 : gnd : : : :
GND* : 47 : : : : 1 : GND* : 47 : : : : 1 :
DQMH : 48 : output : 3.3-V LVTTL : : 1 : N SA[7] : 48 : output : 3.3-V LVTTL : : 1 : N
GND* : 49 : : : : 1 : GND* : 49 : : : : 1 :
GND* : 50 : : : : 1 : GND* : 50 : : : : 1 :
GND* : 51 : : : : 1 : GND* : 51 : : : : 1 :
SA[9] : 52 : output : 3.3-V LVTTL : : 2 : N RD[0] : 52 : bidir : 3.3-V LVTTL : : 2 : N
GND* : 53 : : : : 2 : RA[3] : 53 : input : 3.3-V LVTTL : : 2 : N
SA[4] : 54 : output : 3.3-V LVTTL : : 2 : N RD[3] : 54 : bidir : 3.3-V LVTTL : : 2 : N
SA[10] : 55 : output : 3.3-V LVTTL : : 2 : N RDdir : 55 : output : 3.3-V LVTTL : : 2 : N
GND* : 56 : : : : 2 : RA[2] : 56 : input : 3.3-V LVTTL : : 2 : N
RA[13] : 57 : input : 3.3-V LVTTL : : 2 : N RD[2] : 57 : bidir : 3.3-V LVTTL : : 2 : N
RA[12] : 58 : input : 3.3-V LVTTL : : 2 : N SA[8] : 58 : output : 3.3-V LVTTL : : 2 : N
VCCIO2 : 59 : power : : 3.3V : 2 : VCCIO2 : 59 : power : : 3.3V : 2 :
GNDIO : 60 : gnd : : : : GNDIO : 60 : gnd : : : :
RA[14] : 61 : input : 3.3-V LVTTL : : 2 : N RD[1] : 61 : bidir : 3.3-V LVTTL : : 2 : N
RA[15] : 62 : input : 3.3-V LVTTL : : 2 : N RA[5] : 62 : input : 3.3-V LVTTL : : 2 : N
VCCINT : 63 : power : : 2.5V/3.3V : : VCCINT : 63 : power : : 2.5V/3.3V : :
nIOSTRB : 64 : input : 3.3-V LVTTL : : 2 : N RA[1] : 64 : input : 3.3-V LVTTL : : 2 : N
GNDINT : 65 : gnd : : : : GNDINT : 65 : gnd : : : :
DQML : 66 : output : 3.3-V LVTTL : : 2 : N nIOSEL : 66 : input : 3.3-V LVTTL : : 2 : N
nDEVSEL : 67 : input : 3.3-V LVTTL : : 2 : N RA[0] : 67 : input : 3.3-V LVTTL : : 2 : N
SBA[1] : 68 : output : 3.3-V LVTTL : : 2 : N SetRF : 68 : input : 3.3-V LVTTL : : 2 : N
nRAS : 69 : output : 3.3-V LVTTL : : 2 : N GND* : 69 : : : : 2 :
RCKE : 70 : output : 3.3-V LVTTL : : 2 : N SA[11] : 70 : output : 3.3-V LVTTL : : 2 : N
nIOSEL : 71 : input : 3.3-V LVTTL : : 2 : N SA[9] : 71 : output : 3.3-V LVTTL : : 2 : N
PHI0 : 72 : input : 3.3-V LVTTL : : 2 : N RA[13] : 72 : input : 3.3-V LVTTL : : 2 : N
nRES : 73 : input : 3.3-V LVTTL : : 2 : N RA[12] : 73 : input : 3.3-V LVTTL : : 2 : N
nWE : 74 : input : 3.3-V LVTTL : : 2 : N RA[15] : 74 : input : 3.3-V LVTTL : : 2 : N
RDdir : 75 : output : 3.3-V LVTTL : : 2 : N RA[14] : 75 : input : 3.3-V LVTTL : : 2 : N
GND* : 76 : : : : 2 : SA[12] : 76 : output : 3.3-V LVTTL : : 2 : N
SA[5] : 77 : output : 3.3-V LVTTL : : 2 : N GND* : 77 : : : : 2 :
GND* : 78 : : : : 2 : GND* : 78 : : : : 2 :
GNDIO : 79 : gnd : : : : GNDIO : 79 : gnd : : : :
VCCIO2 : 80 : power : : 3.3V : 2 : VCCIO2 : 80 : power : : 3.3V : 2 :
SA[7] : 81 : output : 3.3-V LVTTL : : 2 : N RD[5] : 81 : bidir : 3.3-V LVTTL : : 2 : N
nSWE : 82 : output : 3.3-V LVTTL : : 2 : N RD[6] : 82 : bidir : 3.3-V LVTTL : : 2 : N
nCAS : 83 : output : 3.3-V LVTTL : : 2 : N RD[7] : 83 : bidir : 3.3-V LVTTL : : 2 : N
nRCS : 84 : output : 3.3-V LVTTL : : 2 : N RD[4] : 84 : bidir : 3.3-V LVTTL : : 2 : N
RD[2] : 85 : bidir : 3.3-V LVTTL : : 2 : N SA[10] : 85 : output : 3.3-V LVTTL : : 2 : N
SBA[0] : 86 : output : 3.3-V LVTTL : : 2 : N DQML : 86 : output : 3.3-V LVTTL : : 2 : N
RD[7] : 87 : bidir : 3.3-V LVTTL : : 2 : N DQMH : 87 : output : 3.3-V LVTTL : : 2 : N
SA[3] : 88 : output : 3.3-V LVTTL : : 2 : N PHI0 : 88 : input : 3.3-V LVTTL : : 2 : N
RD[6] : 89 : bidir : 3.3-V LVTTL : : 2 : N nSWE : 89 : output : 3.3-V LVTTL : : 2 : N
RD[1] : 90 : bidir : 3.3-V LVTTL : : 2 : N nWE : 90 : input : 3.3-V LVTTL : : 2 : N
RA[6] : 91 : input : 3.3-V LVTTL : : 2 : N SA[4] : 91 : output : 3.3-V LVTTL : : 2 : N
RD[0] : 92 : bidir : 3.3-V LVTTL : : 2 : N SD[5] : 92 : bidir : 3.3-V LVTTL : : 2 : N
GNDIO : 93 : gnd : : : : GNDIO : 93 : gnd : : : :
VCCIO2 : 94 : power : : 3.3V : 2 : VCCIO2 : 94 : power : : 3.3V : 2 :
RD[4] : 95 : bidir : 3.3-V LVTTL : : 2 : N SD[6] : 95 : bidir : 3.3-V LVTTL : : 2 : N
RD[3] : 96 : bidir : 3.3-V LVTTL : : 2 : N SD[4] : 96 : bidir : 3.3-V LVTTL : : 2 : N
RD[5] : 97 : bidir : 3.3-V LVTTL : : 2 : N SD[7] : 97 : bidir : 3.3-V LVTTL : : 2 : N
SA[6] : 98 : output : 3.3-V LVTTL : : 2 : N MISO : 98 : input : 3.3-V LVTTL : : 2 : N
GND* : 99 : : : : 2 : nRESout : 99 : output : 3.3-V LVTTL : : 2 : N
SA[1] : 100 : output : 3.3-V LVTTL : : 2 : N GND* : 100 : : : : 2 :

BIN
cpld/output_files/GR8RAM.pof
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1608
cpld/output_files/GR8RAM.sta.rpt
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34
cpld/output_files/GR8RAM.sta.summary
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@ -2,37 +2,21 @@
TimeQuest Timing Analyzer Summary TimeQuest Timing Analyzer Summary
------------------------------------------------------------ ------------------------------------------------------------
Type : Setup 'ARCLK'
Slack : -99.000
TNS : -99.000
Type : Setup 'DRCLK'
Slack : -99.000
TNS : -99.000
Type : Setup 'C25M' Type : Setup 'C25M'
Slack : -9.555 Slack : -9.843
TNS : -547.115 TNS : -651.483
Type : Hold 'ARCLK'
Slack : -16.276
TNS : -16.276
Type : Hold 'DRCLK'
Slack : -16.256
TNS : -16.256
Type : Hold 'C25M' Type : Hold 'C25M'
Slack : 1.377 Slack : 1.395
TNS : 0.000 TNS : 0.000
Type : Minimum Pulse Width 'ARCLK' Type : Recovery 'C25M'
Slack : -29.500 Slack : -4.404
TNS : -59.000 TNS : -132.120
Type : Minimum Pulse Width 'DRCLK' Type : Removal 'C25M'
Slack : -29.500 Slack : 4.850
TNS : -59.000 TNS : 0.000
Type : Minimum Pulse Width 'C25M' Type : Minimum Pulse Width 'C25M'
Slack : -2.289 Slack : -2.289

8
cpld/serv_req_info.txt Executable file
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<internal_error>
<executable>quartus.exe</executable>
<sub_system>MEM</sub_system>
<error>*** Fatal Error: Out of memory in module quartus.exe (1999 megabytes used)</error>
<date>Mon Mar 22 01:13:02 2021</date>
<version>Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition</version>
</internal_error>