mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-06-16 00:29:36 +00:00
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6
.gitignore
vendored
6
.gitignore
vendored
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@ -24,7 +24,7 @@ GR8RAM-backups/*
|
||||||
*.ses
|
*.ses
|
||||||
|
|
||||||
*.DS_Store
|
*.DS_Store
|
||||||
cpld/db/GR8RAM.db_info
|
*.kicad_prl
|
||||||
cpld/db/GR8RAM.tmw_info
|
cpld/db/*
|
||||||
|
cpld/incremental_db/*
|
||||||
cpld/GR8RAM.qws
|
cpld/GR8RAM.qws
|
||||||
Documentation/~$4205AManual.docx
|
|
||||||
|
|
31
cpld/GR8RAM.qpf
Executable file → Normal file
31
cpld/GR8RAM.qpf
Executable file → Normal file
|
@ -1,29 +1,30 @@
|
||||||
# -------------------------------------------------------------------------- #
|
# -------------------------------------------------------------------------- #
|
||||||
#
|
#
|
||||||
# Copyright (C) 1991-2013 Altera Corporation
|
# Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
# Your use of Altera Corporation's design tools, logic functions
|
# Your use of Intel Corporation's design tools, logic functions
|
||||||
# and other software and tools, and its AMPP partner logic
|
# and other software and tools, and any partner logic
|
||||||
# functions, and any output files from any of the foregoing
|
# functions, and any output files from any of the foregoing
|
||||||
# (including device programming or simulation files), and any
|
# (including device programming or simulation files), and any
|
||||||
# associated documentation or information are expressly subject
|
# associated documentation or information are expressly subject
|
||||||
# to the terms and conditions of the Altera Program License
|
# to the terms and conditions of the Intel Program License
|
||||||
# Subscription Agreement, Altera MegaCore Function License
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
# Agreement, or other applicable license agreement, including,
|
# the Intel FPGA IP License Agreement, or other applicable license
|
||||||
# without limitation, that your use is for the sole purpose of
|
# agreement, including, without limitation, that your use is for
|
||||||
# programming logic devices manufactured by Altera and sold by
|
# the sole purpose of programming logic devices manufactured by
|
||||||
# Altera or its authorized distributors. Please refer to the
|
# Intel and sold by Intel or its authorized distributors. Please
|
||||||
# applicable agreement for further details.
|
# refer to the applicable agreement for further details, at
|
||||||
|
# https://fpgasoftware.intel.com/eula.
|
||||||
#
|
#
|
||||||
# -------------------------------------------------------------------------- #
|
# -------------------------------------------------------------------------- #
|
||||||
#
|
#
|
||||||
# Quartus II 32-bit
|
# Quartus Prime
|
||||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
# Date created = 13:41:40 March 15, 2021
|
# Date created = 20:42:53 February 16, 2024
|
||||||
#
|
#
|
||||||
# -------------------------------------------------------------------------- #
|
# -------------------------------------------------------------------------- #
|
||||||
|
|
||||||
QUARTUS_VERSION = "13.0"
|
QUARTUS_VERSION = "19.1"
|
||||||
DATE = "13:41:40 March 15, 2021"
|
DATE = "20:42:53 February 16, 2024"
|
||||||
|
|
||||||
# Revisions
|
# Revisions
|
||||||
|
|
||||||
|
|
62
cpld/GR8RAM.qsf
Executable file → Normal file
62
cpld/GR8RAM.qsf
Executable file → Normal file
|
@ -1,24 +1,25 @@
|
||||||
# -------------------------------------------------------------------------- #
|
# -------------------------------------------------------------------------- #
|
||||||
#
|
#
|
||||||
# Copyright (C) 1991-2013 Altera Corporation
|
# Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
# Your use of Altera Corporation's design tools, logic functions
|
# Your use of Intel Corporation's design tools, logic functions
|
||||||
# and other software and tools, and its AMPP partner logic
|
# and other software and tools, and any partner logic
|
||||||
# functions, and any output files from any of the foregoing
|
# functions, and any output files from any of the foregoing
|
||||||
# (including device programming or simulation files), and any
|
# (including device programming or simulation files), and any
|
||||||
# associated documentation or information are expressly subject
|
# associated documentation or information are expressly subject
|
||||||
# to the terms and conditions of the Altera Program License
|
# to the terms and conditions of the Intel Program License
|
||||||
# Subscription Agreement, Altera MegaCore Function License
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
# Agreement, or other applicable license agreement, including,
|
# the Intel FPGA IP License Agreement, or other applicable license
|
||||||
# without limitation, that your use is for the sole purpose of
|
# agreement, including, without limitation, that your use is for
|
||||||
# programming logic devices manufactured by Altera and sold by
|
# the sole purpose of programming logic devices manufactured by
|
||||||
# Altera or its authorized distributors. Please refer to the
|
# Intel and sold by Intel or its authorized distributors. Please
|
||||||
# applicable agreement for further details.
|
# refer to the applicable agreement for further details, at
|
||||||
|
# https://fpgasoftware.intel.com/eula.
|
||||||
#
|
#
|
||||||
# -------------------------------------------------------------------------- #
|
# -------------------------------------------------------------------------- #
|
||||||
#
|
#
|
||||||
# Quartus II 32-bit
|
# Quartus Prime
|
||||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
# Date created = 13:41:40 March 15, 2021
|
# Date created = 20:36:06 February 16, 2024
|
||||||
#
|
#
|
||||||
# -------------------------------------------------------------------------- #
|
# -------------------------------------------------------------------------- #
|
||||||
#
|
#
|
||||||
|
@ -30,7 +31,7 @@
|
||||||
# assignment_defaults.qdf
|
# assignment_defaults.qdf
|
||||||
#
|
#
|
||||||
# 2) Altera recommends that you do not modify this file. This
|
# 2) Altera recommends that you do not modify this file. This
|
||||||
# file is updated automatically by the Quartus II software
|
# file is updated automatically by the Quartus Prime software
|
||||||
# and any changes you make may be lost or overwritten.
|
# and any changes you make may be lost or overwritten.
|
||||||
#
|
#
|
||||||
# -------------------------------------------------------------------------- #
|
# -------------------------------------------------------------------------- #
|
||||||
|
@ -39,9 +40,11 @@
|
||||||
set_global_assignment -name FAMILY "MAX II"
|
set_global_assignment -name FAMILY "MAX II"
|
||||||
set_global_assignment -name DEVICE EPM240T100C5
|
set_global_assignment -name DEVICE EPM240T100C5
|
||||||
set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
|
set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
|
||||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
|
||||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:41:40 MARCH 15, 2021"
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:36:06 FEBRUARY 16, 2024"
|
||||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
|
||||||
|
set_global_assignment -name SDC_FILE GR8RAM.sdc
|
||||||
|
set_global_assignment -name VERILOG_FILE GR8RAM.v
|
||||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||||
|
@ -50,29 +53,7 @@ set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
|
||||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
|
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
|
||||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
|
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
|
||||||
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
|
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
|
||||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
|
|
||||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
|
|
||||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
|
||||||
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
|
|
||||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
|
|
||||||
set_global_assignment -name SAFE_STATE_MACHINE OFF
|
|
||||||
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
|
|
||||||
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS
|
|
||||||
set_global_assignment -name AUTO_RESOURCE_SHARING ON
|
|
||||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
|
|
||||||
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
|
|
||||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
|
|
||||||
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH
|
|
||||||
set_global_assignment -name MUX_RESTRUCTURE ON
|
|
||||||
set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS"
|
|
||||||
set_global_assignment -name SYNTHESIS_SEED 123
|
|
||||||
set_global_assignment -name SEED 235
|
|
||||||
set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII "MINIMIZE AREA"
|
|
||||||
set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF
|
|
||||||
set_global_assignment -name VERILOG_FILE GR8RAM.v
|
|
||||||
set_location_assignment PIN_1 -to RA[4]
|
|
||||||
set_location_assignment PIN_2 -to RA[5]
|
set_location_assignment PIN_2 -to RA[5]
|
||||||
set_location_assignment PIN_3 -to RA[6]
|
set_location_assignment PIN_3 -to RA[6]
|
||||||
set_location_assignment PIN_4 -to RA[3]
|
set_location_assignment PIN_4 -to RA[3]
|
||||||
|
@ -269,4 +250,3 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD
|
||||||
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SD
|
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SD
|
||||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to SD
|
set_instance_assignment -name SLOW_SLEW_RATE ON -to SD
|
||||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD
|
||||||
set_global_assignment -name SDC_FILE GR8RAM.sdc
|
|
0
cpld/GR8RAM.sdc
Executable file → Normal file
0
cpld/GR8RAM.sdc
Executable file → Normal file
|
@ -24,7 +24,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
reg [1:0] SetFWr;
|
reg [1:0] SetFWr;
|
||||||
reg SetFWLoaded = 0;
|
reg SetFWLoaded = 0;
|
||||||
always @(posedge C25M) begin
|
always @(posedge C25M) begin
|
||||||
if (~SetFWLoaded) begin
|
if (!SetFWLoaded) begin
|
||||||
SetFWLoaded <= 1;
|
SetFWLoaded <= 1;
|
||||||
SetFWr[1:0] <= SetFW[1:0];
|
SetFWr[1:0] <= SetFW[1:0];
|
||||||
end
|
end
|
||||||
|
@ -35,7 +35,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
|
|
||||||
/* State counter from PHI0 rising edge */
|
/* State counter from PHI0 rising edge */
|
||||||
reg [3:0] PS = 0;
|
reg [3:0] PS = 0;
|
||||||
wire PSStart = PS==0 && PHI0r1 && ~PHI0r2;
|
wire PSStart = PS==0 && PHI0r1 && !PHI0r2;
|
||||||
always @(posedge C25M) begin
|
always @(posedge C25M) begin
|
||||||
if (PSStart) PS <= 1;
|
if (PSStart) PS <= 1;
|
||||||
else if (PS==0) PS <= 0;
|
else if (PS==0) PS <= 0;
|
||||||
|
@ -74,43 +74,43 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
end
|
end
|
||||||
|
|
||||||
/* Apple select signals */
|
/* Apple select signals */
|
||||||
wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11]));
|
wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (!RAr[11]));
|
||||||
wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
|
wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
|
||||||
wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
|
wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
|
||||||
wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
|
wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
|
||||||
wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]);
|
wire RAMSpecSEL = RAMRegSpecSEL && (!SetEN24bit || SetEN16MB || !Addr[23]);
|
||||||
wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
|
wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
|
||||||
wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1;
|
wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1;
|
||||||
wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0;
|
wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0;
|
||||||
wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL;
|
wire BankSEL = REGEN && !nDEVSEL && BankSpecSEL;
|
||||||
wire RAMRegSEL = ~nDEVSEL && RAMRegSpecSEL;
|
wire RAMRegSEL = !nDEVSEL && RAMRegSpecSEL;
|
||||||
wire RAMSEL = ~nDEVSEL && RAMSpecSEL;
|
wire RAMSEL = !nDEVSEL && RAMSpecSEL;
|
||||||
wire RAMWR = RAMSEL && ~nWEr;
|
wire RAMWR = RAMSEL && !nWEr;
|
||||||
wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL;
|
wire AddrHSEL = REGEN && !nDEVSEL && AddrHSpecSEL;
|
||||||
wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL;
|
wire AddrMSEL = REGEN && !nDEVSEL && AddrMSpecSEL;
|
||||||
wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL;
|
wire AddrLSEL = REGEN && !nDEVSEL && AddrLSpecSEL;
|
||||||
|
|
||||||
/* IOROMEN and REGEN control */
|
/* IOROMEN and REGEN control */
|
||||||
reg IOROMEN = 0;
|
reg IOROMEN = 0;
|
||||||
reg REGEN = 0;
|
reg REGEN = 0;
|
||||||
reg nIOSTRBr;
|
reg nIOSTRBr;
|
||||||
wire IOROMRES = RAr[10:0]==11'h7FF && ~nIOSTRB && ~nIOSTRBr;
|
wire IOROMRES = RAr[10:0]==11'h7FF && !nIOSTRB && !nIOSTRBr;
|
||||||
always @(posedge C25M, negedge nRESr) begin
|
always @(posedge C25M, negedge nRESr) begin
|
||||||
if (~nRESr) REGEN <= 0;
|
if (!nRESr) REGEN <= 0;
|
||||||
else if (PS==8 && ~nIOSEL) REGEN <= 1;
|
else if (PS==8 && !nIOSEL) REGEN <= 1;
|
||||||
end
|
end
|
||||||
always @(posedge C25M) begin
|
always @(posedge C25M) begin
|
||||||
nIOSTRBr <= nIOSTRB;
|
nIOSTRBr <= nIOSTRB;
|
||||||
if (~nRESr) IOROMEN <= 0;
|
if (!nRESr) IOROMEN <= 0;
|
||||||
else if (PS==8 && IOROMRES) IOROMEN <= 0;
|
else if (PS==8 && IOROMRES) IOROMEN <= 0;
|
||||||
else if (PS==8 && ~nIOSEL) IOROMEN <= 1;
|
else if (PS==8 && !nIOSEL) IOROMEN <= 1;
|
||||||
end
|
end
|
||||||
|
|
||||||
/* Apple data bus */
|
/* Apple data bus */
|
||||||
inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
|
inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
|
||||||
reg [7:0] RDD;
|
reg [7:0] RDD;
|
||||||
output RDdir = ~(PHI0r2 && nWE && PHI0 &&
|
output RDdir = !(PHI0r2 && nWE && PHI0 &&
|
||||||
(~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF)));
|
(!nDEVSEL || !nIOSEL || (!nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF)));
|
||||||
|
|
||||||
/* Slinky address registers */
|
/* Slinky address registers */
|
||||||
reg [23:0] Addr = 0;
|
reg [23:0] Addr = 0;
|
||||||
|
@ -118,7 +118,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
reg AddrIncM = 0;
|
reg AddrIncM = 0;
|
||||||
reg AddrIncH = 0;
|
reg AddrIncH = 0;
|
||||||
always @(posedge C25M, negedge nRESr) begin
|
always @(posedge C25M, negedge nRESr) begin
|
||||||
if (~nRESr) begin
|
if (!nRESr) begin
|
||||||
Addr[23:0] <= 24'h000000;
|
Addr[23:0] <= 24'h000000;
|
||||||
AddrIncL <= 0;
|
AddrIncL <= 0;
|
||||||
AddrIncM <= 0;
|
AddrIncM <= 0;
|
||||||
|
@ -127,23 +127,23 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
if (PS==8 && RAMRegSEL) AddrIncL <= 1;
|
if (PS==8 && RAMRegSEL) AddrIncL <= 1;
|
||||||
else AddrIncL <= 0;
|
else AddrIncL <= 0;
|
||||||
|
|
||||||
if (PS==8 && AddrLSEL && ~nWEr) begin
|
if (PS==8 && AddrLSEL && !nWEr) begin
|
||||||
Addr[7:0] <= RD[7:0];
|
Addr[7:0] <= RD[7:0];
|
||||||
AddrIncM <= Addr[7] && ~RD[7];
|
AddrIncM <= Addr[7] && !RD[7];
|
||||||
end else if (AddrIncL) begin
|
end else if (AddrIncL) begin
|
||||||
Addr[7:0] <= Addr[7:0]+1;
|
Addr[7:0] <= Addr[7:0]+1;
|
||||||
AddrIncM <= Addr[7:0]==8'hFF;
|
AddrIncM <= Addr[7:0]==8'hFF;
|
||||||
end else AddrIncM <= 0;
|
end else AddrIncM <= 0;
|
||||||
|
|
||||||
if (PS==8 && AddrMSEL && ~nWEr) begin
|
if (PS==8 && AddrMSEL && !nWEr) begin
|
||||||
Addr[15:8] <= RD[7:0];
|
Addr[15:8] <= RD[7:0];
|
||||||
AddrIncH <= Addr[15] && ~RD[7];
|
AddrIncH <= Addr[15] && !RD[7];
|
||||||
end else if (AddrIncM) begin
|
end else if (AddrIncM) begin
|
||||||
Addr[15:8] <= Addr[15:8]+1;
|
Addr[15:8] <= Addr[15:8]+1;
|
||||||
AddrIncH <= Addr[15:8]==8'hFF;
|
AddrIncH <= Addr[15:8]==8'hFF;
|
||||||
end else AddrIncH <= 0;
|
end else AddrIncH <= 0;
|
||||||
|
|
||||||
if (PS==8 && AddrHSEL && ~nWEr) begin
|
if (PS==8 && AddrHSEL && !nWEr) begin
|
||||||
Addr[23:16] <= RD[7:0];
|
Addr[23:16] <= RD[7:0];
|
||||||
end else if (AddrIncH) begin
|
end else if (AddrIncH) begin
|
||||||
Addr[23:16] <= Addr[23:16]+1;
|
Addr[23:16] <= Addr[23:16]+1;
|
||||||
|
@ -154,14 +154,14 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
/* ROM bank register */
|
/* ROM bank register */
|
||||||
reg Bank = 0;
|
reg Bank = 0;
|
||||||
always @(posedge C25M, negedge nRESr) begin
|
always @(posedge C25M, negedge nRESr) begin
|
||||||
if (~nRESr) Bank <= 0;
|
if (!nRESr) Bank <= 0;
|
||||||
else if (PS==8 && BankSEL && ~nWEr) begin
|
else if (PS==8 && BankSEL && !nWEr) begin
|
||||||
Bank <= RD[0];
|
Bank <= RD[0];
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
/* SPI flash control signals */
|
/* SPI flash control signals */
|
||||||
output nFCS = FCKOE ? ~FCS : 1'bZ;
|
output nFCS = FCKOE ? !FCS : 1'bZ;
|
||||||
reg FCS = 0;
|
reg FCS = 0;
|
||||||
output FCK = FCKOE ? FCKout : 1'bZ;
|
output FCK = FCKOE ? FCKout : 1'bZ;
|
||||||
reg FCKOE = 0;
|
reg FCKOE = 0;
|
||||||
|
@ -174,35 +174,35 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
0: begin // NOP CKE
|
0: begin // NOP CKE
|
||||||
FCKout <= 1'b1;
|
FCKout <= 1'b1;
|
||||||
end 1: begin // ACT
|
end 1: begin // ACT
|
||||||
FCKout <= ~(IS==5 || IS==6);
|
FCKout <= !(IS==5 || IS==6);
|
||||||
end 2: begin // RD
|
end 2: begin // RD
|
||||||
FCKout <= 1'b1;
|
FCKout <= 1'b1;
|
||||||
end 3: begin // NOP CKE
|
end 3: begin // NOP CKE
|
||||||
FCKout <= ~(IS==5 || IS==6);
|
FCKout <= !(IS==5 || IS==6);
|
||||||
end 4: begin // NOP CKE
|
end 4: begin // NOP CKE
|
||||||
FCKout <= 1'b1;
|
FCKout <= 1'b1;
|
||||||
end 5: begin // NOP CKE
|
end 5: begin // NOP CKE
|
||||||
FCKout <= ~(IS==5 || IS==6);
|
FCKout <= !(IS==5 || IS==6);
|
||||||
end 6: begin // NOP CKE
|
end 6: begin // NOP CKE
|
||||||
FCKout <= 1'b1;
|
FCKout <= 1'b1;
|
||||||
end 7: begin // NOP CKE
|
end 7: begin // NOP CKE
|
||||||
FCKout <= ~(IS==5 || IS==6);
|
FCKout <= !(IS==5 || IS==6);
|
||||||
end 8: begin // WR AP
|
end 8: begin // WR AP
|
||||||
FCKout <= 1'b1;
|
FCKout <= 1'b1;
|
||||||
end 9: begin // NOP CKE
|
end 9: begin // NOP CKE
|
||||||
FCKout <= ~(IS==5);
|
FCKout <= !(IS==5);
|
||||||
end 10: begin // PC all
|
end 10: begin // PC all
|
||||||
FCKout <= 1'b1;
|
FCKout <= 1'b1;
|
||||||
end 11: begin // AREF
|
end 11: begin // AREF
|
||||||
FCKout <= ~(IS==5);
|
FCKout <= !(IS==5);
|
||||||
end 12: begin // NOP CKE
|
end 12: begin // NOP CKE
|
||||||
FCKout <= 1'b1;
|
FCKout <= 1'b1;
|
||||||
end 13: begin // NOP CKE
|
end 13: begin // NOP CKE
|
||||||
FCKout <= ~(IS==5);
|
FCKout <= !(IS==5);
|
||||||
end 14: begin // NOP CKE
|
end 14: begin // NOP CKE
|
||||||
FCKout <= 1'b1;
|
FCKout <= 1'b1;
|
||||||
end 15: begin // NOP CKE
|
end 15: begin // NOP CKE
|
||||||
FCKout <= ~(IS==5);
|
FCKout <= !(IS==5);
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
FCS <= IS==4 || IS==5 || IS==6;
|
FCS <= IS==4 || IS==5 || IS==6;
|
||||||
|
@ -352,14 +352,14 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
SDOE <= 0;
|
SDOE <= 0;
|
||||||
end 1: begin // ACT CKE / NOP CKD (ACT)
|
end 1: begin // ACT CKE / NOP CKD (ACT)
|
||||||
RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL));
|
RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL));
|
||||||
nRCS <= ~(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
|
nRCS <= !(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
|
||||||
nRAS <= 0;
|
nRAS <= 0;
|
||||||
nCAS <= 1;
|
nCAS <= 1;
|
||||||
nSWE <= 1;
|
nSWE <= 1;
|
||||||
SDOE <= 0;
|
SDOE <= 0;
|
||||||
end 2: begin // RD CKE / NOP CKD (RD)
|
end 2: begin // RD CKE / NOP CKD (RD)
|
||||||
RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
|
RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
|
||||||
nRCS <= ~(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL));
|
nRCS <= !(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL));
|
||||||
nRAS <= 1;
|
nRAS <= 1;
|
||||||
nCAS <= 0;
|
nCAS <= 0;
|
||||||
nSWE <= 1;
|
nSWE <= 1;
|
||||||
|
@ -401,7 +401,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
SDOE <= 0;
|
SDOE <= 0;
|
||||||
end 8: begin // WR AP CKE / NOP CKD (WR AP)
|
end 8: begin // WR AP CKE / NOP CKD (WR AP)
|
||||||
RCKE <= IS==6 || (RAMWR && IS==7);
|
RCKE <= IS==6 || (RAMWR && IS==7);
|
||||||
nRCS <= ~(IS==6 || (RAMWR && IS==7));
|
nRCS <= !(IS==6 || (RAMWR && IS==7));
|
||||||
nRAS <= 1;
|
nRAS <= 1;
|
||||||
nCAS <= 0;
|
nCAS <= 0;
|
||||||
nSWE <= 0;
|
nSWE <= 0;
|
||||||
|
@ -422,10 +422,10 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
SDOE <= 0;
|
SDOE <= 0;
|
||||||
end 11: begin // LDM CKE / AREF CKE / NOP CKD
|
end 11: begin // LDM CKE / AREF CKE / NOP CKD
|
||||||
RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
|
RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
|
||||||
nRCS <= ~(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd));
|
nRCS <= !(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd));
|
||||||
nRAS <= 0;
|
nRAS <= 0;
|
||||||
nCAS <= 0;
|
nCAS <= 0;
|
||||||
nSWE <= ~(IS==1);
|
nSWE <= !(IS==1);
|
||||||
SDOE <= 0;
|
SDOE <= 0;
|
||||||
end default: begin // NOP CKD
|
end default: begin // NOP CKD
|
||||||
RCKE <= 0;
|
RCKE <= 0;
|
||||||
|
@ -469,12 +469,12 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
|
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
|
||||||
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
||||||
DQML <= Addr[0];
|
DQML <= Addr[0];
|
||||||
DQMH <= ~Addr[0];
|
DQMH <= !Addr[0];
|
||||||
end else begin
|
end else begin
|
||||||
SBA[1:0] <= 2'b10;
|
SBA[1:0] <= 2'b10;
|
||||||
SA[12:0] <= { 4'b0011, RAr[9:1]};
|
SA[12:0] <= { 4'b0011, RAr[9:1]};
|
||||||
DQML <= RAr[0];
|
DQML <= RAr[0];
|
||||||
DQMH <= ~RAr[0];
|
DQMH <= !RAr[0];
|
||||||
end
|
end
|
||||||
end 3: begin // NOP CKE
|
end 3: begin // NOP CKE
|
||||||
DQML <= 1'b1;
|
DQML <= 1'b1;
|
||||||
|
@ -506,12 +506,12 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
|
||||||
SBA[1:0] <= 2'b10;
|
SBA[1:0] <= 2'b10;
|
||||||
SA[12:0] <= { 4'b0011, LS[9:1] };
|
SA[12:0] <= { 4'b0011, LS[9:1] };
|
||||||
DQML <= LS[0];
|
DQML <= LS[0];
|
||||||
DQMH <= ~LS[0];
|
DQMH <= !LS[0];
|
||||||
end else begin
|
end else begin
|
||||||
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
|
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
|
||||||
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
||||||
DQML <= Addr[0];
|
DQML <= Addr[0];
|
||||||
DQMH <= ~Addr[0];
|
DQMH <= !Addr[0];
|
||||||
end
|
end
|
||||||
end 9: begin // NOP CKE
|
end 9: begin // NOP CKE
|
||||||
DQML <= 1'b1;
|
DQML <= 1'b1;
|
||||||
|
|
|
@ -1,3 +0,0 @@
|
||||||
set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE"
|
|
||||||
set_global_assignment -name IP_TOOL_VERSION "13.0"
|
|
||||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"]
|
|
Binary file not shown.
Binary file not shown.
|
@ -1,6 +0,0 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597731746 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597731746 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:31 2021 " "Processing started: Tue Sep 14 01:35:31 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597731746 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1631597731746 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1631597731746 ""}
|
|
||||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1631597731986 ""}
|
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1631597731986 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:32 2021 " "Processing ended: Tue Sep 14 01:35:32 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597732146 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1631597732146 ""}
|
|
Binary file not shown.
Binary file not shown.
|
@ -1,5 +0,0 @@
|
||||||
<?xml version="1.0" ?>
|
|
||||||
<LOG_ROOT>
|
|
||||||
<PROJECT NAME="GR8RAM">
|
|
||||||
</PROJECT>
|
|
||||||
</LOG_ROOT>
|
|
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
@ -1 +0,0 @@
|
||||||
v1
|
|
Binary file not shown.
Binary file not shown.
|
@ -1,38 +0,0 @@
|
||||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1631597728526 ""}
|
|
||||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1631597728536 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1631597728586 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1631597728586 ""}
|
|
||||||
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1631597728726 ""}
|
|
||||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1631597728736 ""}
|
|
||||||
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1631597728876 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1631597728876 ""}
|
|
||||||
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1631597729026 ""}
|
|
||||||
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1631597729036 ""}
|
|
||||||
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1631597729036 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1631597729036 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1631597729046 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1631597729046 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1631597729046 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 0 { 0 ""} 0 418 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1631597729066 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 94 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1631597729066 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1631597729066 ""}
|
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1631597729066 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1631597729086 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1631597729116 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1631597729116 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1631597729116 ""}
|
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1631597729116 ""}
|
|
||||||
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597729186 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1631597729306 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597729566 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1631597729576 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1631597730096 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730096 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1631597730126 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1631597730346 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1631597730346 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730656 ""}
|
|
||||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1631597730666 ""}
|
|
||||||
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1631597730666 ""}
|
|
||||||
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1631597730716 ""}
|
|
||||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1631597730776 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "544 " "Peak virtual memory: 544 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:30 2021 " "Processing ended: Tue Sep 14 01:35:30 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597730806 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1631597730806 ""}
|
|
|
@ -1,220 +0,0 @@
|
||||||
|GR8RAM
|
|
||||||
C25M => SA[0]~reg0.CLK
|
|
||||||
C25M => SA[1]~reg0.CLK
|
|
||||||
C25M => SA[2]~reg0.CLK
|
|
||||||
C25M => SA[3]~reg0.CLK
|
|
||||||
C25M => SA[4]~reg0.CLK
|
|
||||||
C25M => SA[5]~reg0.CLK
|
|
||||||
C25M => SA[6]~reg0.CLK
|
|
||||||
C25M => SA[7]~reg0.CLK
|
|
||||||
C25M => SA[8]~reg0.CLK
|
|
||||||
C25M => SA[9]~reg0.CLK
|
|
||||||
C25M => SA[10]~reg0.CLK
|
|
||||||
C25M => SA[11]~reg0.CLK
|
|
||||||
C25M => SA[12]~reg0.CLK
|
|
||||||
C25M => SBA[0]~reg0.CLK
|
|
||||||
C25M => SBA[1]~reg0.CLK
|
|
||||||
C25M => DQMH~reg0.CLK
|
|
||||||
C25M => DQML~reg0.CLK
|
|
||||||
C25M => SDOE.CLK
|
|
||||||
C25M => nSWE~reg0.CLK
|
|
||||||
C25M => nCAS~reg0.CLK
|
|
||||||
C25M => nRAS~reg0.CLK
|
|
||||||
C25M => nRCS~reg0.CLK
|
|
||||||
C25M => RCKE~reg0.CLK
|
|
||||||
C25M => WRD[0].CLK
|
|
||||||
C25M => WRD[1].CLK
|
|
||||||
C25M => WRD[2].CLK
|
|
||||||
C25M => WRD[3].CLK
|
|
||||||
C25M => WRD[4].CLK
|
|
||||||
C25M => WRD[5].CLK
|
|
||||||
C25M => WRD[6].CLK
|
|
||||||
C25M => WRD[7].CLK
|
|
||||||
C25M => MOSIout.CLK
|
|
||||||
C25M => FCKOE.CLK
|
|
||||||
C25M => MOSIOE.CLK
|
|
||||||
C25M => FCS.CLK
|
|
||||||
C25M => FCKout.CLK
|
|
||||||
C25M => Bank.CLK
|
|
||||||
C25M => AddrIncH.CLK
|
|
||||||
C25M => AddrIncM.CLK
|
|
||||||
C25M => AddrIncL.CLK
|
|
||||||
C25M => Addr[0].CLK
|
|
||||||
C25M => Addr[1].CLK
|
|
||||||
C25M => Addr[2].CLK
|
|
||||||
C25M => Addr[3].CLK
|
|
||||||
C25M => Addr[4].CLK
|
|
||||||
C25M => Addr[5].CLK
|
|
||||||
C25M => Addr[6].CLK
|
|
||||||
C25M => Addr[7].CLK
|
|
||||||
C25M => Addr[8].CLK
|
|
||||||
C25M => Addr[9].CLK
|
|
||||||
C25M => Addr[10].CLK
|
|
||||||
C25M => Addr[11].CLK
|
|
||||||
C25M => Addr[12].CLK
|
|
||||||
C25M => Addr[13].CLK
|
|
||||||
C25M => Addr[14].CLK
|
|
||||||
C25M => Addr[15].CLK
|
|
||||||
C25M => Addr[16].CLK
|
|
||||||
C25M => Addr[17].CLK
|
|
||||||
C25M => Addr[18].CLK
|
|
||||||
C25M => Addr[19].CLK
|
|
||||||
C25M => Addr[20].CLK
|
|
||||||
C25M => Addr[21].CLK
|
|
||||||
C25M => Addr[22].CLK
|
|
||||||
C25M => Addr[23].CLK
|
|
||||||
C25M => IOROMEN.CLK
|
|
||||||
C25M => nIOSTRBr.CLK
|
|
||||||
C25M => REGEN.CLK
|
|
||||||
C25M => nRESout~reg0.CLK
|
|
||||||
C25M => LS[0].CLK
|
|
||||||
C25M => LS[1].CLK
|
|
||||||
C25M => LS[2].CLK
|
|
||||||
C25M => LS[3].CLK
|
|
||||||
C25M => LS[4].CLK
|
|
||||||
C25M => LS[5].CLK
|
|
||||||
C25M => LS[6].CLK
|
|
||||||
C25M => LS[7].CLK
|
|
||||||
C25M => LS[8].CLK
|
|
||||||
C25M => LS[9].CLK
|
|
||||||
C25M => LS[10].CLK
|
|
||||||
C25M => LS[11].CLK
|
|
||||||
C25M => LS[12].CLK
|
|
||||||
C25M => LS[13].CLK
|
|
||||||
C25M => PS[0].CLK
|
|
||||||
C25M => PS[1].CLK
|
|
||||||
C25M => PS[2].CLK
|
|
||||||
C25M => PS[3].CLK
|
|
||||||
C25M => SetFWr[0].CLK
|
|
||||||
C25M => SetFWr[1].CLK
|
|
||||||
C25M => SetFWLoaded.CLK
|
|
||||||
C25M => nRESr.CLK
|
|
||||||
C25M => nRESf[0].CLK
|
|
||||||
C25M => nRESf[1].CLK
|
|
||||||
C25M => nRESf[2].CLK
|
|
||||||
C25M => nRESf[3].CLK
|
|
||||||
C25M => PHI0r2.CLK
|
|
||||||
C25M => PHI0r1.CLK
|
|
||||||
C25M => IS~7.DATAIN
|
|
||||||
C25M => RDD[0].CLK
|
|
||||||
C25M => RDD[1].CLK
|
|
||||||
C25M => RDD[2].CLK
|
|
||||||
C25M => RDD[3].CLK
|
|
||||||
C25M => RDD[4].CLK
|
|
||||||
C25M => RDD[5].CLK
|
|
||||||
C25M => RDD[6].CLK
|
|
||||||
C25M => RDD[7].CLK
|
|
||||||
PHI0 => comb.IN1
|
|
||||||
PHI0 => nWEr.CLK
|
|
||||||
PHI0 => RAr[0].CLK
|
|
||||||
PHI0 => RAr[1].CLK
|
|
||||||
PHI0 => RAr[2].CLK
|
|
||||||
PHI0 => RAr[3].CLK
|
|
||||||
PHI0 => RAr[4].CLK
|
|
||||||
PHI0 => RAr[5].CLK
|
|
||||||
PHI0 => RAr[6].CLK
|
|
||||||
PHI0 => RAr[7].CLK
|
|
||||||
PHI0 => RAr[8].CLK
|
|
||||||
PHI0 => RAr[9].CLK
|
|
||||||
PHI0 => RAr[10].CLK
|
|
||||||
PHI0 => RAr[11].CLK
|
|
||||||
PHI0 => CXXXr.CLK
|
|
||||||
PHI0 => PHI0r1.DATAIN
|
|
||||||
nRES => nRESf[0].DATAIN
|
|
||||||
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SetFW[0] => SetFWr[0].DATAIN
|
|
||||||
SetFW[1] => SetFWr[1].DATAIN
|
|
||||||
INTin => INTout.DATAIN
|
|
||||||
INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
DMAin => DMAout.DATAIN
|
|
||||||
DMAout <= DMAin.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
nNMIout <= <VCC>
|
|
||||||
nIRQout <= <VCC>
|
|
||||||
nRDYout <= <VCC>
|
|
||||||
nINHout <= <VCC>
|
|
||||||
RWout <= <VCC>
|
|
||||||
nDMAout <= <VCC>
|
|
||||||
RA[0] => RAr[0].DATAIN
|
|
||||||
RA[0] => Equal16.IN10
|
|
||||||
RA[1] => RAr[1].DATAIN
|
|
||||||
RA[1] => Equal16.IN9
|
|
||||||
RA[2] => RAr[2].DATAIN
|
|
||||||
RA[2] => Equal16.IN8
|
|
||||||
RA[3] => RAr[3].DATAIN
|
|
||||||
RA[3] => Equal16.IN7
|
|
||||||
RA[4] => RAr[4].DATAIN
|
|
||||||
RA[4] => Equal16.IN6
|
|
||||||
RA[5] => RAr[5].DATAIN
|
|
||||||
RA[5] => Equal16.IN5
|
|
||||||
RA[6] => RAr[6].DATAIN
|
|
||||||
RA[6] => Equal16.IN4
|
|
||||||
RA[7] => RAr[7].DATAIN
|
|
||||||
RA[7] => Equal16.IN3
|
|
||||||
RA[8] => RAr[8].DATAIN
|
|
||||||
RA[8] => Equal16.IN2
|
|
||||||
RA[9] => RAr[9].DATAIN
|
|
||||||
RA[9] => Equal16.IN1
|
|
||||||
RA[10] => RAr[10].DATAIN
|
|
||||||
RA[10] => Equal16.IN0
|
|
||||||
RA[11] => RAr[11].DATAIN
|
|
||||||
RA[12] => Equal8.IN1
|
|
||||||
RA[13] => Equal8.IN0
|
|
||||||
RA[14] => Equal8.IN3
|
|
||||||
RA[15] => Equal8.IN2
|
|
||||||
nWE => comb.IN1
|
|
||||||
nWE => nWEr.DATAIN
|
|
||||||
RD[0] <> RD[0]
|
|
||||||
RD[1] <> RD[1]
|
|
||||||
RD[2] <> RD[2]
|
|
||||||
RD[3] <> RD[3]
|
|
||||||
RD[4] <> RD[4]
|
|
||||||
RD[5] <> RD[5]
|
|
||||||
RD[6] <> RD[6]
|
|
||||||
RD[7] <> RD[7]
|
|
||||||
RAdir <= <VCC>
|
|
||||||
RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
nIOSEL => comb.IN0
|
|
||||||
nIOSEL => always7.IN1
|
|
||||||
nDEVSEL => comb.IN1
|
|
||||||
nDEVSEL => RAMSEL.IN1
|
|
||||||
nDEVSEL => comb.IN1
|
|
||||||
nDEVSEL => RAMRegSEL.IN1
|
|
||||||
nIOSTRB => nIOSTRBr.DATAIN
|
|
||||||
nIOSTRB => comb.IN1
|
|
||||||
nIOSTRB => comb.IN1
|
|
||||||
SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SA[12] <= SA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
nSWE <= nSWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
SD[0] <> SD[0]
|
|
||||||
SD[1] <> SD[1]
|
|
||||||
SD[2] <> SD[2]
|
|
||||||
SD[3] <> SD[3]
|
|
||||||
SD[4] <> SD[4]
|
|
||||||
SD[5] <> SD[5]
|
|
||||||
SD[6] <> SD[6]
|
|
||||||
SD[7] <> SD[7]
|
|
||||||
nFCS <= nFCS.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
FCK <= FCK.DB_MAX_OUTPUT_PORT_TYPE
|
|
||||||
MISO => WRD.DATAB
|
|
||||||
MOSI <> MOSI
|
|
||||||
|
|
||||||
|
|
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|
@ -1,18 +0,0 @@
|
||||||
<TABLE>
|
|
||||||
<TR bgcolor="#C0C0C0">
|
|
||||||
<TH>Hierarchy</TH>
|
|
||||||
<TH>Input</TH>
|
|
||||||
<TH>Constant Input</TH>
|
|
||||||
<TH>Unused Input</TH>
|
|
||||||
<TH>Floating Input</TH>
|
|
||||||
<TH>Output</TH>
|
|
||||||
<TH>Constant Output</TH>
|
|
||||||
<TH>Unused Output</TH>
|
|
||||||
<TH>Floating Output</TH>
|
|
||||||
<TH>Bidir</TH>
|
|
||||||
<TH>Constant Bidir</TH>
|
|
||||||
<TH>Unused Bidir</TH>
|
|
||||||
<TH>Input only Bidir</TH>
|
|
||||||
<TH>Output only Bidir</TH>
|
|
||||||
</TR>
|
|
||||||
</TABLE>
|
|
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|
@ -1,5 +0,0 @@
|
||||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
||||||
; Legal Partition Candidates ;
|
|
||||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
|
||||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
|
||||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
|
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|
@ -1 +0,0 @@
|
||||||
v1
|
|
|
@ -1,19 +0,0 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597725836 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:25 2021 " "Processing started: Tue Sep 14 01:35:25 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1631597725836 ""}
|
|
||||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1631597726126 ""}
|
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 110 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1631597726216 ""}
|
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(286) " "Verilog HDL warning at GR8RAM.v(286): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 286 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1631597726216 ""}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1631597726226 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1631597726226 ""}
|
|
||||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1631597726256 ""}
|
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
|
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
|
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 134 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
|
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(142) " "Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 142 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
|
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(149) " "Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 149 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1631597726266 "|GR8RAM"}
|
|
||||||
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1631597726806 ""}
|
|
||||||
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 566 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 565 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 564 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 567 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1631597726986 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1631597726986 ""}
|
|
||||||
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1631597727226 ""}
|
|
||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "337 " "Implemented 337 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1631597727256 ""} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Implemented 257 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1631597727256 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1631597727256 ""}
|
|
||||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1631597727336 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "422 " "Peak virtual memory: 422 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:27 2021 " "Processing ended: Tue Sep 14 01:35:27 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1631597727356 ""}
|
|
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|
@ -1 +0,0 @@
|
||||||
DONE
|
|
|
@ -1,9 +0,0 @@
|
||||||
|
|
||||||
State Machine - |GR8RAM|IS
|
|
||||||
Name IS.state_bit_2 IS.state_bit_1 IS.state_bit_0
|
|
||||||
IS.000 0 0 0
|
|
||||||
IS.001 0 0 1
|
|
||||||
IS.100 1 0 0
|
|
||||||
IS.101 1 0 1
|
|
||||||
IS.110 0 1 0
|
|
||||||
IS.111 0 1 1
|
|
|
@ -1,20 +0,0 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1631597733226 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 14 01:35:32 2021 " "Processing started: Tue Sep 14 01:35:32 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1631597733226 ""}
|
|
||||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1631597733306 ""}
|
|
||||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1631597733426 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1631597733476 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1631597733476 ""}
|
|
||||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1631597733536 ""}
|
|
||||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1631597733876 ""}
|
|
||||||
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1631597733926 ""}
|
|
||||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1631597733926 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.419 " "Worst-case setup slack is 12.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 12.419 0.000 C25M " " 12.419 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733936 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.393 " "Worst-case hold slack is 1.393" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.393 0.000 C25M " " 1.393 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.300 " "Worst-case recovery slack is 33.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.300 0.000 C25M " " 33.300 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.146 " "Worst-case removal slack is 6.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.146 0.000 C25M " " 6.146 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1631597733946 ""}
|
|
||||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1631597733996 ""}
|
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1631597734016 ""}
|
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1631597734016 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 14 01:35:34 2021 " "Processing ended: Tue Sep 14 01:35:34 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1631597734056 ""}
|
|
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|
@ -1,91 +0,0 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049425619 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:05 2021 " "Processing started: Wed Apr 21 19:57:05 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049425619 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049425635 ""}
|
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049427276 ""}
|
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(110) " "Verilog HDL warning at GR8RAM.v(110): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 110 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049427432 ""}
|
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(286) " "Verilog HDL warning at GR8RAM.v(286): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 286 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1619049427432 ""}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1619049427448 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1619049427448 ""}
|
|
||||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1619049427557 ""}
|
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427557 "|GR8RAM"}
|
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427557 "|GR8RAM"}
|
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(134) " "Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 134 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427573 "|GR8RAM"}
|
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(142) " "Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 142 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427573 "|GR8RAM"}
|
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(149) " "Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 149 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1619049427589 "|GR8RAM"}
|
|
||||||
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1619049429167 ""}
|
|
||||||
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 563 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 566 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 565 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 564 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 567 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 562 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 561 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1619049429543 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1619049429543 ""}
|
|
||||||
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1619049430027 ""}
|
|
||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "337 " "Implemented 337 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1619049430074 ""} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Implemented 257 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1619049430074 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1619049430074 ""}
|
|
||||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1619049430324 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:10 2021 " "Processing ended: Wed Apr 21 19:57:10 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049430496 ""}
|
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1619049433591 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049433606 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:12 2021 " "Processing started: Wed Apr 21 19:57:12 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049433606 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1619049433606 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1619049433606 ""}
|
|
||||||
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1619049433810 ""}
|
|
||||||
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1619049433810 ""}
|
|
||||||
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1619049433810 ""}
|
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1619049434576 ""}
|
|
||||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1619049434607 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049435513 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1619049435513 ""}
|
|
||||||
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1619049435826 ""}
|
|
||||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1619049435873 ""}
|
|
||||||
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1619049436217 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1619049436217 ""}
|
|
||||||
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1619049436389 ""}
|
|
||||||
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1619049436436 ""}
|
|
||||||
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1619049436451 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1619049436451 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049436451 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1619049436451 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049436467 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 419 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1619049436514 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 94 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1619049436514 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1619049436514 ""}
|
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1619049436529 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1619049436592 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1619049436654 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1619049436670 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1619049436670 ""}
|
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1619049436670 ""}
|
|
||||||
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049436701 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1619049436967 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049437342 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1619049437373 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1619049438593 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049438593 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1619049438686 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "34 " "Router estimated average interconnect usage is 34% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "34 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 34% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1619049439186 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1619049439186 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049439702 ""}
|
|
||||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1619049439718 ""}
|
|
||||||
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1619049439718 ""}
|
|
||||||
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1619049439765 ""}
|
|
||||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1619049440124 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:20 2021 " "Processing ended: Wed Apr 21 19:57:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049440312 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1619049440312 ""}
|
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1619049443282 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049443297 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:22 2021 " "Processing started: Wed Apr 21 19:57:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049443297 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619049443297 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619049443297 ""}
|
|
||||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619049444797 ""}
|
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619049444985 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:26 2021 " "Processing ended: Wed Apr 21 19:57:26 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049446001 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619049446001 ""}
|
|
||||||
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1619049446923 ""}
|
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1619049449251 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 21 19:57:27 2021 " "Processing started: Wed Apr 21 19:57:27 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1619049449267 ""}
|
|
||||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1619049449455 ""}
|
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1619049450502 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049450705 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1619049450705 ""}
|
|
||||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1619049450877 ""}
|
|
||||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1619049451408 ""}
|
|
||||||
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1619049451564 ""}
|
|
||||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1619049451627 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 12.419 " "Worst-case setup slack is 12.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 12.419 0.000 C25M " " 12.419 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.393 " "Worst-case hold slack is 1.393" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.393 0.000 C25M " " 1.393 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451721 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.300 " "Worst-case recovery slack is 33.300" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.300 0.000 C25M " " 33.300 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.146 " "Worst-case removal slack is 6.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.146 0.000 C25M " " 6.146 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451736 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1619049451752 ""}
|
|
||||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1619049451861 ""}
|
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049451924 ""}
|
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1619049451939 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 21 19:57:32 2021 " "Processing ended: Wed Apr 21 19:57:32 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049452143 ""}
|
|
||||||
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Quartus II Full Compilation was successful. 0 errors, 15 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1619049453283 ""}
|
|
|
@ -1,25 +0,0 @@
|
||||||
ERASE_TIME=500000000
|
|
||||||
INTENDED_DEVICE_FAMILY="MAX II"
|
|
||||||
LPM_FILE=UNUSED
|
|
||||||
LPM_HINT=UNUSED
|
|
||||||
LPM_TYPE=altufm_none
|
|
||||||
OSC_FREQUENCY=180000
|
|
||||||
PORT_ARCLKENA=PORT_UNUSED
|
|
||||||
PORT_DRCLKENA=PORT_UNUSED
|
|
||||||
PROGRAM_TIME=1600000
|
|
||||||
WIDTH_UFM_ADDRESS=9
|
|
||||||
DEVICE_FAMILY="MAX II"
|
|
||||||
CBX_AUTO_BLACKBOX=ALL
|
|
||||||
arclk
|
|
||||||
ardin
|
|
||||||
arshft
|
|
||||||
busy
|
|
||||||
drclk
|
|
||||||
drdin
|
|
||||||
drdout
|
|
||||||
drshft
|
|
||||||
erase
|
|
||||||
osc
|
|
||||||
oscena
|
|
||||||
program
|
|
||||||
rtpbusy
|
|
|
@ -1,11 +0,0 @@
|
||||||
This folder contains data for incremental compilation.
|
|
||||||
|
|
||||||
The compiled_partitions sub-folder contains previous compilation results for each partition.
|
|
||||||
As long as this folder is preserved, incremental compilation results from earlier compiles
|
|
||||||
can be re-used. To perform a clean compilation from source files for all partitions, both
|
|
||||||
the db and incremental_db folder should be removed.
|
|
||||||
|
|
||||||
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
|
|
||||||
As long as this folder is preserved, imported partitions will be automatically re-imported
|
|
||||||
when the db or incremental_db/compiled_partitions folders are removed.
|
|
||||||
|
|
|
@ -1,3 +0,0 @@
|
||||||
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
|
||||||
Version_Index = 302049280
|
|
||||||
Creation_Time = Thu Mar 18 03:51:58 2021
|
|
Binary file not shown.
96
cpld/output_files/GR8RAM.asm.rpt
Executable file → Normal file
96
cpld/output_files/GR8RAM.asm.rpt
Executable file → Normal file
|
@ -1,6 +1,6 @@
|
||||||
Assembler report for GR8RAM
|
Assembler report for GR8RAM
|
||||||
Tue Sep 14 01:35:32 2021
|
Fri Feb 16 20:54:00 2024
|
||||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
|
||||||
|
|
||||||
---------------------
|
---------------------
|
||||||
|
@ -10,7 +10,7 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||||
2. Assembler Summary
|
2. Assembler Summary
|
||||||
3. Assembler Settings
|
3. Assembler Settings
|
||||||
4. Assembler Generated Files
|
4. Assembler Generated Files
|
||||||
5. Assembler Device Options: C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof
|
5. Assembler Device Options: /Repos/GR8RAM/cpld/output_files/GR8RAM.pof
|
||||||
6. Assembler Messages
|
6. Assembler Messages
|
||||||
|
|
||||||
|
|
||||||
|
@ -18,26 +18,27 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||||
----------------
|
----------------
|
||||||
; Legal Notice ;
|
; Legal Notice ;
|
||||||
----------------
|
----------------
|
||||||
Copyright (C) 1991-2013 Altera Corporation
|
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Intel Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and any partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
(including device programming or simulation files), and any
|
(including device programming or simulation files), and any
|
||||||
associated documentation or information are expressly subject
|
associated documentation or information are expressly subject
|
||||||
to the terms and conditions of the Altera Program License
|
to the terms and conditions of the Intel Program License
|
||||||
Subscription Agreement, Altera MegaCore Function License
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
Agreement, or other applicable license agreement, including,
|
the Intel FPGA IP License Agreement, or other applicable license
|
||||||
without limitation, that your use is for the sole purpose of
|
agreement, including, without limitation, that your use is for
|
||||||
programming logic devices manufactured by Altera and sold by
|
the sole purpose of programming logic devices manufactured by
|
||||||
Altera or its authorized distributors. Please refer to the
|
Intel and sold by Intel or its authorized distributors. Please
|
||||||
applicable agreement for further details.
|
refer to the applicable agreement for further details, at
|
||||||
|
https://fpgasoftware.intel.com/eula.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------------------------+
|
+---------------------------------------------------------------+
|
||||||
; Assembler Summary ;
|
; Assembler Summary ;
|
||||||
+-----------------------+---------------------------------------+
|
+-----------------------+---------------------------------------+
|
||||||
; Assembler Status ; Successful - Tue Sep 14 01:35:32 2021 ;
|
; Assembler Status ; Successful - Fri Feb 16 20:54:00 2024 ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
; Top-level Entity Name ; GR8RAM ;
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
; Family ; MAX II ;
|
; Family ; MAX II ;
|
||||||
|
@ -45,69 +46,46 @@ applicable agreement for further details.
|
||||||
+-----------------------+---------------------------------------+
|
+-----------------------+---------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------------------------------------------------------------------+
|
+----------------------------------+
|
||||||
; Assembler Settings ;
|
; Assembler Settings ;
|
||||||
+-----------------------------------------------------------------------------+-----------+---------------+
|
+--------+---------+---------------+
|
||||||
; Option ; Setting ; Default Value ;
|
; Option ; Setting ; Default Value ;
|
||||||
+-----------------------------------------------------------------------------+-----------+---------------+
|
+--------+---------+---------------+
|
||||||
; Use smart compilation ; Off ; Off ;
|
|
||||||
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
|
|
||||||
; Enable compact report table ; Off ; Off ;
|
|
||||||
; Compression mode ; Off ; Off ;
|
|
||||||
; Clock source for configuration device ; Internal ; Internal ;
|
|
||||||
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
|
|
||||||
; Divide clock frequency by ; 1 ; 1 ;
|
|
||||||
; Auto user code ; On ; On ;
|
|
||||||
; Security bit ; Off ; Off ;
|
|
||||||
; Use configuration device ; On ; On ;
|
|
||||||
; Configuration device ; Auto ; Auto ;
|
|
||||||
; Configuration device auto user code ; Off ; Off ;
|
|
||||||
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
|
|
||||||
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
|
|
||||||
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
|
|
||||||
; Hexadecimal Output File start address ; 0 ; 0 ;
|
|
||||||
; Hexadecimal Output File count direction ; Up ; Up ;
|
|
||||||
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
|
|
||||||
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
|
|
||||||
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
|
|
||||||
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
|
|
||||||
; In-System Programming Default Clamp State ; Tri-state ; Tri-state ;
|
|
||||||
+-----------------------------------------------------------------------------+-----------+---------------+
|
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------+
|
+--------------------------------------------+
|
||||||
; Assembler Generated Files ;
|
; Assembler Generated Files ;
|
||||||
+-------------------------------------------------------------------+
|
+--------------------------------------------+
|
||||||
; File Name ;
|
; File Name ;
|
||||||
+-------------------------------------------------------------------+
|
+--------------------------------------------+
|
||||||
; C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
; /Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||||
+-------------------------------------------------------------------+
|
+--------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------------------------------------------------------+
|
+----------------------------------------------------------------------+
|
||||||
; Assembler Device Options: C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
; Assembler Device Options: /Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||||
+----------------+----------------------------------------------------------------------------+
|
+----------------+-----------------------------------------------------+
|
||||||
; Option ; Setting ;
|
; Option ; Setting ;
|
||||||
+----------------+----------------------------------------------------------------------------+
|
+----------------+-----------------------------------------------------+
|
||||||
; Device ; EPM240T100C5 ;
|
; JTAG usercode ; 0x00163AA4 ;
|
||||||
; JTAG usercode ; 0x00161CF0 ;
|
; Checksum ; 0x00163E9C ;
|
||||||
; Checksum ; 0x001620E8 ;
|
+----------------+-----------------------------------------------------+
|
||||||
+----------------+----------------------------------------------------------------------------+
|
|
||||||
|
|
||||||
|
|
||||||
+--------------------+
|
+--------------------+
|
||||||
; Assembler Messages ;
|
; Assembler Messages ;
|
||||||
+--------------------+
|
+--------------------+
|
||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus II 64-Bit Assembler
|
Info: Running Quartus Prime Assembler
|
||||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
Info: Processing started: Tue Sep 14 01:35:31 2021
|
Info: Processing started: Fri Feb 16 20:53:59 2024
|
||||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
||||||
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
Info (115031): Writing out detailed assembly data for power analysis
|
Info (115031): Writing out detailed assembly data for power analysis
|
||||||
Info (115030): Assembler is generating device programming files
|
Info (115030): Assembler is generating device programming files
|
||||||
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
|
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
|
||||||
Info: Peak virtual memory: 381 megabytes
|
Info: Peak virtual memory: 13097 megabytes
|
||||||
Info: Processing ended: Tue Sep 14 01:35:32 2021
|
Info: Processing ended: Fri Feb 16 20:54:00 2024
|
||||||
Info: Elapsed time: 00:00:01
|
Info: Elapsed time: 00:00:01
|
||||||
Info: Total CPU time (on all processors): 00:00:01
|
Info: Total CPU time (on all processors): 00:00:01
|
||||||
|
|
||||||
|
|
|
@ -1,10 +1,10 @@
|
||||||
/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */
|
/* Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition */
|
||||||
JedecChain;
|
JedecChain;
|
||||||
FileRevision(JESD32A);
|
FileRevision(JESD32A);
|
||||||
DefaultMfr(6E);
|
DefaultMfr(6E);
|
||||||
|
|
||||||
P ActionCode(Vfy)
|
P ActionCode(Cfg)
|
||||||
Device PartName(EPM240T100) Path("C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(2) SEC_Device(EPM240T100) Child_OpMask(2 2 2));
|
Device PartName(EPM240T100) Path("//mac/iCloud/Repos2/GR8RAM/cpld2/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(1) SEC_Device(EPM240T100) Child_OpMask(2 3 3));
|
||||||
|
|
||||||
ChainEnd;
|
ChainEnd;
|
||||||
|
|
||||||
|
|
2
cpld/output_files/GR8RAM.done
Executable file → Normal file
2
cpld/output_files/GR8RAM.done
Executable file → Normal file
|
@ -1 +1 @@
|
||||||
Tue Sep 14 01:35:34 2021
|
Fri Feb 16 20:54:03 2024
|
||||||
|
|
94
cpld/output_files/GR8RAM.eda.rpt
Normal file
94
cpld/output_files/GR8RAM.eda.rpt
Normal file
|
@ -0,0 +1,94 @@
|
||||||
|
EDA Netlist Writer report for GR8RAM
|
||||||
|
Tue Feb 28 11:21:31 2023
|
||||||
|
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
|
||||||
|
|
||||||
|
|
||||||
|
---------------------
|
||||||
|
; Table of Contents ;
|
||||||
|
---------------------
|
||||||
|
1. Legal Notice
|
||||||
|
2. EDA Netlist Writer Summary
|
||||||
|
3. Simulation Settings
|
||||||
|
4. Simulation Generated Files
|
||||||
|
5. EDA Netlist Writer Messages
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
----------------
|
||||||
|
; Legal Notice ;
|
||||||
|
----------------
|
||||||
|
Copyright (C) 2022 Intel Corporation. All rights reserved.
|
||||||
|
Your use of Intel Corporation's design tools, logic functions
|
||||||
|
and other software and tools, and any partner logic
|
||||||
|
functions, and any output files from any of the foregoing
|
||||||
|
(including device programming or simulation files), and any
|
||||||
|
associated documentation or information are expressly subject
|
||||||
|
to the terms and conditions of the Intel Program License
|
||||||
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
agreement, including, without limitation, that your use is for
|
||||||
|
the sole purpose of programming logic devices manufactured by
|
||||||
|
Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
refer to the applicable agreement for further details, at
|
||||||
|
https://fpgasoftware.intel.com/eula.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
+-------------------------------------------------------------------+
|
||||||
|
; EDA Netlist Writer Summary ;
|
||||||
|
+---------------------------+---------------------------------------+
|
||||||
|
; EDA Netlist Writer Status ; Successful - Tue Feb 28 11:21:31 2023 ;
|
||||||
|
; Revision Name ; GR8RAM ;
|
||||||
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
|
; Family ; MAX II ;
|
||||||
|
; Simulation Files Creation ; Successful ;
|
||||||
|
+---------------------------+---------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+---------------------------------------------------------------------------------------------------------------------------------+
|
||||||
|
; Simulation Settings ;
|
||||||
|
+---------------------------------------------------------------------------------------------------+-----------------------------+
|
||||||
|
; Option ; Setting ;
|
||||||
|
+---------------------------------------------------------------------------------------------------+-----------------------------+
|
||||||
|
; Tool Name ; Questa Intel FPGA (Verilog) ;
|
||||||
|
; Generate functional simulation netlist ; On ;
|
||||||
|
; Truncate long hierarchy paths ; Off ;
|
||||||
|
; Map illegal HDL characters ; Off ;
|
||||||
|
; Flatten buses into individual nodes ; Off ;
|
||||||
|
; Maintain hierarchy ; Off ;
|
||||||
|
; Bring out device-wide set/reset signals as ports ; Off ;
|
||||||
|
; Enable glitch filtering ; Off ;
|
||||||
|
; Do not write top level VHDL entity ; Off ;
|
||||||
|
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
|
||||||
|
; Architecture name in VHDL output netlist ; structure ;
|
||||||
|
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
|
||||||
|
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
|
||||||
|
+---------------------------------------------------------------------------------------------------+-----------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+--------------------------------------------------+
|
||||||
|
; Simulation Generated Files ;
|
||||||
|
+--------------------------------------------------+
|
||||||
|
; Generated Files ;
|
||||||
|
+--------------------------------------------------+
|
||||||
|
; /Repos2/GR8RAM/cpld2/simulation/questa/GR8RAM.vo ;
|
||||||
|
+--------------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+-----------------------------+
|
||||||
|
; EDA Netlist Writer Messages ;
|
||||||
|
+-----------------------------+
|
||||||
|
Info: *******************************************************************
|
||||||
|
Info: Running Quartus Prime EDA Netlist Writer
|
||||||
|
Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
|
||||||
|
Info: Processing started: Tue Feb 28 11:21:30 2023
|
||||||
|
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
||||||
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
|
Info (204019): Generated file GR8RAM.vo in folder "/Repos2/GR8RAM/cpld2/simulation/questa/" for EDA simulation tool
|
||||||
|
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
|
||||||
|
Info: Peak virtual memory: 13024 megabytes
|
||||||
|
Info: Processing ended: Tue Feb 28 11:21:31 2023
|
||||||
|
Info: Elapsed time: 00:00:01
|
||||||
|
Info: Total CPU time (on all processors): 00:00:01
|
||||||
|
|
||||||
|
|
872
cpld/output_files/GR8RAM.fit.rpt
Executable file → Normal file
872
cpld/output_files/GR8RAM.fit.rpt
Executable file → Normal file
File diff suppressed because it is too large
Load Diff
0
cpld/output_files/GR8RAM.fit.smsg
Executable file → Normal file
0
cpld/output_files/GR8RAM.fit.smsg
Executable file → Normal file
6
cpld/output_files/GR8RAM.fit.summary
Executable file → Normal file
6
cpld/output_files/GR8RAM.fit.summary
Executable file → Normal file
|
@ -1,11 +1,11 @@
|
||||||
Fitter Status : Successful - Tue Sep 14 01:35:30 2021
|
Fitter Status : Successful - Fri Feb 16 20:53:58 2024
|
||||||
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
Revision Name : GR8RAM
|
Revision Name : GR8RAM
|
||||||
Top-level Entity Name : GR8RAM
|
Top-level Entity Name : GR8RAM
|
||||||
Family : MAX II
|
Family : MAX II
|
||||||
Device : EPM240T100C5
|
Device : EPM240T100C5
|
||||||
Timing Models : Final
|
Timing Models : Final
|
||||||
Total logic elements : 234 / 240 ( 98 % )
|
Total logic elements : 233 / 240 ( 97 % )
|
||||||
Total pins : 80 / 80 ( 100 % )
|
Total pins : 80 / 80 ( 100 % )
|
||||||
Total virtual pins : 0
|
Total virtual pins : 0
|
||||||
UFM blocks : 0 / 1 ( 0 % )
|
UFM blocks : 0 / 1 ( 0 % )
|
||||||
|
|
102
cpld/output_files/GR8RAM.flow.rpt
Executable file → Normal file
102
cpld/output_files/GR8RAM.flow.rpt
Executable file → Normal file
|
@ -1,6 +1,6 @@
|
||||||
Flow report for GR8RAM
|
Flow report for GR8RAM
|
||||||
Tue Sep 14 01:35:34 2021
|
Fri Feb 16 20:54:03 2024
|
||||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
|
||||||
|
|
||||||
---------------------
|
---------------------
|
||||||
|
@ -21,37 +21,38 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||||
----------------
|
----------------
|
||||||
; Legal Notice ;
|
; Legal Notice ;
|
||||||
----------------
|
----------------
|
||||||
Copyright (C) 1991-2013 Altera Corporation
|
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Intel Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and any partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
(including device programming or simulation files), and any
|
(including device programming or simulation files), and any
|
||||||
associated documentation or information are expressly subject
|
associated documentation or information are expressly subject
|
||||||
to the terms and conditions of the Altera Program License
|
to the terms and conditions of the Intel Program License
|
||||||
Subscription Agreement, Altera MegaCore Function License
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
Agreement, or other applicable license agreement, including,
|
the Intel FPGA IP License Agreement, or other applicable license
|
||||||
without limitation, that your use is for the sole purpose of
|
agreement, including, without limitation, that your use is for
|
||||||
programming logic devices manufactured by Altera and sold by
|
the sole purpose of programming logic devices manufactured by
|
||||||
Altera or its authorized distributors. Please refer to the
|
Intel and sold by Intel or its authorized distributors. Please
|
||||||
applicable agreement for further details.
|
refer to the applicable agreement for further details, at
|
||||||
|
https://fpgasoftware.intel.com/eula.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
+-----------------------------------------------------------------------------+
|
+---------------------------------------------------------------------+
|
||||||
; Flow Summary ;
|
; Flow Summary ;
|
||||||
+---------------------------+-------------------------------------------------+
|
+-----------------------+---------------------------------------------+
|
||||||
; Flow Status ; Successful - Tue Sep 14 01:35:32 2021 ;
|
; Flow Status ; Successful - Fri Feb 16 20:54:00 2024 ;
|
||||||
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
; Top-level Entity Name ; GR8RAM ;
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
; Family ; MAX II ;
|
; Family ; MAX II ;
|
||||||
; Device ; EPM240T100C5 ;
|
; Device ; EPM240T100C5 ;
|
||||||
; Timing Models ; Final ;
|
; Timing Models ; Final ;
|
||||||
; Total logic elements ; 234 / 240 ( 98 % ) ;
|
; Total logic elements ; 233 / 240 ( 97 % ) ;
|
||||||
; Total pins ; 80 / 80 ( 100 % ) ;
|
; Total pins ; 80 / 80 ( 100 % ) ;
|
||||||
; Total virtual pins ; 0 ;
|
; Total virtual pins ; 0 ;
|
||||||
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||||||
+---------------------------+-------------------------------------------------+
|
+-----------------------+---------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+-----------------------------------------+
|
+-----------------------------------------+
|
||||||
|
@ -59,7 +60,7 @@ applicable agreement for further details.
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
; Option ; Setting ;
|
; Option ; Setting ;
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
; Start date & time ; 09/14/2021 01:35:26 ;
|
; Start date & time ; 02/16/2024 20:53:35 ;
|
||||||
; Main task ; Compilation ;
|
; Main task ; Compilation ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
|
@ -67,59 +68,42 @@ applicable agreement for further details.
|
||||||
|
|
||||||
+---------------------------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Flow Non-Default Global Settings ;
|
; Flow Non-Default Global Settings ;
|
||||||
+-------------------------------------------------+------------------------------+---------------+-------------+------------+
|
+---------------------------------------+----------------------------------------+---------------+-------------+------------+
|
||||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||||
+-------------------------------------------------+------------------------------+---------------+-------------+------------+
|
+---------------------------------------+----------------------------------------+---------------+-------------+------------+
|
||||||
; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; On ; Off ; -- ; -- ;
|
; COMPILER_SIGNATURE_ID ; 121380219419.170813481504184 ; -- ; -- ; -- ;
|
||||||
; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always ; Auto ; -- ; -- ;
|
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ;
|
||||||
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
|
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 2 ;
|
||||||
; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ;
|
|
||||||
; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ;
|
|
||||||
; COMPILER_SIGNATURE_ID ; 962837114763.163159772501756 ; -- ; -- ; -- ;
|
|
||||||
; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
|
|
||||||
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
|
|
||||||
; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ;
|
|
||||||
; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 2 ;
|
|
||||||
; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ;
|
|
||||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||||
; MUX_RESTRUCTURE ; On ; Auto ; -- ; -- ;
|
|
||||||
; PLACEMENT_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ;
|
|
||||||
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
|
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
|
||||||
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||||
; REMOVE_REDUNDANT_LOGIC_CELLS ; On ; Off ; -- ; -- ;
|
+---------------------------------------+----------------------------------------+---------------+-------------+------------+
|
||||||
; ROUTER_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ;
|
|
||||||
; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ;
|
|
||||||
; SEED ; 235 ; 1 ; -- ; -- ;
|
|
||||||
; STATE_MACHINE_PROCESSING ; Minimal Bits ; Auto ; -- ; -- ;
|
|
||||||
; SYNTHESIS_SEED ; 123 ; 1 ; -- ; -- ;
|
|
||||||
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
|
|
||||||
+-------------------------------------------------+------------------------------+---------------+-------------+------------+
|
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------------------------------------------------------------------+
|
+--------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Flow Elapsed Time ;
|
; Flow Elapsed Time ;
|
||||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 422 MB ; 00:00:01 ;
|
; Analysis & Synthesis ; 00:00:20 ; 1.0 ; 13135 MB ; 00:00:43 ;
|
||||||
; Fitter ; 00:00:02 ; 1.0 ; 544 MB ; 00:00:02 ;
|
; Fitter ; 00:00:02 ; 1.0 ; 13772 MB ; 00:00:03 ;
|
||||||
; Assembler ; 00:00:01 ; 1.0 ; 381 MB ; 00:00:01 ;
|
; Assembler ; 00:00:01 ; 1.0 ; 13093 MB ; 00:00:01 ;
|
||||||
; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 374 MB ; 00:00:01 ;
|
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13090 MB ; 00:00:01 ;
|
||||||
; Total ; 00:00:07 ; -- ; -- ; 00:00:05 ;
|
; Total ; 00:00:25 ; -- ; -- ; 00:00:48 ;
|
||||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+----------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------+
|
||||||
; Flow OS Summary ;
|
; Flow OS Summary ;
|
||||||
+---------------------------+------------------+-----------+------------+----------------+
|
+----------------------+------------------+------------+------------+----------------+
|
||||||
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||||
+---------------------------+------------------+-----------+------------+----------------+
|
+----------------------+------------------+------------+------------+----------------+
|
||||||
; Analysis & Synthesis ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ;
|
; Analysis & Synthesis ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
|
||||||
; Fitter ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ;
|
; Fitter ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
|
||||||
; Assembler ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ;
|
; Assembler ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
|
||||||
; TimeQuest Timing Analyzer ; Dog-PC ; Windows 7 ; 6.1 ; x86_64 ;
|
; Timing Analyzer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
|
||||||
+---------------------------+------------------+-----------+------------+----------------+
|
+----------------------+------------------+------------+------------+----------------+
|
||||||
|
|
||||||
|
|
||||||
------------
|
------------
|
||||||
|
|
2
cpld/output_files/GR8RAM.jdi
Executable file → Normal file
2
cpld/output_files/GR8RAM.jdi
Executable file → Normal file
|
@ -1,6 +1,6 @@
|
||||||
<sld_project_info>
|
<sld_project_info>
|
||||||
<project>
|
<project>
|
||||||
<hash md5_digest_80b="5cae6640443712869b47"/>
|
<hash md5_digest_80b="1794c049bdbd51a27b8f"/>
|
||||||
</project>
|
</project>
|
||||||
<file_info>
|
<file_info>
|
||||||
<file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>
|
<file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>
|
||||||
|
|
226
cpld/output_files/GR8RAM.map.rpt
Executable file → Normal file
226
cpld/output_files/GR8RAM.map.rpt
Executable file → Normal file
|
@ -1,6 +1,6 @@
|
||||||
Analysis & Synthesis report for GR8RAM
|
Analysis & Synthesis report for GR8RAM
|
||||||
Tue Sep 14 01:35:27 2021
|
Fri Feb 16 20:53:55 2024
|
||||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
|
||||||
|
|
||||||
---------------------
|
---------------------
|
||||||
|
@ -26,61 +26,56 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||||
----------------
|
----------------
|
||||||
; Legal Notice ;
|
; Legal Notice ;
|
||||||
----------------
|
----------------
|
||||||
Copyright (C) 1991-2013 Altera Corporation
|
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
Your use of Intel Corporation's design tools, logic functions
|
||||||
and other software and tools, and its AMPP partner logic
|
and other software and tools, and any partner logic
|
||||||
functions, and any output files from any of the foregoing
|
functions, and any output files from any of the foregoing
|
||||||
(including device programming or simulation files), and any
|
(including device programming or simulation files), and any
|
||||||
associated documentation or information are expressly subject
|
associated documentation or information are expressly subject
|
||||||
to the terms and conditions of the Altera Program License
|
to the terms and conditions of the Intel Program License
|
||||||
Subscription Agreement, Altera MegaCore Function License
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
Agreement, or other applicable license agreement, including,
|
the Intel FPGA IP License Agreement, or other applicable license
|
||||||
without limitation, that your use is for the sole purpose of
|
agreement, including, without limitation, that your use is for
|
||||||
programming logic devices manufactured by Altera and sold by
|
the sole purpose of programming logic devices manufactured by
|
||||||
Altera or its authorized distributors. Please refer to the
|
Intel and sold by Intel or its authorized distributors. Please
|
||||||
applicable agreement for further details.
|
refer to the applicable agreement for further details, at
|
||||||
|
https://fpgasoftware.intel.com/eula.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------+
|
||||||
; Analysis & Synthesis Summary ;
|
; Analysis & Synthesis Summary ;
|
||||||
+-----------------------------+-------------------------------------------------+
|
+-----------------------------+---------------------------------------------+
|
||||||
; Analysis & Synthesis Status ; Successful - Tue Sep 14 01:35:27 2021 ;
|
; Analysis & Synthesis Status ; Successful - Fri Feb 16 20:53:55 2024 ;
|
||||||
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
; Top-level Entity Name ; GR8RAM ;
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
; Family ; MAX II ;
|
; Family ; MAX II ;
|
||||||
; Total logic elements ; 257 ;
|
; Total logic elements ; 253 ;
|
||||||
; Total pins ; 80 ;
|
; Total pins ; 80 ;
|
||||||
; Total virtual pins ; 0 ;
|
; Total virtual pins ; 0 ;
|
||||||
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
; UFM blocks ; 0 / 1 ( 0 % ) ;
|
||||||
+-----------------------------+-------------------------------------------------+
|
+-----------------------------+---------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+----------------------------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------+
|
||||||
; Analysis & Synthesis Settings ;
|
; Analysis & Synthesis Settings ;
|
||||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
+------------------------------------------------------------------+--------------------+--------------------+
|
||||||
; Option ; Setting ; Default Value ;
|
; Option ; Setting ; Default Value ;
|
||||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
+------------------------------------------------------------------+--------------------+--------------------+
|
||||||
; Device ; EPM240T100C5 ; ;
|
; Device ; EPM240T100C5 ; ;
|
||||||
; Top-level entity name ; GR8RAM ; GR8RAM ;
|
; Top-level entity name ; GR8RAM ; GR8RAM ;
|
||||||
; Family name ; MAX II ; Cyclone IV GX ;
|
; Family name ; MAX II ; Cyclone V ;
|
||||||
; Restructure Multiplexers ; On ; Auto ;
|
|
||||||
; State Machine Processing ; Minimal Bits ; Auto ;
|
|
||||||
; Remove Redundant Logic Cells ; On ; Off ;
|
|
||||||
; Optimization Technique ; Area ; Balanced ;
|
|
||||||
; Perform WYSIWYG Primitive Resynthesis ; On ; Off ;
|
|
||||||
; Allow Shift Register Merging across Hierarchies ; Always ; Auto ;
|
|
||||||
; Auto Resource Sharing ; On ; Off ;
|
|
||||||
; Synthesis Seed ; 123 ; 1 ;
|
|
||||||
; Use smart compilation ; Off ; Off ;
|
; Use smart compilation ; Off ; Off ;
|
||||||
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
|
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
|
||||||
; Enable compact report table ; Off ; Off ;
|
; Enable compact report table ; Off ; Off ;
|
||||||
|
; Restructure Multiplexers ; Auto ; Auto ;
|
||||||
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
||||||
; Preserve fewer node names ; On ; On ;
|
; Preserve fewer node names ; On ; On ;
|
||||||
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
|
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
|
||||||
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
||||||
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
||||||
|
; State Machine Processing ; Auto ; Auto ;
|
||||||
; Safe State Machine ; Off ; Off ;
|
; Safe State Machine ; Off ; Off ;
|
||||||
; Extract Verilog State Machines ; On ; On ;
|
; Extract Verilog State Machines ; On ; On ;
|
||||||
; Extract VHDL State Machines ; On ; On ;
|
; Extract VHDL State Machines ; On ; On ;
|
||||||
|
@ -92,6 +87,7 @@ applicable agreement for further details.
|
||||||
; Parallel Synthesis ; On ; On ;
|
; Parallel Synthesis ; On ; On ;
|
||||||
; NOT Gate Push-Back ; On ; On ;
|
; NOT Gate Push-Back ; On ; On ;
|
||||||
; Power-Up Don't Care ; On ; On ;
|
; Power-Up Don't Care ; On ; On ;
|
||||||
|
; Remove Redundant Logic Cells ; Off ; Off ;
|
||||||
; Remove Duplicate Registers ; On ; On ;
|
; Remove Duplicate Registers ; On ; On ;
|
||||||
; Ignore CARRY Buffers ; Off ; Off ;
|
; Ignore CARRY Buffers ; Off ; Off ;
|
||||||
; Ignore CASCADE Buffers ; Off ; Off ;
|
; Ignore CASCADE Buffers ; Off ; Off ;
|
||||||
|
@ -100,13 +96,17 @@ applicable agreement for further details.
|
||||||
; Ignore LCELL Buffers ; Off ; Off ;
|
; Ignore LCELL Buffers ; Off ; Off ;
|
||||||
; Ignore SOFT Buffers ; On ; On ;
|
; Ignore SOFT Buffers ; On ; On ;
|
||||||
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
||||||
|
; Optimization Technique ; Balanced ; Balanced ;
|
||||||
; Carry Chain Length ; 70 ; 70 ;
|
; Carry Chain Length ; 70 ; 70 ;
|
||||||
; Auto Carry Chains ; On ; On ;
|
; Auto Carry Chains ; On ; On ;
|
||||||
; Auto Open-Drain Pins ; On ; On ;
|
; Auto Open-Drain Pins ; On ; On ;
|
||||||
|
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
|
||||||
; Auto Shift Register Replacement ; Auto ; Auto ;
|
; Auto Shift Register Replacement ; Auto ; Auto ;
|
||||||
|
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
|
||||||
; Auto Clock Enable Replacement ; On ; On ;
|
; Auto Clock Enable Replacement ; On ; On ;
|
||||||
; Allow Synchronous Control Signals ; On ; On ;
|
; Allow Synchronous Control Signals ; On ; On ;
|
||||||
; Force Use of Synchronous Clear Signals ; Off ; Off ;
|
; Force Use of Synchronous Clear Signals ; Off ; Off ;
|
||||||
|
; Auto Resource Sharing ; Off ; Off ;
|
||||||
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
||||||
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
||||||
; Report Parameter Settings ; On ; On ;
|
; Report Parameter Settings ; On ; On ;
|
||||||
|
@ -114,7 +114,7 @@ applicable agreement for further details.
|
||||||
; Report Connectivity Checks ; On ; On ;
|
; Report Connectivity Checks ; On ; On ;
|
||||||
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
||||||
; Synchronization Register Chain Length ; 2 ; 2 ;
|
; Synchronization Register Chain Length ; 2 ; 2 ;
|
||||||
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
|
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
|
||||||
; HDL message level ; Level2 ; Level2 ;
|
; HDL message level ; Level2 ; Level2 ;
|
||||||
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
||||||
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||||
|
@ -124,30 +124,34 @@ applicable agreement for further details.
|
||||||
; Block Design Naming ; Auto ; Auto ;
|
; Block Design Naming ; Auto ; Auto ;
|
||||||
; Synthesis Effort ; Auto ; Auto ;
|
; Synthesis Effort ; Auto ; Auto ;
|
||||||
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
||||||
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
|
|
||||||
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
||||||
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
||||||
+----------------------------------------------------------------------------+--------------------+--------------------+
|
+------------------------------------------------------------------+--------------------+--------------------+
|
||||||
|
|
||||||
|
|
||||||
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
+------------------------------------------+
|
||||||
+-------------------------------------+
|
|
||||||
; Parallel Compilation ;
|
; Parallel Compilation ;
|
||||||
+----------------------------+--------+
|
+----------------------------+-------------+
|
||||||
; Processors ; Number ;
|
; Processors ; Number ;
|
||||||
+----------------------------+--------+
|
+----------------------------+-------------+
|
||||||
; Number detected on machine ; 12 ;
|
; Number detected on machine ; 4 ;
|
||||||
; Maximum allowed ; 1 ;
|
; Maximum allowed ; 4 ;
|
||||||
+----------------------------+--------+
|
; ; ;
|
||||||
|
; Average used ; 1.00 ;
|
||||||
|
; Maximum used ; 1 ;
|
||||||
|
; ; ;
|
||||||
|
; Usage by Processor ; % Time Used ;
|
||||||
|
; Processor 1 ; 100.0% ;
|
||||||
|
+----------------------------+-------------+
|
||||||
|
|
||||||
|
|
||||||
+--------------------------------------------------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Analysis & Synthesis Source Files Read ;
|
; Analysis & Synthesis Source Files Read ;
|
||||||
+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
|
+----------------------------------+-----------------+------------------------+---------------------------------------+---------+
|
||||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||||
+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
|
+----------------------------------+-----------------+------------------------+---------------------------------------+---------+
|
||||||
; GR8RAM.v ; yes ; User Verilog HDL File ; C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/GR8RAM.v ; ;
|
; GR8RAM.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v ; ;
|
||||||
+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
|
+----------------------------------+-----------------+------------------------+---------------------------------------+---------+
|
||||||
|
|
||||||
|
|
||||||
+-----------------------------------------------------+
|
+-----------------------------------------------------+
|
||||||
|
@ -155,59 +159,59 @@ Parallel compilation was disabled, but you have multiple processors available. E
|
||||||
+---------------------------------------------+-------+
|
+---------------------------------------------+-------+
|
||||||
; Resource ; Usage ;
|
; Resource ; Usage ;
|
||||||
+---------------------------------------------+-------+
|
+---------------------------------------------+-------+
|
||||||
; Total logic elements ; 257 ;
|
; Total logic elements ; 253 ;
|
||||||
; -- Combinational with no register ; 136 ;
|
; -- Combinational with no register ; 129 ;
|
||||||
; -- Register only ; 24 ;
|
; -- Register only ; 26 ;
|
||||||
; -- Combinational with a register ; 97 ;
|
; -- Combinational with a register ; 98 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Logic element usage by number of LUT inputs ; ;
|
; Logic element usage by number of LUT inputs ; ;
|
||||||
; -- 4 input functions ; 126 ;
|
; -- 4 input functions ; 124 ;
|
||||||
; -- 3 input functions ; 41 ;
|
; -- 3 input functions ; 30 ;
|
||||||
; -- 2 input functions ; 65 ;
|
; -- 2 input functions ; 71 ;
|
||||||
; -- 1 input functions ; 0 ;
|
; -- 1 input functions ; 0 ;
|
||||||
; -- 0 input functions ; 1 ;
|
; -- 0 input functions ; 2 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Logic elements by mode ; ;
|
; Logic elements by mode ; ;
|
||||||
; -- normal mode ; 224 ;
|
; -- normal mode ; 220 ;
|
||||||
; -- arithmetic mode ; 33 ;
|
; -- arithmetic mode ; 33 ;
|
||||||
; -- qfbk mode ; 0 ;
|
; -- qfbk mode ; 0 ;
|
||||||
; -- register cascade mode ; 0 ;
|
; -- register cascade mode ; 0 ;
|
||||||
; -- synchronous clear/load mode ; 45 ;
|
; -- synchronous clear/load mode ; 45 ;
|
||||||
; -- asynchronous clear/load mode ; 29 ;
|
; -- asynchronous clear/load mode ; 29 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Total registers ; 121 ;
|
; Total registers ; 124 ;
|
||||||
; Total logic cells in carry chains ; 37 ;
|
; Total logic cells in carry chains ; 37 ;
|
||||||
; I/O pins ; 80 ;
|
; I/O pins ; 80 ;
|
||||||
; Maximum fan-out node ; C25M ;
|
; Maximum fan-out node ; C25M ;
|
||||||
; Maximum fan-out ; 107 ;
|
; Maximum fan-out ; 110 ;
|
||||||
; Total fan-out ; 1095 ;
|
; Total fan-out ; 1076 ;
|
||||||
; Average fan-out ; 3.25 ;
|
; Average fan-out ; 3.23 ;
|
||||||
+---------------------------------------------+-------+
|
+---------------------------------------------+-------+
|
||||||
|
|
||||||
|
|
||||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
||||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
|
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
||||||
; |GR8RAM ; 257 (257) ; 121 ; 0 ; 80 ; 0 ; 136 (136) ; 24 (24) ; 97 (97) ; 37 (37) ; 0 (0) ; |GR8RAM ; work ;
|
; |GR8RAM ; 253 (253) ; 124 ; 0 ; 80 ; 0 ; 129 (129) ; 26 (26) ; 98 (98) ; 37 (37) ; 0 (0) ; |GR8RAM ; GR8RAM ; work ;
|
||||||
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
|
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
|
||||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||||
|
|
||||||
|
|
||||||
Encoding Type: Minimal Bits
|
Encoding Type: One-Hot
|
||||||
+-----------------------------------------------------------+
|
+--------------------------------------------------------------+
|
||||||
; State Machine - |GR8RAM|IS ;
|
; State Machine - |GR8RAM|IS ;
|
||||||
+--------+----------------+----------------+----------------+
|
+--------+--------+--------+--------+--------+--------+--------+
|
||||||
; Name ; IS.state_bit_2 ; IS.state_bit_1 ; IS.state_bit_0 ;
|
; Name ; IS.111 ; IS.110 ; IS.101 ; IS.100 ; IS.001 ; IS.000 ;
|
||||||
+--------+----------------+----------------+----------------+
|
+--------+--------+--------+--------+--------+--------+--------+
|
||||||
; IS.000 ; 0 ; 0 ; 0 ;
|
; IS.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||||
; IS.001 ; 0 ; 0 ; 1 ;
|
; IS.001 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
|
||||||
; IS.100 ; 1 ; 0 ; 0 ;
|
; IS.100 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
|
||||||
; IS.101 ; 1 ; 0 ; 1 ;
|
; IS.101 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
|
||||||
; IS.110 ; 0 ; 1 ; 0 ;
|
; IS.110 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
|
||||||
; IS.111 ; 0 ; 1 ; 1 ;
|
; IS.111 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
|
||||||
+--------+----------------+----------------+----------------+
|
+--------+--------+--------+--------+--------+--------+--------+
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------+
|
+------------------------------------------------------------+
|
||||||
|
@ -215,8 +219,10 @@ Encoding Type: Minimal Bits
|
||||||
+---------------------------------------+--------------------+
|
+---------------------------------------+--------------------+
|
||||||
; Register name ; Reason for Removal ;
|
; Register name ; Reason for Removal ;
|
||||||
+---------------------------------------+--------------------+
|
+---------------------------------------+--------------------+
|
||||||
|
; IS~8 ; Lost fanout ;
|
||||||
|
; IS~9 ; Lost fanout ;
|
||||||
; IS~10 ; Lost fanout ;
|
; IS~10 ; Lost fanout ;
|
||||||
; Total Number of Removed Registers = 1 ; ;
|
; Total Number of Removed Registers = 3 ; ;
|
||||||
+---------------------------------------+--------------------+
|
+---------------------------------------+--------------------+
|
||||||
|
|
||||||
|
|
||||||
|
@ -225,12 +231,12 @@ Encoding Type: Minimal Bits
|
||||||
+----------------------------------------------+-------+
|
+----------------------------------------------+-------+
|
||||||
; Statistic ; Value ;
|
; Statistic ; Value ;
|
||||||
+----------------------------------------------+-------+
|
+----------------------------------------------+-------+
|
||||||
; Total registers ; 121 ;
|
; Total registers ; 124 ;
|
||||||
; Number of registers using Synchronous Clear ; 12 ;
|
; Number of registers using Synchronous Clear ; 12 ;
|
||||||
; Number of registers using Synchronous Load ; 33 ;
|
; Number of registers using Synchronous Load ; 33 ;
|
||||||
; Number of registers using Asynchronous Clear ; 29 ;
|
; Number of registers using Asynchronous Clear ; 29 ;
|
||||||
; Number of registers using Asynchronous Load ; 0 ;
|
; Number of registers using Asynchronous Load ; 0 ;
|
||||||
; Number of registers using Clock Enable ; 24 ;
|
; Number of registers using Clock Enable ; 29 ;
|
||||||
; Number of registers using Preset ; 0 ;
|
; Number of registers using Preset ; 0 ;
|
||||||
+----------------------------------------------+-------+
|
+----------------------------------------------+-------+
|
||||||
|
|
||||||
|
@ -264,7 +270,7 @@ Encoding Type: Minimal Bits
|
||||||
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[1] ;
|
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[1] ;
|
||||||
; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|RDD[4] ;
|
; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|RDD[4] ;
|
||||||
; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ;
|
; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ;
|
||||||
; 8:1 ; 5 bits ; 25 LEs ; 20 LEs ; 5 LEs ; No ; |GR8RAM|IS ;
|
; 7:1 ; 5 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |GR8RAM|IS ;
|
||||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
@ -272,45 +278,45 @@ Encoding Type: Minimal Bits
|
||||||
; Analysis & Synthesis Messages ;
|
; Analysis & Synthesis Messages ;
|
||||||
+-------------------------------+
|
+-------------------------------+
|
||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus II 64-Bit Analysis & Synthesis
|
Info: Running Quartus Prime Analysis & Synthesis
|
||||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
Info: Processing started: Tue Sep 14 01:35:25 2021
|
Info: Processing started: Fri Feb 16 20:53:35 2024
|
||||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
||||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
|
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||||||
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
|
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
|
||||||
Info (12023): Found entity 1: GR8RAM
|
Info (12023): Found entity 1: GR8RAM File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 1
|
||||||
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
|
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 42
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 47
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 134
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 142
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 149
|
||||||
Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
|
|
||||||
Warning (13024): Output pins are stuck at VCC or GND
|
Warning (13024): Output pins are stuck at VCC or GND
|
||||||
Warning (13410): Pin "nNMIout" is stuck at VCC
|
Warning (13410): Pin "nNMIout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 563
|
||||||
Warning (13410): Pin "nIRQout" is stuck at VCC
|
Warning (13410): Pin "nIRQout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 566
|
||||||
Warning (13410): Pin "nRDYout" is stuck at VCC
|
Warning (13410): Pin "nRDYout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 565
|
||||||
Warning (13410): Pin "nINHout" is stuck at VCC
|
Warning (13410): Pin "nINHout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 564
|
||||||
Warning (13410): Pin "RWout" is stuck at VCC
|
Warning (13410): Pin "RWout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 567
|
||||||
Warning (13410): Pin "nDMAout" is stuck at VCC
|
Warning (13410): Pin "nDMAout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 562
|
||||||
Warning (13410): Pin "RAdir" is stuck at VCC
|
Warning (13410): Pin "RAdir" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 561
|
||||||
Info (17049): 1 registers lost all their fanouts during netlist optimizations.
|
Info (17049): 3 registers lost all their fanouts during netlist optimizations.
|
||||||
Info (21057): Implemented 337 device resources after synthesis - the final resource count might be different
|
Info (21057): Implemented 333 device resources after synthesis - the final resource count might be different
|
||||||
Info (21058): Implemented 28 input pins
|
Info (21058): Implemented 28 input pins
|
||||||
Info (21059): Implemented 35 output pins
|
Info (21059): Implemented 35 output pins
|
||||||
Info (21060): Implemented 17 bidirectional pins
|
Info (21060): Implemented 17 bidirectional pins
|
||||||
Info (21061): Implemented 257 logic cells
|
Info (21061): Implemented 253 logic cells
|
||||||
Info (144001): Generated suppressed messages file C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
Info (144001): Generated suppressed messages file /Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
||||||
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 14 warnings
|
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings
|
||||||
Info: Peak virtual memory: 422 megabytes
|
Info: Peak virtual memory: 13135 megabytes
|
||||||
Info: Processing ended: Tue Sep 14 01:35:27 2021
|
Info: Processing ended: Fri Feb 16 20:53:55 2024
|
||||||
Info: Elapsed time: 00:00:02
|
Info: Elapsed time: 00:00:20
|
||||||
Info: Total CPU time (on all processors): 00:00:01
|
Info: Total CPU time (on all processors): 00:00:43
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------+
|
+------------------------------------------+
|
||||||
; Analysis & Synthesis Suppressed Messages ;
|
; Analysis & Synthesis Suppressed Messages ;
|
||||||
+------------------------------------------+
|
+------------------------------------------+
|
||||||
The suppressed messages can be found in C:/Users/Dog/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
|
The suppressed messages can be found in /Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
|
||||||
|
|
||||||
|
|
||||||
|
|
4
cpld/output_files/GR8RAM.map.smsg
Executable file → Normal file
4
cpld/output_files/GR8RAM.map.smsg
Executable file → Normal file
|
@ -1,2 +1,2 @@
|
||||||
Warning (10273): Verilog HDL warning at GR8RAM.v(110): extended using "x" or "z"
|
Warning (10273): Verilog HDL warning at GR8RAM.v(110): extended using "x" or "z" File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 110
|
||||||
Warning (10273): Verilog HDL warning at GR8RAM.v(286): extended using "x" or "z"
|
Warning (10273): Verilog HDL warning at GR8RAM.v(286): extended using "x" or "z" File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 286
|
||||||
|
|
6
cpld/output_files/GR8RAM.map.summary
Executable file → Normal file
6
cpld/output_files/GR8RAM.map.summary
Executable file → Normal file
|
@ -1,9 +1,9 @@
|
||||||
Analysis & Synthesis Status : Successful - Tue Sep 14 01:35:27 2021
|
Analysis & Synthesis Status : Successful - Fri Feb 16 20:53:55 2024
|
||||||
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
Revision Name : GR8RAM
|
Revision Name : GR8RAM
|
||||||
Top-level Entity Name : GR8RAM
|
Top-level Entity Name : GR8RAM
|
||||||
Family : MAX II
|
Family : MAX II
|
||||||
Total logic elements : 257
|
Total logic elements : 253
|
||||||
Total pins : 80
|
Total pins : 80
|
||||||
Total virtual pins : 0
|
Total virtual pins : 0
|
||||||
UFM blocks : 0 / 1 ( 0 % )
|
UFM blocks : 0 / 1 ( 0 % )
|
||||||
|
|
33
cpld/output_files/GR8RAM.pin
Executable file → Normal file
33
cpld/output_files/GR8RAM.pin
Executable file → Normal file
|
@ -1,21 +1,22 @@
|
||||||
-- Copyright (C) 1991-2013 Altera Corporation
|
-- Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
-- Your use of Altera Corporation's design tools, logic functions
|
-- Your use of Intel Corporation's design tools, logic functions
|
||||||
-- and other software and tools, and its AMPP partner logic
|
-- and other software and tools, and any partner logic
|
||||||
-- functions, and any output files from any of the foregoing
|
-- functions, and any output files from any of the foregoing
|
||||||
-- (including device programming or simulation files), and any
|
-- (including device programming or simulation files), and any
|
||||||
-- associated documentation or information are expressly subject
|
-- associated documentation or information are expressly subject
|
||||||
-- to the terms and conditions of the Altera Program License
|
-- to the terms and conditions of the Intel Program License
|
||||||
-- Subscription Agreement, Altera MegaCore Function License
|
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
-- Agreement, or other applicable license agreement, including,
|
-- the Intel FPGA IP License Agreement, or other applicable license
|
||||||
-- without limitation, that your use is for the sole purpose of
|
-- agreement, including, without limitation, that your use is for
|
||||||
-- programming logic devices manufactured by Altera and sold by
|
-- the sole purpose of programming logic devices manufactured by
|
||||||
-- Altera or its authorized distributors. Please refer to the
|
-- Intel and sold by Intel or its authorized distributors. Please
|
||||||
-- applicable agreement for further details.
|
-- refer to the applicable agreement for further details, at
|
||||||
|
-- https://fpgasoftware.intel.com/eula.
|
||||||
--
|
--
|
||||||
-- This is a Quartus II output file. It is for reporting purposes only, and is
|
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
|
||||||
-- not intended for use as a Quartus II input file. This file cannot be used
|
-- not intended for use as a Quartus Prime input file. This file cannot be used
|
||||||
-- to make Quartus II pin assignments - for instructions on how to make pin
|
-- to make Quartus Prime pin assignments - for instructions on how to make pin
|
||||||
-- assignments, please see Quartus II help.
|
-- assignments, please see Quartus Prime help.
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
@ -57,12 +58,12 @@
|
||||||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
|
|
||||||
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5
|
CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5
|
||||||
|
|
||||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||||
-------------------------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------------------
|
||||||
RA[4] : 1 : input : 3.3-V LVTTL : : 2 : Y
|
RA[4] : 1 : input : 3.3-V LVTTL : : 2 : N
|
||||||
RA[5] : 2 : input : 3.3-V LVTTL : : 1 : Y
|
RA[5] : 2 : input : 3.3-V LVTTL : : 1 : Y
|
||||||
RA[6] : 3 : input : 3.3-V LVTTL : : 1 : Y
|
RA[6] : 3 : input : 3.3-V LVTTL : : 1 : Y
|
||||||
RA[3] : 4 : input : 3.3-V LVTTL : : 1 : Y
|
RA[3] : 4 : input : 3.3-V LVTTL : : 1 : Y
|
||||||
|
|
BIN
cpld/output_files/GR8RAM.pof
Executable file → Normal file
BIN
cpld/output_files/GR8RAM.pof
Executable file → Normal file
Binary file not shown.
1
cpld/output_files/GR8RAM.sld
Normal file
1
cpld/output_files/GR8RAM.sld
Normal file
|
@ -0,0 +1 @@
|
||||||
|
<sld_project_info/>
|
1760
cpld/output_files/GR8RAM.sta.rpt
Executable file → Normal file
1760
cpld/output_files/GR8RAM.sta.rpt
Executable file → Normal file
File diff suppressed because it is too large
Load Diff
10
cpld/output_files/GR8RAM.sta.summary
Executable file → Normal file
10
cpld/output_files/GR8RAM.sta.summary
Executable file → Normal file
|
@ -1,21 +1,21 @@
|
||||||
------------------------------------------------------------
|
------------------------------------------------------------
|
||||||
TimeQuest Timing Analyzer Summary
|
Timing Analyzer Summary
|
||||||
------------------------------------------------------------
|
------------------------------------------------------------
|
||||||
|
|
||||||
Type : Setup 'C25M'
|
Type : Setup 'C25M'
|
||||||
Slack : 12.419
|
Slack : 10.278
|
||||||
TNS : 0.000
|
TNS : 0.000
|
||||||
|
|
||||||
Type : Hold 'C25M'
|
Type : Hold 'C25M'
|
||||||
Slack : 1.393
|
Slack : 1.376
|
||||||
TNS : 0.000
|
TNS : 0.000
|
||||||
|
|
||||||
Type : Recovery 'C25M'
|
Type : Recovery 'C25M'
|
||||||
Slack : 33.300
|
Slack : 33.311
|
||||||
TNS : 0.000
|
TNS : 0.000
|
||||||
|
|
||||||
Type : Removal 'C25M'
|
Type : Removal 'C25M'
|
||||||
Slack : 6.146
|
Slack : 6.135
|
||||||
TNS : 0.000
|
TNS : 0.000
|
||||||
|
|
||||||
Type : Minimum Pulse Width 'C25M'
|
Type : Minimum Pulse Width 'C25M'
|
||||||
|
|
11651
cpld/output_files/GR8RAM.svf
Normal file
11651
cpld/output_files/GR8RAM.svf
Normal file
File diff suppressed because it is too large
Load Diff
|
@ -1,8 +0,0 @@
|
||||||
<internal_error>
|
|
||||||
<executable>quartus.exe</executable>
|
|
||||||
<sub_system>MEM</sub_system>
|
|
||||||
<error>*** Fatal Error: Out of memory in module quartus.exe (1999 megabytes used)</error>
|
|
||||||
<date>Mon Mar 22 01:13:02 2021</date>
|
|
||||||
<version>Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition</version>
|
|
||||||
</internal_error>
|
|
||||||
|
|
BIN
driver/GR8RAM.bin
Executable file
BIN
driver/GR8RAM.bin
Executable file
Binary file not shown.
Loading…
Reference in New Issue
Block a user