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Apple-2-HW:RC-4205A
Apple-2-HW:dev-4205A
Apple-2-HW:release-4205A
Apple-2-HW:dev-4205B
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compare: Apple-2-HW:c3716ebb82e206eaa16893582675c7bae68ff7bf
Branches Tags
Apple-2-HW:RC-4205A
Apple-2-HW:dev-4205A
Apple-2-HW:release-4205A
Apple-2-HW:dev-4205B

15 Commits
85df5cc4b7 ... c3716ebb82

Author SHA1 Message Date
Zane Kaminski
c3716ebb82 Change ~ to ! where appropriate in GR8RAM.v 2024-02-16 20:54:16 -05:00
Zane Kaminski
97943bc2e7 Recompile 2024-02-16 20:48:50 -05:00
Zane Kaminski
7eb62dbe5a Untrack and delete .qws files 2024-02-16 20:46:40 -05:00
Zane Kaminski
f347a27f89 Create new quartus project 2024-02-16 20:43:29 -05:00
Zane Kaminski
9f456e8d0f Delete old quartus stuff 2024-02-16 20:41:52 -05:00
Zane Kaminski
b467eaac6b Update .gitignore 2024-02-16 20:41:33 -05:00
Zane Kaminski
dd6dad0b98 Add back GR8RAM.bin 2023-03-06 11:16:38 -05:00
Zane Kaminski
45ed1b5ffe Merge branch 'dev-4205A' into release-4205A 2023-02-28 11:26:09 -05:00
Zane Kaminski
b1757d3d0f Compiled CPLD again 2023-02-28 11:23:37 -05:00
Zane Kaminski
eca42a0161 Update GR8RAM.qsf 2023-02-28 11:20:35 -05:00
Zane Kaminski
da9197740a Update GR8RAM.qsf 2023-02-28 11:19:03 -05:00
Zane Kaminski
4ae69c54f3 New project 2023-02-28 11:17:29 -05:00
Zane Kaminski
2f593bca65 Merge branch 'dev' into release 2023-02-25 09:30:47 -05:00
Zane Kaminski
e816e117fc Update .gitignore 2023-02-25 09:29:49 -05:00
Zane Kaminski
ce152459a6 Update .gitignore 2022-08-14 05:23:36 -04:00
57 changed files with 424775 additions and 20275 deletions
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7
.gitignore vendored
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@ -24,8 +24,7 @@ GR8RAM-backups/*
*.ses
*.DS_Store
cpld/db/GR8RAM.db_info
cpld/db/GR8RAM.tmw_info
cpld/GR8RAM.qws
Documentation/~$4205AManual.docx
*.kicad_prl
cpld/db/*
cpld/incremental_db/*
cpld/GR8RAM.qws

3579
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18
Documentation/Boot codes
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@ -1,18 +0,0 @@
F0 F1 Outcome
----------------------------------------
11 11 Both erased
XX 11 F1 erased, load F0
11 XX F0 erased, load F1
00 00 Error - tie
10 10 Error - tie
01 01 Error - tie
00 01 F1 newer
00 10 F0 newer
01 00 F0 newer
01 10 F1 newer
10 00 F1 newer
10 01 F0 newer

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997
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(path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3/13d7a51b-3530-4ae9-b53c-5be82bc34799"
(reference "R18") (unit 1)
)
)
)
)
(symbol (lib_id "power:+3V3") (at 124.46 34.29 0) (unit 1)
(in_bom yes) (on_board yes) (dnp no)
(uuid ef5053a5-3874-473e-9819-718589d38f4a)
(property "Reference" "#PWR0142" (at 124.46 38.1 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Value" "+3V3" (at 124.46 30.48 0)
(effects (font (size 1.27 1.27)))
)
(property "Footprint" "" (at 124.46 34.29 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "" (at 124.46 34.29 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 5bcdd992-60aa-43f8-9a53-cbbcac6751f7))
(instances
(project "GR8RAM"
(path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
(reference "#PWR0142") (unit 1)
)
(path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3/13d7a51b-3530-4ae9-b53c-5be82bc34799"
(reference "#PWR043") (unit 1)
)
)
)
)
(symbol (lib_id "power:+3V3") (at 124.46 97.79 0) (unit 1)
(in_bom yes) (on_board yes) (dnp no)
(uuid f03d6d88-452a-4ff6-9b6c-8ec6378dd805)
(property "Reference" "#PWR0142" (at 124.46 101.6 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Value" "+3V3" (at 124.46 93.98 0)
(effects (font (size 1.27 1.27)))
)
(property "Footprint" "" (at 124.46 97.79 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "" (at 124.46 97.79 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 264f1ac8-b8f7-4281-92d2-7ec51c14b2a0))
(instances
(project "GR8RAM"
(path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3"
(reference "#PWR0142") (unit 1)
)
(path "/a29f8df0-3fae-4edf-8d9c-bd5a875b13e3/13d7a51b-3530-4ae9-b53c-5be82bc34799"
(reference "#PWR041") (unit 1)
)
)
)
)
)

21
GR8RAM Normal file
View File

@ -0,0 +1,21 @@
Reference, Quantity, Value, Footprint, Datasheet, LCSC Part
C10 C1 C7 C2 C3 C4 C11 ,7,"10u","stdpads:C_0805","~","C15850"
C31 C30 C44 C43 C42 C35 C34 C33 C32 C26 C28 C27 C25 C24 C18 C23 C22 C21 C20 C19 C16 C15 C14 C13 C12 C29 C5 ,27,"2u2","stdpads:C_0603","~","C23630"
FID5 FID4 FID3 FID2 FID1 ,5,"Fiducial","stdpads:Fiducial","~"
H1 ,1," ","stdpads:PasteHole_1.1mm_PTH","~"
H6 H2 H3 H4 H5 ,5," ","stdpads:PasteHole_1.152mm_NPTH","~"
J1 ,1,"AppleIIBus","stdpads:AppleIIBus_Edge","~"
J2 J5 ,2,"JTAG","Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","~"
J4 ,1,"JTAG","Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical","~"
R22 R31 ,2,"33","stdpads:R_0603","~","C23140"
R28 R29 ,2,"22k","stdpads:R_0603","~","C31850"
RN2 RN3 RN1 ,3,"4x33","stdpads:R4_0402","~","C25501"
RN5 ,1,"4x10k","stdpads:R4_0402","~","C25725"
SW1 ,1,"FW","stdpads:SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm","~","C319052"
U1 ,1,"EPM240T100C5N","stdpads:TQFP-100_14x14mm_P0.5mm","https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf","C10041"
U13 ,1,"25M","stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm","","C669088"
U16 U14 ,2,"74LVC1G125GW","stdpads:SOT-353","","C12519"
U2 ,1,"W9825","stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm","","C62246"
U3 ,1,"W25Q128JVSIQ","stdpads:SOIC-8_5.3mm","","C164122"
U5 U6 U9 U4 ,4,"74AHC245PW","stdpads:TSSOP-20_4.4x6.5mm_P0.65mm","","C5516"
U8 ,1,"XC6206P332MR","stdpads:SOT-23","","C5446"

661
GR8RAM-cache.lib Normal file
View File

@ -0,0 +1,661 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_02x05_Odd_Even
#
DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 300 50 H V C CNN
F1 "Connector_Generic_Conn_02x05_Odd_Even" 50 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 150 -250 1 1 10 f
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_10 10 300 -200 150 L 50 50 1 1 P
X Pin_2 2 300 200 150 L 50 50 1 1 P
X Pin_3 3 -200 100 150 R 50 50 1 1 P
X Pin_4 4 300 100 150 L 50 50 1 1 P
X Pin_5 5 -200 0 150 R 50 50 1 1 P
X Pin_6 6 300 0 150 L 50 50 1 1 P
X Pin_7 7 -200 -100 150 R 50 50 1 1 P
X Pin_8 8 300 -100 150 L 50 50 1 1 P
X Pin_9 9 -200 -200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x25_Counter_Clockwise
#
DEF Connector_Generic_Conn_02x25_Counter_Clockwise J 0 40 Y N 1 F N
F0 "J" 50 1300 50 H V C CNN
F1 "Connector_Generic_Conn_02x25_Counter_Clockwise" 50 -1300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -1195 0 -1205 1 1 6 N
S -50 -1095 0 -1105 1 1 6 N
S -50 -995 0 -1005 1 1 6 N
S -50 -895 0 -905 1 1 6 N
S -50 -795 0 -805 1 1 6 N
S -50 -695 0 -705 1 1 6 N
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 605 0 595 1 1 6 N
S -50 705 0 695 1 1 6 N
S -50 805 0 795 1 1 6 N
S -50 905 0 895 1 1 6 N
S -50 1005 0 995 1 1 6 N
S -50 1105 0 1095 1 1 6 N
S -50 1205 0 1195 1 1 6 N
S -50 1250 150 -1250 1 1 10 f
S 150 -1195 100 -1205 1 1 6 N
S 150 -1095 100 -1105 1 1 6 N
S 150 -995 100 -1005 1 1 6 N
S 150 -895 100 -905 1 1 6 N
S 150 -795 100 -805 1 1 6 N
S 150 -695 100 -705 1 1 6 N
S 150 -595 100 -605 1 1 6 N
S 150 -495 100 -505 1 1 6 N
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
S 150 405 100 395 1 1 6 N
S 150 505 100 495 1 1 6 N
S 150 605 100 595 1 1 6 N
S 150 705 100 695 1 1 6 N
S 150 805 100 795 1 1 6 N
S 150 905 100 895 1 1 6 N
S 150 1005 100 995 1 1 6 N
S 150 1105 100 1095 1 1 6 N
S 150 1205 100 1195 1 1 6 N
X Pin_1 1 -200 1200 150 R 50 50 1 1 P
X Pin_10 10 -200 300 150 R 50 50 1 1 P
X Pin_11 11 -200 200 150 R 50 50 1 1 P
X Pin_12 12 -200 100 150 R 50 50 1 1 P
X Pin_13 13 -200 0 150 R 50 50 1 1 P
X Pin_14 14 -200 -100 150 R 50 50 1 1 P
X Pin_15 15 -200 -200 150 R 50 50 1 1 P
X Pin_16 16 -200 -300 150 R 50 50 1 1 P
X Pin_17 17 -200 -400 150 R 50 50 1 1 P
X Pin_18 18 -200 -500 150 R 50 50 1 1 P
X Pin_19 19 -200 -600 150 R 50 50 1 1 P
X Pin_2 2 -200 1100 150 R 50 50 1 1 P
X Pin_20 20 -200 -700 150 R 50 50 1 1 P
X Pin_21 21 -200 -800 150 R 50 50 1 1 P
X Pin_22 22 -200 -900 150 R 50 50 1 1 P
X Pin_23 23 -200 -1000 150 R 50 50 1 1 P
X Pin_24 24 -200 -1100 150 R 50 50 1 1 P
X Pin_25 25 -200 -1200 150 R 50 50 1 1 P
X Pin_26 26 300 -1200 150 L 50 50 1 1 P
X Pin_27 27 300 -1100 150 L 50 50 1 1 P
X Pin_28 28 300 -1000 150 L 50 50 1 1 P
X Pin_29 29 300 -900 150 L 50 50 1 1 P
X Pin_3 3 -200 1000 150 R 50 50 1 1 P
X Pin_30 30 300 -800 150 L 50 50 1 1 P
X Pin_31 31 300 -700 150 L 50 50 1 1 P
X Pin_32 32 300 -600 150 L 50 50 1 1 P
X Pin_33 33 300 -500 150 L 50 50 1 1 P
X Pin_34 34 300 -400 150 L 50 50 1 1 P
X Pin_35 35 300 -300 150 L 50 50 1 1 P
X Pin_36 36 300 -200 150 L 50 50 1 1 P
X Pin_37 37 300 -100 150 L 50 50 1 1 P
X Pin_38 38 300 0 150 L 50 50 1 1 P
X Pin_39 39 300 100 150 L 50 50 1 1 P
X Pin_4 4 -200 900 150 R 50 50 1 1 P
X Pin_40 40 300 200 150 L 50 50 1 1 P
X Pin_41 41 300 300 150 L 50 50 1 1 P
X Pin_42 42 300 400 150 L 50 50 1 1 P
X Pin_43 43 300 500 150 L 50 50 1 1 P
X Pin_44 44 300 600 150 L 50 50 1 1 P
X Pin_45 45 300 700 150 L 50 50 1 1 P
X Pin_46 46 300 800 150 L 50 50 1 1 P
X Pin_47 47 300 900 150 L 50 50 1 1 P
X Pin_48 48 300 1000 150 L 50 50 1 1 P
X Pin_49 49 300 1100 150 L 50 50 1 1 P
X Pin_5 5 -200 800 150 R 50 50 1 1 P
X Pin_50 50 300 1200 150 L 50 50 1 1 P
X Pin_6 6 -200 700 150 R 50 50 1 1 P
X Pin_7 7 -200 600 150 R 50 50 1 1 P
X Pin_8 8 -200 500 150 R 50 50 1 1 P
X Pin_9 9 -200 400 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Pack04
#
DEF Device_R_Pack04 RN 0 0 Y N 1 F N
F0 "RN" -300 0 50 V V C CNN
F1 "Device_R_Pack04" 200 0 50 V V C CNN
F2 "" 275 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
DIP*
SOIC*
$ENDFPLIST
DRAW
S -250 -95 150 95 0 1 10 f
S -225 75 -175 -75 0 1 10 N
S -125 75 -75 -75 0 1 10 N
S -25 75 25 -75 0 1 10 N
S 75 75 125 -75 0 1 10 N
P 2 0 1 0 -200 -100 -200 -75 N
P 2 0 1 0 -200 75 -200 100 N
P 2 0 1 0 -100 -100 -100 -75 N
P 2 0 1 0 -100 75 -100 100 N
P 2 0 1 0 0 -100 0 -75 N
P 2 0 1 0 0 75 0 100 N
P 2 0 1 0 100 -100 100 -75 N
P 2 0 1 0 100 75 100 100 N
X R1.1 1 -200 -200 100 U 50 50 1 1 P
X R2.1 2 -100 -200 100 U 50 50 1 1 P
X R3.1 3 0 -200 100 U 50 50 1 1 P
X R4.1 4 100 -200 100 U 50 50 1 1 P
X R4.2 5 100 200 100 D 50 50 1 1 P
X R3.2 6 0 200 100 D 50 50 1 1 P
X R2.2 7 -100 200 100 D 50 50 1 1 P
X R1.2 8 -200 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Small
#
DEF Device_R_Small R 0 10 N N 1 F N
F0 "R" 30 20 50 H V L CNN
F1 "Device_R_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -30 70 30 -70 0 1 8 N
X ~ 1 0 100 30 D 50 50 1 1 P
X ~ 2 0 -100 30 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GW_Logic_741G125GW
#
DEF GW_Logic_741G125GW U 0 40 Y Y 1 F N
F0 "U" 0 250 50 H V C CNN
F1 "GW_Logic_741G125GW" 0 -250 50 H V C CNN
F2 "stdpads:SOT-353" 0 -300 50 H I C TNN
F3 "" 0 -200 60 H I C CNN
DRAW
S 200 -200 -200 200 0 1 10 f
X ~OE~ 1 -400 100 200 R 50 50 1 1 I
X A 2 -400 0 200 R 50 50 1 1 I
X GND 3 -400 -100 200 R 50 50 1 1 W
X Y 4 400 -100 200 L 50 50 1 1 O
X Vcc 5 400 100 200 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GW_Logic_74245
#
DEF GW_Logic_74245 U 0 40 Y Y 1 F N
F0 "U" 0 600 50 H V C CNN
F1 "GW_Logic_74245" 0 -600 50 H V C CNN
F2 "" 0 -650 50 H I C TNN
F3 "" 0 100 60 H I C CNN
DRAW
S -200 550 200 -550 0 1 10 f
X AtoB 1 -400 450 200 R 50 50 1 1 I
X GND 10 -400 -450 200 R 50 50 1 1 W
X B7 11 400 -450 200 L 50 50 1 1 B
X B6 12 400 -350 200 L 50 50 1 1 B
X B5 13 400 -250 200 L 50 50 1 1 B
X B4 14 400 -150 200 L 50 50 1 1 B
X B3 15 400 -50 200 L 50 50 1 1 B
X B2 16 400 50 200 L 50 50 1 1 B
X B1 17 400 150 200 L 50 50 1 1 B
X B0 18 400 250 200 L 50 50 1 1 B
X ~OE~ 19 400 350 200 L 50 50 1 1 I
X A0 2 -400 350 200 R 50 50 1 1 B
X Vcc 20 400 450 200 L 50 50 1 1 W
X A1 3 -400 250 200 R 50 50 1 1 B
X A2 4 -400 150 200 R 50 50 1 1 B
X A3 5 -400 50 200 R 50 50 1 1 B
X A4 6 -400 -50 200 R 50 50 1 1 B
X A5 7 -400 -150 200 R 50 50 1 1 B
X A6 8 -400 -250 200 R 50 50 1 1 B
X A7 9 -400 -350 200 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
# GW_Logic_Oscillator_4P
#
DEF GW_Logic_Oscillator_4P U 0 40 Y Y 1 F N
F0 "U" 0 250 50 H V C CNN
F1 "GW_Logic_Oscillator_4P" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -250 200 250 -100 0 1 10 f
X EN 1 -350 100 100 R 50 50 1 1 I
X GND 2 -350 0 100 R 50 50 1 1 W
X Output 3 350 0 100 L 50 50 1 1 O
X Vdd 4 350 100 100 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GW_PLD_EPM240T100
#
DEF GW_PLD_EPM240T100 U 0 40 Y Y 1 F N
F0 "U" 0 50 50 H V C CNN
F1 "GW_PLD_EPM240T100" 0 -50 50 H V C CNN
F2 "stdpads:TQFP-100_14x14mm_P0.5mm" 0 -100 20 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
*QFP*P0.5mm*
$ENDFPLIST
DRAW
S -800 2200 800 -2200 1 1 10 f
X IO2_1 1 1000 2100 200 L 50 50 1 1 B
X GNDIO 10 -200 -2400 200 U 50 50 1 1 W
X IO2_100 100 1000 -2000 200 L 50 50 1 1 B
X GNDINT 11 -400 -2400 200 U 50 50 1 1 W
X IO1_12/GCLK0 12 -1000 1400 200 R 50 50 1 1 B C
X VCCINT 13 -400 2400 200 D 50 50 1 1 W
X IO1_14/GCLK1 14 -1000 1300 200 R 50 50 1 1 B C
X IO1_15 15 -1000 1200 200 R 50 50 1 1 B
X IO1_16 16 -1000 1100 200 R 50 50 1 1 B
X IO1_17 17 -1000 1000 200 R 50 50 1 1 B
X IO1_18 18 -1000 900 200 R 50 50 1 1 B
X IO1_19 19 -1000 800 200 R 50 50 1 1 B
X IO1_2 2 -1000 2100 200 R 50 50 1 1 B
X IO1_20 20 -1000 700 200 R 50 50 1 1 B
X IO1_21 21 -1000 600 200 R 50 50 1 1 B
X TMS 22 -1000 -1700 200 R 50 50 1 1 I
X TDI 23 -1000 -1800 200 R 50 50 1 1 I
X TCK 24 -1000 -1900 200 R 50 50 1 1 I C
X TDO 25 -1000 -2000 200 R 50 50 1 1 O
X IO1_26 26 -1000 500 200 R 50 50 1 1 B
X IO1_27 27 -1000 400 200 R 50 50 1 1 B
X IO1_28 28 -1000 300 200 R 50 50 1 1 B
X IO1_29 29 -1000 200 200 R 50 50 1 1 B
X IO1_3 3 -1000 2000 200 R 50 50 1 1 B
X IO1_30 30 -1000 100 200 R 50 50 1 1 B
X VCCIO1 31 -100 2400 200 D 50 50 1 1 W
X GNDIO 32 -100 -2400 200 U 50 50 1 1 W
X IO1_33 33 -1000 0 200 R 50 50 1 1 B
X IO1_34 34 -1000 -100 200 R 50 50 1 1 B
X IO1_35 35 -1000 -200 200 R 50 50 1 1 B
X IO1_36 36 -1000 -300 200 R 50 50 1 1 B
X IO1_37 37 -1000 -400 200 R 50 50 1 1 B
X IO1_38 38 -1000 -500 200 R 50 50 1 1 B
X IO1_39 39 -1000 -600 200 R 50 50 1 1 B
X IO1_4 4 -1000 1900 200 R 50 50 1 1 B
X IO1_40 40 -1000 -700 200 R 50 50 1 1 B
X IO1_41 41 -1000 -800 200 R 50 50 1 1 B
X IO1_42 42 -1000 -900 200 R 50 50 1 1 B
X IO1_43/DEV_OE 43 -1000 -1000 200 R 50 50 1 1 B
X IO1_44/DEV_CLRn 44 -1000 -1100 200 R 50 50 1 1 B
X VCCIO1 45 0 2400 200 D 50 50 1 1 W
X GNDIO 46 0 -2400 200 U 50 50 1 1 W
X IO1_47 47 -1000 -1200 200 R 50 50 1 1 B
X IO1_48 48 -1000 -1300 200 R 50 50 1 1 B
X IO1_49 49 -1000 -1400 200 R 50 50 1 1 B
X IO1_5 5 -1000 1800 200 R 50 50 1 1 B
X IO1_50 50 -1000 -1500 200 R 50 50 1 1 B
X IO1_51 51 -1000 -1600 200 R 50 50 1 1 B
X IO2_52 52 1000 2000 200 L 50 50 1 1 B
X IO2_53 53 1000 1900 200 L 50 50 1 1 B
X IO2_54 54 1000 1800 200 L 50 50 1 1 B
X IO2_55 55 1000 1700 200 L 50 50 1 1 B
X IO2_56 56 1000 1600 200 L 50 50 1 1 B
X IO2_57 57 1000 1500 200 L 50 50 1 1 B
X IO2_58 58 1000 1400 200 L 50 50 1 1 B
X VCCIO2 59 100 2400 200 D 50 50 1 1 W
X IO1_6 6 -1000 1700 200 R 50 50 1 1 B
X GNDIO 60 100 -2400 200 U 50 50 1 1 W
X IO2_61 61 1000 1300 200 L 50 50 1 1 B
X IO2_62/GCLK2 62 1000 1200 200 L 50 50 1 1 B C
X VCCINT 63 -300 2400 200 D 50 50 1 1 W
X IO2_64/GCLK3 64 1000 1100 200 L 50 50 1 1 B C
X GNDINT 65 -300 -2400 200 U 50 50 1 1 W
X IO2_66 66 1000 1000 200 L 50 50 1 1 B
X IO2_67 67 1000 900 200 L 50 50 1 1 B
X IO2_68 68 1000 800 200 L 50 50 1 1 B
X IO2_69 69 1000 700 200 L 50 50 1 1 B
X IO1_7 7 -1000 1600 200 R 50 50 1 1 B
X IO2_70 70 1000 600 200 L 50 50 1 1 B
X IO2_71 71 1000 500 200 L 50 50 1 1 B
X IO2_72 72 1000 400 200 L 50 50 1 1 B
X IO2_73 73 1000 300 200 L 50 50 1 1 B
X IO2_74 74 1000 200 200 L 50 50 1 1 B
X IO2_75 75 1000 100 200 L 50 50 1 1 B
X IO2_76 76 1000 0 200 L 50 50 1 1 B
X IO2_77 77 1000 -100 200 L 50 50 1 1 B
X IO2_78 78 1000 -200 200 L 50 50 1 1 B
X GNDIO 79 200 -2400 200 U 50 50 1 1 W
X IO1_8 8 -1000 1500 200 R 50 50 1 1 B
X VCCIO2 80 200 2400 200 D 50 50 1 1 W
X IO2_81 81 1000 -300 200 L 50 50 1 1 B
X IO2_82 82 1000 -400 200 L 50 50 1 1 B
X IO2_83 83 1000 -500 200 L 50 50 1 1 B
X IO2_84 84 1000 -600 200 L 50 50 1 1 B
X IO2_85 85 1000 -700 200 L 50 50 1 1 B
X IO2_86 86 1000 -800 200 L 50 50 1 1 B
X IO2_87 87 1000 -900 200 L 50 50 1 1 B
X IO2_88 88 1000 -1000 200 L 50 50 1 1 B
X IO2_89 89 1000 -1100 200 L 50 50 1 1 B
X VCCIO1 9 -200 2400 200 D 50 50 1 1 W
X IO2_90 90 1000 -1200 200 L 50 50 1 1 B
X IO2_91 91 1000 -1300 200 L 50 50 1 1 B
X IO2_92 92 1000 -1400 200 L 50 50 1 1 B
X GNDIO 93 300 -2400 200 U 50 50 1 1 W
X VCCIO2 94 300 2400 200 D 50 50 1 1 W
X IO2_95 95 1000 -1500 200 L 50 50 1 1 B
X IO2_96 96 1000 -1600 200 L 50 50 1 1 B
X IO2_97 97 1000 -1700 200 L 50 50 1 1 B
X IO2_98 98 1000 -1800 200 L 50 50 1 1 B
X IO2_99 99 1000 -1900 200 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# GW_Power_AP2125
#
DEF GW_Power_AP2125 U 0 40 Y Y 1 F N
F0 "U" 0 250 50 H V C CNN
F1 "GW_Power_AP2125" 0 -250 50 H V C CNN
F2 "stdpads:SOT-23" 0 -300 50 H I C TNN
F3 "" 0 -100 60 H I C CNN
DRAW
S -250 200 250 -200 0 1 10 f
X GND 1 -450 -100 200 R 50 50 1 1 W
X Vout 2 450 100 200 L 50 50 1 1 w
X Vin 3 -450 100 200 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GW_RAM_SDRAM-16Mx16-TSOP2-54
#
DEF GW_RAM_SDRAM-16Mx16-TSOP2-54 U 0 40 Y Y 1 F N
F0 "U" 0 1150 50 H V C CNN
F1 "GW_RAM_SDRAM-16Mx16-TSOP2-54" 0 0 50 V V C CNN
F2 "stdpads:Winbond_TSOPII-54" 0 -1650 50 H I C CIN
F3 "" 0 -250 50 H I C CNN
DRAW
S -300 1100 300 -1400 0 1 10 f
X VDD 1 -500 1000 200 R 50 50 1 1 W
X DQ5 10 500 500 200 L 50 50 1 1 B
X DQ6 11 500 400 200 L 50 50 1 1 B
X VSSQ 12 -500 -1300 200 R 50 50 1 1 W N
X DQ7 13 500 300 200 L 50 50 1 1 B
X VDD 14 -500 1000 200 R 50 50 1 1 W N
X DQML 15 500 -600 200 L 50 50 1 1 I
X ~WE~ 16 500 -1100 200 L 50 50 1 1 I
X ~CAS~ 17 500 -1200 200 L 50 50 1 1 I
X ~RAS~ 18 500 -1300 200 L 50 50 1 1 I
X ~CS~ 19 500 -1000 200 L 50 50 1 1 I
X DQ0 2 500 1000 200 L 50 50 1 1 B
X BA0 20 -500 -600 200 R 50 50 1 1 I
X BA1 21 -500 -700 200 R 50 50 1 1 I
X A10 22 -500 -300 200 R 50 50 1 1 I
X A0 23 -500 700 200 R 50 50 1 1 I
X A1 24 -500 600 200 R 50 50 1 1 I
X A2 25 -500 500 200 R 50 50 1 1 I
X A3 26 -500 400 200 R 50 50 1 1 I
X VDD 27 -500 1000 200 R 50 50 1 1 W N
X VSS 28 -500 -1200 200 R 50 50 1 1 W
X A4 29 -500 300 200 R 50 50 1 1 I
X VDDQ 3 -500 900 200 R 50 50 1 1 W
X A5 30 -500 200 200 R 50 50 1 1 I
X A6 31 -500 100 200 R 50 50 1 1 I
X A7 32 -500 0 200 R 50 50 1 1 I
X A8 33 -500 -100 200 R 50 50 1 1 I
X A9 34 -500 -200 200 R 50 50 1 1 I
X A11 35 -500 -400 200 R 50 50 1 1 I
X A12 36 -500 -500 200 R 50 50 1 1 I
X CKE 37 -500 -900 200 R 50 50 1 1 I
X CLK 38 -500 -1000 200 R 50 50 1 1 I
X DQMH 39 500 -700 200 L 50 50 1 1 I
X DQ1 4 500 900 200 L 50 50 1 1 B
X VSS 41 -500 -1200 200 R 50 50 1 1 W N
X DQ8 42 500 200 200 L 50 50 1 1 B
X VDDQ 43 -500 900 200 R 50 50 1 1 W N
X DQ9 44 500 100 200 L 50 50 1 1 B
X DQ10 45 500 0 200 L 50 50 1 1 B
X VSSQ 46 -500 -1300 200 R 50 50 1 1 W N
X DQ11 47 500 -100 200 L 50 50 1 1 B
X DQ12 48 500 -200 200 L 50 50 1 1 B
X VDDQ 49 -500 900 200 R 50 50 1 1 W N
X DQ2 5 500 800 200 L 50 50 1 1 B
X DQ13 50 500 -300 200 L 50 50 1 1 B
X DQ14 51 500 -400 200 L 50 50 1 1 B
X VSSQ 52 -500 -1300 200 R 50 50 1 1 W N
X DQ15 53 500 -500 200 L 50 50 1 1 B
X VSS 54 -500 -1200 200 R 50 50 1 1 W N
X VSSQ 6 -500 -1300 200 R 50 50 1 1 W
X DQ3 7 500 700 200 L 50 50 1 1 B
X DQ4 8 500 600 200 L 50 50 1 1 B
X VDDQ 9 -500 900 200 R 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# GW_RAM_SPIFlash-SO-8
#
DEF GW_RAM_SPIFlash-SO-8 U 0 40 Y Y 1 F N
F0 "U" 0 350 50 H V C CNN
F1 "GW_RAM_SPIFlash-SO-8" 0 -250 50 H V C CNN
F2 "stdpads:Hybrid_SPIFlash_SOIC-8_SOIC-16" 0 -300 50 H I C TNN
F3 "" 0 0 50 H I C TNN
DRAW
S -350 300 350 -200 0 1 10 f
X ~CS~ 1 -550 200 200 R 50 50 1 1 I
X DO/IO1 2 -550 100 200 R 50 50 1 1 B
X ~WP~/IO2 3 -550 0 200 R 50 50 1 1 B
X GND 4 -550 -100 200 R 50 50 1 1 W
X DI/IO0 5 550 -100 200 L 50 50 1 1 B
X CLK 6 550 0 200 L 50 50 1 1 I
X ~HLD~/IO3 7 550 100 200 L 50 50 1 1 B
X Vcc 8 550 200 200 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# Mechanical_Fiducial
#
DEF Mechanical_Fiducial FID 0 20 Y Y 1 F N
F0 "FID" 0 200 50 H V C CNN
F1 "Mechanical_Fiducial" 0 125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Fiducial*
$ENDFPLIST
DRAW
C 0 0 50 0 1 20 f
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole
#
DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
F0 "H" 0 200 50 H V C CNN
F1 "Mechanical_MountingHole" 0 125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*
$ENDFPLIST
DRAW
C 0 0 50 0 1 50 N
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole_Pad
#
DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
F0 "H" 0 250 50 H V C CNN
F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*Pad*
$ENDFPLIST
DRAW
C 0 50 50 0 1 50 N
X 1 1 0 -100 100 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# Switch_SW_DIP_x02
#
DEF Switch_SW_DIP_x02 SW 0 0 Y N 1 F N
F0 "SW" 0 250 50 H V C CNN
F1 "Switch_SW_DIP_x02" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
SW?DIP?x2*
$ENDFPLIST
DRAW
C -80 0 20 0 0 0 N
C -80 100 20 0 0 0 N
C 80 0 20 0 0 0 N
C 80 100 20 0 0 0 N
S -150 200 150 -100 0 1 10 f
P 2 0 0 0 -60 5 93 46 N
P 2 0 0 0 -60 105 93 146 N
X ~ 1 -300 100 200 R 50 50 1 1 P
X ~ 2 -300 0 200 R 50 50 1 1 P
X ~ 3 300 0 200 L 50 50 1 1 P
X ~ 4 300 100 200 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+12V
#
DEF power_+12V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+12V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +12V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3V3
#
DEF power_+3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_-12V
#
DEF power_-12V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 100 50 H I C CNN
F1 "power_-12V" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
X -12V 1 0 0 0 U 50 50 0 0 W N
ENDDRAW
ENDDEF
#
# power_-5V
#
DEF power_-5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 100 50 H I C CNN
F1 "power_-5V" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
X -5V 1 0 0 0 U 50 50 0 0 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

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"active_layer_preset": "All Layers",
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"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
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{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.15,
@ -58,26 +57,20 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
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"items_not_allowed": "error",
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"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
@ -87,14 +80,9 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
@ -103,6 +91,7 @@
"unconnected_items": "error",
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"via_dangling": "warning",
"zone_has_empty_net": "error",
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},
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},
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""
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(kicad_sch (version 20230121) (generator eeschema)
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31
cpld/GR8RAM.qpf Normal file
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@ -0,0 +1,31 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2019 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
# Date created = 20:42:53 February 16, 2024
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "19.1"
DATE = "20:42:53 February 16, 2024"
# Revisions
PROJECT_REVISION = "GR8RAM"

252
cpld/GR8RAM.qsf Normal file
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@ -0,0 +1,252 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2019 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
# Date created = 20:36:06 February 16, 2024
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# GR8RAM_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:36:06 FEBRUARY 16, 2024"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name SDC_FILE GR8RAM.sdc
set_global_assignment -name VERILOG_FILE GR8RAM.v
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_location_assignment PIN_2 -to RA[5]
set_location_assignment PIN_3 -to RA[6]
set_location_assignment PIN_4 -to RA[3]
set_location_assignment PIN_5 -to nFCS
set_location_assignment PIN_6 -to RA[7]
set_location_assignment PIN_7 -to RA[8]
set_location_assignment PIN_8 -to RA[9]
set_location_assignment PIN_12 -to FCK
set_location_assignment PIN_14 -to RA[10]
set_location_assignment PIN_15 -to MOSI
set_location_assignment PIN_16 -to MISO
set_location_assignment PIN_30 -to nRESout
set_location_assignment PIN_34 -to RA[11]
set_location_assignment PIN_35 -to RA[12]
set_location_assignment PIN_36 -to RA[13]
set_location_assignment PIN_37 -to RA[14]
set_location_assignment PIN_38 -to RA[15]
set_location_assignment PIN_39 -to nIOSEL
set_location_assignment PIN_42 -to nIOSTRB
set_location_assignment PIN_40 -to nDEVSEL
set_location_assignment PIN_41 -to PHI0
set_location_assignment PIN_43 -to nWE
set_location_assignment PIN_44 -to nRES
set_location_assignment PIN_47 -to SD[1]
set_location_assignment PIN_50 -to SD[0]
set_location_assignment PIN_51 -to SD[4]
set_location_assignment PIN_100 -to RA[0]
set_location_assignment PIN_99 -to RD[7]
set_location_assignment PIN_52 -to SD[5]
set_location_assignment PIN_54 -to SD[7]
set_location_assignment PIN_55 -to SD[3]
set_location_assignment PIN_56 -to SD[2]
set_location_assignment PIN_53 -to SD[6]
set_location_assignment PIN_57 -to DQMH
set_location_assignment PIN_58 -to nSWE
set_location_assignment PIN_62 -to nRAS
set_location_assignment PIN_61 -to nCAS
set_location_assignment PIN_64 -to C25M
set_location_assignment PIN_66 -to RCKE
set_location_assignment PIN_67 -to nRCS
set_location_assignment PIN_68 -to SA[12]
set_location_assignment PIN_69 -to SBA[0]
set_location_assignment PIN_70 -to SA[11]
set_location_assignment PIN_71 -to SBA[1]
set_location_assignment PIN_72 -to SA[9]
set_location_assignment PIN_73 -to SA[10]
set_location_assignment PIN_74 -to SA[8]
set_location_assignment PIN_75 -to SA[0]
set_location_assignment PIN_76 -to SA[4]
set_location_assignment PIN_77 -to SA[6]
set_location_assignment PIN_78 -to SA[7]
set_location_assignment PIN_81 -to SA[1]
set_location_assignment PIN_82 -to SA[2]
set_location_assignment PIN_83 -to SA[5]
set_location_assignment PIN_84 -to SA[3]
set_location_assignment PIN_85 -to DQML
set_location_assignment PIN_86 -to RD[0]
set_location_assignment PIN_87 -to RD[1]
set_location_assignment PIN_88 -to RD[2]
set_location_assignment PIN_89 -to RD[3]
set_location_assignment PIN_90 -to RD[4]
set_location_assignment PIN_91 -to RD[5]
set_location_assignment PIN_92 -to RD[6]
set_location_assignment PIN_97 -to RA[2]
set_location_assignment PIN_98 -to RA[1]
set_location_assignment PIN_96 -to SetFW[0]
set_location_assignment PIN_95 -to SetFW[1]
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nFCS
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nFCS
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to FCK
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to FCK
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MOSI
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MOSI
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MISO
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MISO
set_location_assignment PIN_21 -to nDMAout
set_location_assignment PIN_19 -to RAdir
set_location_assignment PIN_20 -to INTout
set_location_assignment PIN_26 -to nNMIout
set_location_assignment PIN_27 -to nINHout
set_location_assignment PIN_28 -to nRDYout
set_location_assignment PIN_29 -to nIRQout
set_location_assignment PIN_33 -to RWout
set_location_assignment PIN_48 -to DMAin
set_location_assignment PIN_49 -to INTin
set_location_assignment PIN_17 -to RDdir
set_location_assignment PIN_18 -to DMAout
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAdir
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RAdir
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RAdir
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAdir
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAdir
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RDdir
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RDdir
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RDdir
set_instance_assignment -name SLOW_SLEW_RATE ON -to RDdir
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RDdir
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to PHI0
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI0
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to PHI0
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nWE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nWE
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nDEVSEL
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nDEVSEL
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nDEVSEL
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nIOSEL
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSEL
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSEL
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nIOSTRB
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSTRB
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSTRB
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nRES
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRES
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRES
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRESout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nRESout
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRESout
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRESout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRESout
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nFCS
set_instance_assignment -name SLOW_SLEW_RATE ON -to nFCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nFCS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FCK
set_instance_assignment -name SLOW_SLEW_RATE ON -to FCK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to FCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MOSI
set_instance_assignment -name SLOW_SLEW_RATE ON -to MOSI
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to C25M
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C25M
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to C25M
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRCS
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRCS
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRCS
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRAS
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRAS
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nCAS
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nCAS
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nSWE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nSWE
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nSWE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nSWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSWE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RCKE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RCKE
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RCKE
set_instance_assignment -name SLOW_SLEW_RATE ON -to RCKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBA
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SBA
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SBA
set_instance_assignment -name SLOW_SLEW_RATE ON -to SBA
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SBA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA
set_instance_assignment -name SLOW_SLEW_RATE ON -to SA
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQMH
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQMH
set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQML
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQML
set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SetFW
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SetFW
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SetFW
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SD
set_instance_assignment -name SLOW_SLEW_RATE ON -to SD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD

3
cpld/GR8RAM.sdc Normal file
View File

@ -0,0 +1,3 @@
create_clock -period 40 [get_ports C25M]
create_clock -period 978 [get_ports PHI0]
set_clock_groups -asynchronous -group C25M -group PHI0

568
cpld/GR8RAM.v Normal file
View File

@ -0,0 +1,568 @@
module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
INTin, INTout, DMAin, DMAout,
nNMIout, nIRQout, nRDYout, nINHout, RWout, nDMAout,
RA, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB,
SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
nFCS, FCK, MISO, MOSI);
/* Clock signals */
input C25M, PHI0;
reg PHI0r1, PHI0r2;
always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
/* Reset filter */
input nRES;
reg [3:0] nRESf = 0;
reg nRESr = 0;
always @(posedge C25M) begin
nRESf[3:0] <= { nRESf[2:0], nRES };
nRESr <= nRESf[3] || nRESf[2] || nRESf[1] || nRESf[0];
end
/* Firmware select */
input [1:0] SetFW;
reg [1:0] SetFWr;
reg SetFWLoaded = 0;
always @(posedge C25M) begin
if (!SetFWLoaded) begin
SetFWLoaded <= 1;
SetFWr[1:0] <= SetFW[1:0];
end
end
wire [1:0] SetROM = ~SetFWr[1:0];
wire SetEN16MB = SetROM[1:0]==2'b11;
wire SetEN24bit = SetROM[1];
/* State counter from PHI0 rising edge */
reg [3:0] PS = 0;
wire PSStart = PS==0 && PHI0r1 && !PHI0r2;
always @(posedge C25M) begin
if (PSStart) PS <= 1;
else if (PS==0) PS <= 0;
else PS <= PS+1;
end
/* Long state counter: counts from 0 to $3FFF */
reg [13:0] LS = 0;
always @(posedge C25M) begin if (PS==15) LS <= LS+1; end
/* Init state */
output reg nRESout = 0;
reg [2:0] IS = 0;
always @(posedge C25M) begin
if (IS==7) nRESout <= 1;
else if (PS==15) begin
if (LS==14'h1FCE) IS <= 1; // PC all + load mode
else if (LS==14'h1FCF) IS <= 4; // AREF pause, SPI select
else if (LS==14'h1FFA) IS <= 5; // SPI flash command
else if (LS==14'h1FFF) IS <= 6; // Flash load driver
else if (LS==14'h3FFF) IS <= 7; // Operating mode
end
end
/* Apple IO area select signals */
input nIOSEL, nDEVSEL, nIOSTRB;
/* Apple address bus */
input [15:0] RA; input nWE;
reg [11:0] RAr; reg nWEr;
reg CXXXr;
always @(posedge PHI0) begin
CXXXr <= RA[15:12]==4'hC;
RAr[11:0] <= RA[11:0];
nWEr <= nWE;
end
/* Apple select signals */
wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (!RAr[11]));
wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
wire RAMSpecSEL = RAMRegSpecSEL && (!SetEN24bit || SetEN16MB || !Addr[23]);
wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1;
wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0;
wire BankSEL = REGEN && !nDEVSEL && BankSpecSEL;
wire RAMRegSEL = !nDEVSEL && RAMRegSpecSEL;
wire RAMSEL = !nDEVSEL && RAMSpecSEL;
wire RAMWR = RAMSEL && !nWEr;
wire AddrHSEL = REGEN && !nDEVSEL && AddrHSpecSEL;
wire AddrMSEL = REGEN && !nDEVSEL && AddrMSpecSEL;
wire AddrLSEL = REGEN && !nDEVSEL && AddrLSpecSEL;
/* IOROMEN and REGEN control */
reg IOROMEN = 0;
reg REGEN = 0;
reg nIOSTRBr;
wire IOROMRES = RAr[10:0]==11'h7FF && !nIOSTRB && !nIOSTRBr;
always @(posedge C25M, negedge nRESr) begin
if (!nRESr) REGEN <= 0;
else if (PS==8 && !nIOSEL) REGEN <= 1;
end
always @(posedge C25M) begin
nIOSTRBr <= nIOSTRB;
if (!nRESr) IOROMEN <= 0;
else if (PS==8 && IOROMRES) IOROMEN <= 0;
else if (PS==8 && !nIOSEL) IOROMEN <= 1;
end
/* Apple data bus */
inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
reg [7:0] RDD;
output RDdir = !(PHI0r2 && nWE && PHI0 &&
(!nDEVSEL || !nIOSEL || (!nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF)));
/* Slinky address registers */
reg [23:0] Addr = 0;
reg AddrIncL = 0;
reg AddrIncM = 0;
reg AddrIncH = 0;
always @(posedge C25M, negedge nRESr) begin
if (!nRESr) begin
Addr[23:0] <= 24'h000000;
AddrIncL <= 0;
AddrIncM <= 0;
AddrIncH <= 0;
end else begin
if (PS==8 && RAMRegSEL) AddrIncL <= 1;
else AddrIncL <= 0;
if (PS==8 && AddrLSEL && !nWEr) begin
Addr[7:0] <= RD[7:0];
AddrIncM <= Addr[7] && !RD[7];
end else if (AddrIncL) begin
Addr[7:0] <= Addr[7:0]+1;
AddrIncM <= Addr[7:0]==8'hFF;
end else AddrIncM <= 0;
if (PS==8 && AddrMSEL && !nWEr) begin
Addr[15:8] <= RD[7:0];
AddrIncH <= Addr[15] && !RD[7];
end else if (AddrIncM) begin
Addr[15:8] <= Addr[15:8]+1;
AddrIncH <= Addr[15:8]==8'hFF;
end else AddrIncH <= 0;
if (PS==8 && AddrHSEL && !nWEr) begin
Addr[23:16] <= RD[7:0];
end else if (AddrIncH) begin
Addr[23:16] <= Addr[23:16]+1;
end
end
end
/* ROM bank register */
reg Bank = 0;
always @(posedge C25M, negedge nRESr) begin
if (!nRESr) Bank <= 0;
else if (PS==8 && BankSEL && !nWEr) begin
Bank <= RD[0];
end
end
/* SPI flash control signals */
output nFCS = FCKOE ? !FCS : 1'bZ;
reg FCS = 0;
output FCK = FCKOE ? FCKout : 1'bZ;
reg FCKOE = 0;
reg FCKout = 0;
inout MOSI = MOSIOE ? MOSIout : 1'bZ;
reg MOSIOE = 0;
input MISO;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE
FCKout <= 1'b1;
end 1: begin // ACT
FCKout <= !(IS==5 || IS==6);
end 2: begin // RD
FCKout <= 1'b1;
end 3: begin // NOP CKE
FCKout <= !(IS==5 || IS==6);
end 4: begin // NOP CKE
FCKout <= 1'b1;
end 5: begin // NOP CKE
FCKout <= !(IS==5 || IS==6);
end 6: begin // NOP CKE
FCKout <= 1'b1;
end 7: begin // NOP CKE
FCKout <= !(IS==5 || IS==6);
end 8: begin // WR AP
FCKout <= 1'b1;
end 9: begin // NOP CKE
FCKout <= !(IS==5);
end 10: begin // PC all
FCKout <= 1'b1;
end 11: begin // AREF
FCKout <= !(IS==5);
end 12: begin // NOP CKE
FCKout <= 1'b1;
end 13: begin // NOP CKE
FCKout <= !(IS==5);
end 14: begin // NOP CKE
FCKout <= 1'b1;
end 15: begin // NOP CKE
FCKout <= !(IS==5);
end
endcase
FCS <= IS==4 || IS==5 || IS==6;
MOSIOE <= IS==5;
FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7;
end
/* SPI flash MOSI control */
reg MOSIout = 0;
always @(posedge C25M) begin
case (PS[3:0])
1: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b0; // Command bit 7
3'h4: MOSIout <= 1'b0; // Address bit 23
3'h5: MOSIout <= 1'b0; // Address bit 15
3'h6: MOSIout <= 1'b0; // Address bit 7
default MOSIout <= 1'b0;
endcase
end 3: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b0; // Command bit 6
3'h4: MOSIout <= 1'b0; // Address bit 22
3'h5: MOSIout <= SetROM[1]; // Address bit 14
3'h6: MOSIout <= 1'b0; // Address bit 6
default MOSIout <= 1'b0;
endcase
end 5: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 5
3'h4: MOSIout <= 1'b0; // Address bit 21
3'h5: MOSIout <= SetROM[0]; // Address bit 13
3'h6: MOSIout <= 1'b0; // Address bit 5
default MOSIout <= 1'b0;
endcase
end 7: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 4
3'h4: MOSIout <= 1'b0; // Address bit 20
3'h5: MOSIout <= 1'b0; // Address bit 12
3'h6: MOSIout <= 1'b0; // Address bit 4
default MOSIout <= 1'b0;
endcase
end 9: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 3
3'h4: MOSIout <= 1'b0; // Address bit 19
3'h5: MOSIout <= 1'b0; // Address bit 11
3'h6: MOSIout <= 1'b0; // Address bit 3
default MOSIout <= 1'b0;
endcase
end 11: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b0; // Command bit 2
3'h4: MOSIout <= 1'b0; // Address bit 18
3'h5: MOSIout <= 1'b0; // Address bit 10
3'h6: MOSIout <= 1'b0; // Address bit 2
default MOSIout <= 1'b0;
endcase
end 13: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 1
3'h4: MOSIout <= 1'b0; // Address bit 16
3'h5: MOSIout <= 1'b0; // Address bit 9
3'h6: MOSIout <= 1'b0; // Address bit 1
default MOSIout <= 1'b0;
endcase
end 15: begin
case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 0
3'h4: MOSIout <= 1'b0; // Address bit 15
3'h5: MOSIout <= 1'b0; // Address bit 7
3'h6: MOSIout <= 1'b0; // Address bit 0
default MOSIout <= 1'b0;
endcase
end
endcase
end
/* SDRAM data bus */
inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
reg [7:0] WRD;
reg SDOE = 0;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 1: begin // ACT
end 2: begin // RD
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 3: begin // NOP CKE
end 4: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 5: begin // NOP CKE
end 6: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 7: begin // NOP CKE
end 8: begin // WR AP
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 9: begin // NOP CKE
end 10: begin // PC all
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 11: begin // AREF
end 12: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 13: begin // NOP CKE
end 14: begin // NOP CKE
if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
else WRD[7:0] <= RD[7:0];
end 15: begin // NOP CKE
end
endcase
end
/* Apple data bus from SDRAM */
always @(negedge C25M) begin
if (PS==5) begin
if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
else RDD[7:0] <= SD[7:0];
end
end
/* SDRAM command */
output reg RCKE = 1;
output reg nRCS = 1;
output reg nRAS = 1;
output reg nCAS = 1;
output reg nSWE = 1;
wire RefReqd = LS[1:0] == 2'b11;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE / NOP CKD
RCKE <= PSStart && (IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 1: begin // ACT CKE / NOP CKD (ACT)
RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL));
nRCS <= !(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
nRAS <= 0;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 2: begin // RD CKE / NOP CKD (RD)
RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
nRCS <= !(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL));
nRAS <= 1;
nCAS <= 0;
nSWE <= 1;
SDOE <= 0;
end 3: begin // NOP CKE / CKD
RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 4: begin // NOP CKD
RCKE <= 0;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 5: begin // NOP CKD
RCKE <= 0;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 6: begin // NOP CKD
RCKE <= 0;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 7: begin // NOP CKE / CKD
RCKE <= IS==6 || (RAMWR && IS==7);
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 8: begin // WR AP CKE / NOP CKD (WR AP)
RCKE <= IS==6 || (RAMWR && IS==7);
nRCS <= !(IS==6 || (RAMWR && IS==7));
nRAS <= 1;
nCAS <= 0;
nSWE <= 0;
SDOE <= IS==6 || (RAMWR && IS==7);
end 9: begin // NOP CKE / NOP CKD
RCKE <= 1;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 10: begin // PC all CKE / PC all CKD
RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
nRCS <= 0;
nRAS <= 0;
nCAS <= 1;
nSWE <= 0;
SDOE <= 0;
end 11: begin // LDM CKE / AREF CKE / NOP CKD
RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
nRCS <= !(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd));
nRAS <= 0;
nCAS <= 0;
nSWE <= !(IS==1);
SDOE <= 0;
end default: begin // NOP CKD
RCKE <= 0;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end
endcase
end
/* SDRAM address */
output reg DQML = 1;
output reg DQMH = 1;
output reg [1:0] SBA;
output reg [12:0] SA;
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 1: begin // ACT
DQML <= 1'b1;
DQMH <= 1'b1;
if (IS==6) begin
SBA[1:0] <= { 2'b10 };
SA[12:0] <= { 10'b0011000100, LS[12:10] };
end else if (RAMSpecSEL) begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
SA[9:0] <= Addr[19:10];
end else begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] };
end
end 2: begin // RD
if (RAMSpecSEL) begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0];
DQMH <= !Addr[0];
end else begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, RAr[9:1]};
DQML <= RAr[0];
DQMH <= !RAr[0];
end
end 3: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 4: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 5: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 6: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 7: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 8: begin // WR AP
if (IS==6) begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, LS[9:1] };
DQML <= LS[0];
DQMH <= !LS[0];
end else begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0];
DQMH <= !Addr[0];
end
end 9: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 10: begin // PC all
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 11: begin // AREF / load mode
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0001000100000;
end 12: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 13: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 14: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end 15: begin // NOP CKE
DQML <= 1'b1;
DQMH <= 1'b1;
SBA[1:0] <= 2'b00;
SA[12:0] <= 13'b0011000100000;
end
endcase
end
/* DMA/INT in/out */
input INTin, DMAin;
output INTout = INTin;
output DMAout = DMAin;
/* Unused Pins */
output RAdir = 1;
output nDMAout = 1;
output nNMIout = 1;
output nINHout = 1;
output nRDYout = 1;
output nIRQout = 1;
output RWout = 1;
endmodule

92
cpld/output_files/GR8RAM.asm.rpt Normal file
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Assembler report for GR8RAM
Fri Feb 16 20:54:00 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: /Repos/GR8RAM/cpld/output_files/GR8RAM.pof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Fri Feb 16 20:54:00 2024 ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+--------------------------------------------+
; Assembler Generated Files ;
+--------------------------------------------+
; File Name ;
+--------------------------------------------+
; /Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
+--------------------------------------------+
+----------------------------------------------------------------------+
; Assembler Device Options: /Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
+----------------+-----------------------------------------------------+
; Option ; Setting ;
+----------------+-----------------------------------------------------+
; JTAG usercode ; 0x00163AA4 ;
; Checksum ; 0x00163E9C ;
+----------------+-----------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Fri Feb 16 20:53:59 2024
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 13097 megabytes
Info: Processing ended: Fri Feb 16 20:54:00 2024
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

13
cpld/output_files/GR8RAM.cdf Normal file
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@ -0,0 +1,13 @@
/* Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EPM240T100) Path("//mac/iCloud/Repos2/GR8RAM/cpld2/output_files/") File("GR8RAM.pof") MfrSpec(OpMask(1) SEC_Device(EPM240T100) Child_OpMask(2 3 3));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

1
cpld/output_files/GR8RAM.done Normal file
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@ -0,0 +1 @@
Fri Feb 16 20:54:03 2024

94
cpld/output_files/GR8RAM.eda.rpt Normal file
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@ -0,0 +1,94 @@
EDA Netlist Writer report for GR8RAM
Tue Feb 28 11:21:31 2023
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2022 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Tue Feb 28 11:21:31 2023 ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+-----------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+-----------------------------+
; Tool Name ; Questa Intel FPGA (Verilog) ;
; Generate functional simulation netlist ; On ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+-----------------------------+
+--------------------------------------------------+
; Simulation Generated Files ;
+--------------------------------------------------+
; Generated Files ;
+--------------------------------------------------+
; /Repos2/GR8RAM/cpld2/simulation/questa/GR8RAM.vo ;
+--------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Info: Processing started: Tue Feb 28 11:21:30 2023
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file GR8RAM.vo in folder "/Repos2/GR8RAM/cpld2/simulation/questa/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 13024 megabytes
Info: Processing ended: Tue Feb 28 11:21:31 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

793
cpld/output_files/GR8RAM.fit.rpt Normal file
View File

@ -0,0 +1,793 @@
Fitter report for GR8RAM
Fri Feb 16 20:53:58 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Parallel Compilation
5. Pin-Out File
6. Fitter Resource Usage Summary
7. Input Pins
8. Output Pins
9. Bidir Pins
10. I/O Bank Usage
11. All Package Pins
12. Output Pin Default Load For Reported TCO
13. I/O Assignment Warnings
14. Fitter Resource Utilization by Entity
15. Delay Chain Summary
16. Control Signals
17. Global & Other Fast Signals
18. Routing Usage Summary
19. LAB Logic Elements
20. LAB-wide Signals
21. LAB Signals Sourced
22. LAB Signals Sourced Out
23. LAB Distinct Inputs
24. Fitter Device Options
25. Fitter Messages
26. Fitter Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------------+
; Fitter Status ; Successful - Fri Feb 16 20:53:58 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 233 / 240 ( 97 % ) ;
; Total pins ; 80 / 80 ( 100 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+---------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EPM240T100C5 ; ;
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Always Enable Input Buffers ; Off ; Off ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing ; Off ; Off ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ;
; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize Timing for ECOs ; Off ; Off ;
; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Delay Chains ; On ; On ;
; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
; Perform Register Duplication for Performance ; Off ; Off ;
; Perform Register Retiming for Performance ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Auto ; Auto ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.02 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 0.8% ;
; Processors 3-4 ; 0.7% ;
+----------------------------+-------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in /Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+---------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+-----------------------+
; Resource ; Usage ;
+---------------------------------------------+-----------------------+
; Total logic elements ; 233 / 240 ( 97 % ) ;
; -- Combinational with no register ; 109 ;
; -- Register only ; 6 ;
; -- Combinational with a register ; 118 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 124 ;
; -- 3 input functions ; 30 ;
; -- 2 input functions ; 71 ;
; -- 1 input functions ; 0 ;
; -- 0 input functions ; 2 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 200 ;
; -- arithmetic mode ; 33 ;
; -- qfbk mode ; 18 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 68 ;
; -- asynchronous clear/load mode ; 29 ;
; ; ;
; Total registers ; 124 / 240 ( 52 % ) ;
; Total LABs ; 24 / 24 ( 100 % ) ;
; Logic elements in carry chains ; 37 ;
; Virtual pins ; 0 ;
; I/O pins ; 80 / 80 ( 100 % ) ;
; -- Clock pins ; 4 / 4 ( 100 % ) ;
; ; ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; ; ;
; -- Total Fixed Point DSP Blocks ; 0 ;
; -- Total Floating Point DSP Blocks ; 0 ;
; ; ;
; Global signals ; 3 ;
; -- Global clocks ; 3 / 4 ( 75 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 34.1% / 35.6% / 32.6% ;
; Peak interconnect usage (total/H/V) ; 34.1% / 35.6% / 32.6% ;
; Maximum fan-out ; 110 ;
; Highest non-global fan-out ; 53 ;
; Total fan-out ; 1071 ;
; Average fan-out ; 3.42 ;
+---------------------------------------------+-----------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 110 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVTTL ; User ; no ;
; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 16 ; 0 ; yes ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; no ;
; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ;
; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ;
; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; DMAout ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; yes ; no ; no ; yes ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; INTout ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RDdir ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RWout ; 33 ; 1 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[0] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[10] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[11] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; SA[12] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; SA[1] ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[2] ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[3] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[4] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; SA[6] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[7] ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[9] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SBA[0] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nRDYout ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Bidir Pins ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; MOSIOE ; - ;
; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ;
; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+-------------------------------------------------------------+
; I/O Bank Usage ;
+----------+-------------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+-------------------+---------------+--------------+
; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ;
; 2 ; 42 / 42 ( 100 % ) ; 3.3V ; -- ;
+----------+-------------------+---------------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins ;
+----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+
; 1 ; 83 ; 2 ; RA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
; 2 ; 0 ; 1 ; RA[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 3 ; 1 ; 1 ; RA[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 4 ; 2 ; 1 ; RA[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 5 ; 3 ; 1 ; nFCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 6 ; 4 ; 1 ; RA[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 7 ; 5 ; 1 ; RA[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 8 ; 6 ; 1 ; RA[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 12 ; 7 ; 1 ; FCK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 14 ; 8 ; 1 ; RA[10] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 15 ; 9 ; 1 ; MOSI ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 16 ; 10 ; 1 ; MISO ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 17 ; 11 ; 1 ; RDdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 18 ; 12 ; 1 ; DMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 19 ; 13 ; 1 ; RAdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 20 ; 14 ; 1 ; INTout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 21 ; 15 ; 1 ; nDMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 26 ; 20 ; 1 ; nNMIout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 27 ; 21 ; 1 ; nINHout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 28 ; 22 ; 1 ; nRDYout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 29 ; 23 ; 1 ; nIRQout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 30 ; 24 ; 1 ; nRESout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 33 ; 25 ; 1 ; RWout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 34 ; 26 ; 1 ; RA[11] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 35 ; 27 ; 1 ; RA[12] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 36 ; 28 ; 1 ; RA[13] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 37 ; 29 ; 1 ; RA[14] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 38 ; 30 ; 1 ; RA[15] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 39 ; 31 ; 1 ; nIOSEL ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ;
; 40 ; 32 ; 1 ; nDEVSEL ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ;
; 41 ; 33 ; 1 ; PHI0 ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ;
; 42 ; 34 ; 1 ; nIOSTRB ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ;
; 43 ; 35 ; 1 ; nWE ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ;
; 44 ; 36 ; 1 ; nRES ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ;
; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 47 ; 37 ; 1 ; SD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 48 ; 38 ; 1 ; DMAin ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 49 ; 39 ; 1 ; INTin ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 50 ; 40 ; 1 ; SD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 51 ; 41 ; 1 ; SD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 52 ; 42 ; 2 ; SD[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 53 ; 43 ; 2 ; SD[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 54 ; 44 ; 2 ; SD[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 55 ; 45 ; 2 ; SD[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 56 ; 46 ; 2 ; SD[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 57 ; 47 ; 2 ; DQMH ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 58 ; 48 ; 2 ; nSWE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 61 ; 49 ; 2 ; nCAS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 62 ; 50 ; 2 ; nRAS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 64 ; 51 ; 2 ; C25M ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; 52 ; 2 ; RCKE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 67 ; 53 ; 2 ; nRCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 68 ; 54 ; 2 ; SA[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 69 ; 55 ; 2 ; SBA[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 70 ; 56 ; 2 ; SA[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 71 ; 57 ; 2 ; SBA[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 72 ; 58 ; 2 ; SA[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 73 ; 59 ; 2 ; SA[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 74 ; 60 ; 2 ; SA[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 75 ; 61 ; 2 ; SA[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 76 ; 62 ; 2 ; SA[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 77 ; 63 ; 2 ; SA[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 78 ; 64 ; 2 ; SA[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 81 ; 65 ; 2 ; SA[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 82 ; 66 ; 2 ; SA[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 83 ; 67 ; 2 ; SA[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 84 ; 68 ; 2 ; SA[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 85 ; 69 ; 2 ; DQML ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 86 ; 70 ; 2 ; RD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 87 ; 71 ; 2 ; RD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 88 ; 72 ; 2 ; RD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 90 ; 74 ; 2 ; RD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 91 ; 75 ; 2 ; RD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 92 ; 76 ; 2 ; RD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 95 ; 77 ; 2 ; SetFW[1] ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; On ;
; 96 ; 78 ; 2 ; SetFW[0] ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; On ;
; 97 ; 79 ; 2 ; RA[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 98 ; 80 ; 2 ; RA[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 99 ; 81 ; 2 ; RD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 100 ; 82 ; 2 ; RA[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+-------------------------------------------------------------+
; Output Pin Default Load For Reported TCO ;
+----------------------------+-------+------------------------+
; I/O Standard ; Load ; Termination Resistance ;
+----------------------------+-------+------------------------+
; 3.3-V LVTTL ; 10 pF ; Not Available ;
; 3.3-V LVCMOS ; 10 pF ; Not Available ;
; 2.5 V ; 10 pF ; Not Available ;
; 1.8 V ; 10 pF ; Not Available ;
; 1.5 V ; 10 pF ; Not Available ;
; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available ;
; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available ;
+----------------------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+----------------------------------------+
; I/O Assignment Warnings ;
+----------+-----------------------------+
; Pin Name ; Reason ;
+----------+-----------------------------+
; RA[4] ; Missing location assignment ;
+----------+-----------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
; |GR8RAM ; 233 (233) ; 124 ; 0 ; 80 ; 0 ; 109 (109) ; 6 (6) ; 118 (118) ; 37 (37) ; 18 (18) ; |GR8RAM ; GR8RAM ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------+
; Delay Chain Summary ;
+----------+----------+---------------+
; Name ; Pin Type ; Pad to Core 0 ;
+----------+----------+---------------+
; nRESout ; Output ; -- ;
; INTout ; Output ; -- ;
; DMAout ; Output ; -- ;
; nNMIout ; Output ; -- ;
; nIRQout ; Output ; -- ;
; nRDYout ; Output ; -- ;
; nINHout ; Output ; -- ;
; RWout ; Output ; -- ;
; nDMAout ; Output ; -- ;
; RAdir ; Output ; -- ;
; RDdir ; Output ; -- ;
; SBA[0] ; Output ; -- ;
; SBA[1] ; Output ; -- ;
; SA[0] ; Output ; -- ;
; SA[1] ; Output ; -- ;
; SA[2] ; Output ; -- ;
; SA[3] ; Output ; -- ;
; SA[4] ; Output ; -- ;
; SA[5] ; Output ; -- ;
; SA[6] ; Output ; -- ;
; SA[7] ; Output ; -- ;
; SA[8] ; Output ; -- ;
; SA[9] ; Output ; -- ;
; SA[10] ; Output ; -- ;
; SA[11] ; Output ; -- ;
; SA[12] ; Output ; -- ;
; nRCS ; Output ; -- ;
; nRAS ; Output ; -- ;
; nCAS ; Output ; -- ;
; nSWE ; Output ; -- ;
; DQML ; Output ; -- ;
; DQMH ; Output ; -- ;
; RCKE ; Output ; -- ;
; nFCS ; Output ; -- ;
; FCK ; Output ; -- ;
; RD[0] ; Bidir ; (1) ;
; RD[1] ; Bidir ; (1) ;
; RD[2] ; Bidir ; (1) ;
; RD[3] ; Bidir ; (1) ;
; RD[4] ; Bidir ; (1) ;
; RD[5] ; Bidir ; (1) ;
; RD[6] ; Bidir ; (1) ;
; RD[7] ; Bidir ; (1) ;
; SD[0] ; Bidir ; (1) ;
; SD[1] ; Bidir ; (1) ;
; SD[2] ; Bidir ; (1) ;
; SD[3] ; Bidir ; (1) ;
; SD[4] ; Bidir ; (1) ;
; SD[5] ; Bidir ; (1) ;
; SD[6] ; Bidir ; (1) ;
; SD[7] ; Bidir ; (1) ;
; MOSI ; Bidir ; (1) ;
; INTin ; Input ; (1) ;
; DMAin ; Input ; (1) ;
; PHI0 ; Input ; (0) ;
; nWE ; Input ; (1) ;
; RA[0] ; Input ; (1) ;
; RA[1] ; Input ; (1) ;
; RA[2] ; Input ; (1) ;
; RA[3] ; Input ; (1) ;
; RA[4] ; Input ; (1) ;
; RA[5] ; Input ; (1) ;
; RA[6] ; Input ; (1) ;
; RA[7] ; Input ; (1) ;
; RA[8] ; Input ; (1) ;
; RA[9] ; Input ; (1) ;
; RA[10] ; Input ; (1) ;
; nIOSTRB ; Input ; (1) ;
; nIOSEL ; Input ; (1) ;
; nDEVSEL ; Input ; (1) ;
; C25M ; Input ; (0) ;
; RA[11] ; Input ; (1) ;
; RA[14] ; Input ; (1) ;
; RA[15] ; Input ; (1) ;
; RA[12] ; Input ; (1) ;
; RA[13] ; Input ; (1) ;
; SetFW[1] ; Input ; (1) ;
; SetFW[0] ; Input ; (1) ;
; nRES ; Input ; (1) ;
; MISO ; Input ; (1) ;
+----------+----------+---------------+
+--------------------------------------------------------------------------------------------------------------------------------+
; Control Signals ;
+-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
; C25M ; PIN_64 ; 110 ; Clock ; yes ; Global Clock ; GCLK3 ;
; Equal20~0 ; LC_X2_Y4_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
; Equal2~1 ; LC_X2_Y1_N5 ; 16 ; Clock enable ; no ; -- ; -- ;
; FCKOE ; LC_X3_Y1_N1 ; 2 ; Output enable ; no ; -- ; -- ;
; IS~19 ; LC_X2_Y2_N7 ; 5 ; Clock enable ; no ; -- ; -- ;
; MOSIOE ; LC_X2_Y2_N8 ; 1 ; Output enable ; no ; -- ; -- ;
; PHI0 ; PIN_41 ; 16 ; Clock ; yes ; Global Clock ; GCLK2 ;
; PS[0] ; LC_X6_Y1_N1 ; 52 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ;
; PS[2] ; LC_X2_Y1_N2 ; 27 ; Sync. clear, Sync. load ; no ; -- ; -- ;
; SDOE ; LC_X5_Y1_N4 ; 8 ; Output enable ; no ; -- ; -- ;
; SetFWLoaded ; LC_X4_Y2_N8 ; 2 ; Clock enable ; no ; -- ; -- ;
; always9~2 ; LC_X7_Y3_N6 ; 8 ; Sync. load ; no ; -- ; -- ;
; always9~3 ; LC_X7_Y3_N7 ; 9 ; Sync. load ; no ; -- ; -- ;
; always9~4 ; LC_X6_Y3_N9 ; 9 ; Sync. load ; no ; -- ; -- ;
; comb~2 ; LC_X4_Y1_N8 ; 9 ; Output enable ; no ; -- ; -- ;
; nRESr ; LC_X3_Y1_N7 ; 30 ; Async. clear, Sync. clear ; yes ; Global Clock ; GCLK1 ;
+-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
+-------------------------------------------------------------------------+
; Global & Other Fast Signals ;
+-------+-------------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+-------+-------------+---------+----------------------+------------------+
; C25M ; PIN_64 ; 110 ; Global Clock ; GCLK3 ;
; PHI0 ; PIN_41 ; 16 ; Global Clock ; GCLK2 ;
; nRESr ; LC_X3_Y1_N7 ; 30 ; Global Clock ; GCLK1 ;
+-------+-------------+---------+----------------------+------------------+
+--------------------------------------------+
; Routing Usage Summary ;
+-----------------------+--------------------+
; Routing Resource Type ; Usage ;
+-----------------------+--------------------+
; C4s ; 211 / 784 ( 27 % ) ;
; Direct links ; 50 / 888 ( 6 % ) ;
; Global clocks ; 3 / 4 ( 75 % ) ;
; LAB clocks ; 13 / 32 ( 41 % ) ;
; LUT chains ; 8 / 216 ( 4 % ) ;
; Local interconnects ; 379 / 888 ( 43 % ) ;
; R4s ; 199 / 704 ( 28 % ) ;
+-----------------------+--------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 9.71) ; Number of LABs (Total = 24) ;
+--------------------------------------------+------------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 2 ;
; 10 ; 20 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.71) ; Number of LABs (Total = 24) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 5 ;
; 1 Clock ; 21 ;
; 1 Clock enable ; 5 ;
; 1 Sync. clear ; 4 ;
; 1 Sync. load ; 3 ;
; 2 Clocks ; 3 ;
+------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 10.50) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 15 ;
; 11 ; 0 ;
; 12 ; 3 ;
; 13 ; 1 ;
; 14 ; 1 ;
; 15 ; 1 ;
+----------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 7.42) ; Number of LABs (Total = 24) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 2 ;
; 5 ; 4 ;
; 6 ; 4 ;
; 7 ; 2 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 10 ; 6 ;
; 11 ; 0 ;
; 12 ; 2 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 14.13) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 2 ;
; 6 ; 2 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 2 ;
; 11 ; 1 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 4 ;
; 15 ; 3 ;
; 16 ; 1 ;
; 17 ; 1 ;
; 18 ; 1 ;
; 19 ; 0 ;
; 20 ; 1 ;
; 21 ; 0 ;
; 22 ; 1 ;
; 23 ; 0 ;
; 24 ; 1 ;
; 25 ; 1 ;
; 26 ; 1 ;
+----------------------------------------------+------------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving ground ;
+----------------------------------------------+--------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (119006): Selected device EPM240T100C5 for design "GR8RAM"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info (176445): Device EPM240T100I5 is compatible
Info (176445): Device EPM240T100A5 is compatible
Info (176445): Device EPM570T100C5 is compatible
Info (176445): Device EPM570T100I5 is compatible
Info (176445): Device EPM570T100A5 is compatible
Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 80 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Info (332104): Reading SDC File: 'GR8RAM.sdc'
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 2 clocks
Info (332111): Period Clock Name
Info (332111): ======== ============
Info (332111): 40.000 C25M
Info (332111): 978.000 PHI0
Info (186079): Completed User Assigned Global Signals Promotion Operation
Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
Info (186216): Automatically promoted some destinations of signal "PHI0" to use Global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
Info (186217): Destination "comb~0" may be non-global or may not use global clock
Info (186217): Destination "PHI0r1" may be non-global or may not use global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 10
Info (186228): Pin "PHI0" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 16
Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 94
Info (186079): Completed Auto Global Promotion Operation
Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 1 input, 0 output, 0 bidirectional)
Info (176212): I/O standards used: 3.3-V LVTTL.
Info (176215): I/O bank details before I/O pin placement
Info (176214): Statistics of I/O banks
Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available
Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 1 pins available
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 30% of the available device resources
Info (170196): Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170200): Optimizations that may affect the design's timing were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.16 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info (144001): Generated suppressed messages file /Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 13772 megabytes
Info: Processing ended: Fri Feb 16 20:53:58 2024
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:03
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in /Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg.

4
cpld/output_files/GR8RAM.fit.smsg Normal file
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@ -0,0 +1,4 @@
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
Extra Info (176244): Moving registers into LUTs to improve timing and density
Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00

11
cpld/output_files/GR8RAM.fit.summary Normal file
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Fitter Status : Successful - Fri Feb 16 20:53:58 2024
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
Total logic elements : 233 / 240 ( 97 % )
Total pins : 80 / 80 ( 100 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )

118
cpld/output_files/GR8RAM.flow.rpt Normal file
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Flow report for GR8RAM
Fri Feb 16 20:54:03 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+---------------------------------------------+
; Flow Status ; Successful - Fri Feb 16 20:54:00 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 233 / 240 ( 97 % ) ;
; Total pins ; 80 / 80 ( 100 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 02/16/2024 20:53:35 ;
; Main task ; Compilation ;
; Revision Name ; GR8RAM ;
+-------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+---------------------------------------+----------------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+----------------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 121380219419.170813481504184 ; -- ; -- ; -- ;
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ;
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 2 ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+---------------------------------------+----------------------------------------+---------------+-------------+------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:20 ; 1.0 ; 13135 MB ; 00:00:43 ;
; Fitter ; 00:00:02 ; 1.0 ; 13772 MB ; 00:00:03 ;
; Assembler ; 00:00:01 ; 1.0 ; 13093 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13090 MB ; 00:00:01 ;
; Total ; 00:00:25 ; -- ; -- ; 00:00:48 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; Fitter ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; Timing Analyzer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
+----------------------+------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
quartus_sta GR8RAM -c GR8RAM

8
cpld/output_files/GR8RAM.jdi Normal file
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@ -0,0 +1,8 @@
<sld_project_info>
<project>
<hash md5_digest_80b="1794c049bdbd51a27b8f"/>
</project>
<file_info>
<file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

322
cpld/output_files/GR8RAM.map.rpt Normal file
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Analysis & Synthesis report for GR8RAM
Fri Feb 16 20:53:55 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. State Machine - |GR8RAM|IS
9. Registers Removed During Synthesis
10. General Register Statistics
11. Inverted Register Statistics
12. Multiplexer Restructuring Statistics (Restructuring Performed)
13. Analysis & Synthesis Messages
14. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Feb 16 20:53:55 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
; Total logic elements ; 253 ;
; Total pins ; 80 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------------+--------------------+--------------------+
; Device ; EPM240T100C5 ; ;
; Top-level entity name ; GR8RAM ; GR8RAM ;
; Family name ; MAX II ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
+----------------------------+-------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+---------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------+---------------------------------------+---------+
; GR8RAM.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v ; ;
+----------------------------------+-----------------+------------------------+---------------------------------------+---------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 253 ;
; -- Combinational with no register ; 129 ;
; -- Register only ; 26 ;
; -- Combinational with a register ; 98 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 124 ;
; -- 3 input functions ; 30 ;
; -- 2 input functions ; 71 ;
; -- 1 input functions ; 0 ;
; -- 0 input functions ; 2 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 220 ;
; -- arithmetic mode ; 33 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 45 ;
; -- asynchronous clear/load mode ; 29 ;
; ; ;
; Total registers ; 124 ;
; Total logic cells in carry chains ; 37 ;
; I/O pins ; 80 ;
; Maximum fan-out node ; C25M ;
; Maximum fan-out ; 110 ;
; Total fan-out ; 1076 ;
; Average fan-out ; 3.23 ;
+---------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
; |GR8RAM ; 253 (253) ; 124 ; 0 ; 80 ; 0 ; 129 (129) ; 26 (26) ; 98 (98) ; 37 (37) ; 0 (0) ; |GR8RAM ; GR8RAM ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
Encoding Type: One-Hot
+--------------------------------------------------------------+
; State Machine - |GR8RAM|IS ;
+--------+--------+--------+--------+--------+--------+--------+
; Name ; IS.111 ; IS.110 ; IS.101 ; IS.100 ; IS.001 ; IS.000 ;
+--------+--------+--------+--------+--------+--------+--------+
; IS.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; IS.001 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; IS.100 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; IS.101 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; IS.110 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; IS.111 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+--------+--------+--------+--------+--------+--------+--------+
+------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+--------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+--------------------+
; IS~8 ; Lost fanout ;
; IS~9 ; Lost fanout ;
; IS~10 ; Lost fanout ;
; Total Number of Removed Registers = 3 ; ;
+---------------------------------------+--------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 124 ;
; Number of registers using Synchronous Clear ; 12 ;
; Number of registers using Synchronous Load ; 33 ;
; Number of registers using Asynchronous Clear ; 29 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 29 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; nRCS~reg0 ; 1 ;
; nRAS~reg0 ; 1 ;
; nCAS~reg0 ; 1 ;
; nSWE~reg0 ; 1 ;
; DQML~reg0 ; 1 ;
; DQMH~reg0 ; 1 ;
; RCKE~reg0 ; 1 ;
; Total number of inverted registers = 7 ; ;
+----------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[2] ;
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[11]~reg0 ;
; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[3]~reg0 ;
; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[1]~reg0 ;
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[7] ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|RDD[1] ;
; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |GR8RAM|RDD[4] ;
; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ;
; 7:1 ; 5 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |GR8RAM|IS ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Fri Feb 16 20:53:35 2024
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
Info (12023): Found entity 1: GR8RAM File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 1
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 42
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 47
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(134): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 134
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(142): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 142
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(149): truncated value with size 32 to match size of target (8) File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 149
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "nNMIout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 563
Warning (13410): Pin "nIRQout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 566
Warning (13410): Pin "nRDYout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 565
Warning (13410): Pin "nINHout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 564
Warning (13410): Pin "RWout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 567
Warning (13410): Pin "nDMAout" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 562
Warning (13410): Pin "RAdir" is stuck at VCC File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 561
Info (17049): 3 registers lost all their fanouts during netlist optimizations.
Info (21057): Implemented 333 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 28 input pins
Info (21059): Implemented 35 output pins
Info (21060): Implemented 17 bidirectional pins
Info (21061): Implemented 253 logic cells
Info (144001): Generated suppressed messages file /Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings
Info: Peak virtual memory: 13135 megabytes
Info: Processing ended: Fri Feb 16 20:53:55 2024
Info: Elapsed time: 00:00:20
Info: Total CPU time (on all processors): 00:00:43
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.

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Warning (10273): Verilog HDL warning at GR8RAM.v(110): extended using "x" or "z" File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 110
Warning (10273): Verilog HDL warning at GR8RAM.v(286): extended using "x" or "z" File: //Mac/Home/Repos/GR8RAM/cpld/GR8RAM.v Line: 286

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Analysis & Synthesis Status : Successful - Fri Feb 16 20:53:55 2024
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM
Family : MAX II
Total logic elements : 253
Total pins : 80
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )

165
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-- Copyright (C) 2019 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus Prime input file. This file cannot be used
-- to make Quartus Prime pin assignments - for instructions on how to make pin
-- assignments, please see Quartus Prime help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (2.5V/3.3V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
RA[4] : 1 : input : 3.3-V LVTTL : : 2 : N
RA[5] : 2 : input : 3.3-V LVTTL : : 1 : Y
RA[6] : 3 : input : 3.3-V LVTTL : : 1 : Y
RA[3] : 4 : input : 3.3-V LVTTL : : 1 : Y
nFCS : 5 : output : 3.3-V LVTTL : : 1 : Y
RA[7] : 6 : input : 3.3-V LVTTL : : 1 : Y
RA[8] : 7 : input : 3.3-V LVTTL : : 1 : Y
RA[9] : 8 : input : 3.3-V LVTTL : : 1 : Y
VCCIO1 : 9 : power : : 3.3V : 1 :
GNDIO : 10 : gnd : : : :
GNDINT : 11 : gnd : : : :
FCK : 12 : output : 3.3-V LVTTL : : 1 : Y
VCCINT : 13 : power : : 2.5V/3.3V : :
RA[10] : 14 : input : 3.3-V LVTTL : : 1 : Y
MOSI : 15 : bidir : 3.3-V LVTTL : : 1 : Y
MISO : 16 : input : 3.3-V LVTTL : : 1 : Y
RDdir : 17 : output : 3.3-V LVTTL : : 1 : Y
DMAout : 18 : output : 3.3-V LVTTL : : 1 : Y
RAdir : 19 : output : 3.3-V LVTTL : : 1 : Y
INTout : 20 : output : 3.3-V LVTTL : : 1 : Y
nDMAout : 21 : output : 3.3-V LVTTL : : 1 : Y
TMS : 22 : input : : : 1 :
TDI : 23 : input : : : 1 :
TCK : 24 : input : : : 1 :
TDO : 25 : output : : : 1 :
nNMIout : 26 : output : 3.3-V LVTTL : : 1 : Y
nINHout : 27 : output : 3.3-V LVTTL : : 1 : Y
nRDYout : 28 : output : 3.3-V LVTTL : : 1 : Y
nIRQout : 29 : output : 3.3-V LVTTL : : 1 : Y
nRESout : 30 : output : 3.3-V LVTTL : : 1 : Y
VCCIO1 : 31 : power : : 3.3V : 1 :
GNDIO : 32 : gnd : : : :
RWout : 33 : output : 3.3-V LVTTL : : 1 : Y
RA[11] : 34 : input : 3.3-V LVTTL : : 1 : Y
RA[12] : 35 : input : 3.3-V LVTTL : : 1 : Y
RA[13] : 36 : input : 3.3-V LVTTL : : 1 : Y
RA[14] : 37 : input : 3.3-V LVTTL : : 1 : Y
RA[15] : 38 : input : 3.3-V LVTTL : : 1 : Y
nIOSEL : 39 : input : 3.3V Schmitt Trigger Input : : 1 : Y
nDEVSEL : 40 : input : 3.3V Schmitt Trigger Input : : 1 : Y
PHI0 : 41 : input : 3.3V Schmitt Trigger Input : : 1 : Y
nIOSTRB : 42 : input : 3.3V Schmitt Trigger Input : : 1 : Y
nWE : 43 : input : 3.3V Schmitt Trigger Input : : 1 : Y
nRES : 44 : input : 3.3V Schmitt Trigger Input : : 1 : Y
VCCIO1 : 45 : power : : 3.3V : 1 :
GNDIO : 46 : gnd : : : :
SD[1] : 47 : bidir : 3.3-V LVTTL : : 1 : Y
DMAin : 48 : input : 3.3-V LVTTL : : 1 : Y
INTin : 49 : input : 3.3-V LVTTL : : 1 : Y
SD[0] : 50 : bidir : 3.3-V LVTTL : : 1 : Y
SD[4] : 51 : bidir : 3.3-V LVTTL : : 1 : Y
SD[5] : 52 : bidir : 3.3-V LVTTL : : 2 : Y
SD[6] : 53 : bidir : 3.3-V LVTTL : : 2 : Y
SD[7] : 54 : bidir : 3.3-V LVTTL : : 2 : Y
SD[3] : 55 : bidir : 3.3-V LVTTL : : 2 : Y
SD[2] : 56 : bidir : 3.3-V LVTTL : : 2 : Y
DQMH : 57 : output : 3.3-V LVTTL : : 2 : Y
nSWE : 58 : output : 3.3-V LVTTL : : 2 : Y
VCCIO2 : 59 : power : : 3.3V : 2 :
GNDIO : 60 : gnd : : : :
nCAS : 61 : output : 3.3-V LVTTL : : 2 : Y
nRAS : 62 : output : 3.3-V LVTTL : : 2 : Y
VCCINT : 63 : power : : 2.5V/3.3V : :
C25M : 64 : input : 3.3-V LVTTL : : 2 : Y
GNDINT : 65 : gnd : : : :
RCKE : 66 : output : 3.3-V LVTTL : : 2 : Y
nRCS : 67 : output : 3.3-V LVTTL : : 2 : Y
SA[12] : 68 : output : 3.3-V LVTTL : : 2 : Y
SBA[0] : 69 : output : 3.3-V LVTTL : : 2 : Y
SA[11] : 70 : output : 3.3-V LVTTL : : 2 : Y
SBA[1] : 71 : output : 3.3-V LVTTL : : 2 : Y
SA[9] : 72 : output : 3.3-V LVTTL : : 2 : Y
SA[10] : 73 : output : 3.3-V LVTTL : : 2 : Y
SA[8] : 74 : output : 3.3-V LVTTL : : 2 : Y
SA[0] : 75 : output : 3.3-V LVTTL : : 2 : Y
SA[4] : 76 : output : 3.3-V LVTTL : : 2 : Y
SA[6] : 77 : output : 3.3-V LVTTL : : 2 : Y
SA[7] : 78 : output : 3.3-V LVTTL : : 2 : Y
GNDIO : 79 : gnd : : : :
VCCIO2 : 80 : power : : 3.3V : 2 :
SA[1] : 81 : output : 3.3-V LVTTL : : 2 : Y
SA[2] : 82 : output : 3.3-V LVTTL : : 2 : Y
SA[5] : 83 : output : 3.3-V LVTTL : : 2 : Y
SA[3] : 84 : output : 3.3-V LVTTL : : 2 : Y
DQML : 85 : output : 3.3-V LVTTL : : 2 : Y
RD[0] : 86 : bidir : 3.3-V LVTTL : : 2 : Y
RD[1] : 87 : bidir : 3.3-V LVTTL : : 2 : Y
RD[2] : 88 : bidir : 3.3-V LVTTL : : 2 : Y
RD[3] : 89 : bidir : 3.3-V LVTTL : : 2 : Y
RD[4] : 90 : bidir : 3.3-V LVTTL : : 2 : Y
RD[5] : 91 : bidir : 3.3-V LVTTL : : 2 : Y
RD[6] : 92 : bidir : 3.3-V LVTTL : : 2 : Y
GNDIO : 93 : gnd : : : :
VCCIO2 : 94 : power : : 3.3V : 2 :
SetFW[1] : 95 : input : 3.3V Schmitt Trigger Input : : 2 : Y
SetFW[0] : 96 : input : 3.3V Schmitt Trigger Input : : 2 : Y
RA[2] : 97 : input : 3.3-V LVTTL : : 2 : Y
RA[1] : 98 : input : 3.3-V LVTTL : : 2 : Y
RD[7] : 99 : bidir : 3.3-V LVTTL : : 2 : Y
RA[0] : 100 : input : 3.3-V LVTTL : : 2 : Y

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<sld_project_info/>

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Timing Analyzer report for GR8RAM
Fri Feb 16 20:54:03 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Parallel Compilation
4. SDC File List
5. Clocks
6. Fmax Summary
7. Setup Summary
8. Hold Summary
9. Recovery Summary
10. Removal Summary
11. Minimum Pulse Width Summary
12. Setup: 'C25M'
13. Hold: 'C25M'
14. Recovery: 'C25M'
15. Removal: 'C25M'
16. Setup Transfers
17. Hold Transfers
18. Recovery Transfers
19. Removal Transfers
20. Report TCCS
21. Report RSKM
22. Unconstrained Paths Summary
23. Clock Status Summary
24. Unconstrained Input Ports
25. Unconstrained Output Ports
26. Unconstrained Input Ports
27. Unconstrained Output Ports
28. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+-----------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; GR8RAM ;
; Device Family ; MAX II ;
; Device Name ; EPM240T100C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+-----------------------+-----------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 0.0% ;
+----------------------------+-------------+
+---------------------------------------------------+
; SDC File List ;
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+---------------+--------+--------------------------+
; GR8RAM.sdc ; OK ; Fri Feb 16 20:54:03 2024 ;
+---------------+--------+--------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
; C25M ; Base ; 40.000 ; 25.0 MHz ; 0.000 ; 20.000 ; ; ; ; ; ; ; ; ; ; ; { C25M } ;
; PHI0 ; Base ; 978.000 ; 1.02 MHz ; 0.000 ; 489.000 ; ; ; ; ; ; ; ; ; ; ; { PHI0 } ;
+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
+-------------------------------------------------+
; Fmax Summary ;
+-----------+-----------------+------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------+------+
; 51.43 MHz ; 51.43 MHz ; C25M ; ;
+-----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+--------------------------------+
; Setup Summary ;
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
; C25M ; 10.278 ; 0.000 ;
+-------+--------+---------------+
+-------------------------------+
; Hold Summary ;
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; C25M ; 1.376 ; 0.000 ;
+-------+-------+---------------+
+--------------------------------+
; Recovery Summary ;
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
; C25M ; 33.311 ; 0.000 ;
+-------+--------+---------------+
+-------------------------------+
; Removal Summary ;
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; C25M ; 6.135 ; 0.000 ;
+-------+-------+---------------+
+---------------------------------+
; Minimum Pulse Width Summary ;
+-------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+---------+---------------+
; C25M ; 19.734 ; 0.000 ;
; PHI0 ; 488.734 ; 0.000 ;
+-------+---------+---------------+
+-------------------------------------------------------------------------------------------------------+
; Setup: 'C25M' ;
+--------+-----------+------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+------------+--------------+-------------+--------------+------------+------------+
; 10.278 ; REGEN ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.389 ;
; 10.285 ; REGEN ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.382 ;
; 10.289 ; REGEN ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.378 ;
; 10.642 ; REGEN ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.025 ;
; 11.085 ; REGEN ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.582 ;
; 11.357 ; REGEN ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.310 ;
; 11.401 ; REGEN ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.266 ;
; 11.402 ; REGEN ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.265 ;
; 12.395 ; PS[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ;
; 12.395 ; PS[0] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ;
; 12.395 ; PS[0] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ;
; 12.395 ; PS[0] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ;
; 12.440 ; PS[0] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ;
; 12.440 ; PS[0] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ;
; 12.440 ; PS[0] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ;
; 12.440 ; PS[0] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ;
; 12.450 ; PS[3] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ;
; 12.450 ; PS[3] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ;
; 12.450 ; PS[3] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ;
; 12.450 ; PS[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ;
; 12.495 ; PS[3] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ;
; 12.495 ; PS[3] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ;
; 12.495 ; PS[3] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ;
; 12.495 ; PS[3] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ;
; 12.804 ; PS[2] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ;
; 12.804 ; PS[2] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ;
; 12.804 ; PS[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ;
; 12.804 ; PS[2] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ;
; 12.849 ; PS[2] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ;
; 12.849 ; PS[2] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ;
; 12.849 ; PS[2] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ;
; 12.849 ; PS[2] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ;
; 13.331 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.336 ;
; 13.753 ; PS[1] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ;
; 13.753 ; PS[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ;
; 13.753 ; PS[1] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ;
; 13.753 ; PS[1] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ;
; 13.798 ; PS[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ;
; 13.798 ; PS[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ;
; 13.798 ; PS[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ;
; 13.798 ; PS[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ;
; 13.971 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.696 ;
; 14.103 ; Addr[7] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.564 ;
; 14.314 ; Addr[15] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.353 ;
; 14.675 ; Addr[14] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.992 ;
; 14.748 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.919 ;
; 14.753 ; Addr[9] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.914 ;
; 14.779 ; SetFWr[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.888 ;
; 14.780 ; SetFWr[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.887 ;
; 14.785 ; SetFWr[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.882 ;
; 14.975 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.692 ;
; 15.251 ; SetFWr[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.416 ;
; 15.322 ; Addr[10] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.345 ;
; 15.387 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.280 ;
; 15.489 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.178 ;
; 15.612 ; Addr[17] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.055 ;
; 15.651 ; Addr[13] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.016 ;
; 15.653 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.014 ;
; 15.700 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.967 ;
; 15.911 ; Addr[16] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.756 ;
; 16.065 ; Addr[22] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.602 ;
; 16.103 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.564 ;
; 16.349 ; Addr[23] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.318 ;
; 16.647 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.020 ;
; 16.656 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.011 ;
; 16.711 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.956 ;
; 16.777 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.890 ;
; 17.105 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.562 ;
; 22.720 ; Addr[23] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 16.947 ;
; 23.632 ; Addr[23] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 16.035 ;
; 23.717 ; REGEN ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 15.950 ;
; 23.986 ; SetFWr[0] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 15.681 ;
; 24.629 ; REGEN ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 15.038 ;
; 24.898 ; SetFWr[0] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.769 ;
; 25.067 ; SetFWr[1] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.600 ;
; 25.201 ; PS[1] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.466 ;
; 25.277 ; Addr[23] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.390 ;
; 25.323 ; PS[1] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.344 ;
; 25.783 ; Addr[23] ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.884 ;
; 25.876 ; Addr[23] ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.791 ;
; 25.979 ; SetFWr[1] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.688 ;
; 26.015 ; Addr[23] ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.652 ;
; 26.018 ; Addr[23] ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.649 ;
; 26.117 ; Addr[23] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.550 ;
; 26.222 ; PS[1] ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.274 ; REGEN ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.393 ;
; 26.312 ; Addr[23] ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.355 ;
; 26.361 ; LS[7] ; IS.000 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.306 ;
; 26.498 ; PS[0] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.169 ;
; 26.543 ; SetFWr[0] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.124 ;
; 26.596 ; Addr[23] ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.071 ;
; 26.722 ; PS[0] ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.945 ;
; 26.722 ; PS[0] ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.945 ;
+--------+-----------+------------+--------------+-------------+--------------+------------+------------+
+-----------------------------------------------------------------------------------------------------------+
; Hold: 'C25M' ;
+-------+--------------+--------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------+--------------+--------------+-------------+--------------+------------+------------+
; 1.376 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.597 ;
; 1.412 ; nRESf[1] ; nRESf[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ;
; 1.412 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ;
; 1.419 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.640 ;
; 1.420 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ;
; 1.426 ; nRESf[2] ; nRESf[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.647 ;
; 1.429 ; nRESf[0] ; nRESf[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.650 ;
; 1.646 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.867 ;
; 1.649 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.870 ;
; 1.652 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.873 ;
; 1.653 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.874 ;
; 1.661 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 1.882 ;
; 1.664 ; Addr[19] ; SA[9]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.885 ;
; 1.670 ; IS.000 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 1.891 ;
; 1.675 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.896 ;
; 1.719 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.940 ;
; 1.720 ; PS[2] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 1.941 ;
; 1.793 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.014 ;
; 1.794 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.015 ;
; 1.806 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.027 ;
; 1.809 ; IS.101 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.030 ;
; 1.846 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.067 ;
; 1.942 ; Addr[21] ; SA[11]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.163 ;
; 1.948 ; nRESf[2] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.169 ;
; 2.048 ; nRESf[1] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.269 ;
; 2.063 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.284 ;
; 2.082 ; Addr[15] ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 2.303 ;
; 2.107 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ;
; 2.115 ; Addr[0] ; DQML~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.336 ;
; 2.116 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.337 ;
; 2.116 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.337 ;
; 2.117 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.125 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ;
; 2.126 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
; 2.127 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ;
; 2.128 ; nRESf[3] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.349 ;
; 2.137 ; IS.111 ; IS.111 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ;
; 2.144 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ;
; 2.145 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ;
; 2.149 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.370 ;
; 2.150 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.371 ;
; 2.151 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ;
; 2.153 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.374 ;
; 2.185 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.406 ;
; 2.188 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.409 ;
; 2.232 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ;
; 2.232 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ;
; 2.232 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ;
; 2.239 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.460 ;
; 2.240 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ;
; 2.241 ; PS[0] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ;
; 2.242 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.463 ;
; 2.249 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
; 2.249 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
; 2.250 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ;
; 2.250 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ;
; 2.251 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ;
; 2.252 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ;
; 2.259 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.480 ;
; 2.261 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
; 2.261 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
; 2.263 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.484 ;
; 2.264 ; nRESf[0] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.485 ;
; 2.264 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.485 ;
; 2.267 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.488 ;
; 2.270 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.491 ;
; 2.271 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.492 ;
; 2.272 ; SetFWLoaded ; SetFWr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.493 ;
; 2.272 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.493 ;
; 2.272 ; SetFWLoaded ; SetFWr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.493 ;
; 2.274 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.495 ;
; 2.276 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.497 ;
; 2.287 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.508 ;
; 2.573 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.794 ;
; 2.686 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.907 ;
; 2.690 ; Addr[0] ; DQMH~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.911 ;
; 2.902 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.123 ;
; 2.906 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.127 ;
; 2.939 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ;
; 2.948 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.169 ;
; 2.948 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.169 ;
; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.949 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.949 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.957 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ;
; 2.958 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ;
; 2.959 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ;
; 2.976 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ;
; 2.983 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.204 ;
; 2.985 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.206 ;
; 3.001 ; PHI0r1 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.222 ;
; 3.050 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.271 ;
; 3.059 ; Addr[16] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.280 ;
+-------+--------------+--------------+--------------+-------------+--------------+------------+------------+
+-----------------------------------------------------------------------------------------------------+
; Recovery: 'C25M' ;
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
; 33.311 ; nRESr ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; REGEN ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Bank ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; AddrIncH ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; AddrIncM ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; AddrIncL ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------+
; Removal: 'C25M' ;
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
; 6.135 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
+-------------------------------------------------------------------------+
; Setup Transfers ;
+------------+----------+------------+------------+------------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+------------+------------+------------+----------+
; C25M ; C25M ; 1520 ; 0 ; 88 ; 0 ;
; PHI0 ; C25M ; false path ; false path ; false path ; 0 ;
+------------+----------+------------+------------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-------------------------------------------------------------------------+
; Hold Transfers ;
+------------+----------+------------+------------+------------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+------------+------------+------------+----------+
; C25M ; C25M ; 1520 ; 0 ; 88 ; 0 ;
; PHI0 ; C25M ; false path ; false path ; false path ; 0 ;
+------------+----------+------------+------------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-------------------------------------------------------------------+
; Recovery Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; C25M ; C25M ; 29 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-------------------------------------------------------------------+
; Removal Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; C25M ; C25M ; 29 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 44 ; 44 ;
; Unconstrained Input Port Paths ; 246 ; 246 ;
; Unconstrained Output Ports ; 45 ; 45 ;
; Unconstrained Output Port Paths ; 217 ; 217 ;
+---------------------------------+-------+------+
+-------------------------------------+
; Clock Status Summary ;
+--------+-------+------+-------------+
; Target ; Clock ; Type ; Status ;
+--------+-------+------+-------------+
; C25M ; C25M ; Base ; Constrained ;
; PHI0 ; PHI0 ; Base ; Constrained ;
+--------+-------+------+-------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; DMAin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; INTin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; MISO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; MOSI ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PHI0 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SetFW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SetFW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nDEVSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nIOSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nIOSTRB ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRES ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; DMAout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; FCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; INTout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; MOSI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RCKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RDdir ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nFCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRESout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nSWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; DMAin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; INTin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; MISO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; MOSI ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PHI0 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SetFW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SetFW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nDEVSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nIOSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nIOSTRB ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRES ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; DMAout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; FCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; INTout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; MOSI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RCKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RDdir ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nFCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRESout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nSWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Fri Feb 16 20:54:01 2024
Info: Command: quartus_sta GR8RAM -c GR8RAM
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332104): Reading SDC File: 'GR8RAM.sdc'
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Info (332146): Worst-case setup slack is 10.278
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 10.278 0.000 C25M
Info (332146): Worst-case hold slack is 1.376
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 1.376 0.000 C25M
Info (332146): Worst-case recovery slack is 33.311
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 33.311 0.000 C25M
Info (332146): Worst-case removal slack is 6.135
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 6.135 0.000 C25M
Info (332146): Worst-case minimum pulse width slack is 19.734
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 19.734 0.000 C25M
Info (332119): 488.734 0.000 PHI0
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 13090 megabytes
Info: Processing ended: Fri Feb 16 20:54:03 2024
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01

29
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------------------------------------------------------------
Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'C25M'
Slack : 10.278
TNS : 0.000
Type : Hold 'C25M'
Slack : 1.376
TNS : 0.000
Type : Recovery 'C25M'
Slack : 33.311
TNS : 0.000
Type : Removal 'C25M'
Slack : 6.135
TNS : 0.000
Type : Minimum Pulse Width 'C25M'
Slack : 19.734
TNS : 0.000
Type : Minimum Pulse Width 'PHI0'
Slack : 488.734
TNS : 0.000
------------------------------------------------------------

11651
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BIN
driver/GR8RAM.bin Executable file
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21
gerber/GR8RAM-BOM.csv Normal file
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@ -0,0 +1,21 @@
Reference, Quantity, Value, Footprint, Datasheet, LCSC Part
C10 C1 C7 C2 C3 C4 C11 ,7,"10u","stdpads:C_0805","~","C15850"
C31 C30 C44 C43 C42 C35 C34 C33 C32 C26 C28 C27 C25 C24 C18 C23 C22 C21 C20 C19 C16 C15 C14 C13 C12 C29 C5 ,27,"2u2","stdpads:C_0603","~","C23630"
FID5 FID4 FID3 FID2 FID1 ,5,"Fiducial","stdpads:Fiducial","~"
H1 ,1," ","stdpads:PasteHole_1.1mm_PTH","~"
H6 H2 H3 H4 H5 ,5," ","stdpads:PasteHole_1.152mm_NPTH","~"
J1 ,1,"AppleIIBus","stdpads:AppleIIBus_Edge","~"
J2 J5 ,2,"JTAG","Connector:Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical","~"
J4 ,1,"JTAG","Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical","~"
R22 R31 ,2,"33","stdpads:R_0603","~","C23140"
R28 R29 ,2,"22k","stdpads:R_0603","~","C31850"
RN2 RN3 RN1 ,3,"4x33","stdpads:R4_0402","~","C25501"
RN5 ,1,"4x10k","stdpads:R4_0402","~","C25725"
SW1 ,1,"FW","stdpads:SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm","~","C319052"
U1 ,1,"EPM240T100C5N","stdpads:TQFP-100_14x14mm_P0.5mm","https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max2/max2_mii5v1.pdf","C10041"
U13 ,1,"25M","stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm","","C669088"
U16 U14 ,2,"74LVC1G125GW","stdpads:SOT-353","","C12519"
U2 ,1,"W9825","stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm","","C62246"
U3 ,1,"W25Q128JVSIQ","stdpads:SOIC-8_5.3mm","","C164122"
U5 U6 U9 U4 ,4,"74AHC245PW","stdpads:TSSOP-20_4.4x6.5mm_P0.65mm","","C5516"
U8 ,1,"XC6206P332MR","stdpads:SOT-23","","C5446"
Can't render this file because it has a wrong number of fields in line 4.

17657
gerber/GR8RAM-B_Cu.gbl Normal file
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gerber/GR8RAM-B_Mask.gbs Normal file
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gerber/GR8RAM-Edge_Cuts.gm1 Normal file
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G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5-0-10_14)*
G04 #@! TF.CreationDate,2021-04-19T04:27:15-04:00*
G04 #@! TF.ProjectId,GR8RAM,47523852-414d-42e6-9b69-6361645f7063,0.9*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Profile,NP*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW (5.1.5-0-10_14)) date 2021-04-19 04:27:15*
%MOMM*%
%LPD*%
G04 APERTURE LIST*
%ADD10C,0.150000*%
G04 APERTURE END LIST*
D10*
X57785000Y-80391000D02*
X46101001Y-92074999D01*
X57785000Y-80391000D02*
G75*
G02X59309000Y-79883000I1524000J-2032000D01*
G01*
X46101001Y-92074999D02*
G75*
G03X45593000Y-93599000I2031999J-1524001D01*
G01*
X48133000Y-132080000D02*
X73914000Y-132080000D01*
X59309000Y-79883000D02*
X143002000Y-79883000D01*
X143002000Y-79883000D02*
G75*
G02X145542000Y-82423000I0J-2540000D01*
G01*
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X145542000Y-129540000D02*
X145542000Y-82423000D01*
X74422000Y-139700000D02*
G75*
G02X73914000Y-139192000I0J508000D01*
G01*
X139446000Y-139192000D02*
G75*
G02X138938000Y-139700000I-508000J0D01*
G01*
X73914000Y-132080000D02*
X73914000Y-139192000D01*
X45593000Y-129540000D02*
X45593000Y-93599000D01*
X48133000Y-132080000D02*
G75*
G02X45593000Y-129540000I0J2540000D01*
G01*
X143002000Y-132080000D02*
X139446000Y-132080000D01*
X139446000Y-132080000D02*
X139446000Y-139192000D01*
X145542000Y-129540000D02*
G75*
G02X143002000Y-132080000I-2540000J0D01*
G01*
M02*

67267
gerber/GR8RAM-F_Cu.gtl Normal file
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gerber/GR8RAM-F_Mask.gts Normal file
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gerber/GR8RAM-F_SilkS.gto Normal file
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gerber/GR8RAM-In1_Cu.g2 Normal file
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gerber/GR8RAM-In2_Cu.g3 Normal file
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1
gerber/GR8RAM-bottom-pos.csv Normal file
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Ref,Val,Package,MidX,MidY,Rot,Side
1 Ref Val Package MidX MidY Rot Side

6
gerber/GR8RAM-bottom.pos Normal file
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### Module positions - created on Monday, April 19, 2021 at 04:27:25 AM ###
### Printed by Pcbnew version kicad (5.1.5-0-10_14)
## Unit = mm, Angle = deg.
## Side : bottom
# Ref Val Package PosX PosY Rot Side
## End

9585
gerber/GR8RAM-drl_map.ps Normal file
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gerber/GR8RAM-top-pos.csv Normal file
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Ref,Val,Package,MidX,MidY,Rot,Side
"C1","10u","C_0805",136.310000,-128.270000,180.000000,top
"C2","10u","C_0805",119.976000,-128.270000,180.000000,top
"C3","10u","C_0805",116.244000,-128.270000,0.000000,top
"C4","10u","C_0805",75.350000,-128.270000,180.000000,top
"C5","2u2","C_0603",113.650000,-90.750000,180.000000,top
"C7","10u","C_0805",140.100000,-124.200000,90.000000,top
"C10","10u","C_0805",132.750000,-124.200000,90.000000,top
"C11","10u","C_0805",130.350000,-124.200000,90.000000,top
"C12","2u2","C_0603",123.650000,-90.750000,180.000000,top
"C13","2u2","C_0603",76.600000,-119.800000,270.000000,top
"C14","2u2","C_0603",85.800000,-119.800000,270.000000,top
"C15","2u2","C_0603",95.000000,-119.800000,270.000000,top
"C16","2u2","C_0603",104.200000,-119.800000,270.000000,top
"C18","2u2","C_0603",82.800000,-103.551000,90.000000,top
"C19","2u2","C_0603",84.350000,-98.000000,90.000000,top
"C20","2u2","C_0603",84.350000,-100.900000,90.000000,top
"C21","2u2","C_0603",90.800000,-111.100000,0.000000,top
"C22","2u2","C_0603",97.800000,-111.100000,0.000000,top
"C23","2u2","C_0603",103.750000,-104.300000,270.000000,top
"C24","2u2","C_0603",103.750000,-100.900000,90.000000,top
"C25","2u2","C_0603",97.150000,-91.700000,180.000000,top
"C26","2u2","C_0603",90.150000,-91.700000,180.000000,top
"C27","2u2","C_0603",105.950000,-98.750000,270.000000,top
"C28","2u2","C_0603",123.650000,-115.350000,180.000000,top
"C29","2u2","C_0603",126.450000,-112.600000,270.000000,top
"C30","2u2","C_0603",126.450000,-107.800000,270.000000,top
"C31","2u2","C_0603",126.450000,-103.800000,270.000000,top
"C32","2u2","C_0603",126.450000,-93.400000,270.000000,top
"C33","2u2","C_0603",110.800000,-104.050000,90.000000,top
"C34","2u2","C_0603",110.850000,-108.700000,90.000000,top
"C35","2u2","C_0603",113.650000,-115.350000,180.000000,top
"C42","2u2","C_0603",117.800000,-122.100000,90.000000,top
"C43","2u2","C_0603",104.800000,-112.250000,0.000000,top
"C44","2u2","C_0603",69.000000,-100.650000,270.000000,top
"FID1","Fiducial","Fiducial",143.002000,-82.423000,270.000000,top
"FID2","Fiducial","Fiducial",48.133000,-93.599000,90.000000,top
"FID3","Fiducial","Fiducial",58.801000,-82.931000,90.000000,top
"FID4","Fiducial","Fiducial",143.002000,-129.540000,0.000000,top
"FID5","Fiducial","Fiducial",48.133000,-129.540000,0.000000,top
"R22","33","R_0603",115.800000,-124.200000,180.000000,top
"R28","22k","R_0603",70.550000,-110.650000,0.000000,top
"R29","22k","R_0603",70.550000,-112.100000,180.000000,top
"R31","33","R_0603",80.950000,-108.500000,90.000000,top
"RN1","4x33","R4_0402",108.200000,-95.150000,0.000000,top
"RN2","4x33","R4_0402",108.450000,-106.250000,270.000000,top
"RN3","4x33","R4_0402",108.450000,-110.650000,270.000000,top
"RN5","4x10k","R4_0402",69.100000,-96.450000,90.000000,top
"SW1","FW","SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm",135.763000,-95.885000,0.000000,top
"U1","EPM240T100C5N","TQFP-100_14x14mm_P0.5mm",94.050000,-101.400000,270.000000,top
"U2","W9825","TSOP-II-54_22.2x10.16mm_P0.8mm",118.650000,-103.050000,180.000000,top
"U3","W25Q128JVSIQ","SOIC-8_5.3mm",79.121000,-100.711000,180.000000,top
"U4","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",90.225000,-122.000000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",108.625000,-122.000000,0.000000,top
"U6","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",81.025000,-122.000000,0.000000,top
"U8","XC6206P332MR","SOT-23",136.250000,-124.200000,180.000000,top
"U9","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",99.425000,-122.000000,0.000000,top
"U13","25M","Crystal_SMD_3225-4Pin_3.2x2.5mm",107.100000,-102.500000,0.000000,top
"U14","74LVC1G125GW","SOT-353",115.650000,-121.850000,90.000000,top
"U16","74LVC1G125GW","SOT-353",108.200000,-98.850000,270.000000,top
1 Ref Val Package MidX MidY Rot Side
2 C1 10u C_0805 136.310000 -128.270000 180.000000 top
3 C2 10u C_0805 119.976000 -128.270000 180.000000 top
4 C3 10u C_0805 116.244000 -128.270000 0.000000 top
5 C4 10u C_0805 75.350000 -128.270000 180.000000 top
6 C5 2u2 C_0603 113.650000 -90.750000 180.000000 top
7 C7 10u C_0805 140.100000 -124.200000 90.000000 top
8 C10 10u C_0805 132.750000 -124.200000 90.000000 top
9 C11 10u C_0805 130.350000 -124.200000 90.000000 top
10 C12 2u2 C_0603 123.650000 -90.750000 180.000000 top
11 C13 2u2 C_0603 76.600000 -119.800000 270.000000 top
12 C14 2u2 C_0603 85.800000 -119.800000 270.000000 top
13 C15 2u2 C_0603 95.000000 -119.800000 270.000000 top
14 C16 2u2 C_0603 104.200000 -119.800000 270.000000 top
15 C18 2u2 C_0603 82.800000 -103.551000 90.000000 top
16 C19 2u2 C_0603 84.350000 -98.000000 90.000000 top
17 C20 2u2 C_0603 84.350000 -100.900000 90.000000 top
18 C21 2u2 C_0603 90.800000 -111.100000 0.000000 top
19 C22 2u2 C_0603 97.800000 -111.100000 0.000000 top
20 C23 2u2 C_0603 103.750000 -104.300000 270.000000 top
21 C24 2u2 C_0603 103.750000 -100.900000 90.000000 top
22 C25 2u2 C_0603 97.150000 -91.700000 180.000000 top
23 C26 2u2 C_0603 90.150000 -91.700000 180.000000 top
24 C27 2u2 C_0603 105.950000 -98.750000 270.000000 top
25 C28 2u2 C_0603 123.650000 -115.350000 180.000000 top
26 C29 2u2 C_0603 126.450000 -112.600000 270.000000 top
27 C30 2u2 C_0603 126.450000 -107.800000 270.000000 top
28 C31 2u2 C_0603 126.450000 -103.800000 270.000000 top
29 C32 2u2 C_0603 126.450000 -93.400000 270.000000 top
30 C33 2u2 C_0603 110.800000 -104.050000 90.000000 top
31 C34 2u2 C_0603 110.850000 -108.700000 90.000000 top
32 C35 2u2 C_0603 113.650000 -115.350000 180.000000 top
33 C42 2u2 C_0603 117.800000 -122.100000 90.000000 top
34 C43 2u2 C_0603 104.800000 -112.250000 0.000000 top
35 C44 2u2 C_0603 69.000000 -100.650000 270.000000 top
36 FID1 Fiducial Fiducial 143.002000 -82.423000 270.000000 top
37 FID2 Fiducial Fiducial 48.133000 -93.599000 90.000000 top
38 FID3 Fiducial Fiducial 58.801000 -82.931000 90.000000 top
39 FID4 Fiducial Fiducial 143.002000 -129.540000 0.000000 top
40 FID5 Fiducial Fiducial 48.133000 -129.540000 0.000000 top
41 R22 33 R_0603 115.800000 -124.200000 180.000000 top
42 R28 22k R_0603 70.550000 -110.650000 0.000000 top
43 R29 22k R_0603 70.550000 -112.100000 180.000000 top
44 R31 33 R_0603 80.950000 -108.500000 90.000000 top
45 RN1 4x33 R4_0402 108.200000 -95.150000 0.000000 top
46 RN2 4x33 R4_0402 108.450000 -106.250000 270.000000 top
47 RN3 4x33 R4_0402 108.450000 -110.650000 270.000000 top
48 RN5 4x10k R4_0402 69.100000 -96.450000 90.000000 top
49 SW1 FW SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm 135.763000 -95.885000 0.000000 top
50 U1 EPM240T100C5N TQFP-100_14x14mm_P0.5mm 94.050000 -101.400000 270.000000 top
51 U2 W9825 TSOP-II-54_22.2x10.16mm_P0.8mm 118.650000 -103.050000 180.000000 top
52 U3 W25Q128JVSIQ SOIC-8_5.3mm 79.121000 -100.711000 180.000000 top
53 U4 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 90.225000 -122.000000 0.000000 top
54 U5 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 108.625000 -122.000000 0.000000 top
55 U6 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 81.025000 -122.000000 0.000000 top
56 U8 XC6206P332MR SOT-23 136.250000 -124.200000 180.000000 top
57 U9 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 99.425000 -122.000000 0.000000 top
58 U13 25M Crystal_SMD_3225-4Pin_3.2x2.5mm 107.100000 -102.500000 0.000000 top
59 U14 74LVC1G125GW SOT-353 115.650000 -121.850000 90.000000 top
60 U16 74LVC1G125GW SOT-353 108.200000 -98.850000 270.000000 top

65
gerber/GR8RAM-top.pos Normal file
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### Module positions - created on Monday, April 19, 2021 at 04:27:25 AM ###
### Printed by Pcbnew version kicad (5.1.5-0-10_14)
## Unit = mm, Angle = deg.
## Side : top
# Ref Val Package PosX PosY Rot Side
C1 10u C_0805 136.3100 -128.2700 180.0000 top
C2 10u C_0805 119.9760 -128.2700 180.0000 top
C3 10u C_0805 116.2440 -128.2700 0.0000 top
C4 10u C_0805 75.3500 -128.2700 180.0000 top
C5 2u2 C_0603 113.6500 -90.7500 180.0000 top
C7 10u C_0805 140.1000 -124.2000 90.0000 top
C10 10u C_0805 132.7500 -124.2000 90.0000 top
C11 10u C_0805 130.3500 -124.2000 90.0000 top
C12 2u2 C_0603 123.6500 -90.7500 180.0000 top
C13 2u2 C_0603 76.6000 -119.8000 270.0000 top
C14 2u2 C_0603 85.8000 -119.8000 270.0000 top
C15 2u2 C_0603 95.0000 -119.8000 270.0000 top
C16 2u2 C_0603 104.2000 -119.8000 270.0000 top
C18 2u2 C_0603 82.8000 -103.5510 90.0000 top
C19 2u2 C_0603 84.3500 -98.0000 90.0000 top
C20 2u2 C_0603 84.3500 -100.9000 90.0000 top
C21 2u2 C_0603 90.8000 -111.1000 0.0000 top
C22 2u2 C_0603 97.8000 -111.1000 0.0000 top
C23 2u2 C_0603 103.7500 -104.3000 270.0000 top
C24 2u2 C_0603 103.7500 -100.9000 90.0000 top
C25 2u2 C_0603 97.1500 -91.7000 180.0000 top
C26 2u2 C_0603 90.1500 -91.7000 180.0000 top
C27 2u2 C_0603 105.9500 -98.7500 270.0000 top
C28 2u2 C_0603 123.6500 -115.3500 180.0000 top
C29 2u2 C_0603 126.4500 -112.6000 270.0000 top
C30 2u2 C_0603 126.4500 -107.8000 270.0000 top
C31 2u2 C_0603 126.4500 -103.8000 270.0000 top
C32 2u2 C_0603 126.4500 -93.4000 270.0000 top
C33 2u2 C_0603 110.8000 -104.0500 90.0000 top
C34 2u2 C_0603 110.8500 -108.7000 90.0000 top
C35 2u2 C_0603 113.6500 -115.3500 180.0000 top
C42 2u2 C_0603 117.8000 -122.1000 90.0000 top
C43 2u2 C_0603 104.8000 -112.2500 0.0000 top
C44 2u2 C_0603 69.0000 -100.6500 270.0000 top
FID1 Fiducial Fiducial 143.0020 -82.4230 270.0000 top
FID2 Fiducial Fiducial 48.1330 -93.5990 90.0000 top
FID3 Fiducial Fiducial 58.8010 -82.9310 90.0000 top
FID4 Fiducial Fiducial 143.0020 -129.5400 0.0000 top
FID5 Fiducial Fiducial 48.1330 -129.5400 0.0000 top
R22 33 R_0603 115.8000 -124.2000 180.0000 top
R28 22k R_0603 70.5500 -110.6500 0.0000 top
R29 22k R_0603 70.5500 -112.1000 180.0000 top
R31 33 R_0603 80.9500 -108.5000 90.0000 top
RN1 4x33 R4_0402 108.2000 -95.1500 0.0000 top
RN2 4x33 R4_0402 108.4500 -106.2500 270.0000 top
RN3 4x33 R4_0402 108.4500 -110.6500 270.0000 top
RN5 4x10k R4_0402 69.1000 -96.4500 90.0000 top
SW1 FW SW_DIP_SPSTx02_Slide_DSHP02TS_P1.27mm 135.7630 -95.8850 0.0000 top
U1 EPM240T100C5N TQFP-100_14x14mm_P0.5mm 94.0500 -101.4000 270.0000 top
U2 W9825 TSOP-II-54_22.2x10.16mm_P0.8mm 118.6500 -103.0500 180.0000 top
U3 W25Q128JVSIQ SOIC-8_5.3mm 79.1210 -100.7110 180.0000 top
U4 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 90.2250 -122.0000 0.0000 top
U5 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 108.6250 -122.0000 0.0000 top
U6 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 81.0250 -122.0000 0.0000 top
U8 XC6206P332MR SOT-23 136.2500 -124.2000 180.0000 top
U9 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 99.4250 -122.0000 0.0000 top
U13 25M Crystal_SMD_3225-4Pin_3.2x2.5mm 107.1000 -102.5000 0.0000 top
U14 74LVC1G125GW SOT-353 115.6500 -121.8500 90.0000 top
U16 74LVC1G125GW SOT-353 108.2000 -98.8500 270.0000 top
## End

759
gerber/GR8RAM.drl Normal file
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@ -0,0 +1,759 @@
M48
; DRILL file {KiCad (5.1.5-0-10_14)} date Monday, April 19, 2021 at 04:27:16 AM
; FORMAT={-:-/ absolute / inch / decimal}
; #@! TF.CreationDate,2021-04-19T04:27:16-04:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.1.5-0-10_14)
FMAT,2
INCH
T1C0.0079
T2C0.0118
T3C0.0150
T4C0.0157
T5C0.0300
T6C0.0400
T7C0.0433
T8C0.0390
T9C0.0454
T10C0.0935
%
G90
G05
T1
X1.825Y-3.68
X1.825Y-3.915
X1.825Y-4.115
X1.825Y-4.315
X1.825Y-4.515
X1.825Y-4.715
X1.825Y-4.915
X1.825Y-5.1
X1.895Y-5.17
X1.925Y-3.575
X1.925Y-4.015
X1.925Y-4.215
X1.925Y-4.415
X1.925Y-4.615
X1.925Y-4.815
X2.025Y-3.475
X2.025Y-3.715
X2.025Y-3.915
X2.025Y-4.115
X2.025Y-4.315
X2.025Y-4.515
X2.025Y-4.715
X2.025Y-4.915
X2.025Y-5.17
X2.12Y-5.04
X2.125Y-3.375
X2.125Y-3.615
X2.125Y-3.815
X2.125Y-4.015
X2.125Y-4.215
X2.125Y-4.415
X2.125Y-4.615
X2.125Y-4.815
X2.2Y-3.485
X2.22Y-4.515
X2.22Y-4.715
X2.22Y-4.915
X2.2205Y-3.915
X2.2205Y-4.115
X2.2205Y-4.315
X2.225Y-3.275
X2.225Y-3.715
X2.225Y-5.17
X2.2598Y-4.3327
X2.2598Y-4.878
X2.28Y-3.4
X2.2854Y-4.5354
X2.29Y-3.585
X2.313Y-4.876
X2.32Y-5.04
X2.33Y-3.175
X2.345Y-3.475
X2.345Y-3.675
X2.36Y-3.32
X2.3701Y-4.2067
X2.415Y-4.6375
X2.4225Y-4.91
X2.425Y-5.17
X2.445Y-3.175
X2.445Y-3.375
X2.445Y-3.575
X2.465Y-4.7525
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X3.4193Y-5.1161
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X3.4409Y-4.3996
X3.4449Y-3.9114
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X3.4469Y-4.0709
X3.45Y-5.17
X3.4567Y-4.189
X3.4567Y-4.5059
X3.4646Y-4.6437
X3.4665Y-5.1043
X3.4803Y-5.0413
X3.4823Y-3.8346
X3.4823Y-3.874
X3.4823Y-4.0118
X3.4843Y-3.9232
X3.5039Y-3.7638
X3.5157Y-3.6437
X3.5197Y-5.1122
X3.5217Y-4.0984
X3.545Y-3.3
X3.5453Y-3.7539
X3.5453Y-4.2087
X3.55Y-5.17
X3.5551Y-5.0925
X3.5591Y-4.3386
X3.561Y-4.248
X3.5787Y-3.6457
X3.5787Y-4.9724
X3.5827Y-3.7343
X3.5886Y-4.248
X3.5906Y-4.3386
X3.6063Y-3.6457
X3.6102Y-3.7343
X3.6201Y-4.9902
X3.6201Y-5.1122
X3.6398Y-4.4449
X3.6437Y-5.0374
X3.6437Y-5.0807
X3.645Y-3.175
X3.645Y-3.405
X3.65Y-5.17
X3.6673Y-4.874
X3.6673Y-4.9646
X3.6929Y-4.9193
X3.7067Y-4.6909
X3.7205Y-5.1142
X3.7402Y-5.0354
X3.745Y-3.3
X3.745Y-3.475
X3.75Y-5.17
X3.7746Y-4.687
X3.7746Y-4.7461
X3.7776Y-3.75
X3.7854Y-4.4035
X3.7913Y-3.6457
X3.7992Y-4.6437
X3.7992Y-4.7303
X3.7992Y-4.874
X3.8071Y-3.7776
X3.8169Y-3.7402
X3.8268Y-3.815
X3.8268Y-4.6437
X3.8346Y-4.3386
X3.8366Y-4.248
X3.8366Y-4.9961
X3.845Y-3.175
X3.845Y-3.405
X3.85Y-5.17
X3.8504Y-4.2106
X3.8543Y-3.6457
X3.8563Y-3.7362
X3.8622Y-3.7953
X3.8642Y-4.248
X3.8661Y-4.3386
X3.8799Y-5.0413
X3.8839Y-3.7362
X3.8858Y-3.6457
X3.9035Y-3.7913
X3.9193Y-5.061
X3.9213Y-4.0335
X3.9213Y-4.0945
X3.9232Y-3.7362
X3.9232Y-3.9331
X3.9232Y-3.9724
X3.9272Y-4.2264
X3.9272Y-4.5217
X3.939Y-3.6457
X3.939Y-4.4449
X3.945Y-3.305
X3.945Y-3.475
X3.95Y-5.17
X3.9567Y-4.1142
X3.9587Y-3.7756
X3.9587Y-3.815
X3.9587Y-3.8543
X3.9587Y-3.8937
X3.9587Y-3.9528
X3.9587Y-3.9921
X3.9587Y-4.0472
X3.9587Y-4.0748
X3.9764Y-4.3917
X3.9823Y-3.6614
X4.0197Y-5.1063
X4.0256Y-4.3071
X4.0295Y-4.874
X4.0295Y-4.9646
X4.0354Y-4.6299
X4.045Y-3.175
X4.045Y-3.405
X4.045Y-3.575
X4.0492Y-3.7559
X4.0492Y-3.7953
X4.0492Y-3.8346
X4.0492Y-3.874
X4.0492Y-3.9134
X4.0492Y-3.9528
X4.0492Y-3.9921
X4.0492Y-4.0453
X4.0492Y-4.0768
X4.05Y-5.17
X4.0502Y-4.1398
X4.0551Y-4.9193
X4.061Y-5.0827
X4.065Y-4.4193
X4.0689Y-4.6909
X4.0846Y-4.1673
X4.0925Y-4.5079
X4.0945Y-4.2549
X4.1024Y-4.3858
X4.1024Y-4.4528
X4.122Y-3.9449
X4.124Y-4.0394
X4.1358Y-3.8957
X4.1358Y-4.7461
X4.1368Y-4.687
X4.1417Y-5.0669
X4.1437Y-4.3346
X4.145Y-3.305
X4.145Y-3.475
X4.1496Y-4.3858
X4.1496Y-4.4528
X4.15Y-5.17
X4.1614Y-4.6437
X4.1614Y-4.7303
X4.1614Y-4.874
X4.1713Y-3.8189
X4.1732Y-3.9488
X4.187Y-4.4193
X4.187Y-4.7303
X4.187Y-4.8445
X4.189Y-4.6437
X4.1929Y-4.1555
X4.2028Y-3.8189
X4.2067Y-3.9173
X4.2087Y-4.9921
X4.2106Y-3.8583
X4.2126Y-4.874
X4.2205Y-5.0551
X4.2343Y-3.8228
X4.2343Y-3.9587
X4.2382Y-4.8445
X4.245Y-3.175
X4.245Y-3.405
X4.245Y-3.575
X4.25Y-5.17
X4.2539Y-4.1083
X4.2559Y-4.2697
X4.2598Y-3.8484
X4.2638Y-4.874
X4.2854Y-3.9587
X4.2874Y-4.4646
X4.2874Y-4.9921
X4.2894Y-4.128
X4.2894Y-4.2382
X4.2894Y-4.3012
X4.2894Y-4.4114
X4.2894Y-4.8445
X4.3071Y-3.9252
X4.3189Y-4.1634
X4.3189Y-4.2028
X4.3189Y-4.3366
X4.3189Y-4.376
X4.3228Y-3.7598
X4.3287Y-4.1201
X4.3287Y-4.25
X4.3346Y-5.0571
X4.3406Y-4.9646
X4.345Y-3.305
X4.345Y-3.475
X4.35Y-5.17
X4.3602Y-3.7972
X4.3661Y-3.9291
X4.3917Y-4.874
X4.3917Y-4.9646
X4.3996Y-3.6417
X4.3996Y-4.0571
X4.3996Y-4.1201
X4.3996Y-4.3091
X4.3996Y-4.4035
X4.3996Y-4.4665
X4.4173Y-4.9193
X4.4449Y-4.4902
X4.445Y-3.175
X4.445Y-3.405
X4.45Y-5.17
X4.4547Y-5.0374
X4.455Y-4.875
X4.4902Y-3.6476
X4.4902Y-3.7106
X4.4902Y-3.7736
X4.4902Y-3.8366
X4.4902Y-3.8996
X4.4902Y-3.9941
X4.4902Y-4.0571
X4.4902Y-4.1201
X4.4902Y-4.2146
X4.4902Y-4.3091
X4.4902Y-4.4035
X4.4902Y-4.4665
X4.5039Y-4.7638
X4.5157Y-3.6791
X4.5157Y-3.7421
X4.5157Y-3.8051
X4.5157Y-3.8681
X4.5157Y-3.9311
X4.5177Y-4.0886
X4.5177Y-4.1476
X4.5177Y-4.187
X4.5177Y-4.2421
X4.5177Y-4.2815
X4.5177Y-4.3366
X4.5177Y-4.376
X4.5177Y-4.435
X4.5276Y-4.7283
X4.545Y-3.305
X4.545Y-3.475
X4.55Y-5.17
X4.555Y-4.675
X4.5787Y-4.7283
X4.5906Y-4.937
X4.6004Y-4.8307
X4.6043Y-4.7835
X4.624Y-4.0571
X4.6378Y-4.7461
X4.6378Y-4.8681
X4.645Y-3.175
X4.645Y-3.405
X4.645Y-3.575
X4.645Y-4.575
X4.65Y-5.17
X4.6713Y-4.1201
X4.6713Y-4.1673
X4.6713Y-4.2146
X4.6713Y-4.2618
X4.6713Y-4.3091
X4.6713Y-4.3563
X4.6713Y-4.4035
X4.6713Y-4.4665
X4.6713Y-4.7835
X4.6713Y-4.8307
X4.7185Y-4.0571
X4.745Y-3.275
X4.745Y-3.475
X4.745Y-4.675
X4.745Y-4.875
X4.75Y-5.17
X4.8012Y-3.6791
X4.8248Y-4.0886
X4.8248Y-4.1476
X4.8248Y-4.187
X4.8248Y-4.2421
X4.8248Y-4.2815
X4.8248Y-4.3366
X4.8248Y-4.376
X4.8248Y-4.435
X4.8268Y-3.7106
X4.8268Y-3.7736
X4.8268Y-3.8366
X4.8268Y-3.8996
X4.8268Y-3.9626
X4.8268Y-4.0256
X4.845Y-3.175
X4.845Y-3.375
X4.845Y-4.775
X4.845Y-4.975
X4.85Y-5.17
X4.8524Y-3.6476
X4.8524Y-3.7421
X4.8524Y-3.8051
X4.8524Y-3.8681
X4.8524Y-3.9311
X4.8524Y-3.9941
X4.8524Y-4.0571
X4.8524Y-4.1201
X4.8524Y-4.2146
X4.8524Y-4.3091
X4.8524Y-4.4035
X4.8524Y-4.4665
X4.8976Y-3.6201
X4.8976Y-4.4902
X4.9429Y-3.6476
X4.9429Y-4.0571
X4.9429Y-4.1201
X4.9429Y-4.2146
X4.9429Y-4.4035
X4.9429Y-4.4508
X4.9449Y-3.7067
X4.945Y-3.275
X4.945Y-3.475
X4.945Y-4.675
X4.945Y-4.875
X4.945Y-5.075
X4.95Y-5.17
X5.045Y-3.175
X5.045Y-3.375
X5.045Y-3.575
X5.045Y-3.775
X5.045Y-3.975
X5.045Y-4.575
X5.045Y-4.775
X5.045Y-4.975
X5.05Y-5.17
X5.145Y-3.275
X5.145Y-3.475
X5.145Y-3.675
X5.145Y-3.875
X5.145Y-4.475
X5.145Y-4.675
X5.145Y-5.075
X5.15Y-5.17
X5.2Y-5.165
X5.245Y-3.175
X5.245Y-3.375
X5.245Y-3.575
X5.245Y-3.775
X5.245Y-3.975
X5.245Y-4.575
X5.25Y-5.17
X5.3Y-5.165
X5.3Y-5.165
X5.32Y-3.58
X5.32Y-3.97
X5.345Y-3.275
X5.345Y-3.475
X5.345Y-3.675
X5.345Y-3.875
X5.345Y-4.475
X5.345Y-4.675
X5.35Y-5.17
X5.37Y-3.58
X5.37Y-3.97
X5.445Y-3.175
X5.445Y-3.375
X5.445Y-3.575
X5.445Y-3.775
X5.445Y-3.975
X5.445Y-4.575
X5.445Y-4.775
X5.45Y-5.17
X5.545Y-3.475
X5.545Y-3.675
X5.545Y-3.875
X5.545Y-4.475
X5.545Y-4.675
X5.63Y-3.175
X5.63Y-5.17
X5.645Y-3.375
X5.645Y-3.575
X5.645Y-3.775
X5.645Y-3.975
X5.645Y-4.175
X5.645Y-4.575
X5.645Y-4.775
X5.7Y-3.245
X5.7Y-3.475
X5.7Y-3.675
X5.7Y-3.875
X5.7Y-4.075
X5.7Y-4.275
X5.7Y-4.475
X5.7Y-4.475
X5.7Y-4.675
X5.7Y-4.875
X5.7Y-5.1
T2
X2.9803Y-4.6929
X2.9803Y-4.7402
X3.0157Y-4.6535
X3.0157Y-4.7795
X3.3425Y-4.7402
X3.378Y-4.7795
X3.4862Y-3.6102
X3.5118Y-4.374
X3.5256Y-3.5748
X3.5512Y-4.4094
X3.5728Y-3.5748
X3.5984Y-4.4094
X3.6378Y-4.374
X3.7047Y-4.7402
X3.7402Y-4.7795
X3.7618Y-3.6102
X3.7874Y-4.374
X3.8012Y-3.5748
X3.8268Y-4.4094
X3.8484Y-3.5748
X3.874Y-4.4094
X3.8878Y-3.6102
X3.9134Y-4.374
X4.0669Y-4.7402
X4.1024Y-4.7795
X4.1201Y-4.1358
X4.3622Y-4.0335
X4.4114Y-3.5728
X4.4114Y-4.5413
X4.4449Y-3.6201
X4.4508Y-3.5374
X4.4508Y-4.5768
X4.498Y-3.5374
X4.498Y-3.6083
X4.498Y-4.5059
X4.498Y-4.5768
X4.5374Y-3.5728
X4.5374Y-4.5413
X4.8051Y-3.5728
X4.8051Y-4.5413
X4.8445Y-3.5374
X4.8445Y-3.6083
X4.8445Y-4.5059
X4.8445Y-4.5768
X4.8917Y-3.5374
X4.8917Y-4.5768
X4.9311Y-3.5728
X4.9311Y-4.5413
X4.9783Y-3.6142
X4.9783Y-4.1496
X4.9783Y-4.1811
X4.9783Y-4.3701
X5.0138Y-4.4094
X5.0138Y-4.4567
T3
X4.9783Y-4.311
X5.0177Y-4.0669
X5.0177Y-4.1063
T4
X2.89Y-5.06
X2.935Y-5.1
X3.0Y-5.1
X3.045Y-5.05
X3.378Y-4.6496
X3.7402Y-4.6496
X4.0846Y-4.0394
X4.1024Y-4.6496
X4.124Y-4.002
X4.124Y-4.0768
X4.3091Y-4.0689
X4.3642Y-4.1575
X4.3642Y-4.2126
X4.3642Y-4.3484
X4.5Y-5.05
X4.545Y-5.1
X4.61Y-5.1
X4.69Y-5.1
X4.755Y-5.1
X4.7975Y-5.05
X4.9783Y-3.7441
X4.9783Y-4.0197
X4.9783Y-4.5
X5.0177Y-3.6575
X5.0177Y-3.6969
X5.0177Y-4.2244
X5.0177Y-4.2638
X5.0846Y-4.8563
X5.0846Y-4.9154
X5.1319Y-4.815
X5.1319Y-4.9646
X5.1791Y-4.8642
X5.1791Y-4.9154
X5.2264Y-4.815
X5.2264Y-4.9646
X5.2756Y-4.8622
X5.2756Y-4.9173
X5.29Y-5.05
X5.3228Y-4.815
X5.3228Y-4.9626
X5.335Y-5.0
X5.335Y-5.1
X5.4Y-5.0
X5.445Y-5.05
X5.4685Y-4.8602
X5.5157Y-4.815
X5.563Y-4.8642
T5
X5.4Y-5.11
T6
X2.425Y-3.86
X2.425Y-3.96
X2.425Y-4.06
X2.425Y-4.16
X2.425Y-4.26
X2.525Y-3.86
X2.525Y-3.96
X2.525Y-4.06
X2.525Y-4.16
X2.525Y-4.26
T7
X5.53Y-5.1
T8
X2.365Y-4.695
X2.665Y-4.655
X2.665Y-4.735
X2.365Y-4.695
X2.665Y-4.655
X2.665Y-4.735
T9
X1.895Y-5.0
X2.245Y-3.335
X5.53Y-3.245
X5.63Y-5.0
X1.895Y-3.785
T10
X2.365Y-4.595
X2.365Y-4.795
X2.59Y-4.595
X2.59Y-4.795
X2.365Y-4.595
X2.365Y-4.795
X2.59Y-4.595
X2.59Y-4.795
T0
M30

10
sym-lib-table
View File

@ -1,8 +1,6 @@
(sym_lib_table
(version 7)
(lib (name "GW_RAM")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_RAM.kicad_sym")(options "")(descr ""))
(lib (name "GW_PLD")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_PLD.kicad_sym")(options "")(descr ""))
(lib (name "GW_Logic")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_Logic.kicad_sym")(options "")(descr ""))
(lib (name "GW_Power")(type "KiCad")(uri "${KIPRJMOD}/../GW_Parts/GW_Power.kicad_sym")(options "")(descr ""))
(lib (name "GW_Analog")(type "KiCad")(uri "/Users/zane/Library/Mobile Documents/com~apple~CloudDocs/Repos/GW_Parts/GW_Analog.kicad_sym")(options "")(descr ""))
(lib (name GW_RAM)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_RAM.lib)(options "")(descr ""))
(lib (name GW_PLD)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_PLD.lib)(options "")(descr ""))
(lib (name GW_Logic)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_Logic.lib)(options "")(descr ""))
(lib (name GW_Power)(type Legacy)(uri ${KIPRJMOD}/../GW_Parts/GW_Power.lib)(options "")(descr ""))
)