RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt

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Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
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# Written on Thu Dec 28 23:23:20 2023
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##### FILES SYNTAX CHECKED ##############################################
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Constraint File(s): "\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc"
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#Run constraint checker to find more issues with constraints.
#########################################################################
No issues found in constraint syntax.
Clock Summary
*************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
----------------------------------------------------------------------------------------
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0 - C14M 14.3 MHz 69.841 declared default_clkgroup 122
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0 - System 100.0 MHz 10.000 system system_clkgroup 0
========================================================================================
Clock Load Summary
******************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
----------------------------------------------------------------------------------------
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C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv)
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System 0 - - - -
========================================================================================