2023-09-21 09:45:21 +00:00
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<?xml version="1.0" encoding="UTF-8"?>
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<BaliProject version="3.2" title="RAM2E_LCMXO2_640HC" device="LCMXO2-640HC-4TG100C" default_implementation="impl1">
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<Options/>
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<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
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<Options def_top="RAM2E" top="RAM2E"/>
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2023-12-29 04:12:12 +00:00
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<Source name="../RAM2E.v" type="Verilog" type_short="Verilog">
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2023-09-21 09:45:21 +00:00
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<Options top_module="RAM2E"/>
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</Source>
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2023-12-29 04:12:12 +00:00
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<Source name="../UFM-LCMXO2.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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2023-09-21 09:45:21 +00:00
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<Source name="REFB.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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2024-06-09 05:17:38 +00:00
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<Source name="../DHGR-ON.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
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<Options/>
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</Source>
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2023-09-21 09:45:21 +00:00
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<Source name="../RAM2E-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
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<Options/>
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</Source>
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<Source name="../RAM2E.sdc" type="Synplify Design Constraints File" type_short="SDC">
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<Options/>
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</Source>
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</Implementation>
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<Strategy name="Strategy1" file="RAM2E_LCMXO2_640HC1.sty"/>
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</BaliProject>
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