Compare commits
5 Commits
8e9d1233be
...
1bbca43cfd
| Author | SHA1 | Date |
|---|---|---|
Zane Kaminski
|
1bbca43cfd | |
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Zane Kaminski
|
e73d7034d8 | |
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Zane Kaminski
|
1b7e00193a | |
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Zane Kaminski
|
04eb798443 | |
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Zane Kaminski
|
1de3608efa |
|
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@ -3,9 +3,12 @@
|
|||
<Options/>
|
||||
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
|
||||
<Options def_top="RAM2E" top="RAM2E"/>
|
||||
<Source name="../RAM2E-LCMXO2.v" type="Verilog" type_short="Verilog">
|
||||
<Source name="../RAM2E.v" type="Verilog" type_short="Verilog">
|
||||
<Options top_module="RAM2E"/>
|
||||
</Source>
|
||||
<Source name="../UFM-LCMXO2.v" type="Verilog" type_short="Verilog">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="REFB.v" type="Verilog" type_short="Verilog">
|
||||
<Options/>
|
||||
</Source>
|
||||
|
|
|
|||
|
|
@ -6,13 +6,73 @@
|
|||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn230921045934"></A><B><U><big>pn230921045934</big></U></B>
|
||||
#Start recording tcl command: 9/21/2023 04:58:28
|
||||
<PRE><A name="pn231218062259"></A><B><U><big>pn231218062259</big></U></B>
|
||||
#Start recording tcl command: 12/5/2023 23:09:24
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
|
||||
prj_run PAR -impl impl1 -task IOTiming
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
#Stop recording: 12/18/2023 06:22:59
|
||||
|
||||
|
||||
|
||||
<A name="pn231226182753"></A><B><U><big>pn231226182753</big></U></B>
|
||||
#Start recording tcl command: 12/26/2023 18:26:59
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
|
||||
#Stop recording: 12/26/2023 18:27:53
|
||||
|
||||
|
||||
|
||||
<A name="pn231226232448"></A><B><U><big>pn231226232448</big></U></B>
|
||||
#Start recording tcl command: 12/26/2023 21:40:03
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
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||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 9/21/2023 04:59:34
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_src exclude "//Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v"
|
||||
prj_src remove "//Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v"
|
||||
#Stop recording: 12/26/2023 23:24:48
|
||||
|
||||
|
||||
|
||||
<A name="pn231226233648"></A><B><U><big>pn231226233648</big></U></B>
|
||||
#Start recording tcl command: 12/26/2023 23:26:30
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 12/26/2023 23:36:48
|
||||
|
||||
|
||||
|
||||
<A name="pn231226233754"></A><B><U><big>pn231226233754</big></U></B>
|
||||
#Start recording tcl command: 12/26/2023 23:36:58
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
|
||||
#Stop recording: 12/26/2023 23:37:54
|
||||
|
||||
|
||||
|
||||
<A name="pn231228231137"></A><B><U><big>pn231228231137</big></U></B>
|
||||
#Start recording tcl command: 12/26/2023 23:38:54
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1
|
||||
#Stop recording: 12/28/2023 23:11:37
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Thu Sep 21 05:35:26 2023 *
|
||||
NOTE DATE CREATED: Thu Dec 28 23:24:00 2023 *
|
||||
NOTE DESIGN NAME: RAM2E *
|
||||
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS RD[0] : 36 : inout *
|
||||
NOTE PINS LED : 35 : out *
|
||||
NOTE PINS C14M : 62 : in *
|
||||
NOTE PINS DQMH : 49 : out *
|
||||
NOTE PINS DQML : 48 : out *
|
||||
NOTE PINS RD[7] : 43 : inout *
|
||||
NOTE PINS RD[6] : 42 : inout *
|
||||
NOTE PINS RD[5] : 41 : inout *
|
||||
|
|
@ -16,25 +14,27 @@ NOTE PINS RD[4] : 40 : inout *
|
|||
NOTE PINS RD[3] : 39 : inout *
|
||||
NOTE PINS RD[2] : 38 : inout *
|
||||
NOTE PINS RD[1] : 37 : inout *
|
||||
NOTE PINS RA[11] : 59 : out *
|
||||
NOTE PINS RA[10] : 64 : out *
|
||||
NOTE PINS RA[9] : 63 : out *
|
||||
NOTE PINS RA[8] : 65 : out *
|
||||
NOTE PINS RA[7] : 67 : out *
|
||||
NOTE PINS RA[6] : 69 : out *
|
||||
NOTE PINS RA[5] : 71 : out *
|
||||
NOTE PINS RA[4] : 75 : out *
|
||||
NOTE PINS RA[3] : 74 : out *
|
||||
NOTE PINS RA[2] : 70 : out *
|
||||
NOTE PINS RA[1] : 68 : out *
|
||||
NOTE PINS RA[0] : 66 : out *
|
||||
NOTE PINS DQMH : 49 : out *
|
||||
NOTE PINS DQML : 48 : out *
|
||||
NOTE PINS RAout[11] : 59 : out *
|
||||
NOTE PINS RAout[10] : 64 : out *
|
||||
NOTE PINS RAout[9] : 63 : out *
|
||||
NOTE PINS RAout[8] : 65 : out *
|
||||
NOTE PINS RAout[7] : 67 : out *
|
||||
NOTE PINS RAout[6] : 69 : out *
|
||||
NOTE PINS RAout[5] : 71 : out *
|
||||
NOTE PINS RAout[4] : 75 : out *
|
||||
NOTE PINS RAout[3] : 74 : out *
|
||||
NOTE PINS RAout[2] : 70 : out *
|
||||
NOTE PINS RAout[1] : 68 : out *
|
||||
NOTE PINS RAout[0] : 66 : out *
|
||||
NOTE PINS BA[1] : 60 : out *
|
||||
NOTE PINS BA[0] : 58 : out *
|
||||
NOTE PINS nRWE : 51 : out *
|
||||
NOTE PINS nCAS : 52 : out *
|
||||
NOTE PINS nRAS : 54 : out *
|
||||
NOTE PINS nCS : 57 : out *
|
||||
NOTE PINS CKE : 53 : out *
|
||||
NOTE PINS nRWEout : 51 : out *
|
||||
NOTE PINS nCASout : 52 : out *
|
||||
NOTE PINS nRASout : 54 : out *
|
||||
NOTE PINS nCSout : 57 : out *
|
||||
NOTE PINS CKEout : 53 : out *
|
||||
NOTE PINS nVOE : 10 : out *
|
||||
NOTE PINS Vout[7] : 12 : out *
|
||||
NOTE PINS Vout[6] : 14 : out *
|
||||
|
|
@ -71,7 +71,6 @@ NOTE PINS Ain[1] : 2 : in *
|
|||
NOTE PINS Ain[0] : 3 : in *
|
||||
NOTE PINS nC07X : 34 : in *
|
||||
NOTE PINS nEN80 : 82 : in *
|
||||
NOTE PINS nWE80 : 83 : in *
|
||||
NOTE PINS nWE : 29 : in *
|
||||
NOTE PINS PHI1 : 85 : in *
|
||||
NOTE CONFIGURATION MODE: NONE *
|
||||
|
|
|
|||
|
|
@ -1,41 +1,61 @@
|
|||
----------------------------------------------------------------------
|
||||
Report for cell RAM2E.verilog
|
||||
|
||||
Register bits: 111 of 1280 (9%)
|
||||
Register bits: 122 of 1280 (10%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
I/O cells: 69
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
CCU2D 9 100.0
|
||||
EFB 1 100.0
|
||||
FD1P3AX 48 100.0
|
||||
FD1P3AX 61 100.0
|
||||
FD1P3IX 1 100.0
|
||||
FD1S3AX 22 100.0
|
||||
FD1S3IX 4 100.0
|
||||
FD1S3AX 21 100.0
|
||||
FD1S3AY 4 100.0
|
||||
FD1S3IX 6 100.0
|
||||
GSR 1 100.0
|
||||
IB 22 100.0
|
||||
IB 21 100.0
|
||||
IFS1P3DX 1 100.0
|
||||
INV 1 100.0
|
||||
OB 40 100.0
|
||||
OFS1P3BX 6 100.0
|
||||
OFS1P3DX 27 100.0
|
||||
OFS1P3BX 5 100.0
|
||||
OFS1P3DX 21 100.0
|
||||
OFS1P3IX 2 100.0
|
||||
ORCALUT4 221 100.0
|
||||
ORCALUT4 277 100.0
|
||||
PFUMX 3 100.0
|
||||
PUR 1 100.0
|
||||
VHI 2 100.0
|
||||
VLO 2 100.0
|
||||
VHI 3 100.0
|
||||
VLO 3 100.0
|
||||
SUB MODULES
|
||||
RAM2E_UFM 1 100.0
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 420
|
||||
TOTAL 492
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ufmefb
|
||||
Report for cell RAM2E_UFM.netlist
|
||||
Instance path: ram2e_ufm
|
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Cell usage:
|
||||
cell count Res Usage(%)
|
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EFB 1 100.0
|
||||
VHI 1 50.0
|
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VLO 1 50.0
|
||||
FD1P3AX 30 49.2
|
||||
FD1P3IX 1 100.0
|
||||
FD1S3IX 1 16.7
|
||||
ORCALUT4 272 98.2
|
||||
PFUMX 3 100.0
|
||||
VHI 2 66.7
|
||||
VLO 2 66.7
|
||||
SUB MODULES
|
||||
REFB 1 100.0
|
||||
|
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TOTAL 313
|
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----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
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Instance path: ram2e_ufm.ufmefb
|
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Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EFB 1 100.0
|
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VHI 1 33.3
|
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VLO 1 33.3
|
||||
|
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TOTAL 3
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:21 2023
|
||||
Thu Dec 28 23:23:57 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
|
|
@ -81,6 +81,6 @@ UFM Utilization: General Purpose Flash Memory.
|
|||
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
|
||||
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
|
||||
|
||||
Total CPU Time: 4 secs
|
||||
Total REAL Time: 5 secs
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 3 secs
|
||||
Peak Memory Usage: 275 MB
|
||||
|
|
|
|||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -15,24 +15,24 @@ Target Vendor: LATTICE
|
|||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:34:46
|
||||
Mapped on: 12/28/23 23:23:27
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 111 out of 1520 (7%)
|
||||
PFU registers: 75 out of 1280 (6%)
|
||||
PIO registers: 36 out of 240 (15%)
|
||||
Number of SLICEs: 120 out of 640 (19%)
|
||||
SLICEs as Logic/ROM: 120 out of 640 (19%)
|
||||
Number of registers: 122 out of 1520 (8%)
|
||||
PFU registers: 93 out of 1280 (7%)
|
||||
PIO registers: 29 out of 240 (12%)
|
||||
Number of SLICEs: 148 out of 640 (23%)
|
||||
SLICEs as Logic/ROM: 148 out of 640 (23%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 9 out of 640 (1%)
|
||||
Number of LUT4s: 239 out of 1280 (19%)
|
||||
Number used as logic LUTs: 221
|
||||
Number of LUT4s: 296 out of 1280 (23%)
|
||||
Number used as logic LUTs: 278
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 70 + 4(JTAG) out of 80 (93%)
|
||||
Number of PIO sites used: 69 + 4(JTAG) out of 80 (91%)
|
||||
Number of block RAMs: 0 out of 7 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
|
|
@ -58,64 +58,82 @@ Design Summary
|
|||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 1
|
||||
Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
|
||||
Number of Clock Enables: 11
|
||||
Net C14M_c: 89 loads, 73 rising, 16 falling (Driver: PIO C14M )
|
||||
Number of Clock Enables: 14
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
Design: RAM2E Date: 12/28/23 23:23:27
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
|
||||
Net N_576_i: 17 loads, 9 LSLICEs
|
||||
Net LEDEN13: 4 loads, 4 LSLICEs
|
||||
Net nCS61: 1 loads, 1 LSLICEs
|
||||
Net N_225_i: 2 loads, 0 LSLICEs
|
||||
Net N_201_i: 2 loads, 0 LSLICEs
|
||||
Net N_187_i: 11 loads, 11 LSLICEs
|
||||
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
|
||||
Net RC12: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/CmdBitbangMXO2_RNINSM62: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/wb_we_RNO_0: 1 loads, 1 LSLICEs
|
||||
Net N_185_i: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0]: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0]: 1 loads, 1 LSLICEs
|
||||
Net N_126: 6 loads, 6 LSLICEs
|
||||
Net un9_VOEEN_0_a2_0_a3_0_a3: 1 loads, 1 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
|
||||
Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net N_104: 1 loads, 1 LSLICEs
|
||||
Net N_88: 4 loads, 4 LSLICEs
|
||||
Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Number of LSRs: 7
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net BA_0_sqmuxa: 2 loads, 0 LSLICEs
|
||||
Net S[2]: 1 loads, 1 LSLICEs
|
||||
Net N_566_i: 2 loads, 0 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/wb_rst16_i: 1 loads, 1 LSLICEs
|
||||
Net N_1080_0: 1 loads, 1 LSLICEs
|
||||
Net N_1078_0: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 48 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[0]: 30 loads
|
||||
Net FS[12]: 22 loads
|
||||
Net FS[9]: 21 loads
|
||||
Net S[1]: 21 loads
|
||||
Net FS[10]: 20 loads
|
||||
Net FS[11]: 19 loads
|
||||
Net RWSel: 19 loads
|
||||
Net FS[13]: 17 loads
|
||||
Net S[2]: 50 loads
|
||||
Net S[3]: 45 loads
|
||||
Net S[0]: 37 loads
|
||||
Net S[1]: 34 loads
|
||||
Net FS[12]: 24 loads
|
||||
Net FS[11]: 22 loads
|
||||
Net FS[10]: 19 loads
|
||||
Net FS[13]: 19 loads
|
||||
Net FS[9]: 19 loads
|
||||
Net FS[8]: 18 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 1
|
||||
Number of warnings: 3
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
Design Errors/Warnings
|
||||
----------------------
|
||||
|
||||
WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(93): Semantic
|
||||
error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
|
||||
"nWE80" does not exist in the design. This preference has been disabled.
|
||||
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
temporarily disable certain features of the device including Power
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
discarded.
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 12/28/23 23:23:27
|
||||
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
|
@ -126,24 +144,10 @@ IO (PIO) Attributes
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| C14M | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| DQMH | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| DQML | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS33 | |
|
||||
|
|
@ -158,39 +162,35 @@ IO (PIO) Attributes (cont)
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
| DQMH | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
| DQML | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[9] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[8] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
| RAout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
| RAout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 3
|
||||
|
|
@ -198,13 +198,21 @@ IO (PIO) Attributes (cont)
|
|||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
Design: RAM2E Date: 12/28/23 23:23:27
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| nCS | OUTPUT | LVCMOS33 | OUT |
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CKE | OUTPUT | LVCMOS33 | OUT |
|
||||
| nRWEout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCASout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRASout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCSout | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CKEout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nVOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
|
@ -226,21 +234,21 @@ IO (PIO) Attributes (cont)
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| nDOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
|
@ -250,6 +258,16 @@ IO (PIO) Attributes (cont)
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 12/28/23 23:23:27
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| Din[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
|
|
@ -258,16 +276,6 @@ IO (PIO) Attributes (cont)
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| Ain[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[6] | INPUT | LVCMOS33 | |
|
||||
|
|
@ -288,8 +296,6 @@ IO (PIO) Attributes (cont)
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| nEN80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI1 | INPUT | LVCMOS33 | IN |
|
||||
|
|
@ -299,77 +305,84 @@ Removed logic
|
|||
-------------
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal Dout_0_.CN was merged into signal C14M_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
|
||||
Block ram2e_ufm/GND undriven or does not drive anything - clipped.
|
||||
Signal CKEout.CN was merged into signal C14M_c
|
||||
Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
Design: RAM2E Date: 12/28/23 23:23:27
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block Vout_0_.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
Block nCASout.CN was optimized away.
|
||||
Block ram2e_ufm/ufmefb/VCC was optimized away.
|
||||
Block ram2e_ufm/ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
|
|
@ -377,8 +390,18 @@ Embedded Functional Block Connection Summary
|
|||
--------------------------------------------
|
||||
|
||||
Desired WISHBONE clock frequency: 14.4 MHz
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 12/28/23 23:23:27
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
Clock source: C14M_c
|
||||
Reset source: wb_rst
|
||||
Reset source: ram2e_ufm/wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
|
|
@ -390,16 +413,6 @@ Embedded Functional Block Connection Summary
|
|||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
|
|
@ -424,31 +437,18 @@ Embedded Functional Block Connection Summary (cont)
|
|||
ASIC Components
|
||||
---------------
|
||||
|
||||
Instance Name: ufmefb/EFBInst_0
|
||||
Instance Name: ram2e_ufm/ufmefb/EFBInst_0
|
||||
Type: EFB
|
||||
|
||||
Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 1 secs
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 63 MB
|
||||
Peak Memory Usage: 64 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ Performance Grade: 4
|
|||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.44
|
||||
|
||||
Thu Sep 21 05:34:59 2023
|
||||
Thu Dec 28 23:23:38 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
|
@ -23,7 +23,7 @@ Pinout by Port Name:
|
|||
| BA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| BA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| CKEout | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQMH | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Din[0] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
|
|
@ -34,28 +34,28 @@ Pinout by Port Name:
|
|||
| Din[5] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 87/0 | LVCMOS33_IN | PT12B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[2] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[4] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[5] | 21/3 | LVCMOS33_OUT | PL9B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[0] | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[2] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[4] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[5] | 21/3 | LVCMOS33_OUT | PL9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| LED | 35/2 | LVCMOS33_OUT | PB9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| PHI1 | 85/0 | LVCMOS33_IN | PT12D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[1] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[2] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[5] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[6] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[7] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
|
|
@ -73,15 +73,14 @@ Pinout by Port Name:
|
|||
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nC07X | 34/2 | LVCMOS33_IN | PB9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCAS | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCS | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCASout | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCSout | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nDOE | 20/3 | LVCMOS33_OUT | PL9A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nEN80 | 82/0 | LVCMOS33_IN | PT15C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRAS | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRASout | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWEout | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nVOE | 10/3 | LVCMOS33_OUT | PL4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nWE | 29/2 | LVCMOS33_IN | PB6A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nWE80 | 83/0 | LVCMOS33_IN | PT15B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
|
|
@ -144,33 +143,33 @@ Pinout by Pin Number:
|
|||
| 47/2 | unused, PULL:DOWN | | | PB18D | | | |
|
||||
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
|
||||
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | nRWE | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
|
||||
| 52/1 | nCAS | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
|
||||
| 53/1 | CKE | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
|
||||
| 54/1 | nRAS | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
|
||||
| 57/1 | nCS | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
|
||||
| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
|
||||
| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
|
||||
| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
|
||||
| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
|
||||
| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
|
||||
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
|
||||
| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
|
||||
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
|
||||
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
|
||||
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
|
||||
| 67/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
|
||||
| 68/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
|
||||
| 69/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
|
||||
| 70/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
|
||||
| 71/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
|
||||
| 74/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
|
||||
| 75/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
|
||||
| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
|
||||
| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
|
||||
| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
|
||||
| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
|
||||
| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
|
||||
| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
|
||||
| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
|
||||
| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
|
||||
| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
|
||||
| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
|
||||
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
|
||||
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT16C | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
|
||||
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT15C | JTAGENB | | |
|
||||
| 83/0 | nWE80 | LOCATED | LVCMOS33_IN | PT15B | | | |
|
||||
| 83/0 | unused, PULL:DOWN | | | PT15B | | | |
|
||||
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT15A | | | |
|
||||
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT12D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT12C | SCL/PCLKT0_0 | | |
|
||||
|
|
@ -241,7 +240,7 @@ LOCATE COMP "Ain[7]" SITE "8";
|
|||
LOCATE COMP "BA[0]" SITE "58";
|
||||
LOCATE COMP "BA[1]" SITE "60";
|
||||
LOCATE COMP "C14M" SITE "62";
|
||||
LOCATE COMP "CKE" SITE "53";
|
||||
LOCATE COMP "CKEout" SITE "53";
|
||||
LOCATE COMP "DQMH" SITE "49";
|
||||
LOCATE COMP "DQML" SITE "48";
|
||||
LOCATE COMP "Din[0]" SITE "96";
|
||||
|
|
@ -262,18 +261,18 @@ LOCATE COMP "Dout[6]" SITE "31";
|
|||
LOCATE COMP "Dout[7]" SITE "32";
|
||||
LOCATE COMP "LED" SITE "35";
|
||||
LOCATE COMP "PHI1" SITE "85";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "68";
|
||||
LOCATE COMP "RA[2]" SITE "70";
|
||||
LOCATE COMP "RA[3]" SITE "74";
|
||||
LOCATE COMP "RA[4]" SITE "75";
|
||||
LOCATE COMP "RA[5]" SITE "71";
|
||||
LOCATE COMP "RA[6]" SITE "69";
|
||||
LOCATE COMP "RA[7]" SITE "67";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RAout[0]" SITE "66";
|
||||
LOCATE COMP "RAout[10]" SITE "64";
|
||||
LOCATE COMP "RAout[11]" SITE "59";
|
||||
LOCATE COMP "RAout[1]" SITE "68";
|
||||
LOCATE COMP "RAout[2]" SITE "70";
|
||||
LOCATE COMP "RAout[3]" SITE "74";
|
||||
LOCATE COMP "RAout[4]" SITE "75";
|
||||
LOCATE COMP "RAout[5]" SITE "71";
|
||||
LOCATE COMP "RAout[6]" SITE "69";
|
||||
LOCATE COMP "RAout[7]" SITE "67";
|
||||
LOCATE COMP "RAout[8]" SITE "65";
|
||||
LOCATE COMP "RAout[9]" SITE "63";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
|
|
@ -291,15 +290,14 @@ LOCATE COMP "Vout[5]" SITE "16";
|
|||
LOCATE COMP "Vout[6]" SITE "14";
|
||||
LOCATE COMP "Vout[7]" SITE "12";
|
||||
LOCATE COMP "nC07X" SITE "34";
|
||||
LOCATE COMP "nCAS" SITE "52";
|
||||
LOCATE COMP "nCS" SITE "57";
|
||||
LOCATE COMP "nCASout" SITE "52";
|
||||
LOCATE COMP "nCSout" SITE "57";
|
||||
LOCATE COMP "nDOE" SITE "20";
|
||||
LOCATE COMP "nEN80" SITE "82";
|
||||
LOCATE COMP "nRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "51";
|
||||
LOCATE COMP "nRASout" SITE "54";
|
||||
LOCATE COMP "nRWEout" SITE "51";
|
||||
LOCATE COMP "nVOE" SITE "10";
|
||||
LOCATE COMP "nWE" SITE "29";
|
||||
LOCATE COMP "nWE80" SITE "83";
|
||||
|
||||
|
||||
|
||||
|
|
@ -311,5 +309,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:04 2023
|
||||
Thu Dec 28 23:23:42 2023
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:34:47 2023
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Dec 28 23:23:28 2023
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "LED" SITE "35" ;
|
||||
LOCATE COMP "C14M" SITE "62" ;
|
||||
LOCATE COMP "DQMH" SITE "49" ;
|
||||
LOCATE COMP "DQML" SITE "48" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
|
|
@ -14,25 +12,27 @@ LOCATE COMP "RD[4]" SITE "40" ;
|
|||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[9]" SITE "63" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[7]" SITE "67" ;
|
||||
LOCATE COMP "RA[6]" SITE "69" ;
|
||||
LOCATE COMP "RA[5]" SITE "71" ;
|
||||
LOCATE COMP "RA[4]" SITE "75" ;
|
||||
LOCATE COMP "RA[3]" SITE "74" ;
|
||||
LOCATE COMP "RA[2]" SITE "70" ;
|
||||
LOCATE COMP "RA[1]" SITE "68" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "DQMH" SITE "49" ;
|
||||
LOCATE COMP "DQML" SITE "48" ;
|
||||
LOCATE COMP "RAout[11]" SITE "59" ;
|
||||
LOCATE COMP "RAout[10]" SITE "64" ;
|
||||
LOCATE COMP "RAout[9]" SITE "63" ;
|
||||
LOCATE COMP "RAout[8]" SITE "65" ;
|
||||
LOCATE COMP "RAout[7]" SITE "67" ;
|
||||
LOCATE COMP "RAout[6]" SITE "69" ;
|
||||
LOCATE COMP "RAout[5]" SITE "71" ;
|
||||
LOCATE COMP "RAout[4]" SITE "75" ;
|
||||
LOCATE COMP "RAout[3]" SITE "74" ;
|
||||
LOCATE COMP "RAout[2]" SITE "70" ;
|
||||
LOCATE COMP "RAout[1]" SITE "68" ;
|
||||
LOCATE COMP "RAout[0]" SITE "66" ;
|
||||
LOCATE COMP "BA[1]" SITE "60" ;
|
||||
LOCATE COMP "BA[0]" SITE "58" ;
|
||||
LOCATE COMP "nRWE" SITE "51" ;
|
||||
LOCATE COMP "nCAS" SITE "52" ;
|
||||
LOCATE COMP "nRAS" SITE "54" ;
|
||||
LOCATE COMP "nCS" SITE "57" ;
|
||||
LOCATE COMP "CKE" SITE "53" ;
|
||||
LOCATE COMP "nRWEout" SITE "51" ;
|
||||
LOCATE COMP "nCASout" SITE "52" ;
|
||||
LOCATE COMP "nRASout" SITE "54" ;
|
||||
LOCATE COMP "nCSout" SITE "57" ;
|
||||
LOCATE COMP "CKEout" SITE "53" ;
|
||||
LOCATE COMP "nVOE" SITE "10" ;
|
||||
LOCATE COMP "Vout[7]" SITE "12" ;
|
||||
LOCATE COMP "Vout[6]" SITE "14" ;
|
||||
|
|
@ -69,7 +69,6 @@ LOCATE COMP "Ain[1]" SITE "2" ;
|
|||
LOCATE COMP "Ain[0]" SITE "3" ;
|
||||
LOCATE COMP "nC07X" SITE "34" ;
|
||||
LOCATE COMP "nEN80" SITE "82" ;
|
||||
LOCATE COMP "nWE80" SITE "83" ;
|
||||
LOCATE COMP "nWE" SITE "29" ;
|
||||
LOCATE COMP "PHI1" SITE "85" ;
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
|
@ -79,7 +78,7 @@ BLOCK ASYNCPATHS ;
|
|||
OUTPUT PORT "LED" LOAD 100.000000 pF ;
|
||||
OUTPUT PORT "BA[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "BA[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "CKE" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "CKEout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "DQMH" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "DQML" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
|
||||
|
|
@ -90,18 +89,18 @@ OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
|
|||
OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "RA[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[2]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[3]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[4]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[5]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[6]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[7]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[8]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[9]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[10]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[11]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[2]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[3]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[4]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[5]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[6]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[7]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[8]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[9]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[10]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[11]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ;
|
||||
|
|
@ -110,11 +109,11 @@ OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ;
|
|||
OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "nCAS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nCS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nCASout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nCSout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nDOE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRAS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRWE" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRASout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRWEout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nVOE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
# Thu Dec 28 23:23:19 2023
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
|
@ -48,45 +48,52 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
|
|||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
|
||||
Compiler output is up to date. No re-compile necessary
|
||||
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v changed - recompiling
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
|
||||
Running optimization stage 1 on VLO .......
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
|
||||
Running optimization stage 1 on EFB .......
|
||||
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
|
||||
Running optimization stage 1 on REFB .......
|
||||
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
|
||||
Running optimization stage 1 on RAM2E_UFM .......
|
||||
Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
|
||||
Running optimization stage 1 on RAM2E .......
|
||||
Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
|
||||
Running optimization stage 2 on RAM2E .......
|
||||
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
|
||||
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
|
||||
Running optimization stage 2 on RAM2E_UFM .......
|
||||
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
|
||||
Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on REFB .......
|
||||
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on EFB .......
|
||||
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on VLO .......
|
||||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on VHI .......
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 97MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
# Thu Dec 28 23:23:19 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
|
@ -107,13 +114,14 @@ Implementation : impl1
|
|||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\layer0.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
# Thu Dec 28 23:23:20 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
|
@ -123,12 +131,12 @@ For a summary of runtime and memory usage for all design units, please see file:
|
|||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 31MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
# Thu Dec 28 23:23:20 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
|
@ -151,15 +159,15 @@ Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug
|
|||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:36 2023
|
||||
# Thu Dec 28 23:23:21 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:36 2023
|
||||
# Thu Dec 28 23:23:21 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
|
@ -181,7 +189,7 @@ Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built
|
|||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
|
||||
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 141MB)
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
|
||||
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
|
||||
|
|
@ -190,10 +198,10 @@ See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2
|
|||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
|
||||
|
|
@ -201,46 +209,45 @@ Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00
|
|||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
|
||||
|
||||
@N: FX493 |Applying initial value "0" on instance PHI1reg.
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance DOEEN.
|
||||
@N: FX493 |Applying initial value "0" on instance RWSel.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "1" on instance DQMH.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
|
||||
@N: FX493 |Applying initial value "0" on instance PHI1r.
|
||||
@N: FX493 |Applying initial value "0" on instance RWSel.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWE.
|
||||
@N: FX493 |Applying initial value "0" on instance LEDEN.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance DQMH.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance DQML.
|
||||
@N: FX493 |Applying initial value "0" on instance CKE.
|
||||
@N: FX493 |Applying initial value "1" on instance nCS.
|
||||
@N: FX493 |Applying initial value "1" on instance nRAS.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
@N: FX493 |Applying initial value "1" on instance CKE.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWE.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWEout.
|
||||
@N: FX493 |Applying initial value "1" on instance nCAS.
|
||||
@N: FX493 |Applying initial value "1" on instance nCASout.
|
||||
@N: FX493 |Applying initial value "1" on instance nRAS.
|
||||
@N: FX493 |Applying initial value "1" on instance nRASout.
|
||||
|
||||
Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 182MB)
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
|
||||
|
|
@ -250,7 +257,7 @@ Clock Summary
|
|||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
----------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 122
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
========================================================================================
|
||||
|
|
@ -263,7 +270,7 @@ Clock Load Summary
|
|||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
----------------------------------------------------------------------------------------
|
||||
C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv)
|
||||
C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
========================================================================================
|
||||
|
|
@ -280,14 +287,14 @@ For details review file gcc_ICG_report.rpt
|
|||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
|
||||
1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 111 nCAS
|
||||
@KP:ckid0_0 C14M port 122 nRAS
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
|
@ -299,7 +306,7 @@ Finished Pre Mapping Phase.
|
|||
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
|
@ -308,11 +315,11 @@ Pre-mapping successful!
|
|||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
|
||||
|
||||
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
|
||||
# Thu Sep 21 05:34:38 2023
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Dec 28 23:23:23 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:38 2023
|
||||
# Thu Dec 28 23:23:23 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
|
@ -350,78 +357,78 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
|||
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 179MB peak: 179MB)
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
|
||||
|
||||
@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
|
||||
@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
|
||||
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
None Found
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:02s 29.35ns 222 / 111
|
||||
1 0h:00m:01s 33.71ns 284 / 122
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
|
||||
|
||||
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing report written on Thu Sep 21 05:34:44 2023
|
||||
# Timing report written on Thu Dec 28 23:23:26 2023
|
||||
#
|
||||
|
||||
|
||||
|
|
@ -441,12 +448,12 @@ Performance Summary
|
|||
*******************
|
||||
|
||||
|
||||
Worst slack in design: 31.782
|
||||
Worst slack in design: 33.707
|
||||
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 131.4 MHz 69.841 7.610 31.782 declared default_clkgroup
|
||||
C14M 14.3 MHz 128.0 MHz 69.841 7.813 33.707 declared default_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
===================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
|
@ -464,7 +471,7 @@ Starting Ending | constraint slack | constraint slack | constraint sl
|
|||
----------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 62.231 | No paths - | 34.920 31.782 | No paths -
|
||||
C14M C14M | 69.841 62.028 | No paths - | 34.920 33.707 | No paths -
|
||||
==========================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
|
@ -487,41 +494,41 @@ Detailed Report for Clock: C14M
|
|||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.350 31.782
|
||||
S[3] C14M FD1S3AX Q S[3] 1.350 31.782
|
||||
S[0] C14M FD1S3AX Q S[0] 1.312 31.820
|
||||
S[1] C14M FD1S3AX Q S[1] 1.280 31.852
|
||||
FS[9] C14M FD1S3AX Q FS[9] 1.284 62.425
|
||||
FS[11] C14M FD1S3AX Q FS[11] 1.276 62.433
|
||||
FS[8] C14M FD1S3AX Q FS[8] 1.260 62.449
|
||||
FS[12] C14M FD1S3AX Q FS[12] 1.288 62.525
|
||||
FS[10] C14M FD1S3AX Q FS[10] 1.280 62.533
|
||||
RWSel C14M FD1P3AX Q RWSel 1.276 63.482
|
||||
============================================================================
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------
|
||||
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
|
||||
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
|
||||
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
|
||||
RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771
|
||||
RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771
|
||||
RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
|
||||
RA[6] C14M FD1P3AX Q RA[6] 1.044 33.771
|
||||
RA[7] C14M FD1P3AX Q RA[7] 1.044 33.771
|
||||
RA[8] C14M FD1P3AX Q RA[8] 1.044 33.771
|
||||
RA[9] C14M FD1P3AX Q RA[9] 1.044 33.771
|
||||
===========================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
Dout_0io[0] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[1] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[2] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[3] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[4] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[5] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[6] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[7] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
==================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------
|
||||
RAout_0io[0] C14M OFS1P3DX D RA[0] 34.815 33.707
|
||||
RAout_0io[3] C14M OFS1P3DX D RA[3] 34.815 33.707
|
||||
RAout_0io[1] C14M OFS1P3DX D RA[1] 34.815 33.771
|
||||
RAout_0io[2] C14M OFS1P3DX D RA[2] 34.815 33.771
|
||||
RAout_0io[4] C14M OFS1P3DX D RA[4] 34.815 33.771
|
||||
RAout_0io[5] C14M OFS1P3DX D RA[5] 34.815 33.771
|
||||
RAout_0io[6] C14M OFS1P3DX D RA[6] 34.815 33.771
|
||||
RAout_0io[7] C14M OFS1P3DX D RA[7] 34.815 33.771
|
||||
RAout_0io[8] C14M OFS1P3DX D RA[8] 34.815 33.771
|
||||
RAout_0io[9] C14M OFS1P3DX D RA[9] 34.815 33.771
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -531,30 +538,27 @@ Worst Path Information
|
|||
|
||||
Path information for path number 1:
|
||||
Requested Period: 34.920
|
||||
- Setup time: 0.472
|
||||
- Setup time: 0.106
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.449
|
||||
= Required time: 34.815
|
||||
|
||||
- Propagation time: 2.667
|
||||
- Propagation time: 1.108
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (critical) : 31.782
|
||||
= Slack (critical) : 33.707
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
Ending point: Dout_0io[0] / SP
|
||||
Number of logic level(s): 0
|
||||
Starting point: RA[0] / Q
|
||||
Ending point: RAout_0io[0] / D
|
||||
The start point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
The end point is clocked by C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.350 1.350 r -
|
||||
S[2] Net - - - - 48
|
||||
S_RNII9DO1_2[1] ORCALUT4 B In 0.000 1.350 r -
|
||||
S_RNII9DO1_2[1] ORCALUT4 Z Out 1.317 2.667 r -
|
||||
N_576_i Net - - - - 18
|
||||
Dout_0io[0] OFS1P3DX SP In 0.000 2.667 r -
|
||||
==================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
RA[0] FD1P3AX Q Out 1.108 1.108 r -
|
||||
RA[0] Net - - - - 3
|
||||
RAout_0io[0] OFS1P3DX D In 0.000 1.108 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -568,40 +572,40 @@ Detailed Report for Clock: System
|
|||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
|
||||
=========================================================================================
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
|
||||
===================================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------------
|
||||
RWMask[0] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[1] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[2] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[3] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[4] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[5] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[6] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[7] System FD1P3AX SP N_88 69.369 67.088
|
||||
LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
wb_cyc_stb System FD1P3AX SP N_104 69.369 67.736
|
||||
====================================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0_0[0] 69.369 67.736
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdSetRWBankFFChip13_1_i_0_0[0] 69.369 67.736
|
||||
======================================================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -621,24 +625,24 @@ Path information for path number 1:
|
|||
= Slack (non-critical) : 67.088
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: RWMask[0] / SP
|
||||
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: ram2e_ufm.RWMask[0] / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
|
||||
wb_ack Net - - - - 5
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 A In 0.000 0.000 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 Z Out 1.017 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] Net - - - - 1
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 r -
|
||||
N_88 Net - - - - 8
|
||||
RWMask[0] FD1P3AX SP In 0.000 2.282 r -
|
||||
======================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
|
||||
wb_ack Net - - - - 5
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ORCALUT4 B In 0.000 0.000 r -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ORCALUT4 Z Out 1.017 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0] ORCALUT4 D In 0.000 1.017 r -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0] ORCALUT4 Z Out 1.265 2.282 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_0[0] Net - - - - 8
|
||||
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 r -
|
||||
==================================================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -646,45 +650,47 @@ RWMask[0] FD1P3AX SP In 0.000
|
|||
|
||||
Timing exceptions that could not be applied
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_1200hc-4
|
||||
|
||||
Register bits: 111 of 1280 (9%)
|
||||
Register bits: 122 of 1280 (10%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
I/O cells: 69
|
||||
|
||||
|
||||
Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 48
|
||||
FD1P3AX: 61
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 22
|
||||
FD1S3IX: 4
|
||||
FD1S3AX: 21
|
||||
FD1S3AY: 4
|
||||
FD1S3IX: 6
|
||||
GSR: 1
|
||||
IB: 22
|
||||
IB: 21
|
||||
IFS1P3DX: 1
|
||||
INV: 1
|
||||
OB: 40
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 27
|
||||
OFS1P3BX: 5
|
||||
OFS1P3DX: 21
|
||||
OFS1P3IX: 2
|
||||
ORCALUT4: 221
|
||||
ORCALUT4: 277
|
||||
PFUMX: 3
|
||||
PUR: 1
|
||||
VHI: 2
|
||||
VLO: 2
|
||||
VHI: 3
|
||||
VLO: 3
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 211MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 217MB)
|
||||
|
||||
Process took 0h:00m:06s realtime, 0h:00m:04s cputime
|
||||
# Thu Sep 21 05:34:44 2023
|
||||
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
|
||||
# Thu Dec 28 23:23:26 2023
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ Setup and Hold Report
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:34:48 2023
|
||||
Thu Dec 28 23:23:29 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -38,48 +38,48 @@ BLOCK RESETPATHS
|
|||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
1611 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 58.471ns
|
||||
Passed: The following path meets requirements by 58.937ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS[11] (from C14M_c +)
|
||||
Destination: FF Data in nRWE_0io (to C14M_c +)
|
||||
Source: FF Q S[2] (from C14M_c +)
|
||||
Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +)
|
||||
|
||||
Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels.
|
||||
Delay: 10.827ns (31.6% logic, 68.4% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
|
||||
10.827ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
|
||||
69.930ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
|
||||
0.166ns DIN_SET requirement (totaling 69.764ns) by 58.937ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_3 to nRWE_MGIOL:
|
||||
Data path SLICE_34 to ram2e_ufm/SLICE_47:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_3.CLK to SLICE_3.Q0 SLICE_3 (from C14M_c)
|
||||
ROUTE 19 e 1.234 SLICE_3.Q0 to SLICE_64.A1 FS[11]
|
||||
CTOF_DEL --- 0.495 SLICE_64.A1 to SLICE_64.F1 SLICE_64
|
||||
ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_97.D0 N_577
|
||||
CTOF_DEL --- 0.495 SLICE_97.D0 to SLICE_97.F0 SLICE_97
|
||||
ROUTE 3 e 1.234 SLICE_97.F0 to SLICE_75.D1 N_489
|
||||
CTOF_DEL --- 0.495 SLICE_75.D1 to SLICE_75.F1 SLICE_75
|
||||
ROUTE 3 e 0.480 SLICE_75.F1 to SLICE_75.A0 N_628
|
||||
CTOF_DEL --- 0.495 SLICE_75.A0 to SLICE_75.F0 SLICE_75
|
||||
ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_71.C1 N_640
|
||||
CTOF_DEL --- 0.495 SLICE_71.C1 to SLICE_71.F1 SLICE_71
|
||||
ROUTE 1 e 1.234 SLICE_71.F1 to SLICE_115.A0 un1_nCS61_1_i
|
||||
CTOF_DEL --- 0.495 SLICE_115.A0 to SLICE_115.F0 SLICE_115
|
||||
ROUTE 1 e 1.234 SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
|
||||
REG_DEL --- 0.452 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from C14M_c)
|
||||
ROUTE 50 e 1.234 SLICE_34.Q0 to SLICE_35.A0 S[2]
|
||||
CTOF_DEL --- 0.495 SLICE_35.A0 to SLICE_35.F0 SLICE_35
|
||||
ROUTE 7 e 1.234 SLICE_35.F0 to *m/SLICE_80.D1 N_551
|
||||
CTOF_DEL --- 0.495 *m/SLICE_80.D1 to *m/SLICE_80.F1 ram2e_ufm/SLICE_80
|
||||
ROUTE 8 e 1.234 *m/SLICE_80.F1 to *m/SLICE_98.B1 ram2e_ufm/N_777
|
||||
CTOF_DEL --- 0.495 *m/SLICE_98.B1 to *m/SLICE_98.F1 ram2e_ufm/SLICE_98
|
||||
ROUTE 5 e 1.234 *m/SLICE_98.F1 to *m/SLICE_99.C0 ram2e_ufm/N_781
|
||||
CTOF_DEL --- 0.495 *m/SLICE_99.C0 to *m/SLICE_99.F0 ram2e_ufm/SLICE_99
|
||||
ROUTE 1 e 1.234 *m/SLICE_99.F0 to *m/SLICE_86.C0 ram2e_ufm/wb_adr_7_i_i_1[0]
|
||||
CTOF_DEL --- 0.495 *m/SLICE_86.C0 to *m/SLICE_86.F0 ram2e_ufm/SLICE_86
|
||||
ROUTE 1 e 1.234 *m/SLICE_86.F0 to *m/SLICE_47.C0 ram2e_ufm/wb_adr_7_i_i_4[0]
|
||||
CTOF_DEL --- 0.495 *m/SLICE_47.C0 to *m/SLICE_47.F0 ram2e_ufm/SLICE_47
|
||||
ROUTE 1 e 0.001 *m/SLICE_47.F0 to */SLICE_47.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
|
||||
--------
|
||||
11.306 (30.3% logic, 69.7% route), 7 logic levels.
|
||||
10.827 (31.6% logic, 68.4% route), 7 logic levels.
|
||||
|
||||
Report: 87.268MHz is the maximum frequency for this preference.
|
||||
Report: 90.967MHz is the maximum frequency for this preference.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
|
|
@ -87,7 +87,7 @@ Report Summary
|
|||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 87.268 MHz| 7
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 90.967 MHz| 7
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
|
@ -100,7 +100,7 @@ Clock Domains Analysis
|
|||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 89
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
|
|
@ -110,11 +110,11 @@ Timing summary (Setup):
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:34:49 2023
|
||||
Thu Dec 28 23:23:29 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -139,7 +139,7 @@ BLOCK RESETPATHS
|
|||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
1611 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
|
@ -164,7 +164,7 @@ Passed: The following path meets requirements by 0.447ns
|
|||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from C14M_c)
|
||||
ROUTE 5 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
|
||||
ROUTE 6 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
|
||||
CTOF_DEL --- 0.101 SLICE_0.A1 to SLICE_0.F1 SLICE_0
|
||||
ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 FS_s[0] (to C14M_c)
|
||||
--------
|
||||
|
|
@ -189,7 +189,7 @@ Clock Domains Analysis
|
|||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 89
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
|
|
@ -199,7 +199,7 @@ Timing summary (Hold):
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:17 2023
|
||||
Thu Dec 28 23:23:53 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
|
|
@ -81,7 +81,7 @@ Creating bit map...
|
|||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2E_LCMXO2_1200HC_impl1.bit".
|
||||
Total CPU Time: 4 secs
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 4 secs
|
||||
Peak Memory Usage: 275 MB
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
|||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Thu Sep 21 05:34:38 2023
|
||||
# Written on Thu Dec 28 23:23:22 2023
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
|
|
@ -58,7 +58,7 @@ p:Ain[6]
|
|||
p:Ain[7]
|
||||
p:BA[0]
|
||||
p:BA[1]
|
||||
p:CKE
|
||||
p:CKEout
|
||||
p:DQMH
|
||||
p:DQML
|
||||
p:Din[0]
|
||||
|
|
@ -79,18 +79,18 @@ p:Dout[6]
|
|||
p:Dout[7]
|
||||
p:LED
|
||||
p:PHI1
|
||||
p:RA[0]
|
||||
p:RA[1]
|
||||
p:RA[2]
|
||||
p:RA[3]
|
||||
p:RA[4]
|
||||
p:RA[5]
|
||||
p:RA[6]
|
||||
p:RA[7]
|
||||
p:RA[8]
|
||||
p:RA[9]
|
||||
p:RA[10]
|
||||
p:RA[11]
|
||||
p:RAout[0]
|
||||
p:RAout[1]
|
||||
p:RAout[2]
|
||||
p:RAout[3]
|
||||
p:RAout[4]
|
||||
p:RAout[5]
|
||||
p:RAout[6]
|
||||
p:RAout[7]
|
||||
p:RAout[8]
|
||||
p:RAout[9]
|
||||
p:RAout[10]
|
||||
p:RAout[11]
|
||||
p:RD[0] (bidir end point)
|
||||
p:RD[0] (bidir start point)
|
||||
p:RD[1] (bidir end point)
|
||||
|
|
@ -116,12 +116,12 @@ p:Vout[5]
|
|||
p:Vout[6]
|
||||
p:Vout[7]
|
||||
p:nC07X
|
||||
p:nCAS
|
||||
p:nCS
|
||||
p:nCASout
|
||||
p:nCSout
|
||||
p:nDOE
|
||||
p:nEN80
|
||||
p:nRAS
|
||||
p:nRWE
|
||||
p:nRASout
|
||||
p:nRWEout
|
||||
p:nVOE
|
||||
p:nWE
|
||||
p:nWE80
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ Performance Hardware Data Status: Final Version 34.4.
|
|||
// Package: TQFP100
|
||||
// ncd File: ram2e_lcmxo2_1200hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:35:11 2023
|
||||
// Written on Thu Dec 28 23:23:48 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
|
|
@ -50,82 +50,80 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
|
|||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
Ain[0] C14M R -0.231 M 2.350 4
|
||||
Ain[1] C14M R 1.429 4 0.543 4
|
||||
Ain[2] C14M R 1.518 4 0.412 4
|
||||
Ain[3] C14M R -0.231 M 2.350 4
|
||||
Ain[4] C14M R 0.212 4 1.560 4
|
||||
Ain[5] C14M R 0.742 4 1.110 4
|
||||
Ain[6] C14M R 0.469 4 1.329 4
|
||||
Ain[7] C14M R 1.416 4 0.531 4
|
||||
Din[0] C14M R 8.327 4 1.958 4
|
||||
Din[1] C14M R 5.826 4 2.521 4
|
||||
Din[2] C14M R 6.539 4 2.135 4
|
||||
Din[3] C14M R 5.849 4 2.648 4
|
||||
Din[4] C14M R 7.061 4 2.095 4
|
||||
Din[5] C14M R 6.295 4 2.894 4
|
||||
Din[6] C14M R 4.991 4 2.892 4
|
||||
Din[7] C14M R 6.416 4 2.971 4
|
||||
PHI1 C14M R 1.151 4 4.842 4
|
||||
RD[0] C14M F -0.266 M 3.107 4
|
||||
RD[1] C14M F -0.248 M 3.183 4
|
||||
RD[2] C14M F -0.105 M 2.610 4
|
||||
RD[3] C14M F -0.243 M 3.107 4
|
||||
RD[4] C14M F 0.103 4 2.201 4
|
||||
RD[5] C14M F -0.092 M 2.192 4
|
||||
RD[6] C14M F -0.084 M 1.756 4
|
||||
RD[7] C14M F -0.092 M 2.661 4
|
||||
nC07X C14M R -0.316 M 2.625 4
|
||||
nEN80 C14M R 5.220 4 0.032 M
|
||||
nWE C14M R -0.093 M 2.033 4
|
||||
nWE80 C14M R 1.630 4 0.329 6
|
||||
Ain[0] C14M R 0.163 4 1.694 4
|
||||
Ain[1] C14M R -0.150 M 2.217 4
|
||||
Ain[2] C14M R -0.080 M 2.156 4
|
||||
Ain[3] C14M R 0.466 4 1.338 4
|
||||
Ain[4] C14M R 0.215 4 1.597 4
|
||||
Ain[5] C14M R -0.331 M 2.651 4
|
||||
Ain[6] C14M R 0.065 M 1.882 4
|
||||
Ain[7] C14M R 0.284 4 1.683 4
|
||||
Din[0] C14M R 6.887 4 2.257 4
|
||||
Din[1] C14M R 8.753 4 2.907 4
|
||||
Din[2] C14M R 6.379 4 2.740 4
|
||||
Din[3] C14M R 7.129 4 1.402 4
|
||||
Din[4] C14M R 6.869 4 2.791 4
|
||||
Din[5] C14M R 6.514 4 2.334 4
|
||||
Din[6] C14M R 6.735 4 1.914 4
|
||||
Din[7] C14M R 8.094 4 1.968 4
|
||||
PHI1 C14M R 1.557 4 4.842 4
|
||||
RD[0] C14M R -0.266 M 2.342 4
|
||||
RD[1] C14M R -0.248 M 2.283 4
|
||||
RD[2] C14M R -0.407 M 2.610 4
|
||||
RD[3] C14M R -0.243 M 2.193 4
|
||||
RD[4] C14M R -0.246 M 2.201 4
|
||||
RD[5] C14M R -0.243 M 2.193 4
|
||||
RD[6] C14M R -0.087 M 1.756 4
|
||||
RD[7] C14M R -0.092 M 1.769 4
|
||||
nC07X C14M R -0.320 M 2.703 4
|
||||
nEN80 C14M R 4.607 4 1.925 4
|
||||
nWE C14M R 4.609 4 2.010 4
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
BA[0] C14M R 10.424 4 3.355 M
|
||||
BA[1] C14M R 10.424 4 3.355 M
|
||||
CKE C14M R 10.424 4 3.355 M
|
||||
DQMH C14M R 10.404 4 3.362 M
|
||||
DQML C14M R 10.404 4 3.362 M
|
||||
Dout[0] C14M F 10.750 4 3.634 M
|
||||
Dout[1] C14M F 10.750 4 3.634 M
|
||||
Dout[2] C14M F 10.739 4 3.628 M
|
||||
Dout[3] C14M F 10.750 4 3.634 M
|
||||
Dout[4] C14M F 10.739 4 3.628 M
|
||||
Dout[5] C14M F 10.739 4 3.628 M
|
||||
Dout[6] C14M F 10.750 4 3.634 M
|
||||
Dout[7] C14M F 10.750 4 3.634 M
|
||||
LED C14M R 21.299 4 8.576 M
|
||||
RA[0] C14M R 12.236 4 3.758 M
|
||||
RA[10] C14M R 10.490 4 3.360 M
|
||||
RA[11] C14M R 10.424 4 3.355 M
|
||||
RA[1] C14M R 10.490 4 3.360 M
|
||||
RA[2] C14M R 10.490 4 3.360 M
|
||||
RA[3] C14M R 11.808 4 3.656 M
|
||||
RA[4] C14M R 10.490 4 3.360 M
|
||||
RA[5] C14M R 10.490 4 3.360 M
|
||||
RA[6] C14M R 10.490 4 3.360 M
|
||||
RA[7] C14M R 10.490 4 3.360 M
|
||||
RA[8] C14M R 10.490 4 3.360 M
|
||||
RA[9] C14M R 10.490 4 3.360 M
|
||||
Vout[0] C14M F 11.348 4 3.872 M
|
||||
Vout[1] C14M F 11.434 4 3.871 M
|
||||
Vout[2] C14M F 11.348 4 3.872 M
|
||||
Vout[3] C14M F 11.434 4 3.871 M
|
||||
Vout[4] C14M F 11.348 4 3.872 M
|
||||
Vout[5] C14M F 11.348 4 3.872 M
|
||||
Vout[6] C14M F 11.434 4 3.871 M
|
||||
Vout[7] C14M F 11.434 4 3.871 M
|
||||
nCAS C14M R 10.424 4 3.355 M
|
||||
nCS C14M R 10.424 4 3.355 M
|
||||
nDOE C14M R 14.217 4 4.353 M
|
||||
nRAS C14M R 10.424 4 3.355 M
|
||||
nRWE C14M R 10.424 4 3.355 M
|
||||
BA[0] C14M R 10.424 4 3.355 M
|
||||
BA[1] C14M R 10.424 4 3.355 M
|
||||
CKEout C14M F 10.424 4 3.355 M
|
||||
DQMH C14M R 10.404 4 3.362 M
|
||||
DQML C14M R 10.404 4 3.362 M
|
||||
LED C14M R 22.936 4 8.890 M
|
||||
RAout[0] C14M F 10.490 4 3.360 M
|
||||
RAout[10] C14M F 10.490 4 3.360 M
|
||||
RAout[11] C14M F 10.424 4 3.355 M
|
||||
RAout[1] C14M F 10.490 4 3.360 M
|
||||
RAout[2] C14M F 10.490 4 3.360 M
|
||||
RAout[3] C14M F 10.490 4 3.360 M
|
||||
RAout[4] C14M F 10.490 4 3.360 M
|
||||
RAout[5] C14M F 10.490 4 3.360 M
|
||||
RAout[6] C14M F 10.490 4 3.360 M
|
||||
RAout[7] C14M F 10.490 4 3.360 M
|
||||
RAout[8] C14M F 10.490 4 3.360 M
|
||||
RAout[9] C14M F 10.490 4 3.360 M
|
||||
RD[0] C14M R 13.733 4 3.707 M
|
||||
RD[1] C14M R 13.745 4 3.707 M
|
||||
RD[2] C14M R 14.285 4 3.790 M
|
||||
RD[3] C14M R 13.348 4 3.790 M
|
||||
RD[4] C14M R 14.450 4 3.952 M
|
||||
RD[5] C14M R 14.480 4 3.952 M
|
||||
RD[6] C14M R 14.784 4 3.952 M
|
||||
RD[7] C14M R 14.247 4 3.952 M
|
||||
Vout[0] C14M R 11.348 4 3.872 M
|
||||
Vout[1] C14M R 11.434 4 3.871 M
|
||||
Vout[2] C14M R 11.348 4 3.872 M
|
||||
Vout[3] C14M R 11.434 4 3.871 M
|
||||
Vout[4] C14M R 11.348 4 3.872 M
|
||||
Vout[5] C14M R 11.348 4 3.872 M
|
||||
Vout[6] C14M R 11.434 4 3.871 M
|
||||
Vout[7] C14M R 11.434 4 3.871 M
|
||||
nCASout C14M F 10.424 4 3.355 M
|
||||
nDOE C14M R 13.929 4 4.309 M
|
||||
nRASout C14M F 10.424 4 3.355 M
|
||||
nRWEout C14M F 10.424 4 3.355 M
|
||||
nVOE C14M R 13.926 4 4.281 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with hold speed: 6
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -23,23 +23,23 @@ Target Vendor: LATTICE
|
|||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:34:46
|
||||
Mapped on: 12/28/23 23:23:27
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of registers: 111 out of 1520 (7%)
|
||||
PFU registers: 75 out of 1280 (6%)
|
||||
PIO registers: 36 out of 240 (15%)
|
||||
Number of SLICEs: 120 out of 640 (19%)
|
||||
SLICEs as Logic/ROM: 120 out of 640 (19%)
|
||||
Number of registers: 122 out of 1520 (8%)
|
||||
PFU registers: 93 out of 1280 (7%)
|
||||
PIO registers: 29 out of 240 (12%)
|
||||
Number of SLICEs: 148 out of 640 (23%)
|
||||
SLICEs as Logic/ROM: 148 out of 640 (23%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 9 out of 640 (1%)
|
||||
Number of LUT4s: 239 out of 1280 (19%)
|
||||
Number used as logic LUTs: 221
|
||||
Number of LUT4s: 296 out of 1280 (23%)
|
||||
Number used as logic LUTs: 278
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 70 + 4(JTAG) out of 80 (93%)
|
||||
Number of PIO sites used: 69 + 4(JTAG) out of 80 (91%)
|
||||
Number of block RAMs: 0 out of 7 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
|
|
@ -65,43 +65,48 @@ Mapped on: 09/21/23 05:34:46
|
|||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 1
|
||||
Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
|
||||
Number of Clock Enables: 11
|
||||
Net C14M_c: 89 loads, 73 rising, 16 falling (Driver: PIO C14M )
|
||||
Number of Clock Enables: 14
|
||||
|
||||
Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
|
||||
Net N_576_i: 17 loads, 9 LSLICEs
|
||||
Net LEDEN13: 4 loads, 4 LSLICEs
|
||||
Net nCS61: 1 loads, 1 LSLICEs
|
||||
Net N_225_i: 2 loads, 0 LSLICEs
|
||||
Net N_201_i: 2 loads, 0 LSLICEs
|
||||
Net N_187_i: 11 loads, 11 LSLICEs
|
||||
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
|
||||
Net RC12: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/CmdBitbangMXO2_RNINSM62: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/wb_we_RNO_0: 1 loads, 1 LSLICEs
|
||||
Net N_185_i: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0]: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0]: 1 loads, 1 LSLICEs
|
||||
Net N_126: 6 loads, 6 LSLICEs
|
||||
Net un9_VOEEN_0_a2_0_a3_0_a3: 1 loads, 1 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
|
||||
Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net N_104: 1 loads, 1 LSLICEs
|
||||
Net N_88: 4 loads, 4 LSLICEs
|
||||
Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Number of LSRs: 7
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net BA_0_sqmuxa: 2 loads, 0 LSLICEs
|
||||
Net S[2]: 1 loads, 1 LSLICEs
|
||||
Net N_566_i: 2 loads, 0 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/wb_rst16_i: 1 loads, 1 LSLICEs
|
||||
Net N_1080_0: 1 loads, 1 LSLICEs
|
||||
Net N_1078_0: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 48 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[0]: 30 loads
|
||||
Net FS[12]: 22 loads
|
||||
Net FS[9]: 21 loads
|
||||
Net S[1]: 21 loads
|
||||
Net FS[10]: 20 loads
|
||||
Net FS[11]: 19 loads
|
||||
Net RWSel: 19 loads
|
||||
Net FS[13]: 17 loads
|
||||
Net S[2]: 50 loads
|
||||
Net S[3]: 45 loads
|
||||
Net S[0]: 37 loads
|
||||
Net S[1]: 34 loads
|
||||
Net FS[12]: 24 loads
|
||||
Net FS[11]: 22 loads
|
||||
Net FS[10]: 19 loads
|
||||
Net FS[13]: 19 loads
|
||||
Net FS[9]: 19 loads
|
||||
Net FS[8]: 18 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 1
|
||||
Number of warnings: 3
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
|
|
@ -110,12 +115,18 @@ Mapped on: 09/21/23 05:34:46
|
|||
|
||||
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
|
||||
|
||||
WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(93): Semantic
|
||||
error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
|
||||
"nWE80" does not exist in the design. This preference has been disabled.
|
||||
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
temporarily disable certain features of the device including Power
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
discarded.
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -127,15 +138,10 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| C14M | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| DQMH | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| DQML | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS33 | |
|
||||
|
|
@ -150,44 +156,48 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
| DQMH | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
| DQML | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[9] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[8] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
| RAout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
| RAout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS33 | OUT |
|
||||
| nRWEout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
| nCASout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
| nRASout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| nCS | OUTPUT | LVCMOS33 | OUT |
|
||||
| nCSout | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CKE | OUTPUT | LVCMOS33 | OUT |
|
||||
| CKEout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nVOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
|
@ -209,21 +219,21 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| nDOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
|
@ -233,6 +243,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| Din[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
|
|
@ -241,7 +252,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| Ain[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[6] | INPUT | LVCMOS33 | |
|
||||
|
|
@ -262,8 +272,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| nEN80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI1 | INPUT | LVCMOS33 | IN |
|
||||
|
|
@ -274,68 +282,75 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal Dout_0_.CN was merged into signal C14M_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
|
||||
Block ram2e_ufm/GND undriven or does not drive anything - clipped.
|
||||
Signal CKEout.CN was merged into signal C14M_c
|
||||
Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block Vout_0_.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
Block nCASout.CN was optimized away.
|
||||
Block ram2e_ufm/ufmefb/VCC was optimized away.
|
||||
Block ram2e_ufm/ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
|
|
@ -344,8 +359,9 @@ Block ufmefb/GND was optimized away.
|
|||
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
|
||||
|
||||
Desired WISHBONE clock frequency: 14.4 MHz
|
||||
|
||||
Clock source: C14M_c
|
||||
Reset source: wb_rst
|
||||
Reset source: ram2e_ufm/wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
|
|
@ -357,7 +373,6 @@ Block ufmefb/GND was optimized away.
|
|||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
|
|
@ -384,7 +399,7 @@ Block ufmefb/GND was optimized away.
|
|||
<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
|
||||
---------------
|
||||
|
||||
Instance Name: ufmefb/EFBInst_0
|
||||
Instance Name: ram2e_ufm/ufmefb/EFBInst_0
|
||||
Type: EFB
|
||||
|
||||
|
||||
|
|
@ -392,9 +407,9 @@ Instance Name: ufmefb/EFBInst_0
|
|||
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 1 secs
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 63 MB
|
||||
Peak Memory Usage: 64 MB
|
||||
|
||||
|
||||
|
||||
|
|
@ -402,19 +417,6 @@ Instance Name: ufmefb/EFBInst_0
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ Performance Grade: 4
|
|||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.44
|
||||
|
||||
Thu Sep 21 05:34:59 2023
|
||||
Thu Dec 28 23:23:38 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
|
@ -31,7 +31,7 @@ Pinout by Port Name:
|
|||
| BA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| BA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| CKEout | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQMH | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Din[0] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
|
|
@ -42,28 +42,28 @@ Pinout by Port Name:
|
|||
| Din[5] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 87/0 | LVCMOS33_IN | PT12B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[2] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[4] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[5] | 21/3 | LVCMOS33_OUT | PL9B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[0] | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[2] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[4] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[5] | 21/3 | LVCMOS33_OUT | PL9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| LED | 35/2 | LVCMOS33_OUT | PB9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| PHI1 | 85/0 | LVCMOS33_IN | PT12D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[1] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[2] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[5] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[6] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[7] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
|
|
@ -81,15 +81,14 @@ Pinout by Port Name:
|
|||
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nC07X | 34/2 | LVCMOS33_IN | PB9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCAS | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCS | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCASout | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCSout | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nDOE | 20/3 | LVCMOS33_OUT | PL9A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nEN80 | 82/0 | LVCMOS33_IN | PT15C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRAS | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRASout | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWEout | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nVOE | 10/3 | LVCMOS33_OUT | PL4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nWE | 29/2 | LVCMOS33_IN | PB6A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nWE80 | 83/0 | LVCMOS33_IN | PT15B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
|
|
@ -153,33 +152,33 @@ Vccio by Bank:
|
|||
| 47/2 | unused, PULL:DOWN | | | PB18D | | | |
|
||||
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
|
||||
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | nRWE | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
|
||||
| 52/1 | nCAS | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
|
||||
| 53/1 | CKE | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
|
||||
| 54/1 | nRAS | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
|
||||
| 57/1 | nCS | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
|
||||
| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
|
||||
| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
|
||||
| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
|
||||
| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
|
||||
| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
|
||||
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
|
||||
| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
|
||||
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
|
||||
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
|
||||
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
|
||||
| 67/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
|
||||
| 68/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
|
||||
| 69/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
|
||||
| 70/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
|
||||
| 71/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
|
||||
| 74/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
|
||||
| 75/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
|
||||
| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
|
||||
| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
|
||||
| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
|
||||
| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
|
||||
| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
|
||||
| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
|
||||
| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
|
||||
| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
|
||||
| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
|
||||
| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
|
||||
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
|
||||
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT16C | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
|
||||
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT15C | JTAGENB | | |
|
||||
| 83/0 | nWE80 | LOCATED | LVCMOS33_IN | PT15B | | | |
|
||||
| 83/0 | unused, PULL:DOWN | | | PT15B | | | |
|
||||
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT15A | | | |
|
||||
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT12D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT12C | SCL/PCLKT0_0 | | |
|
||||
|
|
@ -250,7 +249,7 @@ LOCATE COMP "Ain[7]" SITE "8";
|
|||
LOCATE COMP "BA[0]" SITE "58";
|
||||
LOCATE COMP "BA[1]" SITE "60";
|
||||
LOCATE COMP "C14M" SITE "62";
|
||||
LOCATE COMP "CKE" SITE "53";
|
||||
LOCATE COMP "CKEout" SITE "53";
|
||||
LOCATE COMP "DQMH" SITE "49";
|
||||
LOCATE COMP "DQML" SITE "48";
|
||||
LOCATE COMP "Din[0]" SITE "96";
|
||||
|
|
@ -271,18 +270,18 @@ LOCATE COMP "Dout[6]" SITE "31";
|
|||
LOCATE COMP "Dout[7]" SITE "32";
|
||||
LOCATE COMP "LED" SITE "35";
|
||||
LOCATE COMP "PHI1" SITE "85";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "68";
|
||||
LOCATE COMP "RA[2]" SITE "70";
|
||||
LOCATE COMP "RA[3]" SITE "74";
|
||||
LOCATE COMP "RA[4]" SITE "75";
|
||||
LOCATE COMP "RA[5]" SITE "71";
|
||||
LOCATE COMP "RA[6]" SITE "69";
|
||||
LOCATE COMP "RA[7]" SITE "67";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RAout[0]" SITE "66";
|
||||
LOCATE COMP "RAout[10]" SITE "64";
|
||||
LOCATE COMP "RAout[11]" SITE "59";
|
||||
LOCATE COMP "RAout[1]" SITE "68";
|
||||
LOCATE COMP "RAout[2]" SITE "70";
|
||||
LOCATE COMP "RAout[3]" SITE "74";
|
||||
LOCATE COMP "RAout[4]" SITE "75";
|
||||
LOCATE COMP "RAout[5]" SITE "71";
|
||||
LOCATE COMP "RAout[6]" SITE "69";
|
||||
LOCATE COMP "RAout[7]" SITE "67";
|
||||
LOCATE COMP "RAout[8]" SITE "65";
|
||||
LOCATE COMP "RAout[9]" SITE "63";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
|
|
@ -300,15 +299,14 @@ LOCATE COMP "Vout[5]" SITE "16";
|
|||
LOCATE COMP "Vout[6]" SITE "14";
|
||||
LOCATE COMP "Vout[7]" SITE "12";
|
||||
LOCATE COMP "nC07X" SITE "34";
|
||||
LOCATE COMP "nCAS" SITE "52";
|
||||
LOCATE COMP "nCS" SITE "57";
|
||||
LOCATE COMP "nCASout" SITE "52";
|
||||
LOCATE COMP "nCSout" SITE "57";
|
||||
LOCATE COMP "nDOE" SITE "20";
|
||||
LOCATE COMP "nEN80" SITE "82";
|
||||
LOCATE COMP "nRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "51";
|
||||
LOCATE COMP "nRASout" SITE "54";
|
||||
LOCATE COMP "nRWEout" SITE "51";
|
||||
LOCATE COMP "nVOE" SITE "10";
|
||||
LOCATE COMP "nWE" SITE "29";
|
||||
LOCATE COMP "nWE80" SITE "83";
|
||||
|
||||
|
||||
|
||||
|
|
@ -320,7 +318,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:04 2023
|
||||
Thu Dec 28 23:23:42 2023
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:34:51 2023
|
||||
Thu Dec 28 23:23:31 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_1200HC_impl1.p2t
|
||||
RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir
|
||||
|
|
@ -26,17 +26,17 @@ Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
|
|||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 57.121 0 0.333 0 15 Completed
|
||||
5_1 * 0 58.069 0 0.342 0 13 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 15 secs
|
||||
Total (real) run time for 1-seed: 13 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2E_LCMXO2_1200HC_impl1_map.ncd"
|
||||
Thu Sep 21 05:34:51 2023
|
||||
Thu Dec 28 23:23:31 2023
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
|
|
@ -63,28 +63,28 @@ Ignore Preference Error(s): True
|
|||
|
||||
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
|
||||
|
||||
PIO (prelim) 70+4(JTAG)/108 69% used
|
||||
70+4(JTAG)/80 93% bonded
|
||||
IOLOGIC 36/108 33% used
|
||||
PIO (prelim) 69+4(JTAG)/108 68% used
|
||||
69+4(JTAG)/80 91% bonded
|
||||
IOLOGIC 29/108 26% used
|
||||
|
||||
SLICE 120/640 18% used
|
||||
SLICE 148/640 23% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 395
|
||||
Number of Connections: 1126
|
||||
Number of Signals: 459
|
||||
Number of Connections: 1330
|
||||
|
||||
Pin Constraint Summary:
|
||||
70 out of 70 pins locked (100% locked).
|
||||
69 out of 69 pins locked (100% locked).
|
||||
|
||||
The following 1 signal is selected to use the primary clock routing resources:
|
||||
C14M_c (driver: C14M, clk load #: 84)
|
||||
C14M_c (driver: C14M, clk load #: 89)
|
||||
|
||||
WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
N_576_i (driver: SLICE_20, clk load #: 0, sr load #: 0, ce load #: 17)
|
||||
N_187_i (driver: ram2e_ufm/SLICE_130, clk load #: 0, sr load #: 0, ce load #: 11)
|
||||
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
|
|
@ -92,14 +92,14 @@ Starting Placer Phase 0.
|
|||
Finished Placer Phase 0. REAL time: 2 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
..................
|
||||
Placer score = 78271.
|
||||
Finished Placer Phase 1. REAL time: 8 secs
|
||||
....................
|
||||
Placer score = 82860.
|
||||
Finished Placer Phase 1. REAL time: 7 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 77117
|
||||
Finished Placer Phase 2. REAL time: 8 secs
|
||||
Placer score = 82610
|
||||
Finished Placer Phase 2. REAL time: 7 secs
|
||||
|
||||
|
||||
|
||||
|
|
@ -113,8 +113,8 @@ Global Clock Resources:
|
|||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 84
|
||||
SECONDARY "N_576_i" from F1 on comp "SLICE_20" on site "R7C12C", clk load = 0, ce load = 17, sr load = 0
|
||||
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 89
|
||||
SECONDARY "N_187_i" from F1 on comp "ram2e_ufm/SLICE_130" on site "R7C12C", clk load = 0, ce load = 11, sr load = 0
|
||||
|
||||
PRIMARY : 1 out of 8 (12%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
|
@ -126,32 +126,32 @@ Edge Clocks:
|
|||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
70 + 4(JTAG) out of 108 (68.5%) PIO sites used.
|
||||
70 + 4(JTAG) out of 80 (92.5%) bonded PIO sites used.
|
||||
Number of PIO comps: 70; differential: 0.
|
||||
69 + 4(JTAG) out of 108 (67.6%) PIO sites used.
|
||||
69 + 4(JTAG) out of 80 (91.3%) bonded PIO sites used.
|
||||
Number of PIO comps: 69; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 12 / 19 ( 63%) | 3.3V | - |
|
||||
| 0 | 11 / 19 ( 57%) | 3.3V | - |
|
||||
| 1 | 20 / 21 ( 95%) | 3.3V | - |
|
||||
| 2 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
| 3 | 20 / 20 (100%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 7 secs
|
||||
Total placer CPU time: 6 secs
|
||||
|
||||
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1126 unrouted.
|
||||
0 connections routed; 1330 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
Completed router resource preassignment. Real time: 13 secs
|
||||
Completed router resource preassignment. Real time: 12 secs
|
||||
|
||||
Start NBR router at 05:35:04 09/21/23
|
||||
Start NBR router at 23:23:43 12/28/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
|
|
@ -166,32 +166,32 @@ Note: NBR uses a different method to calculate timing slacks. The
|
|||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 05:35:05 09/21/23
|
||||
Start NBR special constraint process at 23:23:43 12/28/23
|
||||
|
||||
Start NBR section for initial routing at 05:35:05 09/21/23
|
||||
Start NBR section for initial routing at 23:23:43 12/28/23
|
||||
Level 4, iteration 1
|
||||
13(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.121ns/0.000ns; real time: 14 secs
|
||||
19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 58.075ns/0.000ns; real time: 12 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 05:35:05 09/21/23
|
||||
Start NBR section for normal routing at 23:23:43 12/28/23
|
||||
Level 4, iteration 1
|
||||
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.121ns/0.000ns; real time: 14 secs
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 58.069ns/0.000ns; real time: 12 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.121ns/0.000ns; real time: 14 secs
|
||||
Estimated worst slack/total negative slack<setup>: 58.069ns/0.000ns; real time: 12 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 05:35:05 09/21/23
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 23:23:43 12/28/23
|
||||
|
||||
Start NBR section for re-routing at 05:35:05 09/21/23
|
||||
Start NBR section for re-routing at 23:23:43 12/28/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.121ns/0.000ns; real time: 14 secs
|
||||
Estimated worst slack/total negative slack<setup>: 58.069ns/0.000ns; real time: 12 secs
|
||||
|
||||
Start NBR section for post-routing at 05:35:05 09/21/23
|
||||
Start NBR section for post-routing at 23:23:43 12/28/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
|
|
@ -199,17 +199,17 @@ NBR Summary
|
|||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 57.121ns
|
||||
Estimated worst slack<setup> : 58.069ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 14 secs
|
||||
Total REAL time: 15 secs
|
||||
Total CPU time 12 secs
|
||||
Total REAL time: 13 secs
|
||||
Completely routed.
|
||||
End of route. 1126 routed (100.00%); 0 unrouted.
|
||||
End of route. 1330 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
|
|
@ -223,14 +223,14 @@ All signals are completely routed.
|
|||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 57.121
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 58.069
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.333
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.342
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 15 secs
|
||||
Total REAL time to completion: 15 secs
|
||||
Total CPU time to completion: 12 secs
|
||||
Total REAL time to completion: 13 secs
|
||||
|
||||
par done!
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
|||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Thu Sep 21 05:34:37 2023
|
||||
# Written on Thu Dec 28 23:23:22 2023
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
|
||||
|
|
@ -33,7 +33,7 @@ Clock Summary
|
|||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
----------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 122
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
========================================================================================
|
||||
|
|
@ -45,7 +45,7 @@ Clock Load Summary
|
|||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
----------------------------------------------------------------------------------------
|
||||
C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv)
|
||||
C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
========================================================================================
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@
|
|||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/09/21 05:35:26</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/12/28 23:24:01</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
# Thu Dec 28 23:23:19 2023
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
|
@ -57,45 +57,52 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
|
|||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
|
||||
Compiler output is up to date. No re-compile necessary
|
||||
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v changed - recompiling
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
|
||||
Running optimization stage 1 on VLO .......
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
|
||||
Running optimization stage 1 on EFB .......
|
||||
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
|
||||
Running optimization stage 1 on REFB .......
|
||||
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
|
||||
Running optimization stage 1 on RAM2E_UFM .......
|
||||
Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
|
||||
Running optimization stage 1 on RAM2E .......
|
||||
Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
|
||||
Running optimization stage 2 on RAM2E .......
|
||||
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
|
||||
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
|
||||
Running optimization stage 2 on RAM2E_UFM .......
|
||||
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
|
||||
Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on REFB .......
|
||||
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on EFB .......
|
||||
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on VLO .......
|
||||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on VHI .......
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 97MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
# Thu Dec 28 23:23:19 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
|
@ -116,13 +123,14 @@ Implementation : impl1
|
|||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\layer0.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
# Thu Dec 28 23:23:20 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
|
@ -132,12 +140,12 @@ For a summary of runtime and memory usage for all design units, please see file:
|
|||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 31MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
# Thu Dec 28 23:23:20 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
|
@ -160,15 +168,15 @@ Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug
|
|||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:36 2023
|
||||
# Thu Dec 28 23:23:21 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:36 2023
|
||||
# Thu Dec 28 23:23:21 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
|
@ -190,7 +198,7 @@ Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built
|
|||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
|
||||
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 141MB)
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
|
||||
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
|
||||
|
|
@ -199,10 +207,10 @@ See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2
|
|||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
|
||||
|
|
@ -210,46 +218,45 @@ Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00
|
|||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
|
||||
|
||||
@N: FX493 |Applying initial value "0" on instance PHI1reg.
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance DOEEN.
|
||||
@N: FX493 |Applying initial value "0" on instance RWSel.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "1" on instance DQMH.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
|
||||
@N: FX493 |Applying initial value "0" on instance PHI1r.
|
||||
@N: FX493 |Applying initial value "0" on instance RWSel.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWE.
|
||||
@N: FX493 |Applying initial value "0" on instance LEDEN.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance DQMH.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance DQML.
|
||||
@N: FX493 |Applying initial value "0" on instance CKE.
|
||||
@N: FX493 |Applying initial value "1" on instance nCS.
|
||||
@N: FX493 |Applying initial value "1" on instance nRAS.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
@N: FX493 |Applying initial value "1" on instance CKE.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWE.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWEout.
|
||||
@N: FX493 |Applying initial value "1" on instance nCAS.
|
||||
@N: FX493 |Applying initial value "1" on instance nCASout.
|
||||
@N: FX493 |Applying initial value "1" on instance nRAS.
|
||||
@N: FX493 |Applying initial value "1" on instance nRASout.
|
||||
|
||||
Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 182MB)
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
|
||||
|
|
@ -259,7 +266,7 @@ Clock Summary
|
|||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
----------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 122
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
========================================================================================
|
||||
|
|
@ -272,7 +279,7 @@ Clock Load Summary
|
|||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
----------------------------------------------------------------------------------------
|
||||
C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv)
|
||||
C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
========================================================================================
|
||||
|
|
@ -289,14 +296,14 @@ For details review file gcc_ICG_report.rpt
|
|||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
|
||||
1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 111 nCAS
|
||||
@KP:ckid0_0 C14M port 122 nRAS
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
|
@ -308,7 +315,7 @@ Finished Pre Mapping Phase.
|
|||
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
|
@ -317,11 +324,11 @@ Pre-mapping successful!
|
|||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
|
||||
|
||||
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
|
||||
# Thu Sep 21 05:34:38 2023
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Dec 28 23:23:23 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:38 2023
|
||||
# Thu Dec 28 23:23:23 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
|
@ -359,78 +366,78 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
|||
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 179MB peak: 179MB)
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
|
||||
|
||||
@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
|
||||
@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
|
||||
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
None Found
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:02s 29.35ns 222 / 111
|
||||
1 0h:00m:01s 33.71ns 284 / 122
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
|
||||
|
||||
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing report written on Thu Sep 21 05:34:44 2023
|
||||
# Timing report written on Thu Dec 28 23:23:26 2023
|
||||
#
|
||||
|
||||
|
||||
|
|
@ -450,12 +457,12 @@ Performance Summary
|
|||
*******************
|
||||
|
||||
|
||||
Worst slack in design: 31.782
|
||||
Worst slack in design: 33.707
|
||||
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 131.4 MHz 69.841 7.610 31.782 declared default_clkgroup
|
||||
C14M 14.3 MHz 128.0 MHz 69.841 7.813 33.707 declared default_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
===================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
|
@ -473,7 +480,7 @@ Starting Ending | constraint slack | constraint slack | constraint sl
|
|||
----------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 62.231 | No paths - | 34.920 31.782 | No paths -
|
||||
C14M C14M | 69.841 62.028 | No paths - | 34.920 33.707 | No paths -
|
||||
==========================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
|
@ -496,41 +503,41 @@ Detailed Report for Clock: C14M
|
|||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.350 31.782
|
||||
S[3] C14M FD1S3AX Q S[3] 1.350 31.782
|
||||
S[0] C14M FD1S3AX Q S[0] 1.312 31.820
|
||||
S[1] C14M FD1S3AX Q S[1] 1.280 31.852
|
||||
FS[9] C14M FD1S3AX Q FS[9] 1.284 62.425
|
||||
FS[11] C14M FD1S3AX Q FS[11] 1.276 62.433
|
||||
FS[8] C14M FD1S3AX Q FS[8] 1.260 62.449
|
||||
FS[12] C14M FD1S3AX Q FS[12] 1.288 62.525
|
||||
FS[10] C14M FD1S3AX Q FS[10] 1.280 62.533
|
||||
RWSel C14M FD1P3AX Q RWSel 1.276 63.482
|
||||
============================================================================
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------
|
||||
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
|
||||
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
|
||||
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
|
||||
RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771
|
||||
RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771
|
||||
RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
|
||||
RA[6] C14M FD1P3AX Q RA[6] 1.044 33.771
|
||||
RA[7] C14M FD1P3AX Q RA[7] 1.044 33.771
|
||||
RA[8] C14M FD1P3AX Q RA[8] 1.044 33.771
|
||||
RA[9] C14M FD1P3AX Q RA[9] 1.044 33.771
|
||||
===========================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
Dout_0io[0] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[1] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[2] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[3] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[4] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[5] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[6] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[7] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
==================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------
|
||||
RAout_0io[0] C14M OFS1P3DX D RA[0] 34.815 33.707
|
||||
RAout_0io[3] C14M OFS1P3DX D RA[3] 34.815 33.707
|
||||
RAout_0io[1] C14M OFS1P3DX D RA[1] 34.815 33.771
|
||||
RAout_0io[2] C14M OFS1P3DX D RA[2] 34.815 33.771
|
||||
RAout_0io[4] C14M OFS1P3DX D RA[4] 34.815 33.771
|
||||
RAout_0io[5] C14M OFS1P3DX D RA[5] 34.815 33.771
|
||||
RAout_0io[6] C14M OFS1P3DX D RA[6] 34.815 33.771
|
||||
RAout_0io[7] C14M OFS1P3DX D RA[7] 34.815 33.771
|
||||
RAout_0io[8] C14M OFS1P3DX D RA[8] 34.815 33.771
|
||||
RAout_0io[9] C14M OFS1P3DX D RA[9] 34.815 33.771
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -540,30 +547,27 @@ Worst Path Information
|
|||
|
||||
Path information for path number 1:
|
||||
Requested Period: 34.920
|
||||
- Setup time: 0.472
|
||||
- Setup time: 0.106
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.449
|
||||
= Required time: 34.815
|
||||
|
||||
- Propagation time: 2.667
|
||||
- Propagation time: 1.108
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (critical) : 31.782
|
||||
= Slack (critical) : 33.707
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
Ending point: Dout_0io[0] / SP
|
||||
Number of logic level(s): 0
|
||||
Starting point: RA[0] / Q
|
||||
Ending point: RAout_0io[0] / D
|
||||
The start point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
The end point is clocked by C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.350 1.350 r -
|
||||
S[2] Net - - - - 48
|
||||
S_RNII9DO1_2[1] ORCALUT4 B In 0.000 1.350 r -
|
||||
S_RNII9DO1_2[1] ORCALUT4 Z Out 1.317 2.667 r -
|
||||
N_576_i Net - - - - 18
|
||||
Dout_0io[0] OFS1P3DX SP In 0.000 2.667 r -
|
||||
==================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
RA[0] FD1P3AX Q Out 1.108 1.108 r -
|
||||
RA[0] Net - - - - 3
|
||||
RAout_0io[0] OFS1P3DX D In 0.000 1.108 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -577,40 +581,40 @@ Detailed Report for Clock: System
|
|||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
|
||||
=========================================================================================
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
|
||||
===================================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------------
|
||||
RWMask[0] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[1] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[2] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[3] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[4] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[5] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[6] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[7] System FD1P3AX SP N_88 69.369 67.088
|
||||
LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
wb_cyc_stb System FD1P3AX SP N_104 69.369 67.736
|
||||
====================================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0_0[0] 69.369 67.736
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdSetRWBankFFChip13_1_i_0_0[0] 69.369 67.736
|
||||
======================================================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -630,24 +634,24 @@ Path information for path number 1:
|
|||
= Slack (non-critical) : 67.088
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: RWMask[0] / SP
|
||||
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: ram2e_ufm.RWMask[0] / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
|
||||
wb_ack Net - - - - 5
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 A In 0.000 0.000 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 Z Out 1.017 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] Net - - - - 1
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 r -
|
||||
N_88 Net - - - - 8
|
||||
RWMask[0] FD1P3AX SP In 0.000 2.282 r -
|
||||
======================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
|
||||
wb_ack Net - - - - 5
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ORCALUT4 B In 0.000 0.000 r -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ORCALUT4 Z Out 1.017 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0] ORCALUT4 D In 0.000 1.017 r -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0] ORCALUT4 Z Out 1.265 2.282 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_0[0] Net - - - - 8
|
||||
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 r -
|
||||
==================================================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -655,46 +659,48 @@ RWMask[0] FD1P3AX SP In 0.000
|
|||
|
||||
Timing exceptions that could not be applied
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_1200hc-4
|
||||
|
||||
Register bits: 111 of 1280 (9%)
|
||||
Register bits: 122 of 1280 (10%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
I/O cells: 69
|
||||
|
||||
|
||||
Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 48
|
||||
FD1P3AX: 61
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 22
|
||||
FD1S3IX: 4
|
||||
FD1S3AX: 21
|
||||
FD1S3AY: 4
|
||||
FD1S3IX: 6
|
||||
GSR: 1
|
||||
IB: 22
|
||||
IB: 21
|
||||
IFS1P3DX: 1
|
||||
INV: 1
|
||||
OB: 40
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 27
|
||||
OFS1P3BX: 5
|
||||
OFS1P3DX: 21
|
||||
OFS1P3IX: 2
|
||||
ORCALUT4: 221
|
||||
ORCALUT4: 277
|
||||
PFUMX: 3
|
||||
PUR: 1
|
||||
VHI: 2
|
||||
VLO: 2
|
||||
VHI: 3
|
||||
VLO: 3
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 211MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 217MB)
|
||||
|
||||
Process took 0h:00m:06s realtime, 0h:00m:04s cputime
|
||||
# Thu Sep 21 05:34:44 2023
|
||||
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
|
||||
# Thu Dec 28 23:23:26 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ Setup and Hold Report
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:34:48 2023
|
||||
Thu Dec 28 23:23:29 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -41,8 +41,8 @@ Report level: verbose report, limited to 1 item per preference
|
|||
|
||||
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1491 items scored, 0 timing errors detected.
|
||||
Report: 87.268MHz is the maximum frequency for this preference.
|
||||
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1611 items scored, 0 timing errors detected.
|
||||
Report: 90.967MHz is the maximum frequency for this preference.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
|
|
@ -52,48 +52,48 @@ BLOCK RESETPATHS
|
|||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
1611 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 58.471ns
|
||||
Passed: The following path meets requirements by 58.937ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS[11] (from C14M_c +)
|
||||
Destination: FF Data in nRWE_0io (to C14M_c +)
|
||||
Source: FF Q S[2] (from C14M_c +)
|
||||
Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +)
|
||||
|
||||
Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels.
|
||||
Delay: 10.827ns (31.6% logic, 68.4% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
|
||||
10.827ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
|
||||
69.930ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
|
||||
0.166ns DIN_SET requirement (totaling 69.764ns) by 58.937ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_3 to nRWE_MGIOL:
|
||||
Data path SLICE_34 to ram2e_ufm/SLICE_47:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_3.CLK to SLICE_3.Q0 SLICE_3 (from C14M_c)
|
||||
ROUTE 19 e 1.234 SLICE_3.Q0 to SLICE_64.A1 FS[11]
|
||||
CTOF_DEL --- 0.495 SLICE_64.A1 to SLICE_64.F1 SLICE_64
|
||||
ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_97.D0 N_577
|
||||
CTOF_DEL --- 0.495 SLICE_97.D0 to SLICE_97.F0 SLICE_97
|
||||
ROUTE 3 e 1.234 SLICE_97.F0 to SLICE_75.D1 N_489
|
||||
CTOF_DEL --- 0.495 SLICE_75.D1 to SLICE_75.F1 SLICE_75
|
||||
ROUTE 3 e 0.480 SLICE_75.F1 to SLICE_75.A0 N_628
|
||||
CTOF_DEL --- 0.495 SLICE_75.A0 to SLICE_75.F0 SLICE_75
|
||||
ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_71.C1 N_640
|
||||
CTOF_DEL --- 0.495 SLICE_71.C1 to SLICE_71.F1 SLICE_71
|
||||
ROUTE 1 e 1.234 SLICE_71.F1 to SLICE_115.A0 un1_nCS61_1_i
|
||||
CTOF_DEL --- 0.495 SLICE_115.A0 to SLICE_115.F0 SLICE_115
|
||||
ROUTE 1 e 1.234 SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
|
||||
REG_DEL --- 0.452 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from C14M_c)
|
||||
ROUTE 50 e 1.234 SLICE_34.Q0 to SLICE_35.A0 S[2]
|
||||
CTOF_DEL --- 0.495 SLICE_35.A0 to SLICE_35.F0 SLICE_35
|
||||
ROUTE 7 e 1.234 SLICE_35.F0 to *m/SLICE_80.D1 N_551
|
||||
CTOF_DEL --- 0.495 *m/SLICE_80.D1 to *m/SLICE_80.F1 ram2e_ufm/SLICE_80
|
||||
ROUTE 8 e 1.234 *m/SLICE_80.F1 to *m/SLICE_98.B1 ram2e_ufm/N_777
|
||||
CTOF_DEL --- 0.495 *m/SLICE_98.B1 to *m/SLICE_98.F1 ram2e_ufm/SLICE_98
|
||||
ROUTE 5 e 1.234 *m/SLICE_98.F1 to *m/SLICE_99.C0 ram2e_ufm/N_781
|
||||
CTOF_DEL --- 0.495 *m/SLICE_99.C0 to *m/SLICE_99.F0 ram2e_ufm/SLICE_99
|
||||
ROUTE 1 e 1.234 *m/SLICE_99.F0 to *m/SLICE_86.C0 ram2e_ufm/wb_adr_7_i_i_1[0]
|
||||
CTOF_DEL --- 0.495 *m/SLICE_86.C0 to *m/SLICE_86.F0 ram2e_ufm/SLICE_86
|
||||
ROUTE 1 e 1.234 *m/SLICE_86.F0 to *m/SLICE_47.C0 ram2e_ufm/wb_adr_7_i_i_4[0]
|
||||
CTOF_DEL --- 0.495 *m/SLICE_47.C0 to *m/SLICE_47.F0 ram2e_ufm/SLICE_47
|
||||
ROUTE 1 e 0.001 *m/SLICE_47.F0 to */SLICE_47.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
|
||||
--------
|
||||
11.306 (30.3% logic, 69.7% route), 7 logic levels.
|
||||
10.827 (31.6% logic, 68.4% route), 7 logic levels.
|
||||
|
||||
Report: 87.268MHz is the maximum frequency for this preference.
|
||||
Report: 90.967MHz is the maximum frequency for this preference.
|
||||
|
||||
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
|
|
@ -101,7 +101,7 @@ Report: 87.268MHz is the maximum frequency for this preference.
|
|||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 87.268 MHz| 7
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 90.967 MHz| 7
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
|
@ -114,7 +114,7 @@ All preferences were met.
|
|||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 89
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
|
|
@ -124,11 +124,11 @@ Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:34:49 2023
|
||||
Thu Dec 28 23:23:29 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -147,7 +147,7 @@ Report level: verbose report, limited to 1 item per preference
|
|||
|
||||
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1491 items scored, 0 timing errors detected.
|
||||
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1611 items scored, 0 timing errors detected.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
|
|
@ -157,7 +157,7 @@ BLOCK RESETPATHS
|
|||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
1611 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
|
@ -182,7 +182,7 @@ Passed: The following path meets requirements by 0.447ns
|
|||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from C14M_c)
|
||||
ROUTE 5 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
|
||||
ROUTE 6 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
|
||||
CTOF_DEL --- 0.101 SLICE_0.A1 to SLICE_0.F1 SLICE_0
|
||||
ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 FS_s[0] (to C14M_c)
|
||||
--------
|
||||
|
|
@ -207,7 +207,7 @@ All preferences were met.
|
|||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 89
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
|
|
@ -217,7 +217,7 @@ Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
|
|
@ -29,7 +29,7 @@ Performance Hardware Data Status: Final Version 34.4.
|
|||
// Package: TQFP100
|
||||
// ncd File: ram2e_lcmxo2_1200hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:35:11 2023
|
||||
// Written on Thu Dec 28 23:23:48 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
|
|
@ -41,80 +41,78 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
|
|||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
Ain[0] C14M R -0.231 M 2.350 4
|
||||
Ain[1] C14M R 1.429 4 0.543 4
|
||||
Ain[2] C14M R 1.518 4 0.412 4
|
||||
Ain[3] C14M R -0.231 M 2.350 4
|
||||
Ain[4] C14M R 0.212 4 1.560 4
|
||||
Ain[5] C14M R 0.742 4 1.110 4
|
||||
Ain[6] C14M R 0.469 4 1.329 4
|
||||
Ain[7] C14M R 1.416 4 0.531 4
|
||||
Din[0] C14M R 8.327 4 1.958 4
|
||||
Din[1] C14M R 5.826 4 2.521 4
|
||||
Din[2] C14M R 6.539 4 2.135 4
|
||||
Din[3] C14M R 5.849 4 2.648 4
|
||||
Din[4] C14M R 7.061 4 2.095 4
|
||||
Din[5] C14M R 6.295 4 2.894 4
|
||||
Din[6] C14M R 4.991 4 2.892 4
|
||||
Din[7] C14M R 6.416 4 2.971 4
|
||||
PHI1 C14M R 1.151 4 4.842 4
|
||||
RD[0] C14M F -0.266 M 3.107 4
|
||||
RD[1] C14M F -0.248 M 3.183 4
|
||||
RD[2] C14M F -0.105 M 2.610 4
|
||||
RD[3] C14M F -0.243 M 3.107 4
|
||||
RD[4] C14M F 0.103 4 2.201 4
|
||||
RD[5] C14M F -0.092 M 2.192 4
|
||||
RD[6] C14M F -0.084 M 1.756 4
|
||||
RD[7] C14M F -0.092 M 2.661 4
|
||||
nC07X C14M R -0.316 M 2.625 4
|
||||
nEN80 C14M R 5.220 4 0.032 M
|
||||
nWE C14M R -0.093 M 2.033 4
|
||||
nWE80 C14M R 1.630 4 0.329 6
|
||||
Ain[0] C14M R 0.163 4 1.694 4
|
||||
Ain[1] C14M R -0.150 M 2.217 4
|
||||
Ain[2] C14M R -0.080 M 2.156 4
|
||||
Ain[3] C14M R 0.466 4 1.338 4
|
||||
Ain[4] C14M R 0.215 4 1.597 4
|
||||
Ain[5] C14M R -0.331 M 2.651 4
|
||||
Ain[6] C14M R 0.065 M 1.882 4
|
||||
Ain[7] C14M R 0.284 4 1.683 4
|
||||
Din[0] C14M R 6.887 4 2.257 4
|
||||
Din[1] C14M R 8.753 4 2.907 4
|
||||
Din[2] C14M R 6.379 4 2.740 4
|
||||
Din[3] C14M R 7.129 4 1.402 4
|
||||
Din[4] C14M R 6.869 4 2.791 4
|
||||
Din[5] C14M R 6.514 4 2.334 4
|
||||
Din[6] C14M R 6.735 4 1.914 4
|
||||
Din[7] C14M R 8.094 4 1.968 4
|
||||
PHI1 C14M R 1.557 4 4.842 4
|
||||
RD[0] C14M R -0.266 M 2.342 4
|
||||
RD[1] C14M R -0.248 M 2.283 4
|
||||
RD[2] C14M R -0.407 M 2.610 4
|
||||
RD[3] C14M R -0.243 M 2.193 4
|
||||
RD[4] C14M R -0.246 M 2.201 4
|
||||
RD[5] C14M R -0.243 M 2.193 4
|
||||
RD[6] C14M R -0.087 M 1.756 4
|
||||
RD[7] C14M R -0.092 M 1.769 4
|
||||
nC07X C14M R -0.320 M 2.703 4
|
||||
nEN80 C14M R 4.607 4 1.925 4
|
||||
nWE C14M R 4.609 4 2.010 4
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
BA[0] C14M R 10.424 4 3.355 M
|
||||
BA[1] C14M R 10.424 4 3.355 M
|
||||
CKE C14M R 10.424 4 3.355 M
|
||||
DQMH C14M R 10.404 4 3.362 M
|
||||
DQML C14M R 10.404 4 3.362 M
|
||||
Dout[0] C14M F 10.750 4 3.634 M
|
||||
Dout[1] C14M F 10.750 4 3.634 M
|
||||
Dout[2] C14M F 10.739 4 3.628 M
|
||||
Dout[3] C14M F 10.750 4 3.634 M
|
||||
Dout[4] C14M F 10.739 4 3.628 M
|
||||
Dout[5] C14M F 10.739 4 3.628 M
|
||||
Dout[6] C14M F 10.750 4 3.634 M
|
||||
Dout[7] C14M F 10.750 4 3.634 M
|
||||
LED C14M R 21.299 4 8.576 M
|
||||
RA[0] C14M R 12.236 4 3.758 M
|
||||
RA[10] C14M R 10.490 4 3.360 M
|
||||
RA[11] C14M R 10.424 4 3.355 M
|
||||
RA[1] C14M R 10.490 4 3.360 M
|
||||
RA[2] C14M R 10.490 4 3.360 M
|
||||
RA[3] C14M R 11.808 4 3.656 M
|
||||
RA[4] C14M R 10.490 4 3.360 M
|
||||
RA[5] C14M R 10.490 4 3.360 M
|
||||
RA[6] C14M R 10.490 4 3.360 M
|
||||
RA[7] C14M R 10.490 4 3.360 M
|
||||
RA[8] C14M R 10.490 4 3.360 M
|
||||
RA[9] C14M R 10.490 4 3.360 M
|
||||
Vout[0] C14M F 11.348 4 3.872 M
|
||||
Vout[1] C14M F 11.434 4 3.871 M
|
||||
Vout[2] C14M F 11.348 4 3.872 M
|
||||
Vout[3] C14M F 11.434 4 3.871 M
|
||||
Vout[4] C14M F 11.348 4 3.872 M
|
||||
Vout[5] C14M F 11.348 4 3.872 M
|
||||
Vout[6] C14M F 11.434 4 3.871 M
|
||||
Vout[7] C14M F 11.434 4 3.871 M
|
||||
nCAS C14M R 10.424 4 3.355 M
|
||||
nCS C14M R 10.424 4 3.355 M
|
||||
nDOE C14M R 14.217 4 4.353 M
|
||||
nRAS C14M R 10.424 4 3.355 M
|
||||
nRWE C14M R 10.424 4 3.355 M
|
||||
BA[0] C14M R 10.424 4 3.355 M
|
||||
BA[1] C14M R 10.424 4 3.355 M
|
||||
CKEout C14M F 10.424 4 3.355 M
|
||||
DQMH C14M R 10.404 4 3.362 M
|
||||
DQML C14M R 10.404 4 3.362 M
|
||||
LED C14M R 22.936 4 8.890 M
|
||||
RAout[0] C14M F 10.490 4 3.360 M
|
||||
RAout[10] C14M F 10.490 4 3.360 M
|
||||
RAout[11] C14M F 10.424 4 3.355 M
|
||||
RAout[1] C14M F 10.490 4 3.360 M
|
||||
RAout[2] C14M F 10.490 4 3.360 M
|
||||
RAout[3] C14M F 10.490 4 3.360 M
|
||||
RAout[4] C14M F 10.490 4 3.360 M
|
||||
RAout[5] C14M F 10.490 4 3.360 M
|
||||
RAout[6] C14M F 10.490 4 3.360 M
|
||||
RAout[7] C14M F 10.490 4 3.360 M
|
||||
RAout[8] C14M F 10.490 4 3.360 M
|
||||
RAout[9] C14M F 10.490 4 3.360 M
|
||||
RD[0] C14M R 13.733 4 3.707 M
|
||||
RD[1] C14M R 13.745 4 3.707 M
|
||||
RD[2] C14M R 14.285 4 3.790 M
|
||||
RD[3] C14M R 13.348 4 3.790 M
|
||||
RD[4] C14M R 14.450 4 3.952 M
|
||||
RD[5] C14M R 14.480 4 3.952 M
|
||||
RD[6] C14M R 14.784 4 3.952 M
|
||||
RD[7] C14M R 14.247 4 3.952 M
|
||||
Vout[0] C14M R 11.348 4 3.872 M
|
||||
Vout[1] C14M R 11.434 4 3.871 M
|
||||
Vout[2] C14M R 11.348 4 3.872 M
|
||||
Vout[3] C14M R 11.434 4 3.871 M
|
||||
Vout[4] C14M R 11.348 4 3.872 M
|
||||
Vout[5] C14M R 11.348 4 3.872 M
|
||||
Vout[6] C14M R 11.434 4 3.871 M
|
||||
Vout[7] C14M R 11.434 4 3.871 M
|
||||
nCASout C14M F 10.424 4 3.355 M
|
||||
nDOE C14M R 13.929 4 4.309 M
|
||||
nRASout C14M F 10.424 4 3.355 M
|
||||
nRWEout C14M F 10.424 4 3.355 M
|
||||
nVOE C14M R 13.926 4 4.281 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with hold speed: 6
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Sep 21 05:35:49 2023" vendor="Lattice Semiconductor Corporation" >
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Dec 28 23:24:04 2023" vendor="Lattice Semiconductor Corporation" >
|
||||
</userSetting>
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
<ReportView version="2.0">
|
||||
<Implement name="impl1">
|
||||
<ToolReport id="tooldec" path="" status="0"/>
|
||||
<ToolReport id="toolhle_genhierarchy" path="Y:/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html" status="1"/>
|
||||
<ToolReport id="toolhle_genhierarchy" path="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html" status="1"/>
|
||||
<ToolReport id="toolpio" path="" status="2"/>
|
||||
<ToolReport id="toolsso" path="" status="2"/>
|
||||
</Implement>
|
||||
|
|
|
|||
|
|
@ -3,9 +3,12 @@
|
|||
<Options/>
|
||||
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
|
||||
<Options def_top="RAM2E" top="RAM2E"/>
|
||||
<Source name="../RAM2E-LCMXO2.v" type="Verilog" type_short="Verilog">
|
||||
<Source name="../RAM2E.v" type="Verilog" type_short="Verilog">
|
||||
<Options top_module="RAM2E"/>
|
||||
</Source>
|
||||
<Source name="../UFM-LCMXO2.v" type="Verilog" type_short="Verilog">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="REFB.v" type="Verilog" type_short="Verilog">
|
||||
<Options/>
|
||||
</Source>
|
||||
|
|
|
|||
|
|
@ -6,12 +6,39 @@
|
|||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn230921045933"></A><B><U><big>pn230921045933</big></U></B>
|
||||
#Start recording tcl command: 9/21/2023 04:58:25
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC; Project name: RAM2E_LCMXO2_640HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf"
|
||||
<PRE><A name="pn231205230924"></A><B><U><big>pn231205230924</big></U></B>
|
||||
#Start recording tcl command: 12/5/2023 14:55:22
|
||||
#Project Location: //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC; Project name: RAM2E_LCMXO2_640HC
|
||||
prj_project open "//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_project save
|
||||
prj_project close
|
||||
#Stop recording: 12/5/2023 23:09:24
|
||||
|
||||
|
||||
|
||||
<A name="pn231226232445"></A><B><U><big>pn231226232445</big></U></B>
|
||||
#Start recording tcl command: 12/26/2023 18:23:53
|
||||
#Project Location: //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC; Project name: RAM2E_LCMXO2_640HC
|
||||
prj_project open "//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -task IBIS
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 9/21/2023 04:59:33
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_src remove "//Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.v"
|
||||
#Stop recording: 12/26/2023 23:24:45
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Thu Sep 21 05:35:24 2023 *
|
||||
NOTE DATE CREATED: Thu Dec 28 23:23:58 2023 *
|
||||
NOTE DESIGN NAME: RAM2E *
|
||||
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS RD[0] : 36 : inout *
|
||||
NOTE PINS LED : 35 : out *
|
||||
NOTE PINS C14M : 62 : in *
|
||||
NOTE PINS DQMH : 49 : out *
|
||||
NOTE PINS DQML : 48 : out *
|
||||
NOTE PINS RD[7] : 43 : inout *
|
||||
NOTE PINS RD[6] : 42 : inout *
|
||||
NOTE PINS RD[5] : 41 : inout *
|
||||
|
|
@ -16,25 +14,27 @@ NOTE PINS RD[4] : 40 : inout *
|
|||
NOTE PINS RD[3] : 39 : inout *
|
||||
NOTE PINS RD[2] : 38 : inout *
|
||||
NOTE PINS RD[1] : 37 : inout *
|
||||
NOTE PINS RA[11] : 59 : out *
|
||||
NOTE PINS RA[10] : 64 : out *
|
||||
NOTE PINS RA[9] : 63 : out *
|
||||
NOTE PINS RA[8] : 65 : out *
|
||||
NOTE PINS RA[7] : 67 : out *
|
||||
NOTE PINS RA[6] : 69 : out *
|
||||
NOTE PINS RA[5] : 71 : out *
|
||||
NOTE PINS RA[4] : 75 : out *
|
||||
NOTE PINS RA[3] : 74 : out *
|
||||
NOTE PINS RA[2] : 70 : out *
|
||||
NOTE PINS RA[1] : 68 : out *
|
||||
NOTE PINS RA[0] : 66 : out *
|
||||
NOTE PINS DQMH : 49 : out *
|
||||
NOTE PINS DQML : 48 : out *
|
||||
NOTE PINS RAout[11] : 59 : out *
|
||||
NOTE PINS RAout[10] : 64 : out *
|
||||
NOTE PINS RAout[9] : 63 : out *
|
||||
NOTE PINS RAout[8] : 65 : out *
|
||||
NOTE PINS RAout[7] : 67 : out *
|
||||
NOTE PINS RAout[6] : 69 : out *
|
||||
NOTE PINS RAout[5] : 71 : out *
|
||||
NOTE PINS RAout[4] : 75 : out *
|
||||
NOTE PINS RAout[3] : 74 : out *
|
||||
NOTE PINS RAout[2] : 70 : out *
|
||||
NOTE PINS RAout[1] : 68 : out *
|
||||
NOTE PINS RAout[0] : 66 : out *
|
||||
NOTE PINS BA[1] : 60 : out *
|
||||
NOTE PINS BA[0] : 58 : out *
|
||||
NOTE PINS nRWE : 51 : out *
|
||||
NOTE PINS nCAS : 52 : out *
|
||||
NOTE PINS nRAS : 54 : out *
|
||||
NOTE PINS nCS : 57 : out *
|
||||
NOTE PINS CKE : 53 : out *
|
||||
NOTE PINS nRWEout : 51 : out *
|
||||
NOTE PINS nCASout : 52 : out *
|
||||
NOTE PINS nRASout : 54 : out *
|
||||
NOTE PINS nCSout : 57 : out *
|
||||
NOTE PINS CKEout : 53 : out *
|
||||
NOTE PINS nVOE : 10 : out *
|
||||
NOTE PINS Vout[7] : 12 : out *
|
||||
NOTE PINS Vout[6] : 14 : out *
|
||||
|
|
@ -71,7 +71,6 @@ NOTE PINS Ain[1] : 2 : in *
|
|||
NOTE PINS Ain[0] : 3 : in *
|
||||
NOTE PINS nC07X : 34 : in *
|
||||
NOTE PINS nEN80 : 82 : in *
|
||||
NOTE PINS nWE80 : 83 : in *
|
||||
NOTE PINS nWE : 29 : in *
|
||||
NOTE PINS PHI1 : 85 : in *
|
||||
NOTE CONFIGURATION MODE: NONE *
|
||||
|
|
|
|||
|
|
@ -1,41 +1,61 @@
|
|||
----------------------------------------------------------------------
|
||||
Report for cell RAM2E.verilog
|
||||
|
||||
Register bits: 111 of 640 (17%)
|
||||
Register bits: 122 of 640 (19%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
I/O cells: 69
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
CCU2D 9 100.0
|
||||
EFB 1 100.0
|
||||
FD1P3AX 48 100.0
|
||||
FD1P3AX 61 100.0
|
||||
FD1P3IX 1 100.0
|
||||
FD1S3AX 22 100.0
|
||||
FD1S3IX 4 100.0
|
||||
FD1S3AX 21 100.0
|
||||
FD1S3AY 4 100.0
|
||||
FD1S3IX 6 100.0
|
||||
GSR 1 100.0
|
||||
IB 22 100.0
|
||||
IB 21 100.0
|
||||
IFS1P3DX 1 100.0
|
||||
INV 1 100.0
|
||||
OB 40 100.0
|
||||
OFS1P3BX 6 100.0
|
||||
OFS1P3DX 27 100.0
|
||||
OFS1P3BX 5 100.0
|
||||
OFS1P3DX 21 100.0
|
||||
OFS1P3IX 2 100.0
|
||||
ORCALUT4 221 100.0
|
||||
ORCALUT4 277 100.0
|
||||
PFUMX 3 100.0
|
||||
PUR 1 100.0
|
||||
VHI 2 100.0
|
||||
VLO 2 100.0
|
||||
VHI 3 100.0
|
||||
VLO 3 100.0
|
||||
SUB MODULES
|
||||
RAM2E_UFM 1 100.0
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 420
|
||||
TOTAL 492
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ufmefb
|
||||
Report for cell RAM2E_UFM.netlist
|
||||
Instance path: ram2e_ufm
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EFB 1 100.0
|
||||
VHI 1 50.0
|
||||
VLO 1 50.0
|
||||
FD1P3AX 30 49.2
|
||||
FD1P3IX 1 100.0
|
||||
FD1S3IX 1 16.7
|
||||
ORCALUT4 272 98.2
|
||||
PFUMX 3 100.0
|
||||
VHI 2 66.7
|
||||
VLO 2 66.7
|
||||
SUB MODULES
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 313
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ram2e_ufm.ufmefb
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EFB 1 100.0
|
||||
VHI 1 33.3
|
||||
VLO 1 33.3
|
||||
|
||||
TOTAL 3
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:20 2023
|
||||
Thu Dec 28 23:23:55 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
|
|
@ -82,5 +82,5 @@ Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
|
|||
Initialized UFM Pages: 1 Page (Page 190).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 4 secs
|
||||
Total REAL Time: 3 secs
|
||||
Peak Memory Usage: 267 MB
|
||||
|
|
|
|||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
|
@ -2,7 +2,7 @@
|
|||
NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.*
|
||||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
|
||||
NOTE All Rights Reserved.*
|
||||
NOTE DATE CREATED: Thu Sep 21 05:35:21 2023*
|
||||
NOTE DATE CREATED: Thu Dec 28 23:23:55 2023*
|
||||
NOTE DESIGN NAME: RAM2E_LCMXO2_640HC_impl1.ncd*
|
||||
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100*
|
||||
NOTE JEDEC FILE STATUS: Final Version 1.95*
|
||||
|
|
@ -10,8 +10,6 @@ NOTE PIN ASSIGNMENTS*
|
|||
NOTE PINS RD[0] : 36 : inout*
|
||||
NOTE PINS LED : 35 : out*
|
||||
NOTE PINS C14M : 62 : in*
|
||||
NOTE PINS DQMH : 49 : out*
|
||||
NOTE PINS DQML : 48 : out*
|
||||
NOTE PINS RD[7] : 43 : inout*
|
||||
NOTE PINS RD[6] : 42 : inout*
|
||||
NOTE PINS RD[5] : 41 : inout*
|
||||
|
|
@ -19,25 +17,27 @@ NOTE PINS RD[4] : 40 : inout*
|
|||
NOTE PINS RD[3] : 39 : inout*
|
||||
NOTE PINS RD[2] : 38 : inout*
|
||||
NOTE PINS RD[1] : 37 : inout*
|
||||
NOTE PINS RA[11] : 59 : out*
|
||||
NOTE PINS RA[10] : 64 : out*
|
||||
NOTE PINS RA[9] : 63 : out*
|
||||
NOTE PINS RA[8] : 65 : out*
|
||||
NOTE PINS RA[7] : 67 : out*
|
||||
NOTE PINS RA[6] : 69 : out*
|
||||
NOTE PINS RA[5] : 71 : out*
|
||||
NOTE PINS RA[4] : 75 : out*
|
||||
NOTE PINS RA[3] : 74 : out*
|
||||
NOTE PINS RA[2] : 70 : out*
|
||||
NOTE PINS RA[1] : 68 : out*
|
||||
NOTE PINS RA[0] : 66 : out*
|
||||
NOTE PINS DQMH : 49 : out*
|
||||
NOTE PINS DQML : 48 : out*
|
||||
NOTE PINS RAout[11] : 59 : out*
|
||||
NOTE PINS RAout[10] : 64 : out*
|
||||
NOTE PINS RAout[9] : 63 : out*
|
||||
NOTE PINS RAout[8] : 65 : out*
|
||||
NOTE PINS RAout[7] : 67 : out*
|
||||
NOTE PINS RAout[6] : 69 : out*
|
||||
NOTE PINS RAout[5] : 71 : out*
|
||||
NOTE PINS RAout[4] : 75 : out*
|
||||
NOTE PINS RAout[3] : 74 : out*
|
||||
NOTE PINS RAout[2] : 70 : out*
|
||||
NOTE PINS RAout[1] : 68 : out*
|
||||
NOTE PINS RAout[0] : 66 : out*
|
||||
NOTE PINS BA[1] : 60 : out*
|
||||
NOTE PINS BA[0] : 58 : out*
|
||||
NOTE PINS nRWE : 51 : out*
|
||||
NOTE PINS nCAS : 52 : out*
|
||||
NOTE PINS nRAS : 54 : out*
|
||||
NOTE PINS nCS : 57 : out*
|
||||
NOTE PINS CKE : 53 : out*
|
||||
NOTE PINS nRWEout : 51 : out*
|
||||
NOTE PINS nCASout : 52 : out*
|
||||
NOTE PINS nRASout : 54 : out*
|
||||
NOTE PINS nCSout : 57 : out*
|
||||
NOTE PINS CKEout : 53 : out*
|
||||
NOTE PINS nVOE : 10 : out*
|
||||
NOTE PINS Vout[7] : 12 : out*
|
||||
NOTE PINS Vout[6] : 14 : out*
|
||||
|
|
@ -74,7 +74,6 @@ NOTE PINS Ain[1] : 2 : in*
|
|||
NOTE PINS Ain[0] : 3 : in*
|
||||
NOTE PINS nC07X : 34 : in*
|
||||
NOTE PINS nEN80 : 82 : in*
|
||||
NOTE PINS nWE80 : 83 : in*
|
||||
NOTE PINS nWE : 29 : in*
|
||||
NOTE PINS PHI1 : 85 : in*
|
||||
QP100*
|
||||
|
|
@ -82,421 +81,421 @@ QF171904*
|
|||
G0*
|
||||
F0*
|
||||
L000000
|
||||
11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000000101000000110000
|
||||
00010001110000000010100000000101010010001111111101000110000000000000000000000000101110001110000000000000110101110000000000000000
|
||||
11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000000000011011000000
|
||||
00001001001010000001000101010000010010001111111101000110000000000000000000000000101110001110000000000000110101110000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000010001000000000000000000000000100010000000000000000000000001000100000000000000000000000000000000000000
|
||||
00000000000000000000000000010010000000000000000000000000100100000000000000000000000001001000000000000000000000000000000000000000
|
||||
00000000000000000000000000010001000000000000000000000000100010000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000010010000000000000000000000000100100000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000010001100000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000100110000000000000000000000000100011010011100010001000000000000000000000000000000000000000000010111100000000000000
|
||||
00000000000000000000000000000000100001000000000100001000000100100001101000001010001100000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000001000110001000011010110000000000000000000000101110001001000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000010011100000100110000100110000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000010000010011100000000000000010001000000000000000000000010000011010000011001100011
|
||||
00000011100000100110000000000000000000000000000000000000000000000000000000000000000000000100100000000000000000000000000000100001
|
||||
00100100000001001000010010100001010101001100000000000000000000000000000000000000000000000000000000000000000000000100101000000000
|
||||
11000000110000001001110000000000010011101101000001000001001100000000010010100000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000010001000000001000110101001000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000010001000000100010000000000000000010000010000001100001100010000110011011010000010000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000100001000000001010010000000000000000010011100100010000010000011000011
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000101110000000000000000100111000001001110000000000010111
|
||||
00001001000010010100100010000000000000000000000000000000000000000000000000000000000000000000000000000000000010011100000000000000
|
||||
00000100010100111000100010000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000010100110001110001001001110010010110001000000000000000000000000000000000000000000001000000000000000000000000
|
||||
00001000010000000000000000000000000000000010010100000100101100000000010010000000000000000000000000000000000010011000000000001000
|
||||
01000000000000000000000000100000000000000000000000000000000000011000100110000100011100110010011110001100010010000100000000000000
|
||||
00000000000000000000100011000000000010000110011100000000000000000000000100111000000000000000000000010101000000000000000111001000
|
||||
01001010000000000000000000000000000000000000000000000000000000000000000000000000000000000001001000000000000100001100001000000000
|
||||
00010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001000100000000000100000100
|
||||
00000000000000100101000001001101001100010000100000000000000000000000000000000000000000000000000000000000000000000010000110011000
|
||||
00000010011100000000000000000000001000111000110000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000110011100011001110000001001110000000000000000000000000000000000000000000000000000000000
|
||||
00100100000100001011100100000000010011100001000110000000000100001010011100000000000100101000011000010100000000000000000000000000
|
||||
00000000000000000000000000000000000000000010011000001110000100100110000011100001000000000000000000100000100010000000000000001001
|
||||
10001010011111001000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001000001001100000000000
|
||||
10000101001100000010011000000100011100001111000101010100100000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000010000110000000000000000000001000000100011000001000110000000001001111001010000000000000000000000010001000000000000000
|
||||
00000000000000000000000000000000000010001010011100010010100000000000000010010100100101001000111000111001001001010010101100000100
|
||||
01101001010000000000001101001001101001000000000000000000000000000000000000000000000000000000000000000000100001100110000010000110
|
||||
01100000110000011011010010010100011001100100010100110010010000100001110100100100001100100010110100100100000000000001000010000000
|
||||
00110110000001001011001100000000000000000000000000000000000000000000000100010100110001001110010011000000100110000001001100100110
|
||||
00010001101001000000000000010011100001110001000000000000000100110000000000100111010000000000000000000000000000000000000000000000
|
||||
00000010110100100001001000000100100000100000000001000000010010000010000101001010001000011001100000010000100000100011000000000000
|
||||
10010000000011000101000000000000000000000000000001001000000000000000000000000000000000001000011001010000000001100001001100100100
|
||||
01110011000000000011001010100001000110100110000000000000000000000110011110000100001100110000000000000000000000000000000000000000
|
||||
00000000000000000001000011001100100100001000011001100000010001101001100000100101100010000000001100100010100110000000000000000000
|
||||
01100111100100111010010110011000000000000000000000000000100110000000000000000010101100000000010011010101000001001101000000000100
|
||||
11000000000100100001001101001100100111001000110100111000010010100000000000000110000111100100001100111010101000000000000000000000
|
||||
00000000000000000000000000000000010000000000100000000001000000000001000011001100001100011001000000100001000000000000000000000000
|
||||
00000000000000000000000000000000000000000100111000000000100000001001101001110100001100111100101010101010101101000011001110010011
|
||||
10000011101000000100100100011011100001000010001111000101011101101010100111001000111100010010100100100111010101010011001001101001
|
||||
10000000000000000110011110010010000000100000000000000000000000000000000000010001000000000000100011100001010010010000000111000010
|
||||
01000100000100111000000010000110010010010110000110011001001001111010001000010001000110010001010001111110000011011101000110100100
|
||||
11010000011101000010000000010000000000000110011110000000000000000000000000000000000000000000000000000000100101001000010100001000
|
||||
00010000100100001100111000011001000011010111100100101100011000110001100111000010100010000010000010011010000100001000001100011001
|
||||
10100100100110000001000011001110001100001111000000000000000000000000000000000000000000000000000000010001010011010000010010110011
|
||||
00001100011000000010001000000000001001010100001010011000100110001000111001111000100110000101010001110011110011010101001000110100
|
||||
01100100100000000000000001100111100000000000000000000000000000001000101001110000000000000000000000000101001100001100101110110000
|
||||
10010000110011100111010100001000100001001111000011110001000100001100001101001100111100000110000110011101000001001101100100101101
|
||||
00110000111100010001000111001000001000111010011101000001010011100000000000011000011110000000000000000000000000000000010000010010
|
||||
10000000000000100011000000000000000110000111010001100000000000001000011001010101011110000101010011010010010010110001101001100101
|
||||
11010011101100010010100111100101110010001010010110000011010001001001110000000000000000000000000000000000000000000000010000100000
|
||||
00000000010010100000000000100011001001001000011101000010000001000010010101010011101000010001000001010101001101001000010001110010
|
||||
00010101101100001001100000100110100100100011101001101101100000110100101000000000000000000000000000000000000000000000001001110000
|
||||
00000000000000000000010011000100011000000000000000100010011001001001001110011100000100110100000110000111100100000100011100110110
|
||||
11000001001101100011000010001101000101000101001010000000000000000011110010000000000000010010000000000000000000000000000000000000
|
||||
00000001001011010010110010000111010001001001110110101001011100001000111000010100010001001001110010001111000001101000001001110011
|
||||
01000010111100001011100000010101011100101101011011100000011110000001101001001101000100111000011010100110011101000000010000100000
|
||||
00110000111100000000000000000000000010001100000000100000100110111011000010001100000000000000000000000000100001010001110000110010
|
||||
00100110010001110000000100110010001101001011100100100011110011001001000110010001010010010001110001100100011100101111000000110001
|
||||
01001000001011010100101100101010001100000000000000000000001000011001110010010100000000000000100001001001100000000000000000000000
|
||||
01000000010100110010010011010000110010001000110100110010010010001011100010000100110101001101010100000110010100101110001000010001
|
||||
00101101111000001001000111000010101001011010010100101010001000011001111001000110010001000000100001100111000000000000000000000000
|
||||
00001001010000000001001101001100000000000000000000000000000101010100011000100100010010100010010001001011000010010010110000001000
|
||||
01001000111000110110100001001100001010100001110101000100001100000110101001100010000000100111000000110000111100000010110000110010
|
||||
01000100101000000000000000000000000000000000000000000001001110010011100101001001000101001110101111100010011100001011010110010001
|
||||
00100111010010101000101110000001010100111101000001000111000001001011001001011001001011000111001101101000100100110100110010001111
|
||||
00100100111000000100000000000000000000000010011100001001110000000000000000000010010000000000000000000000010000010001100010010101
|
||||
11010000001100111000010001100010011001000110001001100000110000110011001000011000101001101000010011001001001110000001100111001100
|
||||
10001011000010011100000110100100000100000100011111010000000000000000000000000110010010001001110000000000000000000010010100000000
|
||||
00000000000000100100000101111000100011110001001010011010000110010001000110100110001000101110001000001010010110010000110000001001
|
||||
10010010001000010110100001010010011010001011000001101001001100110100011100100010100110010110010011100001001001110000000000010101
|
||||
10000000001100011000000010010000000000000000000000000000000000000000000000000000000000010010001001010001001000100101100001001100
|
||||
10010011010100011100011000001001100100010100011000010000010011100100110110000011011010000011001010000000000000000010011100000000
|
||||
00000000000000000110101111100000000000000000000000000111111110010011010100010100001010001111111110110000100111101111111111111101
|
||||
11100100101101111111111111111011010010011110111111111111110111100100101101111111111111111010100111101010101111111011011111001100
|
||||
01010001111101110100001111110111010100001111011111101000100001110000101110100001100000011111110111110000111000010011111011111000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000111100110010001110100011111111101001001110111111110011111
|
||||
01100001101111011110011001111011110110000110111110011001111101100001101111011110011001111011110110000110111110011001111101000111
|
||||
01000101000100100100110110010001010001111100011011111101110101110110010001011101111111000111111011111110111011110010001110111101
|
||||
11000011001000001110101111100100011100111111000110000000000000000000000000000000000000000000111010000000000000000000000000000000
|
||||
11110011001000111101111111010010110100011011111111100001101111011110011001111011110110000110111110011001111101100001101111011110
|
||||
01100111101111011000011011111001100111111100011111101110110011110010001111011111010100011011100101011101100101110110110100101101
|
||||
11111111111111101001001000000100010010100010010010000011111100100000000000000000000000000000000000000000000010100000000000000000
|
||||
00000000000011111111001001101010001111001100011111111011111111100110100000111101111111111111101111000001011011111111111111110110
|
||||
10000011110111111111111110111100000101101111111101000011111111011011001000011111111011101000011001111111101110010100001110010111
|
||||
01100001111010100010100010000111000000111111001000010000011110111111000011100000011111111110100000000000000000000011110100000000
|
||||
00000000000000000000001001110000000000000000000000000010110101000111011000100000111101001110010010001111110001001101101000100000
|
||||
11110100111001001000111111000100110110100010000011110100010011100001000010000001000111111000100001000000011100001000011000000111
|
||||
00100011100001000000000000000000000010001000000000000000000000000000000000000000000000000000000010001100000010000100000010010100
|
||||
10010101001110000100000010101100100011011010000101100100010000000100100000000000010010110100100000001101000010100110000000000000
|
||||
00000000000000000000000000000000000110000100100000000100101011001000101001101110001000000111000101010011001100011000001000011101
|
||||
00110001000111001010001001110001100100010100110100011100100000000000000000001001000000000011011000000100110100110000000000000000
|
||||
00000000000000000000000000001010110000001010010001000101001110010010001110001000100111000100110010010100100011001001011010010010
|
||||
00101000110000011100010001000000001001100000000000000010011000000010011101010100000000000000000000000000000000000000000000000000
|
||||
00000100001101011010001100000010000111001000010000000100111010001100000000010000000011000110010001001010000000000010010000000000
|
||||
00001000100000000000000000000000000000000000000000000000001000010100000100100000000000010010100100101010000000000100100010010000
|
||||
00000010001110010000001000100010011000000000000000000000011001111000000000000000000000000000000000000000000010001100000000000000
|
||||
00000011001000101101000001010010000110000101010011011100000100001000111000100000000000000100110000100000100101000000000000001000
|
||||
11000000011001111001001110100110100110000000000000000000010101100000000000000000100101000000000100010100010100111100101000000001
|
||||
00011000010001110011010010100001001100010110000000000100000000001001100100010100100000000000000110000111100000000100001100111010
|
||||
00001010100000000000000000000000000000000000000000000000000100010000000001000101100001010000011001000011000101001110001011010111
|
||||
01000001000010000000000100101100011001100011001010011001001110001100000011000000000000000000000000000000000000000000000000000000
|
||||
00000000000100100100010011001000101101100000001001011110000001110010001011010100011001000000010010010111110111100101010100110010
|
||||
01101011011000101100000110011000010101000111000011000011001100001100001001100001100100100101000100001100011000000000000000000000
|
||||
01100111100110001100000000100000000000000000000000001100100100000000000000000000000100001010000110001110010111000000111110011000
|
||||
10000101001010101110001100000110110100100111100100010010001011001001101000010010001110001111000101001000011100001001100000100001
|
||||
10010111100101000100101100011010011011011000001001011101000100100100001100011001110001100011011000000000001000000000001000110000
|
||||
01100111100100111010001100000100001100111000000000000000000000000000000000000000101001001000100010011110011100110101001000010010
|
||||
10110010001000100000010011010010100100111100000100100100000010001111100000100110111100010011010011000010110100010100111001001001
|
||||
00110111000010010011100000000000101011110000111100001001010000000000000000000000001010110000000000000000000000010011110000010011
|
||||
00100101100011110010101010010001001100010000010011010011110011000101011100100110100001011100010000110000001110001111110000101001
|
||||
11101111100111011000101011000001000110010001111000001101110000100110110000010011101010101000001101000001010111000000000000000000
|
||||
01100111100000000000000000000000000000000000000000000000000001001001100001010010111110010110011110010011001000011100101010100001
|
||||
10001100110000100100111010000000010011110010111101000000101111011000100101110000101100110110110000010000110101010000110001110010
|
||||
10010000110010001001111001110001001100000000000000110000111100000010111000000000000000000000000000100111000000000000000000000010
|
||||
01011001101001110100100011100000111110000100010100110110000100110110100010011100000101001000011110010100110110000010010000101001
|
||||
10010100010011111011000000111000100010010011100100000011100001101101000100100101100001011010001001100001001100100000000000000000
|
||||
00100101000000000000000001010110000000100010000001000011001110000100001100111000000000001000001001100010001110010110001101101000
|
||||
00100001001111100011000000100010010000100110000101011101000000100100001010100100100100110011100000011010011100011000100000111000
|
||||
10001001001000111011110010011100100001100111000000001010010000000000000000000000000000000000000000000000000000000000010100101110
|
||||
00100001001011000011001001010101100001100000110001100110000110011000100010100110010011000100101110000101000110011100011010100101
|
||||
00000100011111000011000110010001001000011001111100001100100111100101011000101001100001010100100000000000000000000011110010000000
|
||||
00000000010000000000000000001000100000000000000000000010011110100111010001001001111110001000000110000101010010111010000010100101
|
||||
10000010011010000000010111111001001001000101110010101100001001010101010111001110010101010010010000100100101101010100010111001000
|
||||
01010010001100101001100001000100010000000000011000001110000000000000000000000000000000100000000000000000000000000010000101000100
|
||||
10010101011001011100001000011100001001010111100001110000010000010111010011110010011100010001001010101010110010010011010011000010
|
||||
01111011011000000100000010011101011100000000000000000000000010000110011100000000001000010001010110000000001100010010000000000000
|
||||
00000000010011010010010011110100110011101100001100100001100001100001000110000011010110010001100011000010100100110000100011011010
|
||||
00010000101101110100000110000001110000100010000111100001101000111010111000100100011010001010011100000000000000000000000000000000
|
||||
00000000000000000000000000000000000100110100011110000100100110000001110011010010111010001000110101100001001111000011110100000100
|
||||
10010011110000010011001001101100001010100011010011001000001000001001001101000010010001011100001001000101110001000010110010001011
|
||||
11000100010011101001100110001001011100001010000100111000000000110000011100101100000010011100000000000000000000010001100000000000
|
||||
00000000000010000111010001001110001000000010101010011010000001000101100010100100101110110000010001101011110111100100011100100001
|
||||
00111100101100100100010100010100110100101100101010000010000110100110110011001001000110100101010011101001100010001011001001001000
|
||||
11000000000100010000000000100111001010110000000000010011100000000100000001001100000000000000000000000001000000010010101100110110
|
||||
10011000100101011010000011100100010010010100111000001000100001001001011100100001100010100100001001100100101110000101000001110010
|
||||
01100011010000011000011110100100100011000000000000000000000010011010100100000000001000010000000000000000000000000000000000000101
|
||||
11110100110000101001100000001100001001110001100000010000110000101101000010001001011100001001100010100101100111000101010100001101
|
||||
11100110100010111100100100100100100000101111000101100000000000000000000001011001001000100011001110011000000000000000000000010011
|
||||
00110001010000000000000000000000000100001100000010000110011010001110101011010010101101110000000100111100001111001000000001000001
|
||||
00011001100000011100101100001110110000010111011100100001001111010101101110000100111010010000011100100000100100011010001001100001
|
||||
01010011100000000010011000100001000000000000000000000000000000000000001110111011000000000000000000001111101111110111111100111011
|
||||
11110100000101000011000011111101110000011111011111111101111010100011111101110110000111111111100000101101111111000010011011010001
|
||||
00111110111010000111001100111010000111110111111110111110111011111111110111010011110111111000011100001011111111110001101110111111
|
||||
11011100110111111110011110011000000000000000000000000000000000000000000000000100100111001100100000000000000000000101000101000001
|
||||
01000100011011111110111001000010001111111011101111001111100100110111011111111101101100001100111100110011110011001001011011011101
|
||||
10011010001111101000001110101010100100111111000011111100001000111010001111111011100100111011111111110100001000111100001111101000
|
||||
10010001110011000100011110000011111111011101011101010000100011000000000000000000000000000000000000000000000000111001100100000000
|
||||
00000000000011000101011111011010001111001100001111011101010100011101111111000101011010100100101000010001011101010101101010101101
|
||||
11011111011101101100110100011101000111111000010111011011001101111111011011000100111111101110010100011110010000110000011110100010
|
||||
01001100001011111001100001111011111111110111010010111001100111011001000110000000000000000000000000000000000000000000001110111011
|
||||
00000000000000000000110101010111011111000011110111010101101101000011111110111010000110011001110000110000111111100001110011000011
|
||||
00110011111100110010000111111011101111001100100110111100111011101010101000011100110011101000011010111111010000111111011111111110
|
||||
01011000011111111111101100001111011101111111111000101000111110111001111111011111111000010011000000000000000000000000000000000000
|
||||
00000000000000000000000000000000001000000010011100100000001001110011000000111001000111000010000110000001110010010001110110000101
|
||||
10101000111111000100001000000010011100100000001110000100001000000100011101100001001000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000110000011001000110000100110000101011010010000010101100000000000001001100000000000000000000000
|
||||
00000000000000000000100011000001000110000000000000000000000000000000000100110100101000100100100110001000011101000100000011000100
|
||||
10100110100101000000000001001010100111000000000000000000000000000000100001100110000000000000001001010000010010100000000000000000
|
||||
00000000000101001101001000001010010001001000000100110000001001100000001001110000010011110000100000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000010001100010011010001100110010100101011000001011010100101000001000110000010
|
||||
01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001000010000100001100100000100000
|
||||
00000001110010000000000000001000010000001001100000000000000000000000000000000000000000000000000010001100000000000100011000000000
|
||||
00001000011101000001011000100100000000000100110000100100100010100101000010000100000100000100011100111000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000110100010011100100000010000101010011000001001100001101000100000001001
|
||||
10110100001010011000000000010001100100111000001001000000000000000000000000000000000000000000000000000000100101000000000001001010
|
||||
00000000000010000000000111001100110000100001100101001010010000010110110000100000100000000001100001010110010010000000000000000000
|
||||
00000000000000000000000010011000000000000000000000000000000000000011000010010110110000010011100110000100110010011010001001011000
|
||||
10010001001000011000101000100011010011010011001011011000111110001001100010010001000100011101111100101100010100111110000100110000
|
||||
11101001010000000000000000000000000000001001110000000100011000000000000000000000000000000000000100110100101010000010010010111010
|
||||
01001101010010100100100100111001000010010111111001001000010010010101000010100101100100100011100001100000100011111011000111000000
|
||||
11010011011010001010000001000100000000000000000000000000000000000000000000000000000000000000000000000000000000011010010100100011
|
||||
01001010000010001110110100011100001001011000010100101110100001010010110001010011100100010010011010010010011101001010111000100000
|
||||
00000000000000000000000000000001000100000000000000000000000000000000000000000000001100010110100111001001111001111010101101000010
|
||||
11100100000010001000001110010000010100110010111100010000110110000010001011001110011000001001110100000100011100100111000000110010
|
||||
10100101011001001101101110001010011100000000000000000000000000010001000000000000000000000000000000000000000000000001000010010000
|
||||
10100010100110100011010001011000000111010101100100001100001111010000010001000011010000101111001000001000111010101010101001101000
|
||||
01100111011001000100100111000000000000000000000000000000000000010000000000000000000000000000000000000000000000000001001001000100
|
||||
00111001001001110000100101110100100100111100100100101101001011010000100001000010001100100001010001110010011100100000100001100100
|
||||
11010011100111101001001100001001100010100011000000000000000000000000000000000000000000000000000000000000000000000000000001100001
|
||||
00110000100001010111110000001110000011010110110000110010010000110001010011111000001100010000010011010000111100001101001101000110
|
||||
10011001100101001100110100111000110010001010011100000000000000000000000000000000000000000000000000000000000000000000000000000010
|
||||
10100100111100000011000101101001111110010000100111010000110010010010011011000001001111100010100010000110011010001110011111010100
|
||||
10100100110010010010011101001101010011001001100101010010010101100001100101010110011101010011100000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000100001000100001001100011000111000001011100001011010110100010100110010100110011000100
|
||||
00010000111001001010001000110100110101101100101100010110011000101000011001010010010001001010000000000000000000000000000000000010
|
||||
01110000000000000000000000000000000000000110011000100001110100000100100110100001010001010001100100000100011010001010010000010001
|
||||
11001110001000010110000101110010101000001000101100010010100110001011001100011000110001001010011000000100010000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000010001000010010110001111100010001001100001101000110100101001001001000101001
|
||||
11110110000010010100100110100111100101100110100100001000101011000100100010001110000111100000010101011000000000000000000000000000
|
||||
00000100010000000000000000000000000000000000000000010000100100101010000010000010010110000010011000110000101011100100001110000001
|
||||
00100001010011000110001010011011001011001011001011001100010000010101011101100001001111001001010101000101000101110010010100111000
|
||||
00100111000000000000000000000001000100000000000000000000000000000000000000000001000001001010100001100111100110001101010010111010
|
||||
00011110000100110100010100110010110001100001010010011100100100010010110011101000101010011011010100111110010010000010011001100100
|
||||
10000110010010000000000000000000000000000000000010011100000000000000000000000000000000000000000001001100010001101001010011001000
|
||||
01000000010111000100010010011110011001011011001101001111110011110100001010011011000110001100100110100011000110100100111001000101
|
||||
10110000000000000000000000000000000000000000000000000000000000000000000000000000000001100011001100111001001100110000100110001010
|
||||
00110100010100000110100010010001110000100010010010010110010110010010001010010110101011000100101001101001110011001000011100001001
|
||||
11100100001000000010101010101010011100000000000000000000000000000000000000000000000000000000000000000000000010010000111010000000
|
||||
00100001111000100010000011010000101010010100000000011000010100110100010000100111000010010010001110001001000011001111001000100100
|
||||
01001010000000000000000000000000000000000000000000000000000000000000000000000000000000101100111111001101010001111011111011010001
|
||||
00111011001101111011111101000011000000110001110111011100001111101110111111111001001101111111110101000100001110000111110100000111
|
||||
10010100111111001110100001010001111110000011011101111111111001000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000001001001011001100110001110000110011101110101101010101101110110100010011100000111000111010001111111100100100110000001
|
||||
10000101110001000111111101110111010111110010011000011001111111100100011111010101010100010010011111110111100111111100011111101110
|
||||
00100100101000111011100110001100000000000000000000000000000000000000000000000000000000000000000000000000000000101000111110111110
|
||||
00101010101111010101100101101000111001000100101000100101111101111100001011100010001111111111001100001110101110110000110011001100
|
||||
01100011111111011111101010000111111111010100001100001110111111011101110101111000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000011110111111010000100000110101111101101000100111001100101000001101111111010100000011111101011000011
|
||||
11111001111111011101001101111111110111110111010000111000011111111111001100110110111111111111111000101000111101110101010001010000
|
||||
10100010011100000000000000000000000000000000000000000000000000000000000000000000000000001100000011100100100011101100001000000010
|
||||
01100000100011111100010000101101010001111110001000010110100100111001000000010011100000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000100011100110100101000000010000100101111000010000100000100011000000000000000000000010001110000
|
||||
00010010000000000010011001000011001100000000000000010001100000000000000000000001011110000000000000000000000000011001000101001101
|
||||
00100000000100101100011011001000101001100000000000000000000000110100001010100100100101000100111110110000000100110000000000000000
|
||||
00000000000000000000000000000000001010011010010000000000000100100100110100111000010001001001001001010100100000000000000000000000
|
||||
00100110100110001000001001110000001001110100000000000000000000100101000000000000000000000000000000000000001000011001001000110000
|
||||
00001110000001110000011000000000000100000000000000000000000000011000010010001010111001100000000000000000000000000000000000000000
|
||||
00000000000000000000100110100100000101010000100001010000100000010011010000000010001110011100000000000000000000010001100000000000
|
||||
01100111000000000000000000000000001000111000110000010001100000000000000000000000000110000101110001100000000000000000100011000100
|
||||
10001000110000000000000000000001101000010100110000110000111100000110011110010011100100110000000000000000000010010100000010010100
|
||||
00000000000000000000000001101100000100110101001000001010010011010001000000001001111000010001101000001100110000000000000000000000
|
||||
10011010011000011010011110000000010000110011101000000000000000000000000001001010000000000000000000000000000000010000000000000001
|
||||
11000000100000001001000001011011000110000000000000000000000110000100100001101110000000000100001000001000101001110000000000000000
|
||||
00000000000000000010001000000000100001000011100010001000001100001001110110001010000000000010011101011111000111100010010110100010
|
||||
11010111001001100010100100000011010001001000110100011110001100111100000101101010010000001000010000000000000101111100011000000000
|
||||
01100111000110001100000000100000000000000000000000000000000000000001001110000001000010100000011000000111011101001111001111101100
|
||||
00001001110100011000100001010010001000011110000100100101001000001010011110000010011110010110010011010001100000000010001000000000
|
||||
01000000100101000110000011011000011110000110011110010011100000000000000000101011000000000000000000000000000000100011100000100100
|
||||
00000110000100110010011000110100010011100001001100010011010010001001101001011100101010110101000101001100010001101011110000000000
|
||||
00000000000000011010011110000000000000000000000000000000000000000000000000000000000001000111001011011110110010001010001001010101
|
||||
00111000000011011000000110100000110000010011100001000101110110000001001101000001101001001010011101011100010000000010011100000000
|
||||
00000000011001111000000010001000000000000000000000000000000000101001000000000001001000000001000001000110000000100111001000001100
|
||||
10101010011010001111101000001000101110001001110000011010100111101100001100100001100011110000100110000100000000000000000000100111
|
||||
01001110001100001111000000101110000010000000000000000000000000000000000000000000000000010011100000100010110000100110010100010000
|
||||
11001101000110111001000001100100100010001110011010001011011010001001101001011100001100100100001101100000111000010010001100000000
|
||||
00000000000010001000011000001110001001010101001000000000000000000000000000000000000000000000001100100100010001000001001100000000
|
||||
11010000100100011010010001101010101010011010010001101010001110100001001001100100001110100100110011000000000000000000001001000000
|
||||
10000000001001110000000000000000000000000000000000000000000000000001000000000110001101011011000011001100001000011001100001001111
|
||||
00010101101001100100001011000110010010110010001010011010001100000000000000000000000000000100010111100100000000000000100100000001
|
||||
00100000000000000000000000000000000000101010001001010110001100011010100101000011110010000000010011000010001111000100100101011010
|
||||
00101100010100001001100011000001101001001000111001110000000000000000000000010001010110000000000000000000000000000000000000000000
|
||||
00000000000010011000000000111000100000010000110110010001101110100000011000100100100011001001001000001100001101101001100100000100
|
||||
00011100010000000000000000000000000000000000000000000010010100000100101000000000000000000000000000000010010000000000110001001001
|
||||
00111000000001101110000100110001000001101000100100110001110000100011000101001001011001100000000000000000000000000000000001000100
|
||||
00000000000000000000000000000000000000000000000000011000010100100001010111011001001101100001001111000000110011010011001000000111
|
||||
00010000001101001010100000000100110100001110100000111101000000110100001001101000010100101100010001011100000000000000000000000000
|
||||
00101100000010010000000000000000000000000000000000000000000001000111000011100101010000001101000001100100000000000010000011001000
|
||||
10100111100101000100001101001111100001000100011100111101111001001010000000000000000001000100110101100010000010110000000000100111
|
||||
01000110010111100000000000000000000000000000000000000000001000001000000100101101001000100010100000100111000000010010101100100100
|
||||
01000110011010001011100100100110010010010010100011011000011100100010100100100011000000000000000000001001000001001100000000000001
|
||||
00111000000000000000000000000000000000000000000000100000100110010000100010010110010010011010011100001000000001000101001101001000
|
||||
01000001000001000010101010011000010011100001100100110100110000000000000000000001001010000000000000001001101010110000000000000000
|
||||
00000000000000000000000000000001101000100011100010000100110011001010011100101010101111100100100110101110000000101011101101100101
|
||||
00100011101011100100100111100011100110001000001100000011001001000000000000000000001000100100111110000011000000000000000000000000
|
||||
00000000000000000000000000000000000000111001100111100101100100000111111000001101111111110000111100110000101000001111001100111111
|
||||
01111000011101010011111011111110011010100010100001010001010000101000101000010100011111110110000000000000000000000000100110000000
|
||||
00000000000000000000000000000000000000000000000000000100100010100010001111000000110100100101000110001111110001100000011111011001
|
||||
11111011110010010100010011001101111111111111011110010011110111111111001111100011111110111111010111111001001111111011101000100011
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100110110100001111101111001110010001101
|
||||
00000111011001100000101101101110101000101100100011101000111110000001100010011110111111101100110001110000111010111010111011101111
|
||||
11000000000000000000000000000000010110000000000000000000000000000000000000000000000000000001111001111110100010001110111111110101
|
||||
01110111111001111110111110011111101110000100000111110111010000111011010011100111111100110111111011111111100000110011001111001111
|
||||
11011001100111111101110100001110011001110100000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
10000000100111000001001110010000000110100010000100000001001110010000001000111111000100000000000000000000000000001100000011101100
|
||||
01001100100001000000000000000000000000000000000000000000000000000010001100010011010010010010000010010100000000000100110000000000
|
||||
00000000000000000010010001001110000000000100111100110010000110011010010100000000000000000000000000000000000000000000000001001100
|
||||
00100100000001001010000010010101000110110010001011010000011001000000000000000000000000000001100001010100110000000011011100000010
|
||||
01100000000000000000000000000000000000000000000000000010100100010001010110010011000100110100111000000000100100000000000000000000
|
||||
00000000000101011100110001000001001110000010011101101000001010011000000000000000000000000000000000000000000000000000001000101001
|
||||
11000100000010010000000100110010011000100011000000000000000000000000000010000010001100010011000000100101100001001001100000000000
|
||||
00000000000000000000000000010001100000000000110001100000000001000101000010010010100000000000000000000000000000000000001001000000
|
||||
00000000011001111000010000110011010010000000000000000000000000000000000000001001100000000000010011000000000000000100001000011001
|
||||
00010100110010011000100100100001000000010011000000000000000110000101010011000011000011110110011110010011100100110000000000000000
|
||||
00000000000000000000000000000000000000000000110100001000100111000000010010000100100000100110000000010010000000000000000101011100
|
||||
11000011010011110100001100111011010000011000101001110000000000000000000000000000000000000000000000000100101000000010110100100001
|
||||
10001100010011100000000010110110000000000000000000000000001000000000110111000000010000100000000000000000000000100010000000000000
|
||||
00000000000000000100111100110001000001101100000000111001000000101111000000010000101000101000011001011001100100000110000101010000
|
||||
11001100000000000000000000000000000000000110011110011000110000000010000000000000000000000100111000000000000000000000000011001100
|
||||
10100000100110010000000100010011100100000100011010000110011100000110000100100111001000001001001001111110000011110000001101001100
|
||||
10111011001001001000110000010011000000000000100000100001000011000001101100001111011001111001001110000000000000000010101100000000
|
||||
00000000000000000000000000100100000110100001001000110010010101001100000000000110010000110010000010001110000010000101001100000000
|
||||
00000000000000000110100111100000000000000000000010101000000000000000000000000000000000000010011100100011001100011000010011100010
|
||||
00000111000100000000001000000100010101010101111100011010001010010011001001001110100000100111000001000110000000000001000100000000
|
||||
01100111100000000000000000000001001100000000000000000000000000000000000000100011010010000001001110100001100111101001000001000001
|
||||
10000101001001001001010100000100001100011000000000000000000000000011000011110000001011100000000000000000000100011000000000000000
|
||||
00000000000001001010000100111000110000100110000010010110010100010010000011000100100110101100010011010010001101100100011101000001
|
||||
00101100001010011010011110100100000000000000000000000011000001110000000000100101100111000000000000000000000000000000000000000000
|
||||
00000000000000100000100001000001110100000000010011010011010010010100100100110100100010011001000011010011001100000000000000000000
|
||||
00000100000000000010011110010000000000000000000000000000000000000000000000000100100000110000011100000010101110010101000011001100
|
||||
10111110111101000110100001100111010011110001110101011010000111010011000100100011000000000000000000000000000000000011111010000000
|
||||
00000000000000000000000000000000000000000000000000000100011000010000101010010010010110001110011000001000001110001000100110010000
|
||||
00100000000000000000000000000001001110011100001001011000000000001001110000000000000000000000000000000000000000000000000001000000
|
||||
00100010010011100100001011001100100111001100001001011001101101100100110000100101000110001000101110001000000001000011001110000000
|
||||
00010000110110001000100000000000000000010000100000000000000000000000000000000000000000000000000001100001001100010001000001000001
|
||||
00110000010000110011000010001110001101001100000100000100110000000000000000000100100000000000000001000000000000000001011110000000
|
||||
00000000000000000000000000000000000000001001110000101111010010010010010001001001111101010010000100000110001100010011010010001100
|
||||
10010010011110010100000000000000000000000100010000000000001011000010001100000000000000000000000000000000000001000000000000010001
|
||||
10010011000010000100100110000010011001000100000010001110001000100011100110000000000000000000000000010011010111000100000101100000
|
||||
00100111001001010110110000000000000000000000000000000000000000100001000000100011001000001101100000100011000110100010010010111101
|
||||
00000100100001000011001111001010000110000011000010000011000101011001011001111001000010000011001000100100011000000000000000000010
|
||||
00111000100100110010011000100101001001100000000000000010101100000000000000000000000000000100101010101110000001110010000000110010
|
||||
01100010011100010011010010000000001000010100000100100001110010000010000010100101001100000000000000000000100110001100011000000000
|
||||
00110001100000100010011100010000000000000000000000000000000000000000000000010010100000101010010011111011000100001000000100111101
|
||||
11110010000101101001001001001111100011000111000000100100100100111110010010011000010101011110000000000000000000010010010001001001
|
||||
11110000011000000011100100000000000000000000000000000000000000000000000000000000111111011100000100101000001111111011010100010100
|
||||
00000101000111010000001010001010000111111101010100001111111100110111111100000000000000000000000001001100000000000000000000000000
|
||||
00000000000000000000000000000001101101111100011001001001000101101100110100011011010001000010100010001111111101111111111101000011
|
||||
00111111100111100100110111111111110111011000111111111010111111110110010011111111001101111111100011000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000001010000000010100000101000100101011110110011000111101110111101000000100010
|
||||
11011100000100100110011111111110111110111011111111000011001001011110011001101000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000011011001100000100000111101111100111101111100111111100110011010100011110111010000110111011
|
||||
11100110011100001110001100111110111110101000111100110001010001111111011000000000000000000000000000000000001111010000000000000000
|
||||
00000000000000000000000000000000000000000000000001000111011000010110100100111001100000011100100011100001000010000001000111011000
|
||||
00000000000000000000000001100000011101100000000000000110000011000000000000000000000000000000000000110000011010000010100110100100
|
||||
00000000101001100101000000000000000000001000000000000000000000000000000000001001000000000010011001000011001101001010000000000000
|
||||
00000000000000000000001110000010000000000001001010100100000000000000000000011001100101001100110100000110010100000001100110010100
|
||||
11001001011001100000000000000110010001010011000000000000001101100000001001100000000000000000000000000000000000001000110000000000
|
||||
01001110000000000000000000001001001001100110001001010010000000001001001001100101111100100000000000000010010000001001110000111001
|
||||
00000100000010011000000000000000000000000000000000000000000000000000000000000000000000010110110001100000000001011010010010000000
|
||||
00000000000100110000000000000000000000000000000000000100011000000000000000000000000000000000000000000000000010010000000000000000
|
||||
00000000000000000000000001100111100001000011001100000000000000000000000100001100110000000000000000000000000000000000000000000000
|
||||
00000000000001100100010110100010000000000000000001100110010100110000110000111100011001111001001110010011000000000000000000000000
|
||||
11010000010000000000000000000000000000000000000000000000000010010100000001001000000000000000000010010010011000011000011110000000
|
||||
01000011001110100000000000000000000000000001000000000000000000000000000000000000000000000000000000010010110010000000000100000000
|
||||
00000000000001011010000001000010000000000000000000000001001100000000000000000101001000000000001011110000001001001001110000000000
|
||||
01000111000000001001000000000000000000000000000000000000011001111001100011000000001000000000000000000000000000010000000000000101
|
||||
00100000000010001110011010100100000000000000000000010011110101100011000000110000000000000000000000011000000110000011000001101100
|
||||
00111100011001111001001110000000000000000000000000000000000000010001001000110000000011100100001000100000000000000000000000000000
|
||||
00000000000000000000000010011000001101001111000000000000000000000000000000100011000000000000001001000100111000000000100100011100
|
||||
01000000000100101100100000000000000100001000100110000000000000000000000000010010000000000110011110000000000000000000000100010000
|
||||
00000000000000000000000000010011100000000000000000000000000000000010011100000000000000000100111010011101000100110000111100101110
|
||||
00000000000000000000000010011000000000000000000000000010001000000000100010000000000000000000000000000000000000000000001000100010
|
||||
00001100000111000010010100000000000000000000000000000000000000000000000000000000001000000000000000000000000000000100100000000100
|
||||
00110011100101011000000100100101111001010101000001100001110000000010011100000000000000000000100111000100011000000000000000000000
|
||||
00000000000000010101100000000000101110000000000000000000000000000000000000000000001111001000000000000000000000000000000000000000
|
||||
00100111010001000000000000000000000010000000000000000000000000000000000000000000100110000001000101011000001001000000000000000000
|
||||
00000000000000000000010001000010011100000100011000000000000001001110010001100000000001000100000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000100101101010000000000000100001000100101000000000010000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000001001010000000000000000000000000000000000000100
|
||||
01100000000000000010110000101001000000000000000000000001000110000000000010010101000110000000100000010100101110001000000000000000
|
||||
00000000100011100010011010110000000000001000110100110000000000000000101001010011010000010110000000100111001001100111001000000000
|
||||
00000000000000001011100000000000100011110010010001001110000000000000000000000000000000000000000000001001010000000000000000010011
|
||||
00100101010011000010010100100010010001100000000000000000000000000000001000101001011000100100011000000010001001000100100110000000
|
||||
00000000000001010101001011001010000000000000100100000000000000000001110010000000001100011000000010011100000000000000000000010001
|
||||
00000000000100111001001110000000001001010100100000000000000000000000001001110000000000010111100000000000000010001000110000011000
|
||||
00111001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011000
|
||||
00000000100110000001001100001000000000000000000000000000100110000110010010000000000000000000000000000000000000000000000000000000
|
||||
00000000001000011001001001010000000000000010000100000001001000000000000100100000001001000011000010100010011000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000001000110001000011001011000110001001100100011000001000110010000100000000000000
|
||||
00000001001001001110100011000000000000000000000000000000000000000000000000000000000000000000000000100110000100011000001001110000
|
||||
01001110000000000010011000000100110000010010000000000000000000000000000000000000000000000000000000000000000000000000000010000000
|
||||
00000000000000000000000000000000000010000011010000100000011010000010000000000000000000000000000000000000000000000000000000000000
|
||||
01000010000000100100000000000000000000000000000000000000001001001101100000000100000100100100110000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000001011000000000000000000000000000010010100000000000000000000000000000000000000
|
||||
00000000000000000000000000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000100010000001000100000000000000000000100010000100000000100001100000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000001001000000000001100000101100010000010010010011100000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000100111000001001110000000000000100000000110011000010000100000
|
||||
00001001010000000000000000000000000000000000000000000000000000000000000000000000001010100000000000000000000011000001010000001001
|
||||
10010000100000000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000
|
||||
00000000000010001001000010001000110000000000000000000000000000000000000000000000000000000000000000000001000010000000000000000000
|
||||
01000101001110000100101001000010000000010001010000101101000001100100100010010011000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000010000000000000000001001010000011001100000001001110100011001000000000000001110010000100111100101100110100
|
||||
00100001000000000000000000000000000000000000000000000000000000000000000001100000101000000100111000000010100100000100100000000000
|
||||
00000010100101000101001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000101000000
|
||||
00000010011000000100101000001001101001100010001100000000000000000000000000000000000000000000000000000000000101010000000000000001
|
||||
00001100110000000000000010011100000000000100011000001000110000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000010001000000000000000000000000010010011001110000000000000000000000000000000000000000000000000000000000000
|
||||
00100000000000000000000000010011100000000000000010000110000100000010011000000100101010010101001111100001010000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000001110000100000000000000000010000001001110000000000001000100010010110
|
||||
10011111001000000000000000000000000000000000000000000000000000000000000000100010000000000001000010000000101010000000000000000001
|
||||
01010000001000110000010001101110000010110100010010011100001000110000000000000000000000000000000000000000000000000000000000000000
|
||||
00000010000000000100001000000000000000001000101110000100100111000000000000010001000100101000011110010000000000000000000000000000
|
||||
00000000000000000000000000000000010001100000100101101001000000000000000000000000010010010110101001100000100101100101000000000000
|
||||
00000101001100101000000000100110010000110011000000000000000000000000000000000000000000001001100010000110011001001000010000110011
|
||||
00000000000110100011010011001000111000110000100011001000011010010100010001101000010110100101101001000000000000000000001001000000
|
||||
00110110000000100110000000000000000000000000000000000000010110000010011000100111001001100100000000100110100010000100010100110010
|
||||
00100001000110010010100100011110000010100000010010000100011010001100000000000000000010011010001100000000001001110100000000000000
|
||||
00000000000000000000000000000000100000001000010010000000100001001000000010011100110010000100010011100100001010010100010000001001
|
||||
01001000101000010010011100100000000000000000000000010010010011000000010001100000000000000000000000000000000000000000100010100100
|
||||
00000010100100000000000000000000000000100010011100110000000001001010000000000000000000000110011110000100001100110000000000000000
|
||||
00000000000000000000000001100101010110100000100001000011001100000100001100110000000000000000000101010000010001110011100011010000
|
||||
10100110100011100100000000000000000000000110011110010011100110100000100000000000000000000000000000000000001011000010001110011001
|
||||
00011111000100000100110000001001100111000010000100010100110100100000010011001000100001000110000100101100110000010001100000000000
|
||||
00000000000110000111100001100000011100111010000000000000000000000000000000000000000000000101011010011011010000101001100100000000
|
||||
00100000010000101001110110010000101001010001100101001000100111001000010000100000010011000000100101000000000000000000000001000010
|
||||
00000000000000000000000000000000000000000010010101001100000000110000010100110101010000000100110010010011000001010110110000010000
|
||||
10110100100111100000011010011000101100010010100001110010010111100101001001010110000101010100111100000101001110011000011001101000
|
||||
00111001100101001100000000000000000000000110011110011000110000000010000000000000000000000000000000000000000001001111000101001000
|
||||
00000010000000000100011100101100100100001111100001000010000010010001001000100000010111010010001110000001011001000011100010010011
|
||||
00010011010011010010110001001100010010100111000010001000000000000000000001100111100100111000000000000000000000000000000000000000
|
||||
00010100101001101000010000000001000000000000100000100011000111000101010110111000010100100000110010010110001111001000100100100011
|
||||
00010100100010100100000100000100100100100100011100110010101000000000000000001100001111000000000000000000000000000000000000000000
|
||||
00000001000110000000000000010011010001101000011000111001100010001000100110010001001000010111000100000110010000110000111010001101
|
||||
01010010001101000101000001001101001000000010011101011000000000000000000001100111100000000000000000000000000000000000000000100111
|
||||
00001000111100011001011000101001001110100101001000000000011000001010110001010010000111000010100000110100001010011101001001001010
|
||||
01001011001100101010100001111000000110110011100001000001000001100011001111000000110001110011100000000000000000011000011110000000
|
||||
00110011100000000000000000000000000000000000000001000100000100110000111001000000000100001000000001000001001011001010010010110010
|
||||
01111000010110110000001001000110000001111100001000100011010010011001011001100100010101111011001100001001010011000110001001101001
|
||||
10000000000000000000000000100101010000110011100000000000000000000000000000000000000000100010000010010010011100000000101001010011
|
||||
11010010000000000001010111001101001000100001100010100111111010000000100001110001010000100100000000010011000000000000000000100111
|
||||
00000000000000000000000000000000000000000010010110011010010111001010011001110010001000000000001001110100001100101001001011000101
|
||||
10000101001001110010000111000110010010011010011101110000001100000001001011011000100001111001010000000000100100001000011001110000
|
||||
00000000001111001000000000000000000000000000000000000000000000001100011000100111111000010011100000011001110100010011100001010100
|
||||
10010001010001001110000101101001010101011010000100110000010100100100100010110010000111001001011001011001011100000101100110111000
|
||||
01000101001010001111001100001110000010111001000000100011110000010110010010011100000000000000000001100001111000000000000000000000
|
||||
00000000000000000000000000000001100010010000101100010011001000110111010000001001100100011000100011011011000000110010100111001000
|
||||
10110010001001001101001000011010010101000001001100111110000011001000101011011000111000101100100010100100100101110110000010000010
|
||||
01001000110000000000000000000000000010000110011100001000011001110010110000000000000000000000000000000011100100000100011100111110
|
||||
01100000100100010001101001101000110111000000110001101001101010010010101110111011100100000010000010111010001011101000001000001001
|
||||
11000110111000001100010101100000100011100010100110100100000110010010101001100000000000000000000000000000000000000000000000000000
|
||||
00000000000000010000101001110100010010010001001011001100010010001001010001000110010000101000101000101100010010001001101000101110
|
||||
00101011010010010000010000010001110011100110000101010010100000000000000000000110000111100011111000000011001001000100101000000000
|
||||
00000000000000000000000000010000101010101000111000000001010101000100111000010110000001101010100100010010011110011110010110010001
|
||||
00001010100110010111000101001100010010110010010010001110010110010111000100101100100010100101100111010010110010010011011000100101
|
||||
00100100110010000011000010101000000100111000000000000000000000000010011100001001110000000000000000000000000000000000000000010001
|
||||
10100101010011001000110101100010011000000100000100110110110000010000100100010110010000110011100010001110010101000011000011001011
|
||||
10001100011001001000010000100111000110010011000000000000000000000000000000100101001000100000000000000000000000000000000000000000
|
||||
01001011100001100100110100000111001000001000110100110000100011010000101001101001010110000110011100100000011001000011010111011111
|
||||
10110000010010001100100001110010000111000100100100011100010011000001010100110100100100010100001110010101010000111000110100010101
|
||||
00000000000000000000000000110001100000100110011100100000000000000000000000000000000000000000100101001000000000100100010010101000
|
||||
00011100100000100101000010000100001000110001001110100010011100110001001100001000000000100101100101100111000000000000000000000000
|
||||
00100111000000000000000000000000000000000000000000110101010111101000000101000111111111010110111101111111111111101111001001011011
|
||||
11111111111111011010010011110111111111111110111100100101101111111111111111010100110100011111100000011111100001001101110101111111
|
||||
11100001000011010001101110111010100011101010100101000111101111101111011110110000111110000110000011110011110110000001111111110101
|
||||
00001110000001111111111010000000000000000000000000000000000000000000000000000000000000000000100010101011100111110011000011001100
|
||||
11110011111011000011011110111100110011110111101100001101111100110011111011000011011110111100110011110111101100001101111100110011
|
||||
11101000111101111111111010101010010101101100110100011101000110101010111001100001110011001101000100011110011111110100010010011011
|
||||
00110101000100011101000111010101011001100000111100111111000011001000001111001000100100100000111001101010001100000000000000000000
|
||||
00000000000000000000000000000000000000000000100010100000111000100010010111001111111101111111110000110111101111001100111101111011
|
||||
00001101111100110011111011000011011110111100110011110111101100001101111100110011111110001111011111111101010101100101011000011111
|
||||
00011110111001111001100111100110000110011001110100001101100111111111110101100001011111111110101100000111111100110011001100001000
|
||||
00111101000010001001100100010100100100000111110111000000000000000000000000000000000000000000000000000000000000000000011000000111
|
||||
11100110001100111111111111110011010000011110111111111111110111100000101101111111111111111011010000011110111111111111110111100000
|
||||
10110111111110100001111110111111111000000111100110010011010100011111100001000011101100110111111110101111101111101000010100010100
|
||||
00110111011111000011111000011100000011111101110101000001100100010100001110000001110100000000000000000000000000000011111100000000
|
||||
00000000000000000000000000000000000001100000011100100100011101110010000011110100111001001000111111000100110110100010000011110100
|
||||
11100100100011111100010011011010001000001111010001010001110111000101011010001111110001000010000000100111001000000100011111100010
|
||||
00011000000111001000111000010000000000000000000000000000000000000000000000000000000000000000000000000000100110000010001000000010
|
||||
11000000001001010001000110000000000010001110110000000000000001001000000000000010100100000010011001000011001100000000000000000000
|
||||
00000000000000011010000101001100000001001010001100100110110100010100000000100101011001100101001100100100000001000110000001000110
|
||||
00000000111010000000000000000000000000000011011000000010011000000000000000000000000000000000000000000010001100010001010011001000
|
||||
11100011000000010001110011000100110001001101000101001010000001001010000000100110100110111000100010001000000000000000000100110100
|
||||
11000000001001110100000000000000000000000000000000000000001000100000001000101110100000000101011100001010011010011000000100011010
|
||||
10110001001000110001100110000010000000000000001000000000101101000100111000001001010000000000100100100100000000000000000000000000
|
||||
00000000000000000000010001000000000010000000000101101000000100100010001100010110100000100000000110001100010000000000100001000000
|
||||
10011000000000000000000000000000011001111000010000110011000000000000000000000000000000001000000011010000101001100000000000001000
|
||||
11000000100010100110011001000101001101110001000000110011011011010001011000010001000011010010000010001010011110011000001000110000
|
||||
00000000000000001000110001100111100100111001001100000000000000000000000000000000000000000011010000100101100000100000100111000000
|
||||
01001110100100100011111000001000001101000010001000110100101100110000001000101000110000011101000000000000000000000000011000011110
|
||||
01100000011100111010000010001010011100000000000000000000000000000000010001000000110001100100000010001100000010010100001000010000
|
||||
10101110000000100110010110110001010011100000100111100011000000000000000000000000000000000100001000000000000000000000000000000000
|
||||
00001000010011000010100111000100001101001010100000100001101001010000000100001100110100110010000010011111100001001001111000110100
|
||||
01001001010001100001100100101001001100110000110011001001001001101001100011001001001000000011101000000100101101011100010100110111
|
||||
00100000000000100000000000000000011001111001100011000000001000000000000000000000000000010000000000001100000011000100110010011011
|
||||
00010100101001100010010011010000110001110001101100000011010000111010010011100010010010100101000111101001010100100001001011100100
|
||||
00110111110111110000001110110000110010000110010101000111110100011001001101101100010110110000010001100100011110010001011000011100
|
||||
00000000000000000010001101100111100100111000000000000010000110011100101100000000000000000000000010000100101101111000100010010110
|
||||
01011001110100000100100010010000011001010101001011000110010010110110011001000011000100100011100010111000001011110000101001011101
|
||||
01100000100010010010010010001000001000111100011000111001000010010000100000110101001010010000100011000001000010000000000110000111
|
||||
10000000000000000000000000000000000000000000000100000001010110001000011100010010101101100111011001001000110100010010110111100100
|
||||
00100011101001100010010000011100010001001100011100000010010011110001111101010001100010100100010110100011010011110010111000000111
|
||||
00001011100001001010100100011100001100000101111101110010001110110001001111011100100101000000000000000000011001111000000000000000
|
||||
00000000000000000000100111000100001100100001100000101001000011101001001011011100001001010110000110011100000101110000010100111101
|
||||
11011000101000101101100000011101000001001011100101010110011000110000011100001001110100000100000110010010110010110000110000000010
|
||||
01011000111000100011000101001000000011001100001100100010100111100011110100010010000100000000000000000001100001111000000000110011
|
||||
10000000000000000000000000000000000100010000010010000100010000001100101001100010100111010011110001110001110001101101000001110000
|
||||
01011101100000110010010011100100000110100010010000010001011100011001001011001001001010011000110001001110001000000110100000100010
|
||||
01101101010010101001001110000010110010001011010000101001110000000000000000000000001001011001110000000000000000000000000000000000
|
||||
01001101001010000100011100000100110100100100110100100111000100010010111000101001010111101010010100100100110000100001100100100110
|
||||
01100000101110100000110011100010001001000011001111000000111000100001000110010010101100001010101010100100101001100000100000110000
|
||||
01011110100000000000000000000000000000000010011110010000000000000000000000000000000000000110110000100100000000111010100010111111
|
||||
10000010100010100111100101011000100101001100010001101011111110000101101010010101110100100100011011000010101100001100100111100000
|
||||
11010110100100010100010100001110110000111011000001100110000001110001000001001010010110001001011001110000000101100000000000000000
|
||||
00111100100000000000000000000000000000000000000001010011000101100001010000010101101000000001100001010100111011010000111001010100
|
||||
01110000111101000001010100011010000011000011001100001010011000111101000111001000101100010110110100000110011111101000011001010110
|
||||
10010101000010000011011010011010011001110000000000000000001100000111000000000000000000000000000000000000000001000001010100100001
|
||||
10010000100000111010000010011010001001110000010010010101001101000001101100000010000101110010010101010000010001010011001001010110
|
||||
00010111010111110001001100100011101000001110000001010001011000010101100011000010011101001101001101000001000011001101100100101010
|
||||
00010000010001010011000000000000000000000000000000100001100111000000000000000000000000000000000010001110100110011111101000000100
|
||||
11110001001001010100110001000001011001000111001000010011011100010001001001001000100101100001100110100011000100001100001000010010
|
||||
01001010000101101100001000000000100110000000000000000000000000000000000000000000000000000000010001000011100101001010110010101010
|
||||
01111000011001111001010101110100000110100101011000110101010011100011000101010100010110100010010000010011110010100110000101001110
|
||||
01000000010001010000110011010011110001100111001000010100110011010010001011111100001101100101010101010001110010110010010101000000
|
||||
01110001000010010000000000001100000111000011111000000010010001001100000000000000000000000000000000010101010001110000111000001011
|
||||
00000100101101001110110000111001100001100011001100101100101111000010011000110011000001001100100101011000101101000101000111001110
|
||||
10101011010000101010111001101110100000010010010001111100000011001100010000111100010100100011100101010010011001010100000101100110
|
||||
10010100100101100111000000000000001001000000000000100111001000100100101000000000000000000000000000000000100100100010000010001011
|
||||
00100001100111100100111000100001001000100100001000111001111000011001111100100001001100011000100111010101100110001001000010010101
|
||||
00101110011001010011111100100001001011110000100010011001100001010100101001000101101001010000000000000000100011000000000000100101
|
||||
00001010100000000000000000000000000000000001001011000110010000001011011001001000010100100001001000010011011001001000101111100001
|
||||
01001000100011010000110100101001010100101100100010011001100010101100000111010001000110010000110110110001001001100001001100000000
|
||||
00100001100111000000000001011101100011000001100100100000000000000000000000000000000000001000101000000010010000100001100110100000
|
||||
00111000010111110001011110010000000100000110110000010101010001100100000100101110111000001001100110001010110010000000110010010001
|
||||
00001100100010010011010000011110010000011000100101010011000011101000001100111000000000000000000100001000001001110000000000000000
|
||||
00000000000000000000110101111100110110011000111111011111111111000101000111101100001011101110110111100001110001001111110011001001
|
||||
10111111010110011101000001111110111011110111011111101100011111111011111110000100110110000010111101010100111100111111111100001001
|
||||
10101000111010000001111001100101000011111100001110111111011111110011000010101000111111111001010001110001000100110000000000000000
|
||||
00000000000000000000000000000000000000000000001000101110101010010010010100000101000111010100010010011111100111110011000100011111
|
||||
11010101101010111100100011100010001000111100110001010010001010001100001100011110011001001001111111100111001000010001101100100010
|
||||
11001100001110001001110110011011000011001101010101100111110011000011101010101110111011100011011110010011001001010001000011000111
|
||||
10011111101001001111011011100111100011000000000000000000000000000000000000000000000000000000000000000010001011101011110100100111
|
||||
11101100011111101111010001001011010001111001000011000101011111100000100100110001001111100010001000111101111111111011100001111001
|
||||
11011111111001000100010010011000000111111110000110000110011000011111100100010100101100111111100011011000011001101110111010010111
|
||||
11110111111001100101111010101111101110101100011001111101111101100000111110111111101111111011111001100010001100000000000000000000
|
||||
00000000000000000000000000000000000000011101001010100001110110011000101000111011111101111111100111111100101100111111111110111010
|
||||
00010111100110010011010100010100001111001110111101110101111001111111101010110000111001100111110010000100110110011001111101010100
|
||||
01111000110100110110111011111101010000101000111001100001111011111111101110101100111111101000011011101111010000111111101111111111
|
||||
00100110000000000000000000000000001111110000000000000000000000000000000000000001100000011100100010001000100000010001110111000100
|
||||
00000111000010000101011001001110011000000111001000111000010000110001001110010010001110111000110001001110010010001110111000100000
|
||||
00100111001000000010011100100100000000000000000000000000000000000000000000000000000000000000000000100110000001100000101000001011
|
||||
00010000100010011100000000000100000000010000000000000000000000000000000000000000000000000000000000000000000000000001000000000100
|
||||
00110011010001100000000100010000000000100111001100010010100110000000100101000110010001010011000000000000101101000000000000000000
|
||||
00000000000010000110011000000000000000000000000000000100001000000100111100110000010010000010111010011000010000101001100010011100
|
||||
10011000100110000100111000100100110100010000100111001000110100010100111000000000000000000000000000000000000000000000000000000000
|
||||
00000000001001001001000000100110000101101010110000100111111000000110001110001010000100101011000100100000100010000110001100100100
|
||||
00100010000100000100010100111000000000000000000000000000000000100010000000000000000000000000000100000000000000000010010100000110
|
||||
00001010100100010011110000000101100001000111001010000010010100000000001000000000000000000000000000000000000000100000000000000000
|
||||
10001100000000000000000000100001110100010010001000001000011000110001000010000010000110011001000100001011010000000000100100010010
|
||||
10000100011100101000000000000110000001100000000000000000000000000000000000010010100000000000000000000001001111011100000100011000
|
||||
00001001011000100000100111000100101000001001010000100110000001000111001100000000000000000000000000000000000000000000000000000000
|
||||
00000000000100110000001000001000111001000000111010000000001001000000010001100000100001000000101100000101011100010111010000000001
|
||||
00001000000000000000000000000000000000000000100110000000000000000000000000000000000010000111100100101001101101000010101001101110
|
||||
01001000100101100110100101010011111000010100100110111100100010010110000110000110011010011100100111100010110011000010001011101000
|
||||
00010000010101101011010010010101000011001110000010011100010000000000000000000000000000000000100011000000000000000000000000000100
|
||||
00000000001110000001110001011010011000010010110111100100111100011110000001110010011001001000110000001100100011000100011100100110
|
||||
10000101000001001011001001001001000011000101000001101100100100011011000000111100100110001110000011001010010100011010010100110000
|
||||
11011110010000000000000000000000000000000000000000000000000000000000000000000000100101100001110000110010000100010011011100000010
|
||||
10010000010011011000010100100101110000010111001000010100100000100011100100000101101100110100110110000001100010000110011111001000
|
||||
10100110001000101001011001100000100101000000000000000000000000000000000000000000000000000000000000000001000010100010100000101010
|
||||
10001100110001100110001111101101000011000000111100011010100000111000100000100000010010100010011010011010000110011001001111100100
|
||||
01010110111010110101001111001100110000101110110011100011101110001000100100100001111010100011000100101100001010100011010010001000
|
||||
01110010000110101010101000000000000000000000000000000000000000000000000000000000000000011000010101001111000000000011010001011100
|
||||
10000111100010000001101001010100011111010000001101100000010000001010101001111001000110100010110101111001001011010011100100100100
|
||||
01011000010101000011001100100001111001000010001101010010100001111000010010000010001110101000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000010001010101110001100010111010010001111011000111001010011010000101001001110000010001001100111010
|
||||
10001001101000010010011010011001110000100001110110001100110100100110001100001100100010011011000101001100001000001010011000011001
|
||||
00011100100000100100000000000000000000000000000000000000000000000000000000000000000000011101010000100000110010001010011000100011
|
||||
01001011101001010100110100001110000110110110111010000011101100000100101000100010100110011101000000010011010011101010010010010110
|
||||
01100010010101011111101100000000010000010011100000000000000000000000000000000000000000000000000000000000000000010010010011111011
|
||||
00100110011000000011001001001100001010101111000100000010010001001001001011000101011001000001000110100100100100110000101010011010
|
||||
10110100000011000110101100100101001100010100010110110011000001100010110110110010000001000110000000000000000000000000000000000000
|
||||
00000000000000000000000000000000100010111000101010110010011000101100100101010011011010000101001011001001100100110100001101011010
|
||||
00101000101000011001100010010110010010011010000110101000011000110011000111010100010010011000010101001000010001110001010101110000
|
||||
00000101001000000000000000000000000000000000000000000000000000000000000000000000010010110000111001100000001011111110010010100100
|
||||
10010010001101001111110000100110100011010000010010101000110110010010010000000110000101011011000000100011010000101000000000100101
|
||||
11000001011110100100001110000001100010101100100111000100100000000000000000000000000000000000100110000000000000000000000000000000
|
||||
00000011010000101001010100001001011001001101000100110001010011101000001100100101101001100111100111010000010000010111101000111010
|
||||
10100101000100101010000001011101001110100111100101010011001010011011110110100001010000110010000000000000000000000000000000001001
|
||||
00000000000000000000000000000000000000100011101011100111010011010100110000010101111100100001001111001111110101100010000010001110
|
||||
00011010100110110100010010111100000011001100011001001101001001101100000001100101011110010101011000100101001010100110010000011010
|
||||
00010101001111000000110011001000101110001000101010001100000101100011000000000000000000000000000000000000000000000000000000000000
|
||||
10000010011000000010001010110110001011011000000001000000100010111000000111010000011100010100100000100101100000100110010010010001
|
||||
11001111000111001000001101000101100101011101000001001001101000001100001110100001000100010100000010011000010001001001010000100000
|
||||
10011100000000000000000000000000000000000000000000000000000000000000000000110010010100001011001101000101100111100011010000011000
|
||||
11000100111110110001010010000110100000101110000001001101000010110110011001110100100100101100111010001011011010000010011010000011
|
||||
10100100110010100110001100011101000001100100100100111001001111000011101100000000000000000000000000000000000000000000000000000000
|
||||
00000000000000001000001101000001000000111000100011100001001001100110010010011001001001000100011100000011001011000011001110010010
|
||||
01000001000110010010001001011000001000101001010110000010110001010000010011010010000100010100011000000100100000000000000000000000
|
||||
00000000000000000000000000000000000000000110100010011100000011110010000100000100110010000010000111001100001001111001001000001000
|
||||
00100001101001010101001100010100010001011001000010100011100000110010100110011110011110011000100000111000100101001100101100011010
|
||||
00010100111001100100001100000111001000001001001011001000011010111101011000101010000000000000000000000000000000000000000000000000
|
||||
00000000000000011101111111111110101011111101111010000111110111010111001111111110111111101101100110011101000011101110011001110011
|
||||
00010011011110011001010000101000100111010100011100110011001101010001010000101000111100110001010001101111111010100011111100000111
|
||||
10011001110111110011111011001010000101000000111000100000000000000000000000000000000000000000000000000000000000000000000101000101
|
||||
00010010010100011011111111000111100100010110000110110010010100010100010001101111110111100100111111100100111100110011000100111001
|
||||
00011111111010111111100001001001110111111101101100011111111111011110111111001001110111111110100110010001111011111111010001001001
|
||||
10111011111101100001000111010001010001001001001101111001100100011111111101000011100010111000110000000000000000000000000000000000
|
||||
00000000000000000000000000000001111111110101000100100101000101000001100010011011111110000011111111011100010100011101111111100110
|
||||
11111000011101100110011110100010001101101111110110111110001111001100101101000100100100010101110001110100011000011100100101111000
|
||||
10000110011111110100011001100001101111111111000100110001101111001111010100000110011111100011111011110000000000000000000000000000
|
||||
00000000000000000000000000000001111111010111110111101111111110111001100001100100001111010000001111111000100111010100011001001100
|
||||
10100011001100111001101010000010100011011011111001101100110011101010100001110011001111100110011001101100001011111110111001001011
|
||||
00111011001111111111101111100001101000111001100110011011111101111101110111011110111111001110110011011100010100000000000000000000
|
||||
00000000000000000000000000000000000000000000001100000011100100011100001000010000000100111001000000010011100100001001001110010000
|
||||
00011100001000010101100100111001000000100011111100010000101011001001110010000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000010011000010001001001010000010011000010010000000001000000000010100100000000000010000100000000000000000000100101
|
||||
10000000000000000010011001000011001100000000000000000000000000000000000001000111101011000000000100111011010000101001100010111001
|
||||
01111100110000011001000101001101000010000000100010000010010100000000000000000000000000110000101010100100000000000100111110110000
|
||||
00010011000000000000000000000000000000000000011100010001001100001001101001001000011001100100010100110100011100011010001100000010
|
||||
01000000100001010011011100100000100000000010010000000100000000000000000000000001000111001100010000010011100000000010011101000000
|
||||
00000000000000000000000000000000000000001010110101010010010001100010101001101000100100011100110000000000000110100000110111100000
|
||||
00000000000000000000000000000110010000100001001100000000000001000110000000000000000000000000000000000001000000000010011010010000
|
||||
00100101000010111110011011001001010000000000101001010011100100011000000000000000000000000000010010100000011001110000000000000000
|
||||
00000000000000000000000100011010000111010000011000010000000000000000100010100011000000000011000011010000010110110010100000000000
|
||||
00000000000000001100001010110100001000011000011110000000011001111001001110010011000000000000000000000000000000000110000010100001
|
||||
01100000100011010011000001000110000010001100000000100001010011001000010001000000000000000000000000000000000100011110100000100011
|
||||
01001111011000000111001110100000100000000000000000000000000000000000001001100010001100000100001100100000000000001110100000100011
|
||||
00000000110100000110000110110000000100101000000000000000000000000000110010000100001010100100001000000000000001001100000000000000
|
||||
00000000010011101000001101010010100011100101100111001000010000010101101011000010000000100101010010000100011000101101100000100110
|
||||
01100001100001001000000000000000000000000000010101000000000000000110011100011000110000000010000000000001000110000000000000001000
|
||||
00000000010011010001101001111001000011010000011101000100001001101001111100011000100111011000000111001000100011101111110111010010
|
||||
00110011010010011110001101100111100011111011100001001101101000100001001101011001000101000011000101000000000000000000000000000010
|
||||
00000000010111111000011110000000011001111001001110100001100111000000001011000000000000000000000000000001001101001010010000110001
|
||||
11110001000100011000010010000110100100110000110010111010010011001110010010110110100101110110001100010011110001110010111000101001
|
||||
01001010011111000110001001000000000000000000000000000000000011010011110000000000000000000000000000000000000000010010010001111000
|
||||
10010110000101010011001001001000001000001000001001110110010001001101000101100000110000001100110011000100011101010000010011011100
|
||||
00001110101001000100111110100001010101111010100010111000100001001001000010100111000000000000000000000000000000000110011110000000
|
||||
00000000000000000000000000000000100001100111100100110010000111100000010001100011000010011000000100111100110100100010110110000101
|
||||
00111010010011001001101011110100111010001010100111010001101001100010010101001001010100000000000000000000000000100111010011100011
|
||||
00001111001100111000000000000000000000000000000000000000100100010111110001011000011000110001010101110010001111001001011000010110
|
||||
01001101000101100100010100011100100100001100110100101101110100111011110100000010010111010010100111001010001000010110001010000010
|
||||
01111000001001001001110000000000000000000000000100010000110000001100000000100101010100100000000000000000000000000000000001001010
|
||||
10011001010100100101100010100010101001100110010001101001001010111010101010011011000100001101011100011001001011100100101100110100
|
||||
11001000111000011001100000100010001000010000000000000000000000000100100000010000000000000010011110100100000000000000000000000000
|
||||
00000000000100010110000010110001010011100100001100000110010001100111000100011000101101001000001000111100100100100100110110010001
|
||||
00011000110000101101000001110000001111000011010011111100100001001110100011100001100110100111000000000000000000000000000000000000
|
||||
01000101111001000010010000000000000000000000000000000000010011000110001100001100010100111010000010010100110100001010010001001011
|
||||
10001001010011011010000011100100100111001000001000010001001111001010010011101001011011010101101110011101010011000100100101101110
|
||||
00110001001000000000000000000000000000000001000101011100000010010100000000000000000000000000000000010010000100100100101101010100
|
||||
10000111000010010001001000110100000100010010011010010100110001100110111110010110000100100001101101110111000010110111101000000100
|
||||
10101100011000000100100100000010001100000000000000000000000000000000000000001000011001110000100001100111000000000000000000000000
|
||||
00000100010100100100111010011001001010100111100110100110100101110001010001001011001000100000110010010011010010011001110010001011
|
||||
00010010110011001001001001000100010010110011010000110010110010110000110010101001100000000000000000000000000000000000000001000100
|
||||
00000000000000000000000000000000000000100000100000010000010011010001011001010101100000101110000001100010000111000011011001111001
|
||||
10011001100001000011001101100000111001000001000100100111100110110100010001100100110100000110000001110101000101001110010001010011
|
||||
10000000000000000000000000000000000000000011111000000010010101001100000000000000000000000000000000000111001000010011110010110010
|
||||
10010000110011100010001000101010100101011000001011010101010101110000001101100111000001010001010101101001110011010000011100001100
|
||||
11100000101001110010001110110100000000000000000000000000010001110001001101011000010111000010011101001000011001100101001110000000
|
||||
00000000000000000000000001011111100100101010101100110001100111100010000100001100101100110001000110001001101000001001001000110100
|
||||
00001001011000111101000001100101010001110000010010000011001100000100000000000000000001000100000000000010010110010000010011000000
|
||||
00000100011000000000000000000000000000000000001100110001011000110001000001001000100010001000010100001110100010001001101001000010
|
||||
00111001000100110110000010101100100001110000010110000110101111000101000100110010000101001110010000110000100000000000000000000000
|
||||
00001001010000000000100110001001110000000000000000000000000000000110001001001000101000001001100001101000001111000100111101100000
|
||||
10011010110110010011000010100100110100111110011000011000100101110000010111000010000110000010100100111001001111011111111000001111
|
||||
00100001001111001100100011100100000000000000000010011100000000000100010010011110111100000000000000000000000000000000000000000001
|
||||
01000111111001101100110000111111100101010001011100101000111001100110011011001111110100001111011101110100001110111111100010100001
|
||||
11011111111101100110011110111111010000101000110000110001010001111101010010000110011110011001010110101000000000000000000000000000
|
||||
00000000100110000000000000000000000000000000000000000001111101111101000100100111111000011001100111000111100110010101110100100111
|
||||
11101101110010000100011011001100111001001100001011101000100011101000100010100100111110011011011000101000111111011111111111101110
|
||||
01001111011111110000110010001111111111011111101110100100011111100000110000101010101110010011111110110000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000111111110000111111100111101100110101000111111011101010001001111000111010001110111
|
||||
01010010001010001000111100000011010010011111101101100100010011011111111010001001001110111011101000011000011111101000100100101110
|
||||
01100111100111011100011011100010100101000000000000000000000000000000000000000000010111000000000000000000000000000000000000001111
|
||||
11111011100010000101000101000011111111101111110000011101111111110010000100110111111110111101110111000011000001100001111100110110
|
||||
00001111000011000011101101111001101110111110111111110000111101110111111111110011000010111110111111011011001101100110011100110110
|
||||
00001011111011111011101110110000000000000000000000000000000000000000000000000000000000000000000000000011000000111001000100111001
|
||||
00000001001110010101100111000010000101011001110000100001000000011100001000010000000100110001000000010011100000000000000000000000
|
||||
00000000010000110111000001001100100001000000000000000000000000000000000000000000001100100010000010111100110001100000100000100001
|
||||
10110000000000001001100000010000100000000000000000000000000010010101001110000000010011100110000101010011000000000000000000000000
|
||||
00000000000001001010000000000000100110000010011100000000000010011100000000000000000000000000000001011111001100000000000000110111
|
||||
00000010011000000000000000000000000000000000000010011100000101101001000010100110001001100010001010000110011100000000001000110000
|
||||
00000000000000000000000000000100010100110001000001001110001001110111010000100000000000000000000000000000000000000000000000110100
|
||||
00010000000000000000000010001000001000000000000000000000000000000001100100001100011000100110000000100101100001011000001010000000
|
||||
00000000000000000000000000000001000110000100100000100010110001100001000110001001100000000000100001000000010010000000000000000000
|
||||
00000000010010100000000001100111100001000111000010000000000000000000000000000000100001100111000101010010011000000001000011101000
|
||||
00110011101010010000000100100100010000011001100101101000100100101000100100001001100000000000010011000000000000000101111100110000
|
||||
11000011110000000110011110010011100110100000100000000000000000000000000000000000100110010110010011000001001010001001101001110100
|
||||
10100010001110100100010011000001001001101000100100111000010011001100110000000000000001001001011000000000000000100010100110000110
|
||||
10011110010000110011101110100001000000000000000000000000000000000001000000001001000000000100000000000110000010100001010111000000
|
||||
00010101110000100001010110000000000000000000000000000011001000010000101010000000010000100000000000000100000000000000000001000101
|
||||
00111000000001001010100110000010111010100100100001101101100001100110000000100111000100010100110000101101010011100000000000000000
|
||||
00000000000000000000000001100111100110001100000000100000000000000000000000000001000000000000010110111010010101001011000110010000
|
||||
00000111001000110010011110001001001001100001011001101000101001000110011001001101110000010000001001000100011000001100000011000000
|
||||
00000100110000000000001000001100100010000010111111000011110000000110011110010011100000000000000000000000000000000000000101111100
|
||||
00011000101001001100010000100010011110010110010110001110001010111000101100110010010010000110010100011010001001100010100000100101
|
||||
11010000101001001011100000000000000000000000000000000000001101001111000000000000000000001000100000000000000000000000001001101010
|
||||
01100111100111000001010101100100010010111110000000011001100001000001100100010000011001010011000010100111000011100100100000011000
|
||||
00011101010000000000001000110000000000001100010100000000011001111000000000000000000000000000010100100100010100111000000110000110
|
||||
01001111011010000000010010011000001010101100010011000000001000111001001100000101010011010011000100000100001100110000001000111001
|
||||
00000000000000000000000000000000110000111100000000110011100000000000000000000000000000000000000000111001000010110110101010001100
|
||||
00001001000100000110000010111000011000000101101111001001110010110000101001010110000110010010011000100100110110010010100110001100
|
||||
00010100100000000000000000000000000000011000000110000000001001011001110000000000000000101100000000000000000000100101100010100101
|
||||
11011000001001111001100000001010011001110100011010011100010010000100010110110000011000010101101010001101010100111100110000101010
|
||||
10011001000100010011000000000000000000000000000000010000000000000001001000000000000000000000000000000000000010000110011110111111
|
||||
00001010100100000000100110110110000001101000110111100001011011000000001000001101000001101010100011100111100011100101100110010101
|
||||
01000011100000101101101110100100101001000100000100000100110010010100000000000000000000000000000000000000001111101000000010001000
|
||||
00000000000000000000000000000100101100110010001110000000000001001011000011110000101001001110010001111001000101001110010010100100
|
||||
11010011000011001001001010010010000010000101000110000000000000000000000000010010010011100111000010010111000000000000100011000100
|
||||
11100000000000000000000000000000100001010001111001010011110000010110101001000000010001100100100100010111010000001000010111010000
|
||||
11000111000100100011011000101011101110000001001011001001100001010101111000100110001110100000000000000001000011001110000000000010
|
||||
01100110010010000000000000001100100010100111000000000000000000000000000000000010011010001010000011100001000000001001011000101101
|
||||
00110010011110000111000100101010010100010010010000111001000010011110010110000001001000011010000101110000001100101001000110100110
|
||||
00000000000000000000000001001000000000000100000000000000000000000000000000000000000011000100101000111100100010110011000010010010
|
||||
01110000010000110000101100010110110110000010011001001000100001110100001010001110011101001001100001010011101100001000010100110110
|
||||
00110000100110001000101000001001101101000010100111000000000000000000000000000010001000000010111000100101010011000000000000000000
|
||||
00000000000000100101100001100000000000000010010001100010010010110110110001001101010010010001110010100010010110010101000001001111
|
||||
00110000000111001000000000000000000000000000000110011000000010111000000000100111001100100100010001100000000000000000000000000000
|
||||
01100110000010001110110011010010011110010000001001111000010100110100001100100111010000011010000100111010000010011000111001100110
|
||||
00010000110010010001000101000110001110000110100100000001000010000000000000000000000000001000100100110010011000000000010001101001
|
||||
00001000011001110000000000000000000000000001001101000001000100100010100001000101110100101100001001000101010100110100101001110000
|
||||
10010000110000000010011101001110110001001100100001100001001110010000000000000000000000000000000000100110001100011000000000100100
|
||||
00001001110000000000000000000000000000000010011011001000101101001010101010100111101010010000101010010101100001000001110100000010
|
||||
01100100011110011000000100100111001001111001010010011101000001001101100000011010010000000001001100000000000000000000000000100100
|
||||
10001001001111011110000000000000000000000000000000000000000000010000010011101111100110111011111100000111111010001111101111111111
|
||||
01000101110110111111101010001101010101011111101111111111001010100011111110110110011001111111111000110111011111111111100111111101
|
||||
11110011000001111011101000000000000000000000000000000000010011000000000000000000000000000000000000000001010000100100101110101000
|
||||
10001100001111111100110000110011101010101010001100110000101110101000011010101011101110111100100101000111111100110001111000000111
|
||||
01000100100101000111111110010001110100010100010010011111110110100011010100000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000111111111011111100000110011111111101111110000001000101110101110010010110100001000111101011111110001111101
|
||||
10011001111111110010110011000011111011111001011100001111111111100110001010100010100010010111100111111111011101001111101111100101
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000001111111100110111000001100100110110011111100000111
|
||||
00100000111011111011101000100110111001111111100001001101101011111110001111101100010011111111100100101000011000010111111111001011
|
||||
01111111111111111001110011111111101110100101000000000000000000000000000000000000000000000000000000000000000000000000000000000010
|
||||
00000100011101110000000001100000011100100100011101110001000000010011100100000010001110111000110000001110010010001110111000001000
|
||||
11101110000000000000000000000000000000001000011011100000000000000000000000000000000000000000000000100000101001101001000000000010
|
||||
10011001010000000000000000000010000000000000000000000000000000000000000000100110010000110011000000000000000000000000100010100101
|
||||
00000000000100001000000000000010010000000000000000000000001001101001010000000000100101100110000000000000000000000011011000000010
|
||||
01100000000000000000000000001001110000000000010001000000000000000000000000000000000000010101010010000000000001001001001000000000
|
||||
00000000000100111000000000111001000001000000000000000000000000000000100111000000000001000000000000000000000000000000000000000100
|
||||
01101001000000000000000000000000000000000000000000000000000000000000000000001100100100000000000000000000000000000000000100100000
|
||||
00000000000000000000000000000000000000000000000001100111100001000011001100000000000000000000000100001100110000000000000100101000
|
||||
00000001000011001010000000000000000000000000000000000100010000000000000000000000110000111100000001100111100100111001001100000000
|
||||
00000000000000001001100000000000000100101000000000000000000100101000000000000000000000000000000000000000000000000110000111100000
|
||||
01100000011100111010000000000000000000000000000110010010100000000000001001101001000000000000101110000000000000000000000000000000
|
||||
00001000000000000000000000000000010000100000000000000000000000000000000000000010001101001100000000010001010001101001100010010100
|
||||
00000000000000100100000000000000000000000000000000000000011001111001100011000000001000000000000000000000001000010000100000000000
|
||||
00100101010010000000000010010101001000000010001000000000100110000010011110110000000000000000000000000000000000010000111000011110
|
||||
01100111100100111000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000100
|
||||
11000001100001111000000000000000000000000000000000010000100000000000001100100100011100100000000000011001100001110100100011100100
|
||||
00001000110000000000010010000000000110000001100000000000000000000000000100100000000000000110011110000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000001001000000001001110000000000000000010011101001110100010011000011110000000110011
|
||||
10000000000000000000000000000000000000000000000000000000010001100001000100000001000110000000000000000000000000000000000000100010
|
||||
00100000000000000010010100000000000000000000000000000000000000000000000000000100101000010000000000000000010011100000000000010010
|
||||
00000001000011001110010110000000010010010101000110000010100000000010011100000000000000000000000000000000000000000000000000000000
|
||||
00000000010011000001000010011001100000001001010000000000000000000000000000000000001111001000000000000000000000000000000000000000
|
||||
00000000000000000000000000100000000000000000000000000000000000000000000010001000010011010011000000100100000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000110011000000000000000000000000000000000000000000000000000
|
||||
00000000000000000001100000101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000001001110001100110000000000000000000000000000000000000000100111001000110001111100000010011000000
|
||||
00000000000000000001000110000000000010011000000000010000001000110000000000000000000000000110101100000000000010001101001100000000
|
||||
00000000001001100000000000100111010001111000110000111001100000000000000000000000000000000000011010001000111001100010011100000000
|
||||
11011000000111011000000000000000010001100000000110010010000000000000100101000000000000000001000110000000001001010010001100000000
|
||||
00000000000000010011000000000010001000000000000100010000000000000000000000000000000000001100000101000100100000000000000000100100
|
||||
01110110000000000011000110000010010001001110000000000000000000001101000100000000000010011110001001110000100000000000100010010011
|
||||
00000000000001001100000000000100111000000000001010100000000000000001010010010000100000000011100100000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000010000100000000000000000000000100001000000000000000000000001000010000000000000000010000
|
||||
10000000000000000000000010000100000000000000000000000110011001000000000000000000000000110011001000000000000000000000000110011001
|
||||
00000000001111010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
|
||||
10000001110110000000000000000000000000000010000001001111100001001000000000000100101100001000000000010010110000100000000000000000
|
||||
00111000010010001110011010010110000100000001110000100100011100110100101100001000000000000000000000000000000000000000000000000000
|
||||
00010001111011000000000000000010011000000000000100110000000000000000000000011100000101010010010001000000001110000010111100100000
|
||||
10001000000000000000000000000000000000000000000000000000000101101111000001010000000000000001001110000000000010011100000000000000
|
||||
00000000001001011001100000000010000010000111001000011001100000000000000000000000000000000000000000000000001000000111000000110010
|
||||
00000000000000000000000000000000000000000000001000100100110000000001000001000101001111001100000000000000000000000000000000000000
|
||||
00000000000000000000010110111010000011001100000000110000011011000110001000001111111001111110000000000001100000110110001100010000
|
||||
01111111001111110000000000000000000000001000101001001110011001111010000111101000000000000100010100100111001100111101000011110100
|
||||
00000000000000000000000000000000000000000000000000000101101110100000110011000000001100000110110001100010000011111110011111100000
|
||||
00000001100000110110001100010000011111110011111100000000000000000000000000111001100111111000011111100000000000001000001110011001
|
||||
11111000011111100000000000000000000000000000000000000100111000000000000000001001110000000000000000000100001100011100011100111100
|
||||
11101100000110110001100011000110011110000001100111000000000000011000001101100011000110001100111100000011001110000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000001000011000111000111001111001110110000011011000110001100011001111000
|
||||
00011001110110000011011000110001100011001111000000110011100000000000001100000110110001100011000110011110000001100111000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000010001100000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000100000100011000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000100001100011000000000000000000000000000000001001010000000000000001110001
|
||||
01000000001100100110110111111111111111111111111111111111111111111111111111111111111111111100001010000000000000000000000000000000
|
||||
00000000000000000000000000101010101001110010001000000000000000000000000001000000000000000000000000000000111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111101011110000000000000000000000000
|
||||
00100001000000000000000000000001000010000000000000000000000000000000000000000000000100001000000000000000000000001000010000000000
|
||||
00000000000001100110010000000000000000000000001100110010000000000000000000000001000010000000000000111111000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
|
||||
01001111011010000000000001001011000010000000000100101100001000000000000000000000010010110000100000000001001011000010000000000000
|
||||
00000000000000000000000000000000000100011110110000000000000000100110000000000001001100000000000000000000000010011000000000000100
|
||||
11000000000000000000000000000000000000000000000000000000000101011111000001010000000000000001001110000000000010011100000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000100000010011100000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000101011110100000110011000000001011111100011000100000
|
||||
11111110011111100000000000010111111000110001000001111111001111110000000000000000000000001000101001001100011001111010000111101000
|
||||
00000000010001010010011000110011110100001111010000000000000000000000000000000000000000000000000000000101011110100000110011000000
|
||||
00101111110001100010000011111110011111100000000000010111111000110001000001111111001111110000000000000000000000000011000110011111
|
||||
10000111111000000000000001100011001111110000111111000000000000000000000000000000000000000000010011100000000000000000100111000000
|
||||
00000000000000000001011111100011000110001100111100000011001110000000000000101111110001100011000110011110000001100111000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000010000110001110001110011110011101011111100011000110001100111
|
||||
10000001100111010111111000110001100011001111000000110011100000000000001011111100011000110001100111100000011001110000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000001000110000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000010000010001100000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000010000110001100000000000000000000000000000000100101000000000000000111000101000000
|
||||
00010100101010001111111111111111111111111111111111111111111111111111111111111111110000101000000000000000000000000000000000000000
|
||||
00000000000000000010101010100111001000100000000000000000000000000100000000000000000000000000000001011110000000000000000000000000
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
*
|
||||
NOTE END CONFIG DATA*
|
||||
L48896
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
L52736
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
|
|
@ -1432,10 +1431,10 @@ L171648
|
|||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
*
|
||||
C91ED*
|
||||
CA693*
|
||||
NOTE FEATURE_ROW*
|
||||
E0000000000000000000000000000000000000000000000000000000000000000
|
||||
0000010001100000*
|
||||
NOTE User Electronic Signature Data*
|
||||
UH00000000*
|
||||
362B
|
||||
4DD3
|
||||
|
|
|
|||
|
|
@ -8,31 +8,31 @@ Design Information
|
|||
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
|
||||
RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
|
||||
loud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
|
||||
lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
|
||||
loud/Repos/ram2e/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
|
||||
lpf -lpf //Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset
|
||||
//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:34:46
|
||||
Mapped on: 12/28/23 23:23:28
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 111 out of 877 (13%)
|
||||
PFU registers: 75 out of 640 (12%)
|
||||
PIO registers: 36 out of 237 (15%)
|
||||
Number of SLICEs: 120 out of 320 (38%)
|
||||
SLICEs as Logic/ROM: 120 out of 320 (38%)
|
||||
Number of registers: 122 out of 877 (14%)
|
||||
PFU registers: 93 out of 640 (15%)
|
||||
PIO registers: 29 out of 237 (12%)
|
||||
Number of SLICEs: 148 out of 320 (46%)
|
||||
SLICEs as Logic/ROM: 148 out of 320 (46%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 9 out of 320 (3%)
|
||||
Number of LUT4s: 239 out of 640 (37%)
|
||||
Number used as logic LUTs: 221
|
||||
Number of LUT4s: 296 out of 640 (46%)
|
||||
Number used as logic LUTs: 278
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 70 + 4(JTAG) out of 79 (94%)
|
||||
Number of PIO sites used: 69 + 4(JTAG) out of 79 (92%)
|
||||
Number of block RAMs: 0 out of 2 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
|
|
@ -52,70 +52,90 @@ Design Summary
|
|||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 1
|
||||
Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
|
||||
Number of Clock Enables: 11
|
||||
Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
|
||||
Net N_576_i: 17 loads, 9 LSLICEs
|
||||
Net LEDEN13: 4 loads, 4 LSLICEs
|
||||
Net nCS61: 1 loads, 1 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
|
||||
Net C14M_c: 89 loads, 73 rising, 16 falling (Driver: PIO C14M )
|
||||
Number of Clock Enables: 14
|
||||
Net N_225_i: 2 loads, 0 LSLICEs
|
||||
Net N_201_i: 2 loads, 0 LSLICEs
|
||||
Net N_187_i: 11 loads, 11 LSLICEs
|
||||
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
|
||||
Net RC12: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/CmdBitbangMXO2_RNINSM62: 8 loads, 8 LSLICEs
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
Design: RAM2E Date: 12/28/23 23:23:28
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net N_104: 1 loads, 1 LSLICEs
|
||||
Net N_88: 4 loads, 4 LSLICEs
|
||||
Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net ram2e_ufm/wb_we_RNO_0: 1 loads, 1 LSLICEs
|
||||
Net N_185_i: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0]: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0]: 1 loads, 1 LSLICEs
|
||||
Net N_126: 6 loads, 6 LSLICEs
|
||||
Net un9_VOEEN_0_a2_0_a3_0_a3: 1 loads, 1 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Number of LSRs: 7
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net BA_0_sqmuxa: 2 loads, 0 LSLICEs
|
||||
Net S[2]: 1 loads, 1 LSLICEs
|
||||
Net N_566_i: 2 loads, 0 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/wb_rst16_i: 1 loads, 1 LSLICEs
|
||||
Net N_1080_0: 1 loads, 1 LSLICEs
|
||||
Net N_1078_0: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 48 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[0]: 30 loads
|
||||
Net FS[12]: 22 loads
|
||||
Net FS[9]: 21 loads
|
||||
Net S[1]: 21 loads
|
||||
Net FS[10]: 20 loads
|
||||
Net FS[11]: 19 loads
|
||||
Net RWSel: 19 loads
|
||||
Net FS[13]: 17 loads
|
||||
Net S[2]: 50 loads
|
||||
Net S[3]: 45 loads
|
||||
Net S[0]: 37 loads
|
||||
Net S[1]: 34 loads
|
||||
Net FS[12]: 24 loads
|
||||
Net FS[11]: 22 loads
|
||||
Net FS[10]: 19 loads
|
||||
Net FS[13]: 19 loads
|
||||
Net FS[9]: 19 loads
|
||||
Net FS[8]: 18 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 1
|
||||
Number of warnings: 3
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
Design Errors/Warnings
|
||||
----------------------
|
||||
|
||||
WARNING - map: //Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.lpf(93): Semantic
|
||||
error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
|
||||
"nWE80" does not exist in the design. This preference has been disabled.
|
||||
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
temporarily disable certain features of the device including Power
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
discarded.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 12/28/23 23:23:28
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | |
|
||||
|
|
@ -124,20 +144,6 @@ IO (PIO) Attributes
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| C14M | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| DQMH | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| DQML | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS33 | |
|
||||
|
|
@ -152,45 +158,39 @@ IO (PIO) Attributes (cont)
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
| DQMH | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
| DQML | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[9] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[8] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
| RAout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
| RAout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CKE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nVOE | OUTPUT | LVCMOS33 | |
|
||||
| nRWEout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 3
|
||||
|
|
@ -198,10 +198,20 @@ IO (PIO) Attributes (cont)
|
|||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
Design: RAM2E Date: 12/28/23 23:23:28
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| nCASout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRASout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCSout | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CKEout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nVOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
|
|
@ -220,21 +230,21 @@ IO (PIO) Attributes (cont)
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| nDOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
|
@ -248,6 +258,16 @@ IO (PIO) Attributes (cont)
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 12/28/23 23:23:28
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| Din[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | |
|
||||
|
|
@ -258,16 +278,6 @@ IO (PIO) Attributes (cont)
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| Ain[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[3] | INPUT | LVCMOS33 | |
|
||||
|
|
@ -282,8 +292,6 @@ IO (PIO) Attributes (cont)
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| nEN80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI1 | INPUT | LVCMOS33 | IN |
|
||||
|
|
@ -293,77 +301,84 @@ Removed logic
|
|||
-------------
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal Dout_0_.CN was merged into signal C14M_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
|
||||
Block ram2e_ufm/GND undriven or does not drive anything - clipped.
|
||||
Signal CKEout.CN was merged into signal C14M_c
|
||||
Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
Design: RAM2E Date: 12/28/23 23:23:28
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block Vout_0_.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
Block nCASout.CN was optimized away.
|
||||
Block ram2e_ufm/ufmefb/VCC was optimized away.
|
||||
Block ram2e_ufm/ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
|
|
@ -372,9 +387,19 @@ Embedded Functional Block Connection Summary
|
|||
|
||||
Desired WISHBONE clock frequency: 14.4 MHz
|
||||
Clock source: C14M_c
|
||||
Reset source: wb_rst
|
||||
Reset source: ram2e_ufm/wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 12/28/23 23:23:28
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
SPI Function: DISABLED
|
||||
Timer/Counter Function: DISABLED
|
||||
|
|
@ -390,16 +415,6 @@ Embedded Functional Block Connection Summary
|
|||
None
|
||||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
None
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
|
|
@ -418,7 +433,7 @@ Embedded Functional Block Connection Summary (cont)
|
|||
ASIC Components
|
||||
---------------
|
||||
|
||||
Instance Name: ufmefb/EFBInst_0
|
||||
Instance Name: ram2e_ufm/ufmefb/EFBInst_0
|
||||
Type: EFB
|
||||
|
||||
Run Time and Memory Usage
|
||||
|
|
@ -426,7 +441,7 @@ Run Time and Memory Usage
|
|||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 58 MB
|
||||
Peak Memory Usage: 59 MB
|
||||
|
||||
|
||||
|
||||
|
|
@ -436,21 +451,6 @@ Run Time and Memory Usage
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ Performance Grade: 4
|
|||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Thu Sep 21 05:35:00 2023
|
||||
Thu Dec 28 23:23:38 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
|
@ -23,7 +23,7 @@ Pinout by Port Name:
|
|||
| BA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| BA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| CKEout | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQMH | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Din[0] | 96/0 | LVCMOS33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
|
|
@ -34,28 +34,28 @@ Pinout by Port Name:
|
|||
| Din[5] | 99/0 | LVCMOS33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 88/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 87/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 30/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4A | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[2] | 25/3 | LVCMOS33_OUT | PL7D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[4] | 24/3 | LVCMOS33_OUT | PL7C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[5] | 21/3 | LVCMOS33_OUT | PL7B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6A | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[0] | 30/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[2] | 25/3 | LVCMOS33_OUT | PL7D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[4] | 24/3 | LVCMOS33_OUT | PL7C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[5] | 21/3 | LVCMOS33_OUT | PL7B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| LED | 35/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| PHI1 | 85/0 | LVCMOS33_IN | PT9D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[1] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[2] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[5] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[6] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[7] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
|
|
@ -73,15 +73,14 @@ Pinout by Port Name:
|
|||
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nC07X | 34/2 | LVCMOS33_IN | PB6C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCASout | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCSout | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nDOE | 20/3 | LVCMOS33_OUT | PL7A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nEN80 | 82/0 | LVCMOS33_IN | PT10C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRASout | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWEout | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nVOE | 10/3 | LVCMOS33_OUT | PL3D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nWE | 29/2 | LVCMOS33_IN | PB4C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nWE80 | 83/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
|
|
@ -144,32 +143,32 @@ Pinout by Pin Number:
|
|||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
|
||||
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | nRWE | LOCATED | LVCMOS33_OUT | PR7D | | | |
|
||||
| 52/1 | nCAS | LOCATED | LVCMOS33_OUT | PR7C | | | |
|
||||
| 53/1 | CKE | LOCATED | LVCMOS33_OUT | PR7B | | | |
|
||||
| 54/1 | nRAS | LOCATED | LVCMOS33_OUT | PR7A | | | |
|
||||
| 57/1 | nCS | LOCATED | LVCMOS33_OUT | PR6D | | | |
|
||||
| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR7D | | | |
|
||||
| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR7C | | | |
|
||||
| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR7B | | | |
|
||||
| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR7A | | | |
|
||||
| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR6D | | | |
|
||||
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
|
||||
| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
|
||||
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
|
||||
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
|
||||
| 67/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR3C | | | |
|
||||
| 68/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3B | | | |
|
||||
| 69/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3A | | | |
|
||||
| 70/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR2D | | | |
|
||||
| 71/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2C | | | |
|
||||
| 74/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2B | | | |
|
||||
| 75/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2A | | | |
|
||||
| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
|
||||
| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
|
||||
| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
|
||||
| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR3C | | | |
|
||||
| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR3B | | | |
|
||||
| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR3A | | | |
|
||||
| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR2D | | | |
|
||||
| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR2C | | | |
|
||||
| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | | | |
|
||||
| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | | | |
|
||||
| 76/0 | unused, PULL:DOWN | | | PT11D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
|
||||
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT11A | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
|
||||
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT10C | JTAGENB | | |
|
||||
| 83/0 | nWE80 | LOCATED | LVCMOS33_IN | PT10B | | | |
|
||||
| 83/0 | unused, PULL:DOWN | | | PT10B | | | |
|
||||
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT10A | | | |
|
||||
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT9D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT9C | SCL/PCLKT0_0 | | |
|
||||
|
|
@ -213,7 +212,7 @@ LOCATE COMP "Ain[7]" SITE "8";
|
|||
LOCATE COMP "BA[0]" SITE "58";
|
||||
LOCATE COMP "BA[1]" SITE "60";
|
||||
LOCATE COMP "C14M" SITE "62";
|
||||
LOCATE COMP "CKE" SITE "53";
|
||||
LOCATE COMP "CKEout" SITE "53";
|
||||
LOCATE COMP "DQMH" SITE "49";
|
||||
LOCATE COMP "DQML" SITE "48";
|
||||
LOCATE COMP "Din[0]" SITE "96";
|
||||
|
|
@ -234,18 +233,18 @@ LOCATE COMP "Dout[6]" SITE "31";
|
|||
LOCATE COMP "Dout[7]" SITE "32";
|
||||
LOCATE COMP "LED" SITE "35";
|
||||
LOCATE COMP "PHI1" SITE "85";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "68";
|
||||
LOCATE COMP "RA[2]" SITE "70";
|
||||
LOCATE COMP "RA[3]" SITE "74";
|
||||
LOCATE COMP "RA[4]" SITE "75";
|
||||
LOCATE COMP "RA[5]" SITE "71";
|
||||
LOCATE COMP "RA[6]" SITE "69";
|
||||
LOCATE COMP "RA[7]" SITE "67";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RAout[0]" SITE "66";
|
||||
LOCATE COMP "RAout[10]" SITE "64";
|
||||
LOCATE COMP "RAout[11]" SITE "59";
|
||||
LOCATE COMP "RAout[1]" SITE "68";
|
||||
LOCATE COMP "RAout[2]" SITE "70";
|
||||
LOCATE COMP "RAout[3]" SITE "74";
|
||||
LOCATE COMP "RAout[4]" SITE "75";
|
||||
LOCATE COMP "RAout[5]" SITE "71";
|
||||
LOCATE COMP "RAout[6]" SITE "69";
|
||||
LOCATE COMP "RAout[7]" SITE "67";
|
||||
LOCATE COMP "RAout[8]" SITE "65";
|
||||
LOCATE COMP "RAout[9]" SITE "63";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
|
|
@ -263,15 +262,14 @@ LOCATE COMP "Vout[5]" SITE "16";
|
|||
LOCATE COMP "Vout[6]" SITE "14";
|
||||
LOCATE COMP "Vout[7]" SITE "12";
|
||||
LOCATE COMP "nC07X" SITE "34";
|
||||
LOCATE COMP "nCAS" SITE "52";
|
||||
LOCATE COMP "nCS" SITE "57";
|
||||
LOCATE COMP "nCASout" SITE "52";
|
||||
LOCATE COMP "nCSout" SITE "57";
|
||||
LOCATE COMP "nDOE" SITE "20";
|
||||
LOCATE COMP "nEN80" SITE "82";
|
||||
LOCATE COMP "nRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "51";
|
||||
LOCATE COMP "nRASout" SITE "54";
|
||||
LOCATE COMP "nRWEout" SITE "51";
|
||||
LOCATE COMP "nVOE" SITE "10";
|
||||
LOCATE COMP "nWE" SITE "29";
|
||||
LOCATE COMP "nWE80" SITE "83";
|
||||
|
||||
|
||||
|
||||
|
|
@ -283,5 +281,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:04 2023
|
||||
Thu Dec 28 23:23:41 2023
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:34:47 2023
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Dec 28 23:23:28 2023
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "LED" SITE "35" ;
|
||||
LOCATE COMP "C14M" SITE "62" ;
|
||||
LOCATE COMP "DQMH" SITE "49" ;
|
||||
LOCATE COMP "DQML" SITE "48" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
|
|
@ -14,25 +12,27 @@ LOCATE COMP "RD[4]" SITE "40" ;
|
|||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[9]" SITE "63" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[7]" SITE "67" ;
|
||||
LOCATE COMP "RA[6]" SITE "69" ;
|
||||
LOCATE COMP "RA[5]" SITE "71" ;
|
||||
LOCATE COMP "RA[4]" SITE "75" ;
|
||||
LOCATE COMP "RA[3]" SITE "74" ;
|
||||
LOCATE COMP "RA[2]" SITE "70" ;
|
||||
LOCATE COMP "RA[1]" SITE "68" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "DQMH" SITE "49" ;
|
||||
LOCATE COMP "DQML" SITE "48" ;
|
||||
LOCATE COMP "RAout[11]" SITE "59" ;
|
||||
LOCATE COMP "RAout[10]" SITE "64" ;
|
||||
LOCATE COMP "RAout[9]" SITE "63" ;
|
||||
LOCATE COMP "RAout[8]" SITE "65" ;
|
||||
LOCATE COMP "RAout[7]" SITE "67" ;
|
||||
LOCATE COMP "RAout[6]" SITE "69" ;
|
||||
LOCATE COMP "RAout[5]" SITE "71" ;
|
||||
LOCATE COMP "RAout[4]" SITE "75" ;
|
||||
LOCATE COMP "RAout[3]" SITE "74" ;
|
||||
LOCATE COMP "RAout[2]" SITE "70" ;
|
||||
LOCATE COMP "RAout[1]" SITE "68" ;
|
||||
LOCATE COMP "RAout[0]" SITE "66" ;
|
||||
LOCATE COMP "BA[1]" SITE "60" ;
|
||||
LOCATE COMP "BA[0]" SITE "58" ;
|
||||
LOCATE COMP "nRWE" SITE "51" ;
|
||||
LOCATE COMP "nCAS" SITE "52" ;
|
||||
LOCATE COMP "nRAS" SITE "54" ;
|
||||
LOCATE COMP "nCS" SITE "57" ;
|
||||
LOCATE COMP "CKE" SITE "53" ;
|
||||
LOCATE COMP "nRWEout" SITE "51" ;
|
||||
LOCATE COMP "nCASout" SITE "52" ;
|
||||
LOCATE COMP "nRASout" SITE "54" ;
|
||||
LOCATE COMP "nCSout" SITE "57" ;
|
||||
LOCATE COMP "CKEout" SITE "53" ;
|
||||
LOCATE COMP "nVOE" SITE "10" ;
|
||||
LOCATE COMP "Vout[7]" SITE "12" ;
|
||||
LOCATE COMP "Vout[6]" SITE "14" ;
|
||||
|
|
@ -69,7 +69,6 @@ LOCATE COMP "Ain[1]" SITE "2" ;
|
|||
LOCATE COMP "Ain[0]" SITE "3" ;
|
||||
LOCATE COMP "nC07X" SITE "34" ;
|
||||
LOCATE COMP "nEN80" SITE "82" ;
|
||||
LOCATE COMP "nWE80" SITE "83" ;
|
||||
LOCATE COMP "nWE" SITE "29" ;
|
||||
LOCATE COMP "PHI1" SITE "85" ;
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
|
@ -79,7 +78,7 @@ BLOCK ASYNCPATHS ;
|
|||
OUTPUT PORT "LED" LOAD 100.000000 pF ;
|
||||
OUTPUT PORT "BA[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "BA[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "CKE" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "CKEout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "DQMH" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "DQML" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
|
||||
|
|
@ -90,18 +89,18 @@ OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
|
|||
OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "RA[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[2]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[3]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[4]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[5]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[6]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[7]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[8]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[9]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[10]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[11]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[2]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[3]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[4]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[5]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[6]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[7]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[8]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[9]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[10]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[11]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ;
|
||||
|
|
@ -110,11 +109,11 @@ OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ;
|
|||
OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "nCAS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nCS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nCASout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nCSout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nDOE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRAS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRWE" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRASout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRWEout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nVOE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Thu Sep 21 05:34:32 2023
|
||||
# Thu Dec 28 23:23:17 2023
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
|
@ -48,12 +48,12 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
|
|||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
|
||||
Compiler output is up to date. No re-compile necessary
|
||||
|
||||
File \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v changed - recompiling
|
||||
File \\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v changed - recompiling
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
|
|
@ -64,29 +64,36 @@ Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current:
|
|||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
|
||||
Running optimization stage 1 on EFB .......
|
||||
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
|
||||
Running optimization stage 1 on REFB .......
|
||||
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
|
||||
Running optimization stage 1 on RAM2E_UFM .......
|
||||
Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
|
||||
Running optimization stage 1 on RAM2E .......
|
||||
Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
|
||||
Running optimization stage 2 on RAM2E .......
|
||||
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
|
||||
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on RAM2E_UFM .......
|
||||
@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
|
||||
Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on REFB .......
|
||||
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on EFB .......
|
||||
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on VLO .......
|
||||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on VHI .......
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:32 2023
|
||||
# Thu Dec 28 23:23:18 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
|
@ -107,59 +114,60 @@ Implementation : impl1
|
|||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:33 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
For a summary of runtime and memory usage for all design units, please see file:
|
||||
==========================================================
|
||||
@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:33 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
|
||||
File \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\layer0.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
# Thu Dec 28 23:23:18 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
|
||||
For a summary of runtime and memory usage for all design units, please see file:
|
||||
==========================================================
|
||||
@L: A:\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 31MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Dec 28 23:23:18 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Dec 28 23:23:19 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Dec 28 23:23:19 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
|
@ -178,14 +186,14 @@ Implementation : impl1
|
|||
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
|
||||
|
||||
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
|
||||
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt
|
||||
See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt"
|
||||
Reading constraint file: \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc
|
||||
@L: \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt
|
||||
See clock summary report "\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt"
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
|
@ -201,46 +209,45 @@ Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00
|
|||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
|
||||
|
||||
@N: FX493 |Applying initial value "0" on instance PHI1reg.
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance DOEEN.
|
||||
@N: FX493 |Applying initial value "0" on instance RWSel.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "1" on instance DQMH.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
|
||||
@N: FX493 |Applying initial value "0" on instance PHI1r.
|
||||
@N: FX493 |Applying initial value "0" on instance RWSel.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWE.
|
||||
@N: FX493 |Applying initial value "0" on instance LEDEN.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance DQMH.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance DQML.
|
||||
@N: FX493 |Applying initial value "0" on instance CKE.
|
||||
@N: FX493 |Applying initial value "1" on instance nCS.
|
||||
@N: FX493 |Applying initial value "1" on instance nRAS.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
@N: FX493 |Applying initial value "1" on instance CKE.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWE.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWEout.
|
||||
@N: FX493 |Applying initial value "1" on instance nCAS.
|
||||
@N: FX493 |Applying initial value "1" on instance nCASout.
|
||||
@N: FX493 |Applying initial value "1" on instance nRAS.
|
||||
@N: FX493 |Applying initial value "1" on instance nRASout.
|
||||
|
||||
Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
|
||||
|
|
@ -250,7 +257,7 @@ Clock Summary
|
|||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
----------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 122
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
========================================================================================
|
||||
|
|
@ -263,7 +270,7 @@ Clock Load Summary
|
|||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
----------------------------------------------------------------------------------------
|
||||
C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv)
|
||||
C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
========================================================================================
|
||||
|
|
@ -280,14 +287,14 @@ For details review file gcc_ICG_report.rpt
|
|||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
|
||||
1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 111 nCAS
|
||||
@KP:ckid0_0 C14M port 122 nRAS
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
|
@ -296,23 +303,23 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
|
|||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 184MB peak: 184MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
|
||||
|
||||
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
|
||||
# Thu Sep 21 05:34:37 2023
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Dec 28 23:23:21 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:37 2023
|
||||
# Thu Dec 28 23:23:21 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
|
@ -331,97 +338,97 @@ Implementation : impl1
|
|||
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
|
||||
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
|
||||
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
|
||||
|
||||
@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
|
||||
@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
|
||||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
None Found
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:02s 29.35ns 222 / 111
|
||||
1 0h:00m:02s 33.71ns 284 / 122
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 206MB peak: 206MB)
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
|
||||
|
||||
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB)
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing report written on Thu Sep 21 05:34:43 2023
|
||||
# Timing report written on Thu Dec 28 23:23:25 2023
|
||||
#
|
||||
|
||||
|
||||
|
|
@ -429,7 +436,7 @@ Top view: RAM2E
|
|||
Requested Frequency: 14.3 MHz
|
||||
Wire load mode: top
|
||||
Paths requested: 5
|
||||
Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
|
||||
Constraint File(s): \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc
|
||||
|
||||
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
|
||||
|
||||
|
|
@ -441,12 +448,12 @@ Performance Summary
|
|||
*******************
|
||||
|
||||
|
||||
Worst slack in design: 31.782
|
||||
Worst slack in design: 33.707
|
||||
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 131.4 MHz 69.841 7.610 31.782 declared default_clkgroup
|
||||
C14M 14.3 MHz 128.0 MHz 69.841 7.813 33.707 declared default_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
===================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
|
@ -464,7 +471,7 @@ Starting Ending | constraint slack | constraint slack | constraint sl
|
|||
----------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 62.231 | No paths - | 34.920 31.782 | No paths -
|
||||
C14M C14M | 69.841 62.028 | No paths - | 34.920 33.707 | No paths -
|
||||
==========================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
|
@ -487,41 +494,41 @@ Detailed Report for Clock: C14M
|
|||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.350 31.782
|
||||
S[3] C14M FD1S3AX Q S[3] 1.350 31.782
|
||||
S[0] C14M FD1S3AX Q S[0] 1.312 31.820
|
||||
S[1] C14M FD1S3AX Q S[1] 1.280 31.852
|
||||
FS[9] C14M FD1S3AX Q FS[9] 1.284 62.425
|
||||
FS[11] C14M FD1S3AX Q FS[11] 1.276 62.433
|
||||
FS[8] C14M FD1S3AX Q FS[8] 1.260 62.449
|
||||
FS[12] C14M FD1S3AX Q FS[12] 1.288 62.525
|
||||
FS[10] C14M FD1S3AX Q FS[10] 1.280 62.533
|
||||
RWSel C14M FD1P3AX Q RWSel 1.276 63.482
|
||||
============================================================================
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------
|
||||
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
|
||||
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
|
||||
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
|
||||
RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771
|
||||
RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771
|
||||
RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
|
||||
RA[6] C14M FD1P3AX Q RA[6] 1.044 33.771
|
||||
RA[7] C14M FD1P3AX Q RA[7] 1.044 33.771
|
||||
RA[8] C14M FD1P3AX Q RA[8] 1.044 33.771
|
||||
RA[9] C14M FD1P3AX Q RA[9] 1.044 33.771
|
||||
===========================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
Dout_0io[0] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[1] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[2] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[3] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[4] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[5] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[6] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[7] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
==================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------
|
||||
RAout_0io[0] C14M OFS1P3DX D RA[0] 34.815 33.707
|
||||
RAout_0io[3] C14M OFS1P3DX D RA[3] 34.815 33.707
|
||||
RAout_0io[1] C14M OFS1P3DX D RA[1] 34.815 33.771
|
||||
RAout_0io[2] C14M OFS1P3DX D RA[2] 34.815 33.771
|
||||
RAout_0io[4] C14M OFS1P3DX D RA[4] 34.815 33.771
|
||||
RAout_0io[5] C14M OFS1P3DX D RA[5] 34.815 33.771
|
||||
RAout_0io[6] C14M OFS1P3DX D RA[6] 34.815 33.771
|
||||
RAout_0io[7] C14M OFS1P3DX D RA[7] 34.815 33.771
|
||||
RAout_0io[8] C14M OFS1P3DX D RA[8] 34.815 33.771
|
||||
RAout_0io[9] C14M OFS1P3DX D RA[9] 34.815 33.771
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -531,30 +538,27 @@ Worst Path Information
|
|||
|
||||
Path information for path number 1:
|
||||
Requested Period: 34.920
|
||||
- Setup time: 0.472
|
||||
- Setup time: 0.106
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.449
|
||||
= Required time: 34.815
|
||||
|
||||
- Propagation time: 2.667
|
||||
- Propagation time: 1.108
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (critical) : 31.782
|
||||
= Slack (critical) : 33.707
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
Ending point: Dout_0io[0] / SP
|
||||
Number of logic level(s): 0
|
||||
Starting point: RA[0] / Q
|
||||
Ending point: RAout_0io[0] / D
|
||||
The start point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
The end point is clocked by C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.350 1.350 r -
|
||||
S[2] Net - - - - 48
|
||||
S_RNII9DO1_2[1] ORCALUT4 B In 0.000 1.350 r -
|
||||
S_RNII9DO1_2[1] ORCALUT4 Z Out 1.317 2.667 r -
|
||||
N_576_i Net - - - - 18
|
||||
Dout_0io[0] OFS1P3DX SP In 0.000 2.667 r -
|
||||
==================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
RA[0] FD1P3AX Q Out 1.108 1.108 r -
|
||||
RA[0] Net - - - - 3
|
||||
RAout_0io[0] OFS1P3DX D In 0.000 1.108 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -568,40 +572,40 @@ Detailed Report for Clock: System
|
|||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
|
||||
=========================================================================================
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
|
||||
===================================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------------
|
||||
RWMask[0] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[1] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[2] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[3] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[4] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[5] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[6] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[7] System FD1P3AX SP N_88 69.369 67.088
|
||||
LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
wb_cyc_stb System FD1P3AX SP N_104 69.369 67.736
|
||||
====================================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0_0[0] 69.369 67.736
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdSetRWBankFFChip13_1_i_0_0[0] 69.369 67.736
|
||||
======================================================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -621,24 +625,24 @@ Path information for path number 1:
|
|||
= Slack (non-critical) : 67.088
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: RWMask[0] / SP
|
||||
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: ram2e_ufm.RWMask[0] / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
|
||||
wb_ack Net - - - - 5
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 A In 0.000 0.000 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 Z Out 1.017 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] Net - - - - 1
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 r -
|
||||
N_88 Net - - - - 8
|
||||
RWMask[0] FD1P3AX SP In 0.000 2.282 r -
|
||||
======================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
|
||||
wb_ack Net - - - - 5
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ORCALUT4 B In 0.000 0.000 r -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ORCALUT4 Z Out 1.017 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0] ORCALUT4 D In 0.000 1.017 r -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0] ORCALUT4 Z Out 1.265 2.282 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_0[0] Net - - - - 8
|
||||
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 r -
|
||||
==================================================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -646,45 +650,47 @@ RWMask[0] FD1P3AX SP In 0.000
|
|||
|
||||
Timing exceptions that could not be applied
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_640hc-4
|
||||
|
||||
Register bits: 111 of 640 (17%)
|
||||
Register bits: 122 of 640 (19%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
I/O cells: 69
|
||||
|
||||
|
||||
Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 48
|
||||
FD1P3AX: 61
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 22
|
||||
FD1S3IX: 4
|
||||
FD1S3AX: 21
|
||||
FD1S3AY: 4
|
||||
FD1S3IX: 6
|
||||
GSR: 1
|
||||
IB: 22
|
||||
IB: 21
|
||||
IFS1P3DX: 1
|
||||
INV: 1
|
||||
OB: 40
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 27
|
||||
OFS1P3BX: 5
|
||||
OFS1P3DX: 21
|
||||
OFS1P3IX: 2
|
||||
ORCALUT4: 221
|
||||
ORCALUT4: 277
|
||||
PFUMX: 3
|
||||
PUR: 1
|
||||
VHI: 2
|
||||
VLO: 2
|
||||
VHI: 3
|
||||
VLO: 3
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 77MB peak: 211MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 217MB)
|
||||
|
||||
Process took 0h:00m:06s realtime, 0h:00m:04s cputime
|
||||
# Thu Sep 21 05:34:44 2023
|
||||
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
|
||||
# Thu Dec 28 23:23:25 2023
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ Setup and Hold Report
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:34:48 2023
|
||||
Thu Dec 28 23:23:29 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -23,7 +23,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2e_lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: ram2e_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,4
|
||||
|
|
@ -38,48 +38,48 @@ BLOCK RESETPATHS
|
|||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
1611 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 58.471ns
|
||||
Passed: The following path meets requirements by 58.937ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS[11] (from C14M_c +)
|
||||
Destination: FF Data in nRWE_0io (to C14M_c +)
|
||||
Source: FF Q S[2] (from C14M_c +)
|
||||
Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +)
|
||||
|
||||
Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels.
|
||||
Delay: 10.827ns (31.6% logic, 68.4% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
|
||||
10.827ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
|
||||
69.930ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
|
||||
0.166ns DIN_SET requirement (totaling 69.764ns) by 58.937ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_3 to nRWE_MGIOL:
|
||||
Data path SLICE_34 to ram2e_ufm/SLICE_47:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_3.CLK to SLICE_3.Q0 SLICE_3 (from C14M_c)
|
||||
ROUTE 19 e 1.234 SLICE_3.Q0 to SLICE_64.A1 FS[11]
|
||||
CTOF_DEL --- 0.495 SLICE_64.A1 to SLICE_64.F1 SLICE_64
|
||||
ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_97.D0 N_577
|
||||
CTOF_DEL --- 0.495 SLICE_97.D0 to SLICE_97.F0 SLICE_97
|
||||
ROUTE 3 e 1.234 SLICE_97.F0 to SLICE_75.D1 N_489
|
||||
CTOF_DEL --- 0.495 SLICE_75.D1 to SLICE_75.F1 SLICE_75
|
||||
ROUTE 3 e 0.480 SLICE_75.F1 to SLICE_75.A0 N_628
|
||||
CTOF_DEL --- 0.495 SLICE_75.A0 to SLICE_75.F0 SLICE_75
|
||||
ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_71.C1 N_640
|
||||
CTOF_DEL --- 0.495 SLICE_71.C1 to SLICE_71.F1 SLICE_71
|
||||
ROUTE 1 e 1.234 SLICE_71.F1 to SLICE_115.A0 un1_nCS61_1_i
|
||||
CTOF_DEL --- 0.495 SLICE_115.A0 to SLICE_115.F0 SLICE_115
|
||||
ROUTE 1 e 1.234 SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
|
||||
REG_DEL --- 0.452 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from C14M_c)
|
||||
ROUTE 50 e 1.234 SLICE_34.Q0 to SLICE_35.A0 S[2]
|
||||
CTOF_DEL --- 0.495 SLICE_35.A0 to SLICE_35.F0 SLICE_35
|
||||
ROUTE 7 e 1.234 SLICE_35.F0 to *m/SLICE_80.D1 N_551
|
||||
CTOF_DEL --- 0.495 *m/SLICE_80.D1 to *m/SLICE_80.F1 ram2e_ufm/SLICE_80
|
||||
ROUTE 8 e 1.234 *m/SLICE_80.F1 to *m/SLICE_98.B1 ram2e_ufm/N_777
|
||||
CTOF_DEL --- 0.495 *m/SLICE_98.B1 to *m/SLICE_98.F1 ram2e_ufm/SLICE_98
|
||||
ROUTE 5 e 1.234 *m/SLICE_98.F1 to *m/SLICE_99.C0 ram2e_ufm/N_781
|
||||
CTOF_DEL --- 0.495 *m/SLICE_99.C0 to *m/SLICE_99.F0 ram2e_ufm/SLICE_99
|
||||
ROUTE 1 e 1.234 *m/SLICE_99.F0 to *m/SLICE_86.C0 ram2e_ufm/wb_adr_7_i_i_1[0]
|
||||
CTOF_DEL --- 0.495 *m/SLICE_86.C0 to *m/SLICE_86.F0 ram2e_ufm/SLICE_86
|
||||
ROUTE 1 e 1.234 *m/SLICE_86.F0 to *m/SLICE_47.C0 ram2e_ufm/wb_adr_7_i_i_4[0]
|
||||
CTOF_DEL --- 0.495 *m/SLICE_47.C0 to *m/SLICE_47.F0 ram2e_ufm/SLICE_47
|
||||
ROUTE 1 e 0.001 *m/SLICE_47.F0 to */SLICE_47.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
|
||||
--------
|
||||
11.306 (30.3% logic, 69.7% route), 7 logic levels.
|
||||
10.827 (31.6% logic, 68.4% route), 7 logic levels.
|
||||
|
||||
Report: 87.268MHz is the maximum frequency for this preference.
|
||||
Report: 90.967MHz is the maximum frequency for this preference.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
|
|
@ -87,7 +87,7 @@ Report Summary
|
|||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 87.268 MHz| 7
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 90.967 MHz| 7
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
|
@ -100,7 +100,7 @@ Clock Domains Analysis
|
|||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 89
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
|
|
@ -110,11 +110,11 @@ Timing summary (Setup):
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:34:48 2023
|
||||
Thu Dec 28 23:23:29 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -124,7 +124,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2e_lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: ram2e_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,M
|
||||
|
|
@ -139,7 +139,7 @@ BLOCK RESETPATHS
|
|||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
1611 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
|
@ -164,7 +164,7 @@ Passed: The following path meets requirements by 0.447ns
|
|||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from C14M_c)
|
||||
ROUTE 5 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
|
||||
ROUTE 6 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
|
||||
CTOF_DEL --- 0.101 SLICE_0.A1 to SLICE_0.F1 SLICE_0
|
||||
ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 FS_s[0] (to C14M_c)
|
||||
--------
|
||||
|
|
@ -189,7 +189,7 @@ Clock Domains Analysis
|
|||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 89
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
|
|
@ -199,7 +199,7 @@ Timing summary (Hold):
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:15 2023
|
||||
Thu Dec 28 23:23:51 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC -w -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC -w -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
|
|
@ -81,8 +81,8 @@ Creating bit map...
|
|||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2E_LCMXO2_640HC_impl1.bit".
|
||||
Total CPU Time: 4 secs
|
||||
Total REAL Time: 5 secs
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 4 secs
|
||||
Peak Memory Usage: 267 MB
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -13,12 +13,12 @@ Hostname: ZANEMACWIN11
|
|||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Thu Sep 21 05:34:37 2023
|
||||
# Written on Thu Dec 28 23:23:21 2023
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
Top View: "RAM2E"
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc"
|
||||
|
||||
|
||||
|
||||
|
|
@ -58,7 +58,7 @@ p:Ain[6]
|
|||
p:Ain[7]
|
||||
p:BA[0]
|
||||
p:BA[1]
|
||||
p:CKE
|
||||
p:CKEout
|
||||
p:DQMH
|
||||
p:DQML
|
||||
p:Din[0]
|
||||
|
|
@ -79,18 +79,18 @@ p:Dout[6]
|
|||
p:Dout[7]
|
||||
p:LED
|
||||
p:PHI1
|
||||
p:RA[0]
|
||||
p:RA[1]
|
||||
p:RA[2]
|
||||
p:RA[3]
|
||||
p:RA[4]
|
||||
p:RA[5]
|
||||
p:RA[6]
|
||||
p:RA[7]
|
||||
p:RA[8]
|
||||
p:RA[9]
|
||||
p:RA[10]
|
||||
p:RA[11]
|
||||
p:RAout[0]
|
||||
p:RAout[1]
|
||||
p:RAout[2]
|
||||
p:RAout[3]
|
||||
p:RAout[4]
|
||||
p:RAout[5]
|
||||
p:RAout[6]
|
||||
p:RAout[7]
|
||||
p:RAout[8]
|
||||
p:RAout[9]
|
||||
p:RAout[10]
|
||||
p:RAout[11]
|
||||
p:RD[0] (bidir end point)
|
||||
p:RD[0] (bidir start point)
|
||||
p:RD[1] (bidir end point)
|
||||
|
|
@ -116,12 +116,12 @@ p:Vout[5]
|
|||
p:Vout[6]
|
||||
p:Vout[7]
|
||||
p:nC07X
|
||||
p:nCAS
|
||||
p:nCS
|
||||
p:nCASout
|
||||
p:nCSout
|
||||
p:nDOE
|
||||
p:nEN80
|
||||
p:nRAS
|
||||
p:nRWE
|
||||
p:nRASout
|
||||
p:nRWEout
|
||||
p:nVOE
|
||||
p:nWE
|
||||
p:nWE80
|
||||
|
|
|
|||
|
|
@ -38,9 +38,9 @@ Performance Hardware Data Status: Final Version 34.4.
|
|||
// Package: TQFP100
|
||||
// ncd File: ram2e_lcmxo2_640hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:35:10 2023
|
||||
// Written on Thu Dec 28 23:23:47 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
|
||||
// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
|
|
@ -50,81 +50,82 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
|
|||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
Ain[0] C14M R 0.502 4 0.868 4
|
||||
Ain[1] C14M R 2.364 4 -0.126 M
|
||||
Ain[2] C14M R 2.421 4 -0.129 M
|
||||
Ain[3] C14M R 0.574 4 0.786 4
|
||||
Ain[4] C14M R 1.452 4 0.140 M
|
||||
Ain[5] C14M R 2.076 4 -0.039 M
|
||||
Ain[6] C14M R 1.515 4 0.124 M
|
||||
Ain[7] C14M R 2.270 4 -0.095 M
|
||||
Din[0] C14M R 9.252 4 1.162 4
|
||||
Din[1] C14M R 8.868 4 0.657 4
|
||||
Din[2] C14M R 8.368 4 0.864 4
|
||||
Din[3] C14M R 8.749 4 1.339 4
|
||||
Din[4] C14M R 9.095 4 0.770 4
|
||||
Din[5] C14M R 8.195 4 1.176 4
|
||||
Din[6] C14M R 6.162 4 0.760 4
|
||||
Din[7] C14M R 7.060 4 1.093 4
|
||||
PHI1 C14M R 2.045 4 3.047 4
|
||||
RD[0] C14M F 0.267 4 0.866 4
|
||||
RD[1] C14M F 0.173 4 1.383 4
|
||||
RD[2] C14M F 0.924 4 1.018 4
|
||||
RD[3] C14M F 0.267 4 0.866 4
|
||||
RD[4] C14M F 0.173 4 0.937 4
|
||||
RD[5] C14M F 0.267 4 0.866 4
|
||||
RD[6] C14M F 0.766 4 0.866 4
|
||||
RD[7] C14M F 0.267 4 1.312 4
|
||||
nC07X C14M R 0.077 4 1.144 4
|
||||
nEN80 C14M R 6.415 4 -0.286 M
|
||||
nWE C14M R 0.691 4 0.684 4
|
||||
nWE80 C14M R 2.845 4 -0.260 M
|
||||
Ain[0] C14M R 2.463 4 -0.066 M
|
||||
Ain[1] C14M R 1.330 4 0.135 6
|
||||
Ain[2] C14M R 1.221 4 0.223 4
|
||||
Ain[3] C14M R 2.776 4 -0.165 M
|
||||
Ain[4] C14M R 1.603 4 0.140 M
|
||||
Ain[5] C14M R 0.021 6 1.287 4
|
||||
Ain[6] C14M R 1.444 4 0.205 M
|
||||
Ain[7] C14M R 1.816 4 0.114 M
|
||||
Din[0] C14M R 8.919 4 0.723 4
|
||||
Din[1] C14M R 8.410 4 1.156 4
|
||||
Din[2] C14M R 8.503 4 1.181 4
|
||||
Din[3] C14M R 8.783 4 0.110 M
|
||||
Din[4] C14M R 10.420 4 1.022 4
|
||||
Din[5] C14M R 8.001 4 0.566 4
|
||||
Din[6] C14M R 9.731 4 1.050 4
|
||||
Din[7] C14M R 10.052 4 0.862 4
|
||||
PHI1 C14M R 2.579 4 3.047 4
|
||||
RD[0] C14M R 0.267 4 0.866 4
|
||||
RD[1] C14M R 0.173 4 0.937 4
|
||||
RD[2] C14M R 0.100 4 1.018 4
|
||||
RD[3] C14M R 0.267 4 0.866 4
|
||||
RD[4] C14M R 0.172 4 0.936 4
|
||||
RD[5] C14M R 0.267 4 0.866 4
|
||||
RD[6] C14M R 0.766 4 0.420 4
|
||||
RD[7] C14M R 0.267 4 0.866 4
|
||||
nC07X C14M R 0.998 4 0.405 6
|
||||
nEN80 C14M R 6.107 4 0.114 M
|
||||
nWE C14M R 6.726 4 0.069 M
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
BA[0] C14M R 8.629 4 2.885 M
|
||||
BA[1] C14M R 8.629 4 2.885 M
|
||||
CKE C14M R 8.629 4 2.885 M
|
||||
DQMH C14M R 8.609 4 2.892 M
|
||||
DQML C14M R 8.609 4 2.892 M
|
||||
Dout[0] C14M F 8.955 4 3.164 M
|
||||
Dout[1] C14M F 8.955 4 3.164 M
|
||||
Dout[2] C14M F 8.944 4 3.158 M
|
||||
Dout[3] C14M F 8.955 4 3.164 M
|
||||
Dout[4] C14M F 8.944 4 3.158 M
|
||||
Dout[5] C14M F 8.944 4 3.158 M
|
||||
Dout[6] C14M F 8.955 4 3.164 M
|
||||
Dout[7] C14M F 8.955 4 3.164 M
|
||||
LED C14M R 19.941 4 8.191 M
|
||||
RA[0] C14M R 10.013 4 3.186 M
|
||||
RA[10] C14M R 8.629 4 2.885 M
|
||||
RA[11] C14M R 8.629 4 2.885 M
|
||||
RA[1] C14M R 8.695 4 2.890 M
|
||||
RA[2] C14M R 8.695 4 2.890 M
|
||||
RA[3] C14M R 10.013 4 3.186 M
|
||||
RA[4] C14M R 8.695 4 2.890 M
|
||||
RA[5] C14M R 8.695 4 2.890 M
|
||||
RA[6] C14M R 8.695 4 2.890 M
|
||||
RA[7] C14M R 8.695 4 2.890 M
|
||||
RA[8] C14M R 8.629 4 2.885 M
|
||||
RA[9] C14M R 8.629 4 2.885 M
|
||||
Vout[0] C14M F 9.553 4 3.402 M
|
||||
Vout[1] C14M F 9.553 4 3.402 M
|
||||
Vout[2] C14M F 9.553 4 3.402 M
|
||||
Vout[3] C14M F 9.553 4 3.402 M
|
||||
Vout[4] C14M F 9.553 4 3.402 M
|
||||
Vout[5] C14M F 9.553 4 3.402 M
|
||||
Vout[6] C14M F 9.553 4 3.402 M
|
||||
Vout[7] C14M F 9.553 4 3.402 M
|
||||
nCAS C14M R 8.629 4 2.885 M
|
||||
nCS C14M R 8.629 4 2.885 M
|
||||
nDOE C14M R 11.976 4 3.776 M
|
||||
nRAS C14M R 8.629 4 2.885 M
|
||||
nRWE C14M R 8.629 4 2.885 M
|
||||
BA[0] C14M R 8.629 4 2.885 M
|
||||
BA[1] C14M R 8.629 4 2.885 M
|
||||
CKEout C14M F 8.629 4 2.885 M
|
||||
DQMH C14M R 8.609 4 2.892 M
|
||||
DQML C14M R 8.609 4 2.892 M
|
||||
LED C14M R 19.935 4 8.161 M
|
||||
RAout[0] C14M F 8.695 4 2.890 M
|
||||
RAout[10] C14M F 8.629 4 2.885 M
|
||||
RAout[11] C14M F 8.629 4 2.885 M
|
||||
RAout[1] C14M F 8.695 4 2.890 M
|
||||
RAout[2] C14M F 8.695 4 2.890 M
|
||||
RAout[3] C14M F 8.695 4 2.890 M
|
||||
RAout[4] C14M F 8.695 4 2.890 M
|
||||
RAout[5] C14M F 8.695 4 2.890 M
|
||||
RAout[6] C14M F 8.695 4 2.890 M
|
||||
RAout[7] C14M F 8.695 4 2.890 M
|
||||
RAout[8] C14M F 8.629 4 2.885 M
|
||||
RAout[9] C14M F 8.629 4 2.885 M
|
||||
RD[0] C14M R 11.414 4 3.265 M
|
||||
RD[1] C14M R 11.811 4 3.265 M
|
||||
RD[2] C14M R 11.925 4 3.265 M
|
||||
RD[3] C14M R 11.384 4 3.265 M
|
||||
RD[4] C14M R 12.301 4 3.371 M
|
||||
RD[5] C14M R 12.767 4 3.371 M
|
||||
RD[6] C14M R 12.010 4 3.371 M
|
||||
RD[7] C14M R 12.313 4 3.371 M
|
||||
Vout[0] C14M R 9.553 4 3.402 M
|
||||
Vout[1] C14M R 9.553 4 3.402 M
|
||||
Vout[2] C14M R 9.553 4 3.402 M
|
||||
Vout[3] C14M R 9.553 4 3.402 M
|
||||
Vout[4] C14M R 9.553 4 3.402 M
|
||||
Vout[5] C14M R 9.553 4 3.402 M
|
||||
Vout[6] C14M R 9.553 4 3.402 M
|
||||
Vout[7] C14M R 9.553 4 3.402 M
|
||||
nCASout C14M F 8.629 4 2.885 M
|
||||
nDOE C14M R 12.048 4 3.811 M
|
||||
nRASout C14M F 8.629 4 2.885 M
|
||||
nRWEout C14M F 8.629 4 2.885 M
|
||||
nVOE C14M R 12.164 4 3.783 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with setup speed: 6
|
||||
WARNING: you must also run trce with hold speed: 6
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -16,30 +16,30 @@
|
|||
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
|
||||
RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
|
||||
loud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
|
||||
lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
|
||||
loud/Repos/ram2e/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
|
||||
lpf -lpf //Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset
|
||||
//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:34:46
|
||||
Mapped on: 12/28/23 23:23:28
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of registers: 111 out of 877 (13%)
|
||||
PFU registers: 75 out of 640 (12%)
|
||||
PIO registers: 36 out of 237 (15%)
|
||||
Number of SLICEs: 120 out of 320 (38%)
|
||||
SLICEs as Logic/ROM: 120 out of 320 (38%)
|
||||
Number of registers: 122 out of 877 (14%)
|
||||
PFU registers: 93 out of 640 (15%)
|
||||
PIO registers: 29 out of 237 (12%)
|
||||
Number of SLICEs: 148 out of 320 (46%)
|
||||
SLICEs as Logic/ROM: 148 out of 320 (46%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 9 out of 320 (3%)
|
||||
Number of LUT4s: 239 out of 640 (37%)
|
||||
Number used as logic LUTs: 221
|
||||
Number of LUT4s: 296 out of 640 (46%)
|
||||
Number used as logic LUTs: 278
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 70 + 4(JTAG) out of 79 (94%)
|
||||
Number of PIO sites used: 69 + 4(JTAG) out of 79 (92%)
|
||||
Number of block RAMs: 0 out of 2 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
|
|
@ -59,43 +59,48 @@ Mapped on: 09/21/23 05:34:46
|
|||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 1
|
||||
Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
|
||||
Number of Clock Enables: 11
|
||||
Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
|
||||
Net N_576_i: 17 loads, 9 LSLICEs
|
||||
Net LEDEN13: 4 loads, 4 LSLICEs
|
||||
Net nCS61: 1 loads, 1 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
|
||||
Net C14M_c: 89 loads, 73 rising, 16 falling (Driver: PIO C14M )
|
||||
Number of Clock Enables: 14
|
||||
Net N_225_i: 2 loads, 0 LSLICEs
|
||||
Net N_201_i: 2 loads, 0 LSLICEs
|
||||
Net N_187_i: 11 loads, 11 LSLICEs
|
||||
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
|
||||
Net RC12: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/CmdBitbangMXO2_RNINSM62: 8 loads, 8 LSLICEs
|
||||
|
||||
Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net N_104: 1 loads, 1 LSLICEs
|
||||
Net N_88: 4 loads, 4 LSLICEs
|
||||
Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net ram2e_ufm/wb_we_RNO_0: 1 loads, 1 LSLICEs
|
||||
Net N_185_i: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0]: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0]: 1 loads, 1 LSLICEs
|
||||
Net N_126: 6 loads, 6 LSLICEs
|
||||
Net un9_VOEEN_0_a2_0_a3_0_a3: 1 loads, 1 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Number of LSRs: 7
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net BA_0_sqmuxa: 2 loads, 0 LSLICEs
|
||||
Net S[2]: 1 loads, 1 LSLICEs
|
||||
Net N_566_i: 2 loads, 0 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/wb_rst16_i: 1 loads, 1 LSLICEs
|
||||
Net N_1080_0: 1 loads, 1 LSLICEs
|
||||
Net N_1078_0: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 48 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[0]: 30 loads
|
||||
Net FS[12]: 22 loads
|
||||
Net FS[9]: 21 loads
|
||||
Net S[1]: 21 loads
|
||||
Net FS[10]: 20 loads
|
||||
Net FS[11]: 19 loads
|
||||
Net RWSel: 19 loads
|
||||
Net FS[13]: 17 loads
|
||||
Net S[2]: 50 loads
|
||||
Net S[3]: 45 loads
|
||||
Net S[0]: 37 loads
|
||||
Net S[1]: 34 loads
|
||||
Net FS[12]: 24 loads
|
||||
Net FS[11]: 22 loads
|
||||
Net FS[10]: 19 loads
|
||||
Net FS[13]: 19 loads
|
||||
Net FS[9]: 19 loads
|
||||
Net FS[8]: 18 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 1
|
||||
Number of warnings: 3
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
|
|
@ -104,12 +109,17 @@ Mapped on: 09/21/23 05:34:46
|
|||
|
||||
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
|
||||
|
||||
WARNING - map: //Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.lpf(93): Semantic
|
||||
error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
|
||||
"nWE80" does not exist in the design. This preference has been disabled.
|
||||
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
temporarily disable certain features of the device including Power
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
discarded.
|
||||
|
||||
|
||||
|
||||
|
|
@ -117,6 +127,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | |
|
||||
|
|
@ -125,11 +136,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| C14M | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| DQMH | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| DQML | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS33 | |
|
||||
|
|
@ -144,47 +150,51 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
| DQMH | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
| DQML | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[9] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[8] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
| RAout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
| RAout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
| RAout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS33 | OUT |
|
||||
| nRWEout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
|
||||
| nCASout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
| nRASout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCS | OUTPUT | LVCMOS33 | OUT |
|
||||
| nCSout | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CKE | OUTPUT | LVCMOS33 | OUT |
|
||||
| CKEout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nVOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| Vout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
|
|
@ -203,21 +213,21 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| nDOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
|
@ -231,6 +241,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| Din[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | |
|
||||
|
|
@ -241,7 +252,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| Ain[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[3] | INPUT | LVCMOS33 | |
|
||||
|
|
@ -256,8 +266,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| nEN80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI1 | INPUT | LVCMOS33 | IN |
|
||||
|
|
@ -268,68 +276,75 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal Dout_0_.CN was merged into signal C14M_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
|
||||
Block ram2e_ufm/GND undriven or does not drive anything - clipped.
|
||||
Signal CKEout.CN was merged into signal C14M_c
|
||||
Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block Vout_0_.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
Block nCASout.CN was optimized away.
|
||||
Block ram2e_ufm/ufmefb/VCC was optimized away.
|
||||
Block ram2e_ufm/ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
|
|
@ -339,9 +354,10 @@ Block ufmefb/GND was optimized away.
|
|||
|
||||
Desired WISHBONE clock frequency: 14.4 MHz
|
||||
Clock source: C14M_c
|
||||
Reset source: wb_rst
|
||||
Reset source: ram2e_ufm/wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
SPI Function: DISABLED
|
||||
Timer/Counter Function: DISABLED
|
||||
|
|
@ -357,7 +373,6 @@ Block ufmefb/GND was optimized away.
|
|||
None
|
||||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
|
||||
None
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
|
|
@ -378,7 +393,7 @@ Block ufmefb/GND was optimized away.
|
|||
<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
|
||||
---------------
|
||||
|
||||
Instance Name: ufmefb/EFBInst_0
|
||||
Instance Name: ram2e_ufm/ufmefb/EFBInst_0
|
||||
Type: EFB
|
||||
|
||||
|
||||
|
|
@ -388,7 +403,7 @@ Instance Name: ufmefb/EFBInst_0
|
|||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 58 MB
|
||||
Peak Memory Usage: 59 MB
|
||||
|
||||
|
||||
|
||||
|
|
@ -400,21 +415,6 @@ Instance Name: ufmefb/EFBInst_0
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ Performance Grade: 4
|
|||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Thu Sep 21 05:35:00 2023
|
||||
Thu Dec 28 23:23:38 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
|
@ -31,7 +31,7 @@ Pinout by Port Name:
|
|||
| BA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| BA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| CKEout | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQMH | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Din[0] | 96/0 | LVCMOS33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
|
|
@ -42,28 +42,28 @@ Pinout by Port Name:
|
|||
| Din[5] | 99/0 | LVCMOS33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 88/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 87/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 30/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4A | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[2] | 25/3 | LVCMOS33_OUT | PL7D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[4] | 24/3 | LVCMOS33_OUT | PL7C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[5] | 21/3 | LVCMOS33_OUT | PL7B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6A | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[0] | 30/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[2] | 25/3 | LVCMOS33_OUT | PL7D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[4] | 24/3 | LVCMOS33_OUT | PL7C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[5] | 21/3 | LVCMOS33_OUT | PL7B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| LED | 35/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| PHI1 | 85/0 | LVCMOS33_IN | PT9D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[1] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[2] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[5] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[6] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[7] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
|
|
@ -81,15 +81,14 @@ Pinout by Port Name:
|
|||
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nC07X | 34/2 | LVCMOS33_IN | PB6C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCASout | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCSout | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nDOE | 20/3 | LVCMOS33_OUT | PL7A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nEN80 | 82/0 | LVCMOS33_IN | PT10C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRASout | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWEout | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nVOE | 10/3 | LVCMOS33_OUT | PL3D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nWE | 29/2 | LVCMOS33_IN | PB4C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nWE80 | 83/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
|
|
@ -153,32 +152,32 @@ Vccio by Bank:
|
|||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
|
||||
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | nRWE | LOCATED | LVCMOS33_OUT | PR7D | | | |
|
||||
| 52/1 | nCAS | LOCATED | LVCMOS33_OUT | PR7C | | | |
|
||||
| 53/1 | CKE | LOCATED | LVCMOS33_OUT | PR7B | | | |
|
||||
| 54/1 | nRAS | LOCATED | LVCMOS33_OUT | PR7A | | | |
|
||||
| 57/1 | nCS | LOCATED | LVCMOS33_OUT | PR6D | | | |
|
||||
| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR7D | | | |
|
||||
| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR7C | | | |
|
||||
| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR7B | | | |
|
||||
| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR7A | | | |
|
||||
| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR6D | | | |
|
||||
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
|
||||
| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
|
||||
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
|
||||
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
|
||||
| 67/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR3C | | | |
|
||||
| 68/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3B | | | |
|
||||
| 69/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3A | | | |
|
||||
| 70/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR2D | | | |
|
||||
| 71/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2C | | | |
|
||||
| 74/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2B | | | |
|
||||
| 75/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2A | | | |
|
||||
| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
|
||||
| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
|
||||
| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
|
||||
| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR3C | | | |
|
||||
| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR3B | | | |
|
||||
| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR3A | | | |
|
||||
| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR2D | | | |
|
||||
| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR2C | | | |
|
||||
| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | | | |
|
||||
| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | | | |
|
||||
| 76/0 | unused, PULL:DOWN | | | PT11D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
|
||||
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT11A | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
|
||||
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT10C | JTAGENB | | |
|
||||
| 83/0 | nWE80 | LOCATED | LVCMOS33_IN | PT10B | | | |
|
||||
| 83/0 | unused, PULL:DOWN | | | PT10B | | | |
|
||||
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT10A | | | |
|
||||
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT9D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT9C | SCL/PCLKT0_0 | | |
|
||||
|
|
@ -222,7 +221,7 @@ LOCATE COMP "Ain[7]" SITE "8";
|
|||
LOCATE COMP "BA[0]" SITE "58";
|
||||
LOCATE COMP "BA[1]" SITE "60";
|
||||
LOCATE COMP "C14M" SITE "62";
|
||||
LOCATE COMP "CKE" SITE "53";
|
||||
LOCATE COMP "CKEout" SITE "53";
|
||||
LOCATE COMP "DQMH" SITE "49";
|
||||
LOCATE COMP "DQML" SITE "48";
|
||||
LOCATE COMP "Din[0]" SITE "96";
|
||||
|
|
@ -243,18 +242,18 @@ LOCATE COMP "Dout[6]" SITE "31";
|
|||
LOCATE COMP "Dout[7]" SITE "32";
|
||||
LOCATE COMP "LED" SITE "35";
|
||||
LOCATE COMP "PHI1" SITE "85";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "68";
|
||||
LOCATE COMP "RA[2]" SITE "70";
|
||||
LOCATE COMP "RA[3]" SITE "74";
|
||||
LOCATE COMP "RA[4]" SITE "75";
|
||||
LOCATE COMP "RA[5]" SITE "71";
|
||||
LOCATE COMP "RA[6]" SITE "69";
|
||||
LOCATE COMP "RA[7]" SITE "67";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RAout[0]" SITE "66";
|
||||
LOCATE COMP "RAout[10]" SITE "64";
|
||||
LOCATE COMP "RAout[11]" SITE "59";
|
||||
LOCATE COMP "RAout[1]" SITE "68";
|
||||
LOCATE COMP "RAout[2]" SITE "70";
|
||||
LOCATE COMP "RAout[3]" SITE "74";
|
||||
LOCATE COMP "RAout[4]" SITE "75";
|
||||
LOCATE COMP "RAout[5]" SITE "71";
|
||||
LOCATE COMP "RAout[6]" SITE "69";
|
||||
LOCATE COMP "RAout[7]" SITE "67";
|
||||
LOCATE COMP "RAout[8]" SITE "65";
|
||||
LOCATE COMP "RAout[9]" SITE "63";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
|
|
@ -272,15 +271,14 @@ LOCATE COMP "Vout[5]" SITE "16";
|
|||
LOCATE COMP "Vout[6]" SITE "14";
|
||||
LOCATE COMP "Vout[7]" SITE "12";
|
||||
LOCATE COMP "nC07X" SITE "34";
|
||||
LOCATE COMP "nCAS" SITE "52";
|
||||
LOCATE COMP "nCS" SITE "57";
|
||||
LOCATE COMP "nCASout" SITE "52";
|
||||
LOCATE COMP "nCSout" SITE "57";
|
||||
LOCATE COMP "nDOE" SITE "20";
|
||||
LOCATE COMP "nEN80" SITE "82";
|
||||
LOCATE COMP "nRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "51";
|
||||
LOCATE COMP "nRASout" SITE "54";
|
||||
LOCATE COMP "nRWEout" SITE "51";
|
||||
LOCATE COMP "nVOE" SITE "10";
|
||||
LOCATE COMP "nWE" SITE "29";
|
||||
LOCATE COMP "nWE80" SITE "83";
|
||||
|
||||
|
||||
|
||||
|
|
@ -292,7 +290,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:04 2023
|
||||
Thu Dec 28 23:23:41 2023
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -12,12 +12,12 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:34:51 2023
|
||||
Thu Dec 28 23:23:31 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t
|
||||
RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir
|
||||
RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
|
||||
//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
|
||||
|
|
@ -26,22 +26,22 @@ Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
|
|||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 57.366 0 0.346 0 15 Completed
|
||||
5_1 * 0 57.938 0 0.379 0 13 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 15 secs
|
||||
Total (real) run time for 1-seed: 13 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2E_LCMXO2_640HC_impl1_map.ncd"
|
||||
Thu Sep 21 05:34:51 2023
|
||||
Thu Dec 28 23:23:31 2023
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
|
@ -63,43 +63,43 @@ Ignore Preference Error(s): True
|
|||
|
||||
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
|
||||
|
||||
PIO (prelim) 70+4(JTAG)/80 93% used
|
||||
70+4(JTAG)/79 94% bonded
|
||||
IOLOGIC 36/80 45% used
|
||||
PIO (prelim) 69+4(JTAG)/80 91% used
|
||||
69+4(JTAG)/79 92% bonded
|
||||
IOLOGIC 29/80 36% used
|
||||
|
||||
SLICE 120/320 37% used
|
||||
SLICE 148/320 46% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 395
|
||||
Number of Connections: 1126
|
||||
Number of Signals: 459
|
||||
Number of Connections: 1330
|
||||
|
||||
Pin Constraint Summary:
|
||||
70 out of 70 pins locked (100% locked).
|
||||
69 out of 69 pins locked (100% locked).
|
||||
|
||||
The following 1 signal is selected to use the primary clock routing resources:
|
||||
C14M_c (driver: C14M, clk load #: 84)
|
||||
C14M_c (driver: C14M, clk load #: 89)
|
||||
|
||||
WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
N_576_i (driver: SLICE_20, clk load #: 0, sr load #: 0, ce load #: 17)
|
||||
N_187_i (driver: ram2e_ufm/SLICE_130, clk load #: 0, sr load #: 0, ce load #: 11)
|
||||
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
............
|
||||
...........
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
.....................
|
||||
Placer score = 63243.
|
||||
Finished Placer Phase 1. REAL time: 8 secs
|
||||
....................
|
||||
Placer score = 69810.
|
||||
Finished Placer Phase 1. REAL time: 7 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 62715
|
||||
Finished Placer Phase 2. REAL time: 8 secs
|
||||
Placer score = 69262
|
||||
Finished Placer Phase 2. REAL time: 7 secs
|
||||
|
||||
|
||||
|
||||
|
|
@ -112,8 +112,8 @@ Global Clock Resources:
|
|||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 84
|
||||
SECONDARY "N_576_i" from F1 on comp "SLICE_20" on site "R6C8A", clk load = 0, ce load = 17, sr load = 0
|
||||
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 89
|
||||
SECONDARY "N_187_i" from F1 on comp "ram2e_ufm/SLICE_130" on site "R6C8B", clk load = 0, ce load = 11, sr load = 0
|
||||
|
||||
PRIMARY : 1 out of 8 (12%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
|
@ -122,32 +122,32 @@ Global Clocks:
|
|||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
70 + 4(JTAG) out of 80 (92.5%) PIO sites used.
|
||||
70 + 4(JTAG) out of 79 (93.7%) bonded PIO sites used.
|
||||
Number of PIO comps: 70; differential: 0.
|
||||
69 + 4(JTAG) out of 80 (91.3%) PIO sites used.
|
||||
69 + 4(JTAG) out of 79 (92.4%) bonded PIO sites used.
|
||||
Number of PIO comps: 69; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 12 / 19 ( 63%) | 3.3V | - |
|
||||
| 0 | 11 / 19 ( 57%) | 3.3V | - |
|
||||
| 1 | 20 / 20 (100%) | 3.3V | - |
|
||||
| 2 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
| 3 | 20 / 20 (100%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 8 secs
|
||||
Total placer CPU time: 6 secs
|
||||
|
||||
Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1126 unrouted.
|
||||
0 connections routed; 1330 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
Completed router resource preassignment. Real time: 13 secs
|
||||
Completed router resource preassignment. Real time: 11 secs
|
||||
|
||||
Start NBR router at 05:35:04 09/21/23
|
||||
Start NBR router at 23:23:42 12/28/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
|
|
@ -162,32 +162,35 @@ Note: NBR uses a different method to calculate timing slacks. The
|
|||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 05:35:05 09/21/23
|
||||
Start NBR special constraint process at 23:23:42 12/28/23
|
||||
|
||||
Start NBR section for initial routing at 05:35:05 09/21/23
|
||||
Start NBR section for initial routing at 23:23:42 12/28/23
|
||||
Level 4, iteration 1
|
||||
14(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.366ns/0.000ns; real time: 14 secs
|
||||
19(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 58.137ns/0.000ns; real time: 11 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 05:35:05 09/21/23
|
||||
Start NBR section for normal routing at 23:23:42 12/28/23
|
||||
Level 4, iteration 1
|
||||
4(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.366ns/0.000ns; real time: 14 secs
|
||||
8(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 11 secs
|
||||
Level 4, iteration 2
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 11 secs
|
||||
Level 4, iteration 3
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.366ns/0.000ns; real time: 14 secs
|
||||
Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 12 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 05:35:05 09/21/23
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 23:23:43 12/28/23
|
||||
|
||||
Start NBR section for re-routing at 05:35:05 09/21/23
|
||||
Start NBR section for re-routing at 23:23:43 12/28/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.366ns/0.000ns; real time: 14 secs
|
||||
Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 12 secs
|
||||
|
||||
Start NBR section for post-routing at 05:35:05 09/21/23
|
||||
Start NBR section for post-routing at 23:23:43 12/28/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
|
|
@ -195,17 +198,17 @@ NBR Summary
|
|||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 57.366ns
|
||||
Estimated worst slack<setup> : 57.938ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 14 secs
|
||||
Total REAL time: 15 secs
|
||||
Total CPU time 12 secs
|
||||
Total REAL time: 12 secs
|
||||
Completely routed.
|
||||
End of route. 1126 routed (100.00%); 0 unrouted.
|
||||
End of route. 1330 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
|
|
@ -219,14 +222,14 @@ All signals are completely routed.
|
|||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 57.366
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 57.938
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.346
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.379
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 15 secs
|
||||
Total REAL time to completion: 15 secs
|
||||
Total CPU time to completion: 12 secs
|
||||
Total REAL time to completion: 13 secs
|
||||
|
||||
par done!
|
||||
|
||||
|
|
|
|||
|
|
@ -13,10 +13,10 @@ Hostname: ZANEMACWIN11
|
|||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Thu Sep 21 05:34:35 2023
|
||||
# Written on Thu Dec 28 23:23:20 2023
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc"
|
||||
|
||||
#Run constraint checker to find more issues with constraints.
|
||||
#########################################################################
|
||||
|
|
@ -33,7 +33,7 @@ Clock Summary
|
|||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
----------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 122
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
========================================================================================
|
||||
|
|
@ -45,7 +45,7 @@ Clock Load Summary
|
|||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
----------------------------------------------------------------------------------------
|
||||
C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv)
|
||||
C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
========================================================================================
|
||||
|
|
|
|||
|
|
@ -62,15 +62,15 @@
|
|||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/09/21 05:35:24</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/12/28 23:23:58</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/impl1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf</SPAN></TD>
|
||||
</TR>
|
||||
</small></TABLE>
|
||||
<BR>
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Thu Sep 21 05:34:32 2023
|
||||
# Thu Dec 28 23:23:17 2023
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
|
@ -57,12 +57,12 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
|
|||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
|
||||
Compiler output is up to date. No re-compile necessary
|
||||
|
||||
File \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v changed - recompiling
|
||||
File \\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v changed - recompiling
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
|
|
@ -73,29 +73,36 @@ Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current:
|
|||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
|
||||
Running optimization stage 1 on EFB .......
|
||||
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
|
||||
Running optimization stage 1 on REFB .......
|
||||
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
|
||||
Running optimization stage 1 on RAM2E_UFM .......
|
||||
Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
|
||||
Running optimization stage 1 on RAM2E .......
|
||||
Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
|
||||
Running optimization stage 2 on RAM2E .......
|
||||
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
|
||||
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on RAM2E_UFM .......
|
||||
@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
|
||||
Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on REFB .......
|
||||
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on EFB .......
|
||||
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on VLO .......
|
||||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on VHI .......
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:32 2023
|
||||
# Thu Dec 28 23:23:18 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
|
@ -116,59 +123,60 @@ Implementation : impl1
|
|||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:33 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
For a summary of runtime and memory usage for all design units, please see file:
|
||||
==========================================================
|
||||
@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:33 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
|
||||
File \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\layer0.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
# Thu Dec 28 23:23:18 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
|
||||
For a summary of runtime and memory usage for all design units, please see file:
|
||||
==========================================================
|
||||
@L: A:\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 31MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Dec 28 23:23:18 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Dec 28 23:23:19 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Dec 28 23:23:19 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
|
@ -187,14 +195,14 @@ Implementation : impl1
|
|||
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
|
||||
|
||||
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
|
||||
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt
|
||||
See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt"
|
||||
Reading constraint file: \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc
|
||||
@L: \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt
|
||||
See clock summary report "\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt"
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
|
@ -210,46 +218,45 @@ Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00
|
|||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
|
||||
|
||||
@N: FX493 |Applying initial value "0" on instance PHI1reg.
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance DOEEN.
|
||||
@N: FX493 |Applying initial value "0" on instance RWSel.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "1" on instance DQMH.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
|
||||
@N: FX493 |Applying initial value "0" on instance PHI1r.
|
||||
@N: FX493 |Applying initial value "0" on instance RWSel.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWE.
|
||||
@N: FX493 |Applying initial value "0" on instance LEDEN.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance DQMH.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance DQML.
|
||||
@N: FX493 |Applying initial value "0" on instance CKE.
|
||||
@N: FX493 |Applying initial value "1" on instance nCS.
|
||||
@N: FX493 |Applying initial value "1" on instance nRAS.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
@N: FX493 |Applying initial value "1" on instance CKE.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWE.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWEout.
|
||||
@N: FX493 |Applying initial value "1" on instance nCAS.
|
||||
@N: FX493 |Applying initial value "1" on instance nCASout.
|
||||
@N: FX493 |Applying initial value "1" on instance nRAS.
|
||||
@N: FX493 |Applying initial value "1" on instance nRASout.
|
||||
|
||||
Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
|
||||
|
|
@ -259,7 +266,7 @@ Clock Summary
|
|||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
----------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 122
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
========================================================================================
|
||||
|
|
@ -272,7 +279,7 @@ Clock Load Summary
|
|||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
----------------------------------------------------------------------------------------
|
||||
C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv)
|
||||
C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
========================================================================================
|
||||
|
|
@ -289,14 +296,14 @@ For details review file gcc_ICG_report.rpt
|
|||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
|
||||
1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 111 nCAS
|
||||
@KP:ckid0_0 C14M port 122 nRAS
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
|
@ -305,23 +312,23 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
|
|||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 184MB peak: 184MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
|
||||
|
||||
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
|
||||
# Thu Sep 21 05:34:37 2023
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Dec 28 23:23:21 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:37 2023
|
||||
# Thu Dec 28 23:23:21 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
|
@ -340,97 +347,97 @@ Implementation : impl1
|
|||
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
|
||||
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
|
||||
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
|
||||
|
||||
@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
|
||||
@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
|
||||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
None Found
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:02s 29.35ns 222 / 111
|
||||
1 0h:00m:02s 33.71ns 284 / 122
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 206MB peak: 206MB)
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
|
||||
|
||||
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB)
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing report written on Thu Sep 21 05:34:43 2023
|
||||
# Timing report written on Thu Dec 28 23:23:25 2023
|
||||
#
|
||||
|
||||
|
||||
|
|
@ -438,7 +445,7 @@ Top view: RAM2E
|
|||
Requested Frequency: 14.3 MHz
|
||||
Wire load mode: top
|
||||
Paths requested: 5
|
||||
Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
|
||||
Constraint File(s): \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc
|
||||
|
||||
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
|
||||
|
||||
|
|
@ -450,12 +457,12 @@ Performance Summary
|
|||
*******************
|
||||
|
||||
|
||||
Worst slack in design: 31.782
|
||||
Worst slack in design: 33.707
|
||||
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 131.4 MHz 69.841 7.610 31.782 declared default_clkgroup
|
||||
C14M 14.3 MHz 128.0 MHz 69.841 7.813 33.707 declared default_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
===================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
|
@ -473,7 +480,7 @@ Starting Ending | constraint slack | constraint slack | constraint sl
|
|||
----------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 62.231 | No paths - | 34.920 31.782 | No paths -
|
||||
C14M C14M | 69.841 62.028 | No paths - | 34.920 33.707 | No paths -
|
||||
==========================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
|
@ -496,41 +503,41 @@ Detailed Report for Clock: C14M
|
|||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.350 31.782
|
||||
S[3] C14M FD1S3AX Q S[3] 1.350 31.782
|
||||
S[0] C14M FD1S3AX Q S[0] 1.312 31.820
|
||||
S[1] C14M FD1S3AX Q S[1] 1.280 31.852
|
||||
FS[9] C14M FD1S3AX Q FS[9] 1.284 62.425
|
||||
FS[11] C14M FD1S3AX Q FS[11] 1.276 62.433
|
||||
FS[8] C14M FD1S3AX Q FS[8] 1.260 62.449
|
||||
FS[12] C14M FD1S3AX Q FS[12] 1.288 62.525
|
||||
FS[10] C14M FD1S3AX Q FS[10] 1.280 62.533
|
||||
RWSel C14M FD1P3AX Q RWSel 1.276 63.482
|
||||
============================================================================
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------
|
||||
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
|
||||
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
|
||||
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
|
||||
RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771
|
||||
RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771
|
||||
RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
|
||||
RA[6] C14M FD1P3AX Q RA[6] 1.044 33.771
|
||||
RA[7] C14M FD1P3AX Q RA[7] 1.044 33.771
|
||||
RA[8] C14M FD1P3AX Q RA[8] 1.044 33.771
|
||||
RA[9] C14M FD1P3AX Q RA[9] 1.044 33.771
|
||||
===========================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
Dout_0io[0] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[1] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[2] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[3] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[4] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[5] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[6] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[7] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
==================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------
|
||||
RAout_0io[0] C14M OFS1P3DX D RA[0] 34.815 33.707
|
||||
RAout_0io[3] C14M OFS1P3DX D RA[3] 34.815 33.707
|
||||
RAout_0io[1] C14M OFS1P3DX D RA[1] 34.815 33.771
|
||||
RAout_0io[2] C14M OFS1P3DX D RA[2] 34.815 33.771
|
||||
RAout_0io[4] C14M OFS1P3DX D RA[4] 34.815 33.771
|
||||
RAout_0io[5] C14M OFS1P3DX D RA[5] 34.815 33.771
|
||||
RAout_0io[6] C14M OFS1P3DX D RA[6] 34.815 33.771
|
||||
RAout_0io[7] C14M OFS1P3DX D RA[7] 34.815 33.771
|
||||
RAout_0io[8] C14M OFS1P3DX D RA[8] 34.815 33.771
|
||||
RAout_0io[9] C14M OFS1P3DX D RA[9] 34.815 33.771
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -540,30 +547,27 @@ Worst Path Information
|
|||
|
||||
Path information for path number 1:
|
||||
Requested Period: 34.920
|
||||
- Setup time: 0.472
|
||||
- Setup time: 0.106
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.449
|
||||
= Required time: 34.815
|
||||
|
||||
- Propagation time: 2.667
|
||||
- Propagation time: 1.108
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (critical) : 31.782
|
||||
= Slack (critical) : 33.707
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
Ending point: Dout_0io[0] / SP
|
||||
Number of logic level(s): 0
|
||||
Starting point: RA[0] / Q
|
||||
Ending point: RAout_0io[0] / D
|
||||
The start point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
The end point is clocked by C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.350 1.350 r -
|
||||
S[2] Net - - - - 48
|
||||
S_RNII9DO1_2[1] ORCALUT4 B In 0.000 1.350 r -
|
||||
S_RNII9DO1_2[1] ORCALUT4 Z Out 1.317 2.667 r -
|
||||
N_576_i Net - - - - 18
|
||||
Dout_0io[0] OFS1P3DX SP In 0.000 2.667 r -
|
||||
==================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
RA[0] FD1P3AX Q Out 1.108 1.108 r -
|
||||
RA[0] Net - - - - 3
|
||||
RAout_0io[0] OFS1P3DX D In 0.000 1.108 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -577,40 +581,40 @@ Detailed Report for Clock: System
|
|||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
|
||||
=========================================================================================
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
|
||||
===================================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------------
|
||||
RWMask[0] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[1] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[2] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[3] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[4] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[5] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[6] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[7] System FD1P3AX SP N_88 69.369 67.088
|
||||
LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
wb_cyc_stb System FD1P3AX SP N_104 69.369 67.736
|
||||
====================================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0_0[0] 69.369 67.736
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdSetRWBankFFChip13_1_i_0_0[0] 69.369 67.736
|
||||
======================================================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -630,24 +634,24 @@ Path information for path number 1:
|
|||
= Slack (non-critical) : 67.088
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: RWMask[0] / SP
|
||||
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: ram2e_ufm.RWMask[0] / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
|
||||
wb_ack Net - - - - 5
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 A In 0.000 0.000 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 Z Out 1.017 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] Net - - - - 1
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 r -
|
||||
N_88 Net - - - - 8
|
||||
RWMask[0] FD1P3AX SP In 0.000 2.282 r -
|
||||
======================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
|
||||
wb_ack Net - - - - 5
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ORCALUT4 B In 0.000 0.000 r -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ORCALUT4 Z Out 1.017 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0] ORCALUT4 D In 0.000 1.017 r -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0] ORCALUT4 Z Out 1.265 2.282 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_0[0] Net - - - - 8
|
||||
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 r -
|
||||
==================================================================================================================
|
||||
|
||||
|
||||
|
||||
|
|
@ -655,46 +659,48 @@ RWMask[0] FD1P3AX SP In 0.000
|
|||
|
||||
Timing exceptions that could not be applied
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_640hc-4
|
||||
|
||||
Register bits: 111 of 640 (17%)
|
||||
Register bits: 122 of 640 (19%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
I/O cells: 69
|
||||
|
||||
|
||||
Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 48
|
||||
FD1P3AX: 61
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 22
|
||||
FD1S3IX: 4
|
||||
FD1S3AX: 21
|
||||
FD1S3AY: 4
|
||||
FD1S3IX: 6
|
||||
GSR: 1
|
||||
IB: 22
|
||||
IB: 21
|
||||
IFS1P3DX: 1
|
||||
INV: 1
|
||||
OB: 40
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 27
|
||||
OFS1P3BX: 5
|
||||
OFS1P3DX: 21
|
||||
OFS1P3IX: 2
|
||||
ORCALUT4: 221
|
||||
ORCALUT4: 277
|
||||
PFUMX: 3
|
||||
PUR: 1
|
||||
VHI: 2
|
||||
VLO: 2
|
||||
VHI: 3
|
||||
VLO: 3
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 77MB peak: 211MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 217MB)
|
||||
|
||||
Process took 0h:00m:06s realtime, 0h:00m:04s cputime
|
||||
# Thu Sep 21 05:34:44 2023
|
||||
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
|
||||
# Thu Dec 28 23:23:25 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ Setup and Hold Report
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:34:48 2023
|
||||
Thu Dec 28 23:23:29 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -32,7 +32,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|||
|
||||
<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2e_lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: ram2e_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,4
|
||||
|
|
@ -41,8 +41,8 @@ Report level: verbose report, limited to 1 item per preference
|
|||
|
||||
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1491 items scored, 0 timing errors detected.
|
||||
Report: 87.268MHz is the maximum frequency for this preference.
|
||||
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1611 items scored, 0 timing errors detected.
|
||||
Report: 90.967MHz is the maximum frequency for this preference.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
|
|
@ -52,48 +52,48 @@ BLOCK RESETPATHS
|
|||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
1611 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 58.471ns
|
||||
Passed: The following path meets requirements by 58.937ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS[11] (from C14M_c +)
|
||||
Destination: FF Data in nRWE_0io (to C14M_c +)
|
||||
Source: FF Q S[2] (from C14M_c +)
|
||||
Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +)
|
||||
|
||||
Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels.
|
||||
Delay: 10.827ns (31.6% logic, 68.4% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
|
||||
10.827ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
|
||||
69.930ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
|
||||
0.166ns DIN_SET requirement (totaling 69.764ns) by 58.937ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_3 to nRWE_MGIOL:
|
||||
Data path SLICE_34 to ram2e_ufm/SLICE_47:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_3.CLK to SLICE_3.Q0 SLICE_3 (from C14M_c)
|
||||
ROUTE 19 e 1.234 SLICE_3.Q0 to SLICE_64.A1 FS[11]
|
||||
CTOF_DEL --- 0.495 SLICE_64.A1 to SLICE_64.F1 SLICE_64
|
||||
ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_97.D0 N_577
|
||||
CTOF_DEL --- 0.495 SLICE_97.D0 to SLICE_97.F0 SLICE_97
|
||||
ROUTE 3 e 1.234 SLICE_97.F0 to SLICE_75.D1 N_489
|
||||
CTOF_DEL --- 0.495 SLICE_75.D1 to SLICE_75.F1 SLICE_75
|
||||
ROUTE 3 e 0.480 SLICE_75.F1 to SLICE_75.A0 N_628
|
||||
CTOF_DEL --- 0.495 SLICE_75.A0 to SLICE_75.F0 SLICE_75
|
||||
ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_71.C1 N_640
|
||||
CTOF_DEL --- 0.495 SLICE_71.C1 to SLICE_71.F1 SLICE_71
|
||||
ROUTE 1 e 1.234 SLICE_71.F1 to SLICE_115.A0 un1_nCS61_1_i
|
||||
CTOF_DEL --- 0.495 SLICE_115.A0 to SLICE_115.F0 SLICE_115
|
||||
ROUTE 1 e 1.234 SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
|
||||
REG_DEL --- 0.452 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from C14M_c)
|
||||
ROUTE 50 e 1.234 SLICE_34.Q0 to SLICE_35.A0 S[2]
|
||||
CTOF_DEL --- 0.495 SLICE_35.A0 to SLICE_35.F0 SLICE_35
|
||||
ROUTE 7 e 1.234 SLICE_35.F0 to *m/SLICE_80.D1 N_551
|
||||
CTOF_DEL --- 0.495 *m/SLICE_80.D1 to *m/SLICE_80.F1 ram2e_ufm/SLICE_80
|
||||
ROUTE 8 e 1.234 *m/SLICE_80.F1 to *m/SLICE_98.B1 ram2e_ufm/N_777
|
||||
CTOF_DEL --- 0.495 *m/SLICE_98.B1 to *m/SLICE_98.F1 ram2e_ufm/SLICE_98
|
||||
ROUTE 5 e 1.234 *m/SLICE_98.F1 to *m/SLICE_99.C0 ram2e_ufm/N_781
|
||||
CTOF_DEL --- 0.495 *m/SLICE_99.C0 to *m/SLICE_99.F0 ram2e_ufm/SLICE_99
|
||||
ROUTE 1 e 1.234 *m/SLICE_99.F0 to *m/SLICE_86.C0 ram2e_ufm/wb_adr_7_i_i_1[0]
|
||||
CTOF_DEL --- 0.495 *m/SLICE_86.C0 to *m/SLICE_86.F0 ram2e_ufm/SLICE_86
|
||||
ROUTE 1 e 1.234 *m/SLICE_86.F0 to *m/SLICE_47.C0 ram2e_ufm/wb_adr_7_i_i_4[0]
|
||||
CTOF_DEL --- 0.495 *m/SLICE_47.C0 to *m/SLICE_47.F0 ram2e_ufm/SLICE_47
|
||||
ROUTE 1 e 0.001 *m/SLICE_47.F0 to */SLICE_47.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
|
||||
--------
|
||||
11.306 (30.3% logic, 69.7% route), 7 logic levels.
|
||||
10.827 (31.6% logic, 68.4% route), 7 logic levels.
|
||||
|
||||
Report: 87.268MHz is the maximum frequency for this preference.
|
||||
Report: 90.967MHz is the maximum frequency for this preference.
|
||||
|
||||
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
|
|
@ -101,7 +101,7 @@ Report: 87.268MHz is the maximum frequency for this preference.
|
|||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 87.268 MHz| 7
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 90.967 MHz| 7
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
|
@ -114,7 +114,7 @@ All preferences were met.
|
|||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 89
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
|
|
@ -124,11 +124,11 @@ Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:34:48 2023
|
||||
Thu Dec 28 23:23:29 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -138,7 +138,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|||
|
||||
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2e_lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: ram2e_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,M
|
||||
|
|
@ -147,7 +147,7 @@ Report level: verbose report, limited to 1 item per preference
|
|||
|
||||
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1491 items scored, 0 timing errors detected.
|
||||
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1611 items scored, 0 timing errors detected.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
|
|
@ -157,7 +157,7 @@ BLOCK RESETPATHS
|
|||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
1611 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
|
@ -182,7 +182,7 @@ Passed: The following path meets requirements by 0.447ns
|
|||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from C14M_c)
|
||||
ROUTE 5 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
|
||||
ROUTE 6 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
|
||||
CTOF_DEL --- 0.101 SLICE_0.A1 to SLICE_0.F1 SLICE_0
|
||||
ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 FS_s[0] (to C14M_c)
|
||||
--------
|
||||
|
|
@ -207,7 +207,7 @@ All preferences were met.
|
|||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 89
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
|
|
@ -217,7 +217,7 @@ Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
|
|
@ -29,9 +29,9 @@ Performance Hardware Data Status: Final Version 34.4.
|
|||
// Package: TQFP100
|
||||
// ncd File: ram2e_lcmxo2_640hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:35:10 2023
|
||||
// Written on Thu Dec 28 23:23:47 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
|
||||
// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
|
|
@ -41,78 +41,79 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
|
|||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
Ain[0] C14M R 0.502 4 0.868 4
|
||||
Ain[1] C14M R 2.364 4 -0.126 M
|
||||
Ain[2] C14M R 2.421 4 -0.129 M
|
||||
Ain[3] C14M R 0.574 4 0.786 4
|
||||
Ain[4] C14M R 1.452 4 0.140 M
|
||||
Ain[5] C14M R 2.076 4 -0.039 M
|
||||
Ain[6] C14M R 1.515 4 0.124 M
|
||||
Ain[7] C14M R 2.270 4 -0.095 M
|
||||
Din[0] C14M R 9.252 4 1.162 4
|
||||
Din[1] C14M R 8.868 4 0.657 4
|
||||
Din[2] C14M R 8.368 4 0.864 4
|
||||
Din[3] C14M R 8.749 4 1.339 4
|
||||
Din[4] C14M R 9.095 4 0.770 4
|
||||
Din[5] C14M R 8.195 4 1.176 4
|
||||
Din[6] C14M R 6.162 4 0.760 4
|
||||
Din[7] C14M R 7.060 4 1.093 4
|
||||
PHI1 C14M R 2.045 4 3.047 4
|
||||
RD[0] C14M F 0.267 4 0.866 4
|
||||
RD[1] C14M F 0.173 4 1.383 4
|
||||
RD[2] C14M F 0.924 4 1.018 4
|
||||
RD[3] C14M F 0.267 4 0.866 4
|
||||
RD[4] C14M F 0.173 4 0.937 4
|
||||
RD[5] C14M F 0.267 4 0.866 4
|
||||
RD[6] C14M F 0.766 4 0.866 4
|
||||
RD[7] C14M F 0.267 4 1.312 4
|
||||
nC07X C14M R 0.077 4 1.144 4
|
||||
nEN80 C14M R 6.415 4 -0.286 M
|
||||
nWE C14M R 0.691 4 0.684 4
|
||||
nWE80 C14M R 2.845 4 -0.260 M
|
||||
Ain[0] C14M R 2.463 4 -0.066 M
|
||||
Ain[1] C14M R 1.330 4 0.135 6
|
||||
Ain[2] C14M R 1.221 4 0.223 4
|
||||
Ain[3] C14M R 2.776 4 -0.165 M
|
||||
Ain[4] C14M R 1.603 4 0.140 M
|
||||
Ain[5] C14M R 0.021 6 1.287 4
|
||||
Ain[6] C14M R 1.444 4 0.205 M
|
||||
Ain[7] C14M R 1.816 4 0.114 M
|
||||
Din[0] C14M R 8.919 4 0.723 4
|
||||
Din[1] C14M R 8.410 4 1.156 4
|
||||
Din[2] C14M R 8.503 4 1.181 4
|
||||
Din[3] C14M R 8.783 4 0.110 M
|
||||
Din[4] C14M R 10.420 4 1.022 4
|
||||
Din[5] C14M R 8.001 4 0.566 4
|
||||
Din[6] C14M R 9.731 4 1.050 4
|
||||
Din[7] C14M R 10.052 4 0.862 4
|
||||
PHI1 C14M R 2.579 4 3.047 4
|
||||
RD[0] C14M R 0.267 4 0.866 4
|
||||
RD[1] C14M R 0.173 4 0.937 4
|
||||
RD[2] C14M R 0.100 4 1.018 4
|
||||
RD[3] C14M R 0.267 4 0.866 4
|
||||
RD[4] C14M R 0.172 4 0.936 4
|
||||
RD[5] C14M R 0.267 4 0.866 4
|
||||
RD[6] C14M R 0.766 4 0.420 4
|
||||
RD[7] C14M R 0.267 4 0.866 4
|
||||
nC07X C14M R 0.998 4 0.405 6
|
||||
nEN80 C14M R 6.107 4 0.114 M
|
||||
nWE C14M R 6.726 4 0.069 M
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
BA[0] C14M R 8.629 4 2.885 M
|
||||
BA[1] C14M R 8.629 4 2.885 M
|
||||
CKE C14M R 8.629 4 2.885 M
|
||||
DQMH C14M R 8.609 4 2.892 M
|
||||
DQML C14M R 8.609 4 2.892 M
|
||||
Dout[0] C14M F 8.955 4 3.164 M
|
||||
Dout[1] C14M F 8.955 4 3.164 M
|
||||
Dout[2] C14M F 8.944 4 3.158 M
|
||||
Dout[3] C14M F 8.955 4 3.164 M
|
||||
Dout[4] C14M F 8.944 4 3.158 M
|
||||
Dout[5] C14M F 8.944 4 3.158 M
|
||||
Dout[6] C14M F 8.955 4 3.164 M
|
||||
Dout[7] C14M F 8.955 4 3.164 M
|
||||
LED C14M R 19.941 4 8.191 M
|
||||
RA[0] C14M R 10.013 4 3.186 M
|
||||
RA[10] C14M R 8.629 4 2.885 M
|
||||
RA[11] C14M R 8.629 4 2.885 M
|
||||
RA[1] C14M R 8.695 4 2.890 M
|
||||
RA[2] C14M R 8.695 4 2.890 M
|
||||
RA[3] C14M R 10.013 4 3.186 M
|
||||
RA[4] C14M R 8.695 4 2.890 M
|
||||
RA[5] C14M R 8.695 4 2.890 M
|
||||
RA[6] C14M R 8.695 4 2.890 M
|
||||
RA[7] C14M R 8.695 4 2.890 M
|
||||
RA[8] C14M R 8.629 4 2.885 M
|
||||
RA[9] C14M R 8.629 4 2.885 M
|
||||
Vout[0] C14M F 9.553 4 3.402 M
|
||||
Vout[1] C14M F 9.553 4 3.402 M
|
||||
Vout[2] C14M F 9.553 4 3.402 M
|
||||
Vout[3] C14M F 9.553 4 3.402 M
|
||||
Vout[4] C14M F 9.553 4 3.402 M
|
||||
Vout[5] C14M F 9.553 4 3.402 M
|
||||
Vout[6] C14M F 9.553 4 3.402 M
|
||||
Vout[7] C14M F 9.553 4 3.402 M
|
||||
nCAS C14M R 8.629 4 2.885 M
|
||||
nCS C14M R 8.629 4 2.885 M
|
||||
nDOE C14M R 11.976 4 3.776 M
|
||||
nRAS C14M R 8.629 4 2.885 M
|
||||
nRWE C14M R 8.629 4 2.885 M
|
||||
BA[0] C14M R 8.629 4 2.885 M
|
||||
BA[1] C14M R 8.629 4 2.885 M
|
||||
CKEout C14M F 8.629 4 2.885 M
|
||||
DQMH C14M R 8.609 4 2.892 M
|
||||
DQML C14M R 8.609 4 2.892 M
|
||||
LED C14M R 19.935 4 8.161 M
|
||||
RAout[0] C14M F 8.695 4 2.890 M
|
||||
RAout[10] C14M F 8.629 4 2.885 M
|
||||
RAout[11] C14M F 8.629 4 2.885 M
|
||||
RAout[1] C14M F 8.695 4 2.890 M
|
||||
RAout[2] C14M F 8.695 4 2.890 M
|
||||
RAout[3] C14M F 8.695 4 2.890 M
|
||||
RAout[4] C14M F 8.695 4 2.890 M
|
||||
RAout[5] C14M F 8.695 4 2.890 M
|
||||
RAout[6] C14M F 8.695 4 2.890 M
|
||||
RAout[7] C14M F 8.695 4 2.890 M
|
||||
RAout[8] C14M F 8.629 4 2.885 M
|
||||
RAout[9] C14M F 8.629 4 2.885 M
|
||||
RD[0] C14M R 11.414 4 3.265 M
|
||||
RD[1] C14M R 11.811 4 3.265 M
|
||||
RD[2] C14M R 11.925 4 3.265 M
|
||||
RD[3] C14M R 11.384 4 3.265 M
|
||||
RD[4] C14M R 12.301 4 3.371 M
|
||||
RD[5] C14M R 12.767 4 3.371 M
|
||||
RD[6] C14M R 12.010 4 3.371 M
|
||||
RD[7] C14M R 12.313 4 3.371 M
|
||||
Vout[0] C14M R 9.553 4 3.402 M
|
||||
Vout[1] C14M R 9.553 4 3.402 M
|
||||
Vout[2] C14M R 9.553 4 3.402 M
|
||||
Vout[3] C14M R 9.553 4 3.402 M
|
||||
Vout[4] C14M R 9.553 4 3.402 M
|
||||
Vout[5] C14M R 9.553 4 3.402 M
|
||||
Vout[6] C14M R 9.553 4 3.402 M
|
||||
Vout[7] C14M R 9.553 4 3.402 M
|
||||
nCASout C14M F 8.629 4 2.885 M
|
||||
nDOE C14M R 12.048 4 3.811 M
|
||||
nRASout C14M F 8.629 4 2.885 M
|
||||
nRWEout C14M F 8.629 4 2.885 M
|
||||
nVOE C14M R 12.164 4 3.783 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with setup speed: 6
|
||||
WARNING: you must also run trce with hold speed: 6
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Sep 21 05:35:47 2023" vendor="Lattice Semiconductor Corporation" >
|
||||
<userSetting name="//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Dec 28 23:24:03 2023" vendor="Lattice Semiconductor Corporation" >
|
||||
</userSetting>
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
<ReportView version="2.0">
|
||||
<Implement name="impl1">
|
||||
<ToolReport id="tooldec" path="" status="0"/>
|
||||
<ToolReport id="toolhle_genhierarchy" path="Y:/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html" status="1"/>
|
||||
<ToolReport id="toolhle_genhierarchy" path="//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html" status="1"/>
|
||||
<ToolReport id="toolpio" path="" status="2"/>
|
||||
<ToolReport id="toolsso" path="" status="2"/>
|
||||
</Implement>
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EPM240T100C5
|
|||
set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:26:23 AUGUST 20, 2023"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
|
@ -75,7 +75,6 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nEN80
|
|||
|
||||
set_location_assignment PIN_33 -to nWE80
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE80
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE80
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE80
|
||||
|
||||
set_location_assignment PIN_52 -to nC07X
|
||||
|
|
@ -124,7 +123,6 @@ set_location_assignment PIN_85 -to Dout[7]
|
|||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Dout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to Dout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Dout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout
|
||||
|
||||
set_location_assignment PIN_50 -to nVOE
|
||||
|
|
@ -147,40 +145,39 @@ set_instance_assignment -name SLOW_SLEW_RATE ON -to Vout
|
|||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Vout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Vout
|
||||
|
||||
set_location_assignment PIN_4 -to CKE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to CKE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKE
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKE
|
||||
set_location_assignment PIN_4 -to CKEout
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKEout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKEout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to CKEout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKEout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKEout
|
||||
|
||||
set_location_assignment PIN_8 -to nCS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCS
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCS
|
||||
set_location_assignment PIN_8 -to nCSout
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCSout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCSout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCSout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCSout
|
||||
|
||||
set_location_assignment PIN_2 -to nRWE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWE
|
||||
set_location_assignment PIN_2 -to nRWEout
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWEout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWEout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWEout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWEout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWEout
|
||||
|
||||
set_location_assignment PIN_5 -to nRAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRAS
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS
|
||||
set_location_assignment PIN_5 -to nRASout
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRASout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRASout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRASout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRASout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRASout
|
||||
|
||||
set_location_assignment PIN_3 -to nCAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCAS
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS
|
||||
set_location_assignment PIN_3 -to nCASout
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCASout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCASout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCASout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCASout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCASout
|
||||
|
||||
set_location_assignment PIN_6 -to BA[0]
|
||||
set_location_assignment PIN_14 -to BA[1]
|
||||
|
|
@ -190,23 +187,23 @@ set_instance_assignment -name SLOW_SLEW_RATE ON -to BA
|
|||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BA
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to BA
|
||||
|
||||
set_location_assignment PIN_18 -to RA[0]
|
||||
set_location_assignment PIN_20 -to RA[1]
|
||||
set_location_assignment PIN_30 -to RA[2]
|
||||
set_location_assignment PIN_27 -to RA[3]
|
||||
set_location_assignment PIN_26 -to RA[4]
|
||||
set_location_assignment PIN_29 -to RA[5]
|
||||
set_location_assignment PIN_21 -to RA[6]
|
||||
set_location_assignment PIN_19 -to RA[7]
|
||||
set_location_assignment PIN_17 -to RA[8]
|
||||
set_location_assignment PIN_15 -to RA[9]
|
||||
set_location_assignment PIN_16 -to RA[10]
|
||||
set_location_assignment PIN_7 -to RA[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RA
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to RA
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RA
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA
|
||||
set_location_assignment PIN_18 -to RAout[0]
|
||||
set_location_assignment PIN_20 -to RAout[1]
|
||||
set_location_assignment PIN_30 -to RAout[2]
|
||||
set_location_assignment PIN_27 -to RAout[3]
|
||||
set_location_assignment PIN_26 -to RAout[4]
|
||||
set_location_assignment PIN_29 -to RAout[5]
|
||||
set_location_assignment PIN_21 -to RAout[6]
|
||||
set_location_assignment PIN_19 -to RAout[7]
|
||||
set_location_assignment PIN_17 -to RAout[8]
|
||||
set_location_assignment PIN_15 -to RAout[9]
|
||||
set_location_assignment PIN_16 -to RAout[10]
|
||||
set_location_assignment PIN_7 -to RAout[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RAout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RAout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RAout
|
||||
|
||||
set_location_assignment PIN_100 -to DQMH
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQMH
|
||||
|
|
@ -238,11 +235,12 @@ set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
|
|||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
|
||||
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
|
||||
set_global_assignment -name VERILOG_FILE "../RAM2E-MAX.v"
|
||||
set_location_assignment PIN_88 -to LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
|
||||
set_global_assignment -name VERILOG_FILE ../RAM2E.v
|
||||
set_global_assignment -name VERILOG_FILE "../UFM-MAX.v"
|
||||
set_global_assignment -name QIP_FILE UFM.qip
|
||||
set_global_assignment -name MIF_FILE ../RAM2E.mif
|
||||
set_global_assignment -name SDC_FILE ../RAM2E.sdc
|
||||
set_global_assignment -name SDC_FILE "../RAM2E-MAX.sdc"
|
||||
set_location_assignment PIN_88 -to LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
|
||||
set_global_assignment -name SDC_FILE "../RAM2E-MAX.sdc"
|
||||
Binary file not shown.
|
|
@ -1,6 +1,6 @@
|
|||
Assembler report for RAM2E
|
||||
Thu Sep 21 05:34:41 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Thu Dec 28 23:09:46 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
|
@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
|||
2. Assembler Summary
|
||||
3. Assembler Settings
|
||||
4. Assembler Generated Files
|
||||
5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof
|
||||
5. Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof
|
||||
6. Assembler Messages
|
||||
|
||||
|
||||
|
|
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Thu Sep 21 05:34:41 2023 ;
|
||||
; Assembler Status ; Successful - Thu Dec 28 23:09:46 2023 ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
|
|
@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula.
|
|||
+--------+---------+---------------+
|
||||
|
||||
|
||||
+------------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+------------------------------------------------+
|
||||
; File Name ;
|
||||
+------------------------------------------------+
|
||||
; /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
|
||||
+------------------------------------------------+
|
||||
+--------------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+--------------------------------------------------+
|
||||
; File Name ;
|
||||
+--------------------------------------------------+
|
||||
; Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
|
||||
+--------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------+
|
||||
; Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
|
||||
+----------------+---------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+---------------------------------------------------------+
|
||||
; JTAG usercode ; 0x0016D33C ;
|
||||
; Checksum ; 0x0016D634 ;
|
||||
+----------------+---------------------------------------------------------+
|
||||
+----------------------------------------------------------------------------+
|
||||
; Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
|
||||
+----------------+-----------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+-----------------------------------------------------------+
|
||||
; JTAG usercode ; 0x00165DEE ;
|
||||
; Checksum ; 0x0016605E ;
|
||||
+----------------+-----------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------+
|
||||
|
|
@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula.
|
|||
+--------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Assembler
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:34:39 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Thu Dec 28 23:09:46 2023
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 13092 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:41 2023
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Peak virtual memory: 13071 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:47 2023
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Thu Sep 21 05:34:46 2023
|
||||
Thu Dec 28 23:09:51 2023
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
Fitter report for RAM2E
|
||||
Thu Sep 21 05:34:37 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Thu Dec 28 23:09:44 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
|
@ -54,21 +54,21 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Fitter Status ; Successful - Thu Sep 21 05:34:37 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 197 / 240 ( 82 % ) ;
|
||||
; Total pins ; 70 / 80 ( 88 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
+-------------------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
; Fitter Status ; Successful - Thu Dec 28 23:09:44 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 238 / 240 ( 99 % ) ;
|
||||
; Total pins ; 70 / 80 ( 88 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
|
@ -134,15 +134,15 @@ https://fpgasoftware.intel.com/eula.
|
|||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 1.2% ;
|
||||
; Processors 3-4 ; 1.1% ;
|
||||
; Processor 2 ; 1.1% ;
|
||||
; Processors 3-4 ; 1.0% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
+--------------+
|
||||
; Pin-Out File ;
|
||||
+--------------+
|
||||
The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
|
||||
The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
|
|
@ -150,27 +150,27 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
|
|||
+---------------------------------------------+-----------------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-----------------------+
|
||||
; Total logic elements ; 197 / 240 ( 82 % ) ;
|
||||
; -- Combinational with no register ; 85 ;
|
||||
; -- Register only ; 19 ;
|
||||
; -- Combinational with a register ; 93 ;
|
||||
; Total logic elements ; 238 / 240 ( 99 % ) ;
|
||||
; -- Combinational with no register ; 115 ;
|
||||
; -- Register only ; 26 ;
|
||||
; -- Combinational with a register ; 97 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 103 ;
|
||||
; -- 3 input functions ; 29 ;
|
||||
; -- 2 input functions ; 42 ;
|
||||
; -- 1 input functions ; 3 ;
|
||||
; -- 4 input functions ; 118 ;
|
||||
; -- 3 input functions ; 41 ;
|
||||
; -- 2 input functions ; 48 ;
|
||||
; -- 1 input functions ; 4 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 183 ;
|
||||
; -- normal mode ; 224 ;
|
||||
; -- arithmetic mode ; 14 ;
|
||||
; -- qfbk mode ; 8 ;
|
||||
; -- qfbk mode ; 6 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 12 ;
|
||||
; -- synchronous clear/load mode ; 24 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 112 / 240 ( 47 % ) ;
|
||||
; Total registers ; 123 / 240 ( 51 % ) ;
|
||||
; Total LABs ; 24 / 24 ( 100 % ) ;
|
||||
; Logic elements in carry chains ; 15 ;
|
||||
; Virtual pins ; 0 ;
|
||||
|
|
@ -185,11 +185,11 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
|
|||
; Global signals ; 1 ;
|
||||
; -- Global clocks ; 1 / 4 ( 25 % ) ;
|
||||
; JTAGs ; 0 / 1 ( 0 % ) ;
|
||||
; Average interconnect usage (total/H/V) ; 22.5% / 24.3% / 20.7% ;
|
||||
; Peak interconnect usage (total/H/V) ; 22.5% / 24.3% / 20.7% ;
|
||||
; Maximum fan-out ; 112 ;
|
||||
; Highest non-global fan-out ; 31 ;
|
||||
; Total fan-out ; 847 ;
|
||||
; Average interconnect usage (total/H/V) ; 26.0% / 25.7% / 26.3% ;
|
||||
; Peak interconnect usage (total/H/V) ; 26.0% / 25.7% / 26.3% ;
|
||||
; Maximum fan-out ; 123 ;
|
||||
; Highest non-global fan-out ; 35 ;
|
||||
; Total fan-out ; 976 ;
|
||||
; Average fan-out ; 3.16 ;
|
||||
+---------------------------------------------+-----------------------+
|
||||
|
||||
|
|
@ -207,69 +207,69 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
|
|||
; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 112 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 14 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 123 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 15 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 12 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nWE80 ; 33 ; 1 ; 3 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nWE80 ; 33 ; 1 ; 3 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Output Pins ;
|
||||
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
|
||||
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
; BA[0] ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; CKE ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[3] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[4] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nCAS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nCS ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nRAS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nRWE ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Output Pins ;
|
||||
+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
|
||||
+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
; BA[0] ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; CKEout ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[3] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[4] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RAout[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nCASout ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nCSout ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nRASout ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nRWEout ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
|
@ -304,35 +304,35 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
|
|||
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
|
||||
+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
|
||||
; 1 ; 83 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 2 ; 0 ; 1 ; nRWE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 3 ; 1 ; 1 ; nCAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 4 ; 2 ; 1 ; CKE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 5 ; 3 ; 1 ; nRAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 2 ; 0 ; 1 ; nRWEout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 3 ; 1 ; 1 ; nCASout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 4 ; 2 ; 1 ; CKEout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 5 ; 3 ; 1 ; nRASout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 6 ; 4 ; 1 ; BA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 7 ; 5 ; 1 ; RA[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 8 ; 6 ; 1 ; nCS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 7 ; 5 ; 1 ; RAout[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 8 ; 6 ; 1 ; nCSout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
|
||||
; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; 12 ; 7 ; 1 ; C14M ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
|
||||
; 14 ; 8 ; 1 ; BA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 15 ; 9 ; 1 ; RA[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 16 ; 10 ; 1 ; RA[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 17 ; 11 ; 1 ; RA[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 18 ; 12 ; 1 ; RA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 19 ; 13 ; 1 ; RA[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 20 ; 14 ; 1 ; RA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 21 ; 15 ; 1 ; RA[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 15 ; 9 ; 1 ; RAout[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 16 ; 10 ; 1 ; RAout[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 17 ; 11 ; 1 ; RAout[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 18 ; 12 ; 1 ; RAout[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 19 ; 13 ; 1 ; RAout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 20 ; 14 ; 1 ; RAout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 21 ; 15 ; 1 ; RAout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
|
||||
; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
|
||||
; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
|
||||
; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
|
||||
; 26 ; 20 ; 1 ; RA[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 27 ; 21 ; 1 ; RA[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 26 ; 20 ; 1 ; RAout[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 27 ; 21 ; 1 ; RAout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 28 ; 22 ; 1 ; nEN80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 29 ; 23 ; 1 ; RA[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 30 ; 24 ; 1 ; RA[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 29 ; 23 ; 1 ; RAout[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 30 ; 24 ; 1 ; RAout[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
|
||||
; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; 33 ; 25 ; 1 ; nWE80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
|
|
@ -423,112 +423,119 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
|
|||
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Fitter Resource Utilization by Entity ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 197 (197) ; 112 ; 1 ; 70 ; 0 ; 85 (85) ; 19 (19) ; 93 (93) ; 15 (15) ; 8 (8) ; |RAM2E ; RAM2E ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Fitter Resource Utilization by Entity ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 238 (180) ; 123 ; 1 ; 70 ; 0 ; 115 (90) ; 26 (23) ; 97 (67) ; 15 (15) ; 6 (1) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E_UFM:ram2e_ufm| ; 58 (58) ; 33 ; 1 ; 0 ; 0 ; 25 (25) ; 3 (3) ; 30 (30) ; 0 (0) ; 5 (5) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
|
||||
+------------------------------------+
|
||||
; Delay Chain Summary ;
|
||||
+---------+----------+---------------+
|
||||
; Name ; Pin Type ; Pad to Core 0 ;
|
||||
+---------+----------+---------------+
|
||||
; LED ; Output ; -- ;
|
||||
; Dout[0] ; Output ; -- ;
|
||||
; Dout[1] ; Output ; -- ;
|
||||
; Dout[2] ; Output ; -- ;
|
||||
; Dout[3] ; Output ; -- ;
|
||||
; Dout[4] ; Output ; -- ;
|
||||
; Dout[5] ; Output ; -- ;
|
||||
; Dout[6] ; Output ; -- ;
|
||||
; Dout[7] ; Output ; -- ;
|
||||
; nDOE ; Output ; -- ;
|
||||
; Vout[0] ; Output ; -- ;
|
||||
; Vout[1] ; Output ; -- ;
|
||||
; Vout[2] ; Output ; -- ;
|
||||
; Vout[3] ; Output ; -- ;
|
||||
; Vout[4] ; Output ; -- ;
|
||||
; Vout[5] ; Output ; -- ;
|
||||
; Vout[6] ; Output ; -- ;
|
||||
; Vout[7] ; Output ; -- ;
|
||||
; nVOE ; Output ; -- ;
|
||||
; CKE ; Output ; -- ;
|
||||
; nCS ; Output ; -- ;
|
||||
; nRAS ; Output ; -- ;
|
||||
; nCAS ; Output ; -- ;
|
||||
; nRWE ; Output ; -- ;
|
||||
; BA[0] ; Output ; -- ;
|
||||
; BA[1] ; Output ; -- ;
|
||||
; RA[0] ; Output ; -- ;
|
||||
; RA[1] ; Output ; -- ;
|
||||
; RA[2] ; Output ; -- ;
|
||||
; RA[3] ; Output ; -- ;
|
||||
; RA[4] ; Output ; -- ;
|
||||
; RA[5] ; Output ; -- ;
|
||||
; RA[6] ; Output ; -- ;
|
||||
; RA[7] ; Output ; -- ;
|
||||
; RA[8] ; Output ; -- ;
|
||||
; RA[9] ; Output ; -- ;
|
||||
; RA[10] ; Output ; -- ;
|
||||
; RA[11] ; Output ; -- ;
|
||||
; DQML ; Output ; -- ;
|
||||
; DQMH ; Output ; -- ;
|
||||
; RD[0] ; Bidir ; (0) ;
|
||||
; RD[1] ; Bidir ; (0) ;
|
||||
; RD[2] ; Bidir ; (0) ;
|
||||
; RD[3] ; Bidir ; (0) ;
|
||||
; RD[4] ; Bidir ; (0) ;
|
||||
; RD[5] ; Bidir ; (0) ;
|
||||
; RD[6] ; Bidir ; (0) ;
|
||||
; RD[7] ; Bidir ; (0) ;
|
||||
; nEN80 ; Input ; (0) ;
|
||||
; nWE ; Input ; (0) ;
|
||||
; PHI1 ; Input ; (1) ;
|
||||
; Din[0] ; Input ; (0) ;
|
||||
; C14M ; Input ; (0) ;
|
||||
; nWE80 ; Input ; (0) ;
|
||||
; Ain[0] ; Input ; (0) ;
|
||||
; Ain[1] ; Input ; (0) ;
|
||||
; Ain[2] ; Input ; (0) ;
|
||||
; Ain[3] ; Input ; (0) ;
|
||||
; Ain[4] ; Input ; (0) ;
|
||||
; Ain[5] ; Input ; (0) ;
|
||||
; Ain[6] ; Input ; (0) ;
|
||||
; Ain[7] ; Input ; (0) ;
|
||||
; Din[6] ; Input ; (0) ;
|
||||
; Din[2] ; Input ; (0) ;
|
||||
; Din[1] ; Input ; (0) ;
|
||||
; Din[5] ; Input ; (0) ;
|
||||
; Din[7] ; Input ; (0) ;
|
||||
; Din[4] ; Input ; (0) ;
|
||||
; Din[3] ; Input ; (0) ;
|
||||
; nC07X ; Input ; (0) ;
|
||||
+---------+----------+---------------+
|
||||
+--------------------------------------+
|
||||
; Delay Chain Summary ;
|
||||
+-----------+----------+---------------+
|
||||
; Name ; Pin Type ; Pad to Core 0 ;
|
||||
+-----------+----------+---------------+
|
||||
; LED ; Output ; -- ;
|
||||
; nWE80 ; Input ; (0) ;
|
||||
; Dout[0] ; Output ; -- ;
|
||||
; Dout[1] ; Output ; -- ;
|
||||
; Dout[2] ; Output ; -- ;
|
||||
; Dout[3] ; Output ; -- ;
|
||||
; Dout[4] ; Output ; -- ;
|
||||
; Dout[5] ; Output ; -- ;
|
||||
; Dout[6] ; Output ; -- ;
|
||||
; Dout[7] ; Output ; -- ;
|
||||
; nDOE ; Output ; -- ;
|
||||
; Vout[0] ; Output ; -- ;
|
||||
; Vout[1] ; Output ; -- ;
|
||||
; Vout[2] ; Output ; -- ;
|
||||
; Vout[3] ; Output ; -- ;
|
||||
; Vout[4] ; Output ; -- ;
|
||||
; Vout[5] ; Output ; -- ;
|
||||
; Vout[6] ; Output ; -- ;
|
||||
; Vout[7] ; Output ; -- ;
|
||||
; nVOE ; Output ; -- ;
|
||||
; CKEout ; Output ; -- ;
|
||||
; nCSout ; Output ; -- ;
|
||||
; nRASout ; Output ; -- ;
|
||||
; nCASout ; Output ; -- ;
|
||||
; nRWEout ; Output ; -- ;
|
||||
; BA[0] ; Output ; -- ;
|
||||
; BA[1] ; Output ; -- ;
|
||||
; RAout[0] ; Output ; -- ;
|
||||
; RAout[1] ; Output ; -- ;
|
||||
; RAout[2] ; Output ; -- ;
|
||||
; RAout[3] ; Output ; -- ;
|
||||
; RAout[4] ; Output ; -- ;
|
||||
; RAout[5] ; Output ; -- ;
|
||||
; RAout[6] ; Output ; -- ;
|
||||
; RAout[7] ; Output ; -- ;
|
||||
; RAout[8] ; Output ; -- ;
|
||||
; RAout[9] ; Output ; -- ;
|
||||
; RAout[10] ; Output ; -- ;
|
||||
; RAout[11] ; Output ; -- ;
|
||||
; DQML ; Output ; -- ;
|
||||
; DQMH ; Output ; -- ;
|
||||
; RD[0] ; Bidir ; (0) ;
|
||||
; RD[1] ; Bidir ; (0) ;
|
||||
; RD[2] ; Bidir ; (0) ;
|
||||
; RD[3] ; Bidir ; (0) ;
|
||||
; RD[4] ; Bidir ; (0) ;
|
||||
; RD[5] ; Bidir ; (0) ;
|
||||
; RD[6] ; Bidir ; (0) ;
|
||||
; RD[7] ; Bidir ; (0) ;
|
||||
; nEN80 ; Input ; (0) ;
|
||||
; nWE ; Input ; (0) ;
|
||||
; PHI1 ; Input ; (1) ;
|
||||
; C14M ; Input ; (0) ;
|
||||
; Din[0] ; Input ; (0) ;
|
||||
; Din[6] ; Input ; (0) ;
|
||||
; Din[1] ; Input ; (0) ;
|
||||
; Din[5] ; Input ; (0) ;
|
||||
; Din[7] ; Input ; (0) ;
|
||||
; Din[4] ; Input ; (0) ;
|
||||
; Din[2] ; Input ; (0) ;
|
||||
; Din[3] ; Input ; (0) ;
|
||||
; nC07X ; Input ; (0) ;
|
||||
; Ain[0] ; Input ; (0) ;
|
||||
; Ain[1] ; Input ; (0) ;
|
||||
; Ain[2] ; Input ; (0) ;
|
||||
; Ain[3] ; Input ; (0) ;
|
||||
; Ain[4] ; Input ; (0) ;
|
||||
; Ain[5] ; Input ; (0) ;
|
||||
; Ain[6] ; Input ; (0) ;
|
||||
; Ain[7] ; Input ; (0) ;
|
||||
+-----------+----------+---------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------+
|
||||
; Control Signals ;
|
||||
+------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; C14M ; PIN_12 ; 112 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; CS[0]~2 ; LC_X3_Y2_N8 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal9~1 ; LC_X3_Y3_N0 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal9~2 ; LC_X7_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RA[0]~15 ; LC_X2_Y2_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RDOE ; LC_X3_Y3_N5 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; RWMask~1 ; LC_X4_Y1_N4 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; S[2] ; LC_X6_Y3_N6 ; 22 ; Sync. clear ; no ; -- ; -- ;
|
||||
; UFMD[15]~0 ; LC_X6_Y1_N2 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; always2~8 ; LC_X3_Y3_N7 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
+------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
+---------------------------------------------------------------------------------------------------------------------------+
|
||||
; Control Signals ;
|
||||
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; BA[1]~0 ; LC_X2_Y2_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; C14M ; PIN_12 ; 123 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; CS[0]~2 ; LC_X6_Y4_N2 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; DQML~0 ; LC_X2_Y4_N0 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~1 ; LC_X7_Y4_N1 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~2 ; LC_X7_Y4_N2 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~4 ; LC_X5_Y4_N7 ; 4 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~5 ; LC_X4_Y4_N9 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; Mux14~0 ; LC_X2_Y2_N0 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X6_Y1_N3 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X4_Y1_N1 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X7_Y4_N3 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
; RA[2]~0 ; LC_X2_Y2_N5 ; 6 ; Clock enable ; no ; -- ; -- ;
|
||||
; RDOE ; LC_X7_Y2_N7 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; S[0] ; LC_X7_Y3_N8 ; 35 ; Sync. clear ; no ; -- ; -- ;
|
||||
; S[3] ; LC_X5_Y4_N6 ; 32 ; Sync. clear ; no ; -- ; -- ;
|
||||
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
|
|
@ -536,7 +543,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+------+----------+---------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
; C14M ; PIN_12 ; 112 ; Global Clock ; GCLK0 ;
|
||||
; C14M ; PIN_12 ; 123 ; Global Clock ; GCLK0 ;
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
|
||||
|
||||
|
|
@ -545,120 +552,122 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+-----------------------+--------------------+
|
||||
; Routing Resource Type ; Usage ;
|
||||
+-----------------------+--------------------+
|
||||
; C4s ; 139 / 784 ( 18 % ) ;
|
||||
; Direct links ; 38 / 888 ( 4 % ) ;
|
||||
; C4s ; 163 / 784 ( 21 % ) ;
|
||||
; Direct links ; 46 / 888 ( 5 % ) ;
|
||||
; Global clocks ; 1 / 4 ( 25 % ) ;
|
||||
; LAB clocks ; 6 / 32 ( 19 % ) ;
|
||||
; LUT chains ; 4 / 216 ( 2 % ) ;
|
||||
; Local interconnects ; 282 / 888 ( 32 % ) ;
|
||||
; R4s ; 134 / 704 ( 19 % ) ;
|
||||
; LUT chains ; 9 / 216 ( 4 % ) ;
|
||||
; Local interconnects ; 324 / 888 ( 36 % ) ;
|
||||
; R4s ; 142 / 704 ( 20 % ) ;
|
||||
+-----------------------+--------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Logic Elements ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; Number of Logic Elements (Average = 8.21) ; Number of LABs (Total = 24) ;
|
||||
; Number of Logic Elements (Average = 9.92) ; Number of LABs (Total = 24) ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; 1 ; 2 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 1 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 1 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 3 ;
|
||||
; 9 ; 3 ;
|
||||
; 10 ; 13 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 23 ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; LAB-wide Signals ;
|
||||
+------------------------------------+------------------------------+
|
||||
; LAB-wide Signals (Average = 1.38) ; Number of LABs (Total = 24) ;
|
||||
; LAB-wide Signals (Average = 1.54) ; Number of LABs (Total = 24) ;
|
||||
+------------------------------------+------------------------------+
|
||||
; 1 Clock ; 23 ;
|
||||
; 1 Clock enable ; 9 ;
|
||||
; 2 Clock enables ; 1 ;
|
||||
; 1 Clock enable ; 10 ;
|
||||
; 1 Sync. clear ; 2 ;
|
||||
; 2 Clock enables ; 2 ;
|
||||
+------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced (Average = 8.54) ; Number of LABs (Total = 24) ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 2 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 3 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 11 ;
|
||||
; 11 ; 1 ;
|
||||
; 12 ; 1 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 1 ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
+-----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced (Average = 10.17) ; Number of LABs (Total = 24) ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 21 ;
|
||||
; 11 ; 1 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 1 ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced Out ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced Out (Average = 6.33) ; Number of LABs (Total = 24) ;
|
||||
; Number of Signals Sourced Out (Average = 7.08) ; Number of LABs (Total = 24) ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 2 ;
|
||||
; 1 ; 1 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 2 ;
|
||||
; 4 ; 2 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 3 ;
|
||||
; 6 ; 4 ;
|
||||
; 6 ; 2 ;
|
||||
; 7 ; 3 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 2 ;
|
||||
; 8 ; 4 ;
|
||||
; 9 ; 4 ;
|
||||
; 10 ; 3 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 1 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 1 ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; Number of Distinct Inputs (Average = 10.42) ; Number of LABs (Total = 24) ;
|
||||
; Number of Distinct Inputs (Average = 12.17) ; Number of LABs (Total = 24) ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 3 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 2 ;
|
||||
; 6 ; 2 ;
|
||||
; 7 ; 1 ;
|
||||
; 8 ; 3 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 2 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 1 ;
|
||||
; 10 ; 0 ;
|
||||
; 11 ; 2 ;
|
||||
; 12 ; 2 ;
|
||||
; 13 ; 1 ;
|
||||
; 14 ; 2 ;
|
||||
; 10 ; 2 ;
|
||||
; 11 ; 1 ;
|
||||
; 12 ; 3 ;
|
||||
; 13 ; 3 ;
|
||||
; 14 ; 1 ;
|
||||
; 15 ; 1 ;
|
||||
; 16 ; 1 ;
|
||||
; 17 ; 1 ;
|
||||
; 18 ; 0 ;
|
||||
; 19 ; 1 ;
|
||||
; 16 ; 2 ;
|
||||
; 17 ; 2 ;
|
||||
; 18 ; 1 ;
|
||||
; 19 ; 0 ;
|
||||
; 20 ; 0 ;
|
||||
; 21 ; 0 ;
|
||||
; 22 ; 0 ;
|
||||
; 23 ; 0 ;
|
||||
; 24 ; 0 ;
|
||||
; 25 ; 1 ;
|
||||
; 24 ; 1 ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
|
|
@ -697,17 +706,17 @@ Info (332129): Detected timing requirements -- optimizing circuit to achieve onl
|
|||
Info (332111): Found 3 clocks
|
||||
Info (332111): Period Clock Name
|
||||
Info (332111): ======== ============
|
||||
Info (332111): 200.000 ARCLK
|
||||
Info (332111): 69.841 C14M
|
||||
Info (332111): 200.000 DRCLK
|
||||
Info (332111): 200.000 ram2e_ufm|ARCLK|regout
|
||||
Info (332111): 200.000 ram2e_ufm|DRCLK|regout
|
||||
Info (186079): Completed User Assigned Global Signals Promotion Operation
|
||||
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 8
|
||||
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8
|
||||
Info (186079): Completed Auto Global Promotion Operation
|
||||
Info (176234): Starting register packing
|
||||
Info (186468): Started processing fast register assignments
|
||||
Info (186469): Finished processing fast register assignments
|
||||
Info (176235): Finished register packing
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
|
||||
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
|
||||
Info (170189): Fitter placement preparation operations beginning
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
|
||||
|
|
@ -715,18 +724,17 @@ Info (170191): Fitter placement operations beginning
|
|||
Info (170137): Fitter placement was successful
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
|
||||
Info (170193): Fitter routing operations beginning
|
||||
Info (170089): 5e+01 ns of routing delay (approximately 3.1% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
|
||||
Info (170195): Router estimated average interconnect usage is 20% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
||||
Info (170201): Optimizations that may affect the design's routability were skipped
|
||||
Info (170089): 5e+01 ns of routing delay (approximately 3.0% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
|
||||
Info (170195): Router estimated average interconnect usage is 24% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 24% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.83 seconds.
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.84 seconds.
|
||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg
|
||||
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 13770 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:37 2023
|
||||
Info: Peak virtual memory: 13747 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:44 2023
|
||||
Info: Elapsed time: 00:00:04
|
||||
Info: Total CPU time (on all processors): 00:00:04
|
||||
|
||||
|
|
@ -734,6 +742,6 @@ Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
|
|||
+----------------------------+
|
||||
; Fitter Suppressed Messages ;
|
||||
+----------------------------+
|
||||
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg.
|
||||
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg.
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
Fitter Status : Successful - Thu Sep 21 05:34:37 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Fitter Status : Successful - Thu Dec 28 23:09:44 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
Family : MAX II
|
||||
Device : EPM240T100C5
|
||||
Timing Models : Final
|
||||
Total logic elements : 197 / 240 ( 82 % )
|
||||
Total logic elements : 238 / 240 ( 99 % )
|
||||
Total pins : 70 / 80 ( 88 % )
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
Flow report for RAM2E
|
||||
Thu Sep 21 05:34:45 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Thu Dec 28 23:09:50 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
|
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Flow Status ; Successful - Thu Sep 21 05:34:41 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 197 / 240 ( 82 % ) ;
|
||||
; Total pins ; 70 / 80 ( 88 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
+-------------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
; Flow Status ; Successful - Thu Dec 28 23:09:46 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 238 / 240 ( 99 % ) ;
|
||||
; Total pins ; 70 / 80 ( 88 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
|
|
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 09/21/2023 05:33:57 ;
|
||||
; Start date & time ; 12/28/2023 23:09:12 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; RAM2E ;
|
||||
+-------------------+---------------------+
|
||||
|
|
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.169528883703908 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.170382295203604 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
|
||||
|
|
@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula.
|
|||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:35 ; 1.0 ; 13144 MB ; 00:00:49 ;
|
||||
; Fitter ; 00:00:04 ; 1.0 ; 13770 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:02 ; 1.0 ; 13091 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13089 MB ; 00:00:02 ;
|
||||
; Total ; 00:00:43 ; -- ; -- ; 00:00:56 ;
|
||||
; Analysis & Synthesis ; 00:00:28 ; 1.0 ; 13113 MB ; 00:00:42 ;
|
||||
; Fitter ; 00:00:04 ; 1.0 ; 13747 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:00 ; 1.0 ; 13067 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13064 MB ; 00:00:02 ;
|
||||
; Total ; 00:00:34 ; -- ; -- ; 00:00:49 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="c40857e37f967e83d8af"/>
|
||||
<hash md5_digest_80b="f1177731eb35f907c990"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EPM240T100C5" path="RAM2E.sof" usercode="0xFFFFFFFF"/>
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
Analysis & Synthesis report for RAM2E
|
||||
Thu Sep 21 05:34:32 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Thu Dec 28 23:09:39 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
|
@ -17,7 +17,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
|||
9. General Register Statistics
|
||||
10. Inverted Register Statistics
|
||||
11. Multiplexer Restructuring Statistics (Restructuring Performed)
|
||||
12. Port Connectivity Checks: "UFM:UFM_inst"
|
||||
12. Port Connectivity Checks: "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst"
|
||||
13. Analysis & Synthesis Messages
|
||||
14. Analysis & Synthesis Suppressed Messages
|
||||
|
||||
|
|
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Thu Sep 21 05:34:32 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Total logic elements ; 205 ;
|
||||
; Total pins ; 70 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
+-------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+-------------------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Thu Dec 28 23:09:39 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Total logic elements ; 244 ;
|
||||
; Total pins ; 70 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------------+-------------------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
|
|
@ -146,15 +146,16 @@ https://fpgasoftware.intel.com/eula.
|
|||
+----------------------------+-------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
|
||||
; ../RAM2E-MAX.v ; yes ; User Verilog HDL File ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v ; ;
|
||||
; UFM.v ; yes ; User Wizard-Generated File ; //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v ; ;
|
||||
; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.mif ; ;
|
||||
+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+----------------------------------+---------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+----------------------------------+---------------------------------+---------+
|
||||
; ../RAM2E.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/RAM2E.v ; ;
|
||||
; ../UFM-MAX.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/UFM-MAX.v ; ;
|
||||
; UFM.v ; yes ; User Wizard-Generated File ; Y:/Repos/RAM2E/CPLD/MAXII/UFM.v ; ;
|
||||
; ../RAM2E.mif ; yes ; User Memory Initialization File ; Y:/Repos/RAM2E/CPLD/RAM2E.mif ; ;
|
||||
+----------------------------------+-----------------+----------------------------------+---------------------------------+---------+
|
||||
|
||||
|
||||
+-----------------------------------------------------+
|
||||
|
|
@ -162,56 +163,57 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------------+-------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-------+
|
||||
; Total logic elements ; 205 ;
|
||||
; -- Combinational with no register ; 93 ;
|
||||
; -- Register only ; 27 ;
|
||||
; -- Combinational with a register ; 85 ;
|
||||
; Total logic elements ; 244 ;
|
||||
; -- Combinational with no register ; 121 ;
|
||||
; -- Register only ; 32 ;
|
||||
; -- Combinational with a register ; 91 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 103 ;
|
||||
; -- 3 input functions ; 29 ;
|
||||
; -- 2 input functions ; 42 ;
|
||||
; -- 1 input functions ; 3 ;
|
||||
; -- 4 input functions ; 118 ;
|
||||
; -- 3 input functions ; 41 ;
|
||||
; -- 2 input functions ; 48 ;
|
||||
; -- 1 input functions ; 4 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 191 ;
|
||||
; -- normal mode ; 230 ;
|
||||
; -- arithmetic mode ; 14 ;
|
||||
; -- qfbk mode ; 0 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 1 ;
|
||||
; -- synchronous clear/load mode ; 3 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 112 ;
|
||||
; Total registers ; 123 ;
|
||||
; Total logic cells in carry chains ; 15 ;
|
||||
; I/O pins ; 70 ;
|
||||
; UFM blocks ; 1 ;
|
||||
; Maximum fan-out node ; C14M ;
|
||||
; Maximum fan-out ; 112 ;
|
||||
; Total fan-out ; 850 ;
|
||||
; Average fan-out ; 3.08 ;
|
||||
; Maximum fan-out ; 123 ;
|
||||
; Total fan-out ; 977 ;
|
||||
; Average fan-out ; 3.10 ;
|
||||
+---------------------------------------------+-------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 205 (205) ; 112 ; 1 ; 70 ; 0 ; 93 (93) ; 27 (27) ; 85 (85) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 244 (181) ; 123 ; 1 ; 70 ; 0 ; 121 (91) ; 32 (24) ; 91 (66) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E_UFM:ram2e_ufm| ; 63 (63) ; 33 ; 1 ; 0 ; 0 ; 30 (30) ; 8 (8) ; 25 (25) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis IP Cores Summary ;
|
||||
+--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+
|
||||
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
|
||||
+--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+
|
||||
; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1 ; N/A ; N/A ; |RAM2E|UFM:UFM_inst ; UFM.v ;
|
||||
+--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis IP Cores Summary ;
|
||||
+--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+
|
||||
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
|
||||
+--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+
|
||||
; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1 ; N/A ; N/A ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM.v ;
|
||||
+--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+
|
||||
|
||||
|
||||
+------------------------------------------------------+
|
||||
|
|
@ -219,12 +221,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 112 ;
|
||||
; Number of registers using Synchronous Clear ; 1 ;
|
||||
; Total registers ; 123 ;
|
||||
; Number of registers using Synchronous Clear ; 3 ;
|
||||
; Number of registers using Synchronous Load ; 0 ;
|
||||
; Number of registers using Asynchronous Clear ; 0 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 60 ;
|
||||
; Number of registers using Clock Enable ; 62 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
|
|
@ -234,30 +236,36 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+----------------------------------------+---------+
|
||||
; Inverted Register ; Fan out ;
|
||||
+----------------------------------------+---------+
|
||||
; nCS~reg0 ; 1 ;
|
||||
; nRAS~reg0 ; 1 ;
|
||||
; nCAS~reg0 ; 1 ;
|
||||
; nRWE~reg0 ; 1 ;
|
||||
; nRASout~reg0 ; 1 ;
|
||||
; nCASout~reg0 ; 1 ;
|
||||
; nRWEout~reg0 ; 1 ;
|
||||
; DQML~reg0 ; 1 ;
|
||||
; DQMH~reg0 ; 1 ;
|
||||
; Total number of inverted registers = 6 ; ;
|
||||
; CKE ; 1 ;
|
||||
; nRAS ; 1 ;
|
||||
; nCAS ; 1 ;
|
||||
; nRWE ; 1 ;
|
||||
; Total number of inverted registers = 9 ; ;
|
||||
+----------------------------------------+---------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |RAM2E|RA[0]~reg0 ;
|
||||
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[2] ;
|
||||
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[0] ;
|
||||
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RWMask[4] ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
|
||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
|
||||
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[0] ;
|
||||
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[0] ;
|
||||
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RAM2E_UFM:ram2e_ufm|RWMask[5] ;
|
||||
; 16:1 ; 2 bits ; 20 LEs ; 2 LEs ; 18 LEs ; Yes ; |RAM2E|BA[1]~reg0 ;
|
||||
; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |RAM2E|RA[4] ;
|
||||
; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |RAM2E|RA[2] ;
|
||||
; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |RAM2E|DQML~reg0 ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "UFM:UFM_inst" ;
|
||||
; Port Connectivity Checks: "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" ;
|
||||
+--------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+--------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
|
|
@ -272,35 +280,50 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:33:57 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Thu Dec 28 23:09:11 2023
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2e/cpld/ram2e-max.v
|
||||
Info (12023): Found entity 1: RAM2E File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 1
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e.v
|
||||
Info (12023): Found entity 1: RAM2E File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 1
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ufm-max.v
|
||||
Info (12023): Found entity 1: RAM2E_UFM File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1
|
||||
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
|
||||
Info (12023): Found entity 1: UFM_altufm_none_lbr File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47
|
||||
Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166
|
||||
Info (12023): Found entity 1: UFM_altufm_none_lbr File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47
|
||||
Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166
|
||||
Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
|
||||
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 93
|
||||
Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217
|
||||
Info (21057): Implemented 276 device resources after synthesis - the final resource count might be different
|
||||
Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 112
|
||||
Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 79
|
||||
Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "nCSout" is stuck at GND File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 78
|
||||
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (21074): Design contains 1 input pin(s) that do not drive logic
|
||||
Warning (15610): No output dependent on input pin "nWE80" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 11
|
||||
Info (21057): Implemented 315 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 22 input pins
|
||||
Info (21059): Implemented 40 output pins
|
||||
Info (21060): Implemented 8 bidirectional pins
|
||||
Info (21061): Implemented 205 logic cells
|
||||
Info (21061): Implemented 244 logic cells
|
||||
Info (21070): Implemented 1 User Flash Memory blocks
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 13144 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:32 2023
|
||||
Info: Elapsed time: 00:00:35
|
||||
Info: Total CPU time (on all processors): 00:00:49
|
||||
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
|
||||
Info: Peak virtual memory: 13113 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:39 2023
|
||||
Info: Elapsed time: 00:00:28
|
||||
Info: Total CPU time (on all processors): 00:00:42
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Analysis & Synthesis Suppressed Messages ;
|
||||
+------------------------------------------+
|
||||
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg.
|
||||
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg.
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
Warning (10273): Verilog HDL warning at RAM2E-MAX.v(46): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 46
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189
|
||||
Warning (10273): Verilog HDL warning at RAM2E.v(74): extended using "x" or "z" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 74
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
Analysis & Synthesis Status : Successful - Thu Sep 21 05:34:32 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Analysis & Synthesis Status : Successful - Thu Dec 28 23:09:39 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
Family : MAX II
|
||||
Total logic elements : 205
|
||||
Total logic elements : 244
|
||||
Total pins : 70
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
|
|
|||
|
|
@ -58,41 +58,41 @@
|
|||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
CHIP "RAM2E" ASSIGNED TO AN: EPM240T100C5
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
GND* : 1 : : : : 2 :
|
||||
nRWE : 2 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nCAS : 3 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
CKE : 4 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nRAS : 5 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nRWEout : 2 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nCASout : 3 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
CKEout : 4 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nRASout : 5 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
BA[0] : 6 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nCS : 8 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nCSout : 8 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
VCCIO1 : 9 : power : : 3.3V : 1 :
|
||||
GNDIO : 10 : gnd : : : :
|
||||
GNDINT : 11 : gnd : : : :
|
||||
C14M : 12 : input : 3.3-V LVCMOS : : 1 : Y
|
||||
VCCINT : 13 : power : : 2.5V/3.3V : :
|
||||
BA[1] : 14 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[8] : 17 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[0] : 18 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[7] : 19 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[1] : 20 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[6] : 21 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[8] : 17 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[0] : 18 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[7] : 19 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[1] : 20 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[6] : 21 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
TMS : 22 : input : : : 1 :
|
||||
TDI : 23 : input : : : 1 :
|
||||
TCK : 24 : input : : : 1 :
|
||||
TDO : 25 : output : : : 1 :
|
||||
RA[4] : 26 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[3] : 27 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[4] : 26 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[3] : 27 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nEN80 : 28 : input : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
VCCIO1 : 31 : power : : 3.3V : 1 :
|
||||
GNDIO : 32 : gnd : : : :
|
||||
nWE80 : 33 : input : 3.3-V LVCMOS : : 1 : Y
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,6 +1,6 @@
|
|||
Timing Analyzer report for RAM2E
|
||||
Thu Sep 21 05:34:45 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Thu Dec 28 23:09:50 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
|
@ -17,11 +17,11 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
|||
9. Recovery Summary
|
||||
10. Removal Summary
|
||||
11. Minimum Pulse Width Summary
|
||||
12. Setup: 'DRCLK'
|
||||
13. Setup: 'ARCLK'
|
||||
12. Setup: 'ram2e_ufm|DRCLK|regout'
|
||||
13. Setup: 'ram2e_ufm|ARCLK|regout'
|
||||
14. Setup: 'C14M'
|
||||
15. Hold: 'ARCLK'
|
||||
16. Hold: 'DRCLK'
|
||||
15. Hold: 'ram2e_ufm|DRCLK|regout'
|
||||
16. Hold: 'ram2e_ufm|ARCLK|regout'
|
||||
17. Hold: 'C14M'
|
||||
18. Setup Transfers
|
||||
19. Hold Transfers
|
||||
|
|
@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------+
|
||||
; Timing Analyzer Summary ;
|
||||
+-----------------------+-----------------------------------------------------+
|
||||
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Timing Analyzer ; Legacy Timing Analyzer ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Device Family ; MAX II ;
|
||||
; Device Name ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Delay Model ; Slow Model ;
|
||||
; Rise/Fall Delays ; Unavailable ;
|
||||
+-----------------------+-----------------------------------------------------+
|
||||
+---------------------------------------------------------------------------------------------+
|
||||
; Timing Analyzer Summary ;
|
||||
+-----------------------+---------------------------------------------------------------------+
|
||||
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Timing Analyzer ; Legacy Timing Analyzer ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Device Family ; MAX II ;
|
||||
; Device Name ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Delay Model ; Slow Model ;
|
||||
; Rise/Fall Delays ; Unavailable ;
|
||||
+-----------------------+---------------------------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
|
|
@ -80,11 +80,10 @@ https://fpgasoftware.intel.com/eula.
|
|||
; Maximum allowed ; 4 ;
|
||||
; ; ;
|
||||
; Average used ; 1.00 ;
|
||||
; Maximum used ; 2 ;
|
||||
; Maximum used ; 1 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 0.2% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
|
|
@ -93,54 +92,54 @@ https://fpgasoftware.intel.com/eula.
|
|||
+------------------+--------+--------------------------+
|
||||
; SDC File Path ; Status ; Read at ;
|
||||
+------------------+--------+--------------------------+
|
||||
; ../RAM2E.sdc ; OK ; Thu Sep 21 05:34:44 2023 ;
|
||||
; ../RAM2E-MAX.sdc ; OK ; Thu Sep 21 05:34:44 2023 ;
|
||||
; ../RAM2E.sdc ; OK ; Thu Dec 28 23:09:50 2023 ;
|
||||
; ../RAM2E-MAX.sdc ; OK ; Thu Dec 28 23:09:50 2023 ;
|
||||
+------------------+--------+--------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Clocks ;
|
||||
+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
|
||||
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
|
||||
+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
|
||||
; ARCLK ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { ARCLK } ;
|
||||
; C14M ; Base ; 69.841 ; 14.32 MHz ; 0.000 ; 34.920 ; ; ; ; ; ; ; ; ; ; ; { C14M } ;
|
||||
; DRCLK ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { DRCLK } ;
|
||||
+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Clocks ;
|
||||
+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
|
||||
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
|
||||
+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
|
||||
; C14M ; Base ; 69.841 ; 14.32 MHz ; 0.000 ; 34.920 ; ; ; ; ; ; ; ; ; ; ; { C14M } ;
|
||||
; ram2e_ufm|ARCLK|regout ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { ram2e_ufm|ARCLK|regout } ;
|
||||
; ram2e_ufm|DRCLK|regout ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { ram2e_ufm|DRCLK|regout } ;
|
||||
+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------+
|
||||
; Fmax Summary ;
|
||||
+-----------+-----------------+------------+------+
|
||||
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
||||
+-----------+-----------------+------------+------+
|
||||
; 10.0 MHz ; 10.0 MHz ; ARCLK ; ;
|
||||
; 10.0 MHz ; 10.0 MHz ; DRCLK ; ;
|
||||
; 61.13 MHz ; 61.13 MHz ; C14M ; ;
|
||||
+-----------+-----------------+------------+------+
|
||||
+-------------------------------------------------------------+
|
||||
; Fmax Summary ;
|
||||
+-----------+-----------------+------------------------+------+
|
||||
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
||||
+-----------+-----------------+------------------------+------+
|
||||
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|ARCLK|regout ; ;
|
||||
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|DRCLK|regout ; ;
|
||||
; 70.81 MHz ; 70.81 MHz ; C14M ; ;
|
||||
+-----------+-----------------+------------------------+------+
|
||||
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
||||
|
||||
|
||||
+---------------------------------+
|
||||
; Setup Summary ;
|
||||
+-------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+---------+---------------+
|
||||
; DRCLK ; -23.265 ; -23.265 ;
|
||||
; ARCLK ; -23.125 ; -23.125 ;
|
||||
; C14M ; -8.026 ; -92.836 ;
|
||||
+-------+---------+---------------+
|
||||
+--------------------------------------------------+
|
||||
; Setup Summary ;
|
||||
+------------------------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+------------------------+---------+---------------+
|
||||
; ram2e_ufm|DRCLK|regout ; -23.738 ; -23.738 ;
|
||||
; ram2e_ufm|ARCLK|regout ; -23.720 ; -23.720 ;
|
||||
; C14M ; -9.644 ; -106.641 ;
|
||||
+------------------------+---------+---------------+
|
||||
|
||||
|
||||
+---------------------------------+
|
||||
; Hold Summary ;
|
||||
+-------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+---------+---------------+
|
||||
; ARCLK ; -16.874 ; -16.874 ;
|
||||
; DRCLK ; -16.746 ; -16.746 ;
|
||||
; C14M ; 1.415 ; 0.000 ;
|
||||
+-------+---------+---------------+
|
||||
+--------------------------------------------------+
|
||||
; Hold Summary ;
|
||||
+------------------------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+------------------------+---------+---------------+
|
||||
; ram2e_ufm|DRCLK|regout ; -16.287 ; -16.287 ;
|
||||
; ram2e_ufm|ARCLK|regout ; -16.279 ; -16.279 ;
|
||||
; C14M ; 1.421 ; 0.000 ;
|
||||
+------------------------+---------+---------------+
|
||||
|
||||
|
||||
--------------------
|
||||
|
|
@ -155,302 +154,302 @@ No paths to report.
|
|||
No paths to report.
|
||||
|
||||
|
||||
+--------------------------------+
|
||||
; Minimum Pulse Width Summary ;
|
||||
+-------+--------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+--------+---------------+
|
||||
; C14M ; 34.654 ; 0.000 ;
|
||||
; ARCLK ; 70.000 ; 0.000 ;
|
||||
; DRCLK ; 70.000 ; 0.000 ;
|
||||
+-------+--------+---------------+
|
||||
+-------------------------------------------------+
|
||||
; Minimum Pulse Width Summary ;
|
||||
+------------------------+--------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+------------------------+--------+---------------+
|
||||
; C14M ; 34.654 ; 0.000 ;
|
||||
; ram2e_ufm|ARCLK|regout ; 70.000 ; 0.000 ;
|
||||
; ram2e_ufm|DRCLK|regout ; 70.000 ; 0.000 ;
|
||||
+------------------------+--------+---------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'DRCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -23.265 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.725 ; 1.541 ;
|
||||
; -23.253 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.725 ; 1.529 ;
|
||||
; 100.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'ram2e_ufm|DRCLK|regout' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; -23.738 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -1.671 ; 2.068 ;
|
||||
; -23.712 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -1.671 ; 2.042 ;
|
||||
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'ARCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -23.125 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.001 ; -1.597 ; 1.529 ;
|
||||
; 100.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'ram2e_ufm|ARCLK|regout' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; -23.720 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -1.663 ; 2.058 ;
|
||||
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'C14M' ;
|
||||
+--------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+--------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[4] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[5] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[7] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[0] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[1] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[2] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[3] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[6] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -7.612 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; LEDEN ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.005 ;
|
||||
; -7.370 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFMInitDone ; DRCLK ; C14M ; 0.001 ; 1.725 ; 8.763 ;
|
||||
; -7.319 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFMReqErase ; DRCLK ; C14M ; 0.001 ; 1.725 ; 8.712 ;
|
||||
; -6.327 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFMD[8] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 7.720 ;
|
||||
; 27.280 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.307 ;
|
||||
; 27.280 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.307 ;
|
||||
; 27.332 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.255 ;
|
||||
; 27.332 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.255 ;
|
||||
; 27.332 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.255 ;
|
||||
; 27.583 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ;
|
||||
; 27.583 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ;
|
||||
; 27.583 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ;
|
||||
; 27.583 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ;
|
||||
; 27.583 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ;
|
||||
; 27.583 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ;
|
||||
; 27.585 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.002 ;
|
||||
; 27.590 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.997 ;
|
||||
; 27.761 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ;
|
||||
; 27.761 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ;
|
||||
; 27.761 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ;
|
||||
; 27.761 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ;
|
||||
; 27.761 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ;
|
||||
; 27.761 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ;
|
||||
; 27.763 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.824 ;
|
||||
; 27.768 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.819 ;
|
||||
; 27.779 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ;
|
||||
; 27.779 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ;
|
||||
; 27.779 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ;
|
||||
; 27.779 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ;
|
||||
; 27.779 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ;
|
||||
; 27.779 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ;
|
||||
; 27.781 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.806 ;
|
||||
; 27.786 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.801 ;
|
||||
; 27.878 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.709 ;
|
||||
; 27.878 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.709 ;
|
||||
; 27.930 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.657 ;
|
||||
; 27.930 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.657 ;
|
||||
; 27.930 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.657 ;
|
||||
; 28.203 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ;
|
||||
; 28.203 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ;
|
||||
; 28.203 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ;
|
||||
; 28.203 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ;
|
||||
; 28.203 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ;
|
||||
; 28.203 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ;
|
||||
; 28.205 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.382 ;
|
||||
; 28.210 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.377 ;
|
||||
; 28.368 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.219 ;
|
||||
; 28.368 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.219 ;
|
||||
; 28.368 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.219 ;
|
||||
; 28.431 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.156 ;
|
||||
; 28.431 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.156 ;
|
||||
; 28.483 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.104 ;
|
||||
; 28.483 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.104 ;
|
||||
; 28.483 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.104 ;
|
||||
; 28.546 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.041 ;
|
||||
; 28.546 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.041 ;
|
||||
; 28.598 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.989 ;
|
||||
; 28.598 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.989 ;
|
||||
; 28.598 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.989 ;
|
||||
; 28.966 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.621 ;
|
||||
; 28.966 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.621 ;
|
||||
; 28.966 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.621 ;
|
||||
; 29.519 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.068 ;
|
||||
; 29.519 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.068 ;
|
||||
; 29.519 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.068 ;
|
||||
; 29.634 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.953 ;
|
||||
; 29.634 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.953 ;
|
||||
; 29.634 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.953 ;
|
||||
; 53.482 ; FS[15] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 16.026 ;
|
||||
; 53.855 ; FS[14] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 15.653 ;
|
||||
; 54.606 ; FS[15] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.902 ;
|
||||
; 54.773 ; FS[15] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.735 ;
|
||||
; 54.979 ; FS[14] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.529 ;
|
||||
; 55.110 ; FS[15] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.398 ;
|
||||
; 55.146 ; FS[14] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.362 ;
|
||||
; 55.483 ; FS[14] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.025 ;
|
||||
; 55.674 ; FS[11] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 13.834 ;
|
||||
; 55.804 ; FS[10] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 13.704 ;
|
||||
; 56.000 ; FS[8] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 13.508 ;
|
||||
; 56.341 ; FS[9] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 13.167 ;
|
||||
; 56.591 ; FS[12] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.917 ;
|
||||
; 56.798 ; FS[11] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.710 ;
|
||||
; 56.928 ; FS[10] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.580 ;
|
||||
; 56.931 ; FS[13] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.577 ;
|
||||
; 56.965 ; FS[11] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.543 ;
|
||||
; 56.994 ; S[2] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ;
|
||||
; 56.994 ; S[2] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ;
|
||||
; 56.994 ; S[2] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ;
|
||||
; 56.994 ; S[2] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ;
|
||||
; 56.994 ; S[2] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ;
|
||||
; 56.994 ; S[2] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ;
|
||||
; 56.994 ; S[2] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ;
|
||||
+--------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'C14M' ;
|
||||
+--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
|
||||
; -9.644 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.983 ;
|
||||
; -9.644 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.983 ;
|
||||
; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.496 ;
|
||||
; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.496 ;
|
||||
; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.496 ;
|
||||
; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.496 ;
|
||||
; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.496 ;
|
||||
; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.496 ;
|
||||
; -8.710 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.049 ;
|
||||
; -8.708 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.047 ;
|
||||
; -8.612 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 9.951 ;
|
||||
; -6.381 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 7.720 ;
|
||||
; 31.279 ; RA[8] ; RAout[8]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.308 ;
|
||||
; 31.326 ; RA[11] ; RAout[11]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.261 ;
|
||||
; 31.442 ; RA[9] ; RAout[9]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.145 ;
|
||||
; 31.464 ; RA[0] ; RAout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.123 ;
|
||||
; 31.631 ; RA[10] ; RAout[10]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.956 ;
|
||||
; 31.767 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.820 ;
|
||||
; 31.783 ; RA[5] ; RAout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.804 ;
|
||||
; 31.887 ; RA[3] ; RAout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.700 ;
|
||||
; 32.525 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.062 ;
|
||||
; 32.582 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.005 ;
|
||||
; 32.583 ; RA[1] ; RAout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.004 ;
|
||||
; 32.593 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 1.994 ;
|
||||
; 32.721 ; RA[4] ; RAout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 1.866 ;
|
||||
; 32.969 ; RA[2] ; RAout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 1.618 ;
|
||||
; 32.978 ; RA[7] ; RAout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 1.609 ;
|
||||
; 32.989 ; RA[6] ; RAout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 1.598 ;
|
||||
; 55.719 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.789 ;
|
||||
; 55.719 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.789 ;
|
||||
; 56.206 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.302 ;
|
||||
; 56.206 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.302 ;
|
||||
; 56.206 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.302 ;
|
||||
; 56.206 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.302 ;
|
||||
; 56.206 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.302 ;
|
||||
; 56.206 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.302 ;
|
||||
; 56.603 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 12.905 ;
|
||||
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
|
||||
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
|
||||
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
|
||||
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
|
||||
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
|
||||
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
|
||||
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
|
||||
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
|
||||
; 56.915 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 12.593 ;
|
||||
; 57.079 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.429 ;
|
||||
; 57.079 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.429 ;
|
||||
; 57.323 ; FS[4] ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 69.841 ; 0.000 ; 12.185 ;
|
||||
; 57.476 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.032 ;
|
||||
; 57.476 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.032 ;
|
||||
; 57.566 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.942 ;
|
||||
; 57.566 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.942 ;
|
||||
; 57.566 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.942 ;
|
||||
; 57.566 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.942 ;
|
||||
; 57.566 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.942 ;
|
||||
; 57.566 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.942 ;
|
||||
; 57.651 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 11.857 ;
|
||||
; 57.772 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.736 ;
|
||||
; 57.772 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.736 ;
|
||||
; 57.960 ; FS[4] ; nCAS ; C14M ; C14M ; 69.841 ; 0.000 ; 11.548 ;
|
||||
; 57.963 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
|
||||
; 57.963 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
|
||||
; 57.963 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
|
||||
; 57.963 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
|
||||
; 57.963 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
|
||||
; 57.963 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
|
||||
; 57.963 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
|
||||
; 57.963 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
|
||||
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
|
||||
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
|
||||
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
|
||||
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
|
||||
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
|
||||
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
|
||||
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
|
||||
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
|
||||
; 58.030 ; FS[3] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.478 ;
|
||||
; 58.030 ; FS[3] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.478 ;
|
||||
; 58.039 ; CS[1] ; CS[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.469 ;
|
||||
; 58.040 ; CS[1] ; CS[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.468 ;
|
||||
; 58.040 ; CS[1] ; CS[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.468 ;
|
||||
; 58.068 ; FS[4] ; nRWE ; C14M ; C14M ; 69.841 ; 0.000 ; 11.440 ;
|
||||
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
|
||||
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
|
||||
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
|
||||
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
|
||||
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
|
||||
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
|
||||
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
|
||||
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
|
||||
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
|
||||
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
|
||||
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
|
||||
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
|
||||
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
|
||||
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
|
||||
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
|
||||
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
|
||||
; 58.230 ; S[0] ; S[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.278 ;
|
||||
+--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'ARCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -16.874 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.000 ; -1.597 ; 1.529 ;
|
||||
; 60.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'ram2e_ufm|DRCLK|regout' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; -16.287 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -1.671 ; 2.042 ;
|
||||
; -16.261 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -1.671 ; 2.068 ;
|
||||
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'DRCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -16.746 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.725 ; 1.529 ;
|
||||
; -16.734 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.725 ; 1.541 ;
|
||||
; 60.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'ram2e_ufm|ARCLK|regout' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; -16.279 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -1.663 ; 2.058 ;
|
||||
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'C14M' ;
|
||||
+-------+-------------------+-------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+-------------------+-------------+--------------+-------------+--------------+------------+------------+
|
||||
; 1.415 ; UFMD[12] ; UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.636 ;
|
||||
; 1.421 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.642 ;
|
||||
; 1.639 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 1.860 ;
|
||||
; 1.639 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.860 ;
|
||||
; 1.660 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.881 ;
|
||||
; 1.669 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.890 ;
|
||||
; 1.701 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.922 ;
|
||||
; 1.701 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.922 ;
|
||||
; 1.730 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.951 ;
|
||||
; 1.732 ; S[0] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.953 ;
|
||||
; 1.822 ; UFMD[8] ; UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.043 ;
|
||||
; 1.844 ; UFMD[9] ; UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.065 ;
|
||||
; 1.953 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 2.174 ;
|
||||
; 1.981 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.202 ;
|
||||
; 1.991 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.212 ;
|
||||
; 2.107 ; LEDEN ; LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
|
||||
; 2.107 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
|
||||
; 2.107 ; CmdBitbangMAX ; DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
|
||||
; 2.118 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 2.339 ;
|
||||
; 2.126 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.347 ;
|
||||
; 2.126 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.347 ;
|
||||
; 2.134 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.355 ;
|
||||
; 2.138 ; CmdPrgmMAX ; CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.359 ;
|
||||
; 2.143 ; CmdPrgmMAX ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.364 ;
|
||||
; 2.144 ; UFMErase ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.365 ;
|
||||
; 2.146 ; UFMProgram ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.367 ;
|
||||
; 2.152 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.373 ;
|
||||
; 2.152 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.373 ;
|
||||
; 2.162 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.383 ;
|
||||
; 2.165 ; CmdEraseMAX ; CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.386 ;
|
||||
; 2.199 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.420 ;
|
||||
; 2.207 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.428 ;
|
||||
; 2.218 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.439 ;
|
||||
; 2.233 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.454 ;
|
||||
; 2.247 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.468 ;
|
||||
; 2.249 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.470 ;
|
||||
; 2.260 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.481 ;
|
||||
; 2.262 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.483 ;
|
||||
; 2.268 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.489 ;
|
||||
; 2.273 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.494 ;
|
||||
; 2.290 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.511 ;
|
||||
; 2.291 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.512 ;
|
||||
; 2.295 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.516 ;
|
||||
; 2.308 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.529 ;
|
||||
; 2.309 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.530 ;
|
||||
; 2.382 ; UFMReqErase ; UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.603 ;
|
||||
; 2.390 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.611 ;
|
||||
; 2.448 ; UFMD[14] ; UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.669 ;
|
||||
; 2.455 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.676 ;
|
||||
; 2.461 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.682 ;
|
||||
; 2.622 ; RTPBusyReg ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.843 ;
|
||||
; 2.624 ; UFMBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.845 ;
|
||||
; 2.626 ; RWBank[3] ; RA[11]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.847 ;
|
||||
; 2.645 ; UFMD[13] ; UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.866 ;
|
||||
; 2.655 ; PHI1reg ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.876 ;
|
||||
; 2.720 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 2.941 ;
|
||||
; 2.732 ; UFMD[15] ; RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.953 ;
|
||||
; 2.766 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.987 ;
|
||||
; 2.823 ; RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.044 ;
|
||||
; 2.844 ; UFMD[9] ; RWMask[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.065 ;
|
||||
; 2.851 ; RWBank[5] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.072 ;
|
||||
; 2.911 ; S[3] ; nCS~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.132 ;
|
||||
; 2.913 ; S[3] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.134 ;
|
||||
; 2.952 ; RTPBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.173 ;
|
||||
; 2.958 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.179 ;
|
||||
; 2.966 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.187 ;
|
||||
; 2.984 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.205 ;
|
||||
; 2.984 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.205 ;
|
||||
; 2.992 ; RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.213 ;
|
||||
; 3.041 ; RWBank[0] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.262 ;
|
||||
; 3.063 ; RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.284 ;
|
||||
; 3.069 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.290 ;
|
||||
; 3.077 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.298 ;
|
||||
; 3.095 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.316 ;
|
||||
; 3.095 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.316 ;
|
||||
; 3.096 ; RWSel ; DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 3.317 ;
|
||||
; 3.098 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.319 ;
|
||||
; 3.118 ; S[0] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 3.339 ;
|
||||
; 3.134 ; RWBank[1] ; RA[9]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.355 ;
|
||||
; 3.163 ; UFMD[11] ; RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.384 ;
|
||||
; 3.168 ; DRCLKPulse ; DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 3.389 ;
|
||||
; 3.170 ; RWBank[7] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.391 ;
|
||||
; 3.173 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.394 ;
|
||||
; 3.187 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.408 ;
|
||||
; 3.188 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.409 ;
|
||||
; 3.189 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.410 ;
|
||||
; 3.189 ; RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.410 ;
|
||||
; 3.200 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.421 ;
|
||||
; 3.203 ; RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.424 ;
|
||||
; 3.206 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.427 ;
|
||||
; 3.208 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.429 ;
|
||||
; 3.213 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.434 ;
|
||||
; 3.218 ; CmdSetRWBankFFLED ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.439 ;
|
||||
; 3.222 ; CmdSetRWBankFFLED ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.443 ;
|
||||
; 3.230 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.451 ;
|
||||
; 3.230 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.451 ;
|
||||
; 3.236 ; S[0] ; nCS~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.457 ;
|
||||
; 3.241 ; UFMD[12] ; RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.462 ;
|
||||
; 3.274 ; UFMD[14] ; RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.495 ;
|
||||
; 3.299 ; FS[8] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.520 ;
|
||||
+-------+-------------------+-------------+--------------+-------------+--------------+------------+------------+
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'C14M' ;
|
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; 1.421 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.642 ;
|
||||
; 1.421 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.642 ;
|
||||
; 1.445 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.666 ;
|
||||
; 1.451 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.672 ;
|
||||
; 1.461 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.682 ;
|
||||
; 1.639 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 1.860 ;
|
||||
; 1.684 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.905 ;
|
||||
; 1.687 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.908 ;
|
||||
; 1.688 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.909 ;
|
||||
; 1.696 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.917 ;
|
||||
; 1.702 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.923 ;
|
||||
; 1.706 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.927 ;
|
||||
; 1.716 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 1.937 ;
|
||||
; 1.818 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.039 ;
|
||||
; 1.905 ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.126 ;
|
||||
; 1.928 ; RWBank[1] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.149 ;
|
||||
; 1.935 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.156 ;
|
||||
; 1.954 ; RC[0] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.175 ;
|
||||
; 1.961 ; RC[0] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.182 ;
|
||||
; 1.968 ; RC[0] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.189 ;
|
||||
; 1.971 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.192 ;
|
||||
; 1.972 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.193 ;
|
||||
; 1.984 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.205 ;
|
||||
; 1.993 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.214 ;
|
||||
; 1.995 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.216 ;
|
||||
; 2.107 ; RAM2E_UFM:ram2e_ufm|LEDEN ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
|
||||
; 2.109 ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.330 ;
|
||||
; 2.116 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.337 ;
|
||||
; 2.117 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.338 ;
|
||||
; 2.117 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.338 ;
|
||||
; 2.125 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.346 ;
|
||||
; 2.126 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 2.347 ;
|
||||
; 2.126 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.347 ;
|
||||
; 2.128 ; RWBank[7] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.349 ;
|
||||
; 2.133 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.354 ;
|
||||
; 2.136 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 2.357 ;
|
||||
; 2.143 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.364 ;
|
||||
; 2.150 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 2.371 ;
|
||||
; 2.163 ; RC[1] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.384 ;
|
||||
; 2.181 ; RC[1] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.402 ;
|
||||
; 2.182 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.403 ;
|
||||
; 2.184 ; RC[1] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.405 ;
|
||||
; 2.212 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.433 ;
|
||||
; 2.230 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.451 ;
|
||||
; 2.232 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.453 ;
|
||||
; 2.239 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ;
|
||||
; 2.239 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ;
|
||||
; 2.241 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.462 ;
|
||||
; 2.249 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.470 ;
|
||||
; 2.250 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.471 ;
|
||||
; 2.259 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.480 ;
|
||||
; 2.261 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.482 ;
|
||||
; 2.272 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.493 ;
|
||||
; 2.277 ; RC[2] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.498 ;
|
||||
; 2.279 ; RC[2] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.500 ;
|
||||
; 2.282 ; RC[2] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.503 ;
|
||||
; 2.302 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.523 ;
|
||||
; 2.305 ; S[3] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.526 ;
|
||||
; 2.310 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.531 ;
|
||||
; 2.313 ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.534 ;
|
||||
; 2.316 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.537 ;
|
||||
; 2.319 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.540 ;
|
||||
; 2.323 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 2.544 ;
|
||||
; 2.332 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.553 ;
|
||||
; 2.347 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.568 ;
|
||||
; 2.372 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.593 ;
|
||||
; 2.446 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.667 ;
|
||||
; 2.455 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.676 ;
|
||||
; 2.457 ; S[3] ; CKE ; C14M ; C14M ; 0.000 ; 0.000 ; 2.678 ;
|
||||
; 2.459 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.680 ;
|
||||
; 2.531 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.752 ;
|
||||
; 2.542 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.763 ;
|
||||
; 2.544 ; S[2] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.765 ;
|
||||
; 2.563 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.784 ;
|
||||
; 2.606 ; RAM2E_UFM:ram2e_ufm|UFMErase ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.827 ;
|
||||
; 2.610 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.831 ;
|
||||
; 2.653 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.874 ;
|
||||
; 2.655 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.876 ;
|
||||
; 2.656 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.877 ;
|
||||
; 2.657 ; S[0] ; VOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.878 ;
|
||||
; 2.660 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.881 ;
|
||||
; 2.678 ; S[1] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.899 ;
|
||||
; 2.719 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.940 ;
|
||||
; 2.750 ; S[0] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.971 ;
|
||||
; 2.764 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.985 ;
|
||||
; 2.773 ; S[1] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.994 ;
|
||||
; 2.785 ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.006 ;
|
||||
; 2.794 ; S[0] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.015 ;
|
||||
; 2.815 ; FS[4] ; RA[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.036 ;
|
||||
; 2.830 ; S[3] ; RA[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.051 ;
|
||||
; 2.850 ; FS[1] ; RA[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.071 ;
|
||||
; 2.851 ; RWBank[5] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.072 ;
|
||||
; 2.902 ; S[2] ; nRWE ; C14M ; C14M ; 0.000 ; 0.000 ; 3.123 ;
|
||||
; 2.911 ; S[2] ; nCAS ; C14M ; C14M ; 0.000 ; 0.000 ; 3.132 ;
|
||||
; 2.929 ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.150 ;
|
||||
; 2.933 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.154 ;
|
||||
; 2.935 ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.156 ;
|
||||
; 2.948 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.169 ;
|
||||
; 2.949 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.170 ;
|
||||
; 2.957 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.178 ;
|
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; Setup Transfers ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; C14M ; 1607 ; 0 ; 64 ; 0 ;
|
||||
; DRCLK ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; DRCLK ; 2 ; 0 ; 0 ; 0 ;
|
||||
; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
+---------------------------------------------------------------------------------------------+
|
||||
; Setup Transfers ;
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
; C14M ; C14M ; 1625 ; 0 ; 16 ; 0 ;
|
||||
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ram2e_ufm|DRCLK|regout ; 2 ; 0 ; 0 ; 0 ;
|
||||
; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; Hold Transfers ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; C14M ; 1607 ; 0 ; 64 ; 0 ;
|
||||
; DRCLK ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; DRCLK ; 2 ; 0 ; 0 ; 0 ;
|
||||
; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
+---------------------------------------------------------------------------------------------+
|
||||
; Hold Transfers ;
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
; C14M ; C14M ; 1625 ; 0 ; 16 ; 0 ;
|
||||
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ram2e_ufm|DRCLK|regout ; 2 ; 0 ; 0 ; 0 ;
|
||||
; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||||
|
||||
|
||||
|
|
@ -473,22 +472,22 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
+---------------------------------+-------+------+
|
||||
; Illegal Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Input Ports ; 29 ; 29 ;
|
||||
; Unconstrained Input Port Paths ; 169 ; 169 ;
|
||||
; Unconstrained Output Ports ; 48 ; 48 ;
|
||||
; Unconstrained Output Port Paths ; 67 ; 67 ;
|
||||
; Unconstrained Input Ports ; 28 ; 28 ;
|
||||
; Unconstrained Input Port Paths ; 176 ; 176 ;
|
||||
; Unconstrained Output Ports ; 47 ; 47 ;
|
||||
; Unconstrained Output Port Paths ; 76 ; 76 ;
|
||||
+---------------------------------+-------+------+
|
||||
|
||||
|
||||
+-------------------------------------+
|
||||
; Clock Status Summary ;
|
||||
+--------+-------+------+-------------+
|
||||
; Target ; Clock ; Type ; Status ;
|
||||
+--------+-------+------+-------------+
|
||||
; ARCLK ; ARCLK ; Base ; Constrained ;
|
||||
; C14M ; C14M ; Base ; Constrained ;
|
||||
; DRCLK ; DRCLK ; Base ; Constrained ;
|
||||
+--------+-------+------+-------------+
|
||||
+----------------------------------------------------------------------+
|
||||
; Clock Status Summary ;
|
||||
+------------------------+------------------------+------+-------------+
|
||||
; Target ; Clock ; Type ; Status ;
|
||||
+------------------------+------------------------+------+-------------+
|
||||
; C14M ; C14M ; Base ; Constrained ;
|
||||
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; Base ; Constrained ;
|
||||
; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; Base ; Constrained ;
|
||||
+------------------------+------------------------+------+-------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------+
|
||||
|
|
@ -524,7 +523,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
; nC07X ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nEN80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nWE80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
|
@ -535,7 +533,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
+-------------+---------------------------------------------------------------------------------------+
|
||||
; BA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; BA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; CKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; CKEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
|
|
@ -547,18 +545,18 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
|
|
@ -575,11 +573,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRWEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nVOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
|
||||
|
|
@ -617,7 +614,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
; nC07X ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nEN80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nWE80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
|
@ -628,7 +624,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
+-------------+---------------------------------------------------------------------------------------+
|
||||
; BA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; BA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; CKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; CKEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
|
|
@ -640,18 +636,18 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
|
|
@ -668,11 +664,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRWEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nVOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
|
||||
|
|
@ -682,8 +677,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
+--------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Timing Analyzer
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:34:43 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Thu Dec 28 23:09:48 2023
|
||||
Info: Command: quartus_sta RAM2E-MAXII -c RAM2E
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
|
|
@ -695,37 +690,37 @@ Info (332104): Reading SDC File: '../RAM2E.sdc'
|
|||
Info (332104): Reading SDC File: '../RAM2E-MAX.sdc'
|
||||
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
||||
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ARCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: DRCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Critical Warning (332148): Timing requirements not met
|
||||
Info (332146): Worst-case setup slack is -23.265
|
||||
Info (332146): Worst-case setup slack is -23.738
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= =================== =====================
|
||||
Info (332119): -23.265 -23.265 DRCLK
|
||||
Info (332119): -23.125 -23.125 ARCLK
|
||||
Info (332119): -8.026 -92.836 C14M
|
||||
Info (332146): Worst-case hold slack is -16.874
|
||||
Info (332119): -23.738 -23.738 ram2e_ufm|DRCLK|regout
|
||||
Info (332119): -23.720 -23.720 ram2e_ufm|ARCLK|regout
|
||||
Info (332119): -9.644 -106.641 C14M
|
||||
Info (332146): Worst-case hold slack is -16.287
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= =================== =====================
|
||||
Info (332119): -16.874 -16.874 ARCLK
|
||||
Info (332119): -16.746 -16.746 DRCLK
|
||||
Info (332119): 1.415 0.000 C14M
|
||||
Info (332119): -16.287 -16.287 ram2e_ufm|DRCLK|regout
|
||||
Info (332119): -16.279 -16.279 ram2e_ufm|ARCLK|regout
|
||||
Info (332119): 1.421 0.000 C14M
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Info (332146): Worst-case minimum pulse width slack is 34.654
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= =================== =====================
|
||||
Info (332119): 34.654 0.000 C14M
|
||||
Info (332119): 70.000 0.000 ARCLK
|
||||
Info (332119): 70.000 0.000 DRCLK
|
||||
Info (332119): 70.000 0.000 ram2e_ufm|ARCLK|regout
|
||||
Info (332119): 70.000 0.000 ram2e_ufm|DRCLK|regout
|
||||
Info (332001): The selected device family is not supported by the report_metastability command.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ARCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: DRCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
|
||||
Info: Peak virtual memory: 13089 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:45 2023
|
||||
Info: Peak virtual memory: 13064 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:50 2023
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
|
||||
|
|
|
|||
|
|
@ -2,39 +2,39 @@
|
|||
Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Setup 'DRCLK'
|
||||
Slack : -23.265
|
||||
TNS : -23.265
|
||||
Type : Setup 'ram2e_ufm|DRCLK|regout'
|
||||
Slack : -23.738
|
||||
TNS : -23.738
|
||||
|
||||
Type : Setup 'ARCLK'
|
||||
Slack : -23.125
|
||||
TNS : -23.125
|
||||
Type : Setup 'ram2e_ufm|ARCLK|regout'
|
||||
Slack : -23.720
|
||||
TNS : -23.720
|
||||
|
||||
Type : Setup 'C14M'
|
||||
Slack : -8.026
|
||||
TNS : -92.836
|
||||
Slack : -9.644
|
||||
TNS : -106.641
|
||||
|
||||
Type : Hold 'ARCLK'
|
||||
Slack : -16.874
|
||||
TNS : -16.874
|
||||
Type : Hold 'ram2e_ufm|DRCLK|regout'
|
||||
Slack : -16.287
|
||||
TNS : -16.287
|
||||
|
||||
Type : Hold 'DRCLK'
|
||||
Slack : -16.746
|
||||
TNS : -16.746
|
||||
Type : Hold 'ram2e_ufm|ARCLK|regout'
|
||||
Slack : -16.279
|
||||
TNS : -16.279
|
||||
|
||||
Type : Hold 'C14M'
|
||||
Slack : 1.415
|
||||
Slack : 1.421
|
||||
TNS : 0.000
|
||||
|
||||
Type : Minimum Pulse Width 'C14M'
|
||||
Slack : 34.654
|
||||
TNS : 0.000
|
||||
|
||||
Type : Minimum Pulse Width 'ARCLK'
|
||||
Type : Minimum Pulse Width 'ram2e_ufm|ARCLK|regout'
|
||||
Slack : 70.000
|
||||
TNS : 0.000
|
||||
|
||||
Type : Minimum Pulse Width 'DRCLK'
|
||||
Type : Minimum Pulse Width 'ram2e_ufm|DRCLK|regout'
|
||||
Slack : 70.000
|
||||
TNS : 0.000
|
||||
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ set_global_assignment -name DEVICE 5M240ZT100C5
|
|||
set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:27:32 AUGUST 20, 2023"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
|
@ -74,7 +74,6 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nEN80
|
|||
|
||||
set_location_assignment PIN_33 -to nWE80
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE80
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE80
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE80
|
||||
|
||||
set_location_assignment PIN_52 -to nC07X
|
||||
|
|
@ -123,7 +122,6 @@ set_location_assignment PIN_85 -to Dout[7]
|
|||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Dout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to Dout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Dout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout
|
||||
|
||||
set_location_assignment PIN_50 -to nVOE
|
||||
|
|
@ -146,40 +144,39 @@ set_instance_assignment -name SLOW_SLEW_RATE ON -to Vout
|
|||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Vout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Vout
|
||||
|
||||
set_location_assignment PIN_4 -to CKE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to CKE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKE
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKE
|
||||
set_location_assignment PIN_4 -to CKEout
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKEout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKEout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to CKEout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKEout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKEout
|
||||
|
||||
set_location_assignment PIN_8 -to nCS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCS
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCS
|
||||
set_location_assignment PIN_8 -to nCSout
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCSout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCSout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCSout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCSout
|
||||
|
||||
set_location_assignment PIN_2 -to nRWE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWE
|
||||
set_location_assignment PIN_2 -to nRWEout
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWEout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWEout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWEout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWEout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWEout
|
||||
|
||||
set_location_assignment PIN_5 -to nRAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRAS
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS
|
||||
set_location_assignment PIN_5 -to nRASout
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRASout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRASout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRASout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRASout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRASout
|
||||
|
||||
set_location_assignment PIN_3 -to nCAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCAS
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS
|
||||
set_location_assignment PIN_3 -to nCASout
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCASout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCASout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCASout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCASout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCASout
|
||||
|
||||
set_location_assignment PIN_6 -to BA[0]
|
||||
set_location_assignment PIN_14 -to BA[1]
|
||||
|
|
@ -189,23 +186,23 @@ set_instance_assignment -name SLOW_SLEW_RATE ON -to BA
|
|||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BA
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to BA
|
||||
|
||||
set_location_assignment PIN_18 -to RA[0]
|
||||
set_location_assignment PIN_20 -to RA[1]
|
||||
set_location_assignment PIN_30 -to RA[2]
|
||||
set_location_assignment PIN_27 -to RA[3]
|
||||
set_location_assignment PIN_26 -to RA[4]
|
||||
set_location_assignment PIN_29 -to RA[5]
|
||||
set_location_assignment PIN_21 -to RA[6]
|
||||
set_location_assignment PIN_19 -to RA[7]
|
||||
set_location_assignment PIN_17 -to RA[8]
|
||||
set_location_assignment PIN_15 -to RA[9]
|
||||
set_location_assignment PIN_16 -to RA[10]
|
||||
set_location_assignment PIN_7 -to RA[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RA
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to RA
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RA
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA
|
||||
set_location_assignment PIN_18 -to RAout[0]
|
||||
set_location_assignment PIN_20 -to RAout[1]
|
||||
set_location_assignment PIN_30 -to RAout[2]
|
||||
set_location_assignment PIN_27 -to RAout[3]
|
||||
set_location_assignment PIN_26 -to RAout[4]
|
||||
set_location_assignment PIN_29 -to RAout[5]
|
||||
set_location_assignment PIN_21 -to RAout[6]
|
||||
set_location_assignment PIN_19 -to RAout[7]
|
||||
set_location_assignment PIN_17 -to RAout[8]
|
||||
set_location_assignment PIN_15 -to RAout[9]
|
||||
set_location_assignment PIN_16 -to RAout[10]
|
||||
set_location_assignment PIN_7 -to RAout[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RAout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RAout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RAout
|
||||
|
||||
set_location_assignment PIN_100 -to DQMH
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQMH
|
||||
|
|
@ -237,11 +234,12 @@ set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
|
|||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
|
||||
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
|
||||
set_global_assignment -name VERILOG_FILE "../RAM2E-MAX.v"
|
||||
set_location_assignment PIN_88 -to LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
|
||||
set_global_assignment -name VERILOG_FILE ../RAM2E.v
|
||||
set_global_assignment -name VERILOG_FILE "../UFM-MAX.v"
|
||||
set_global_assignment -name QIP_FILE UFM.qip
|
||||
set_global_assignment -name MIF_FILE ../RAM2E.mif
|
||||
set_global_assignment -name SDC_FILE ../RAM2E.sdc
|
||||
set_global_assignment -name SDC_FILE "../RAM2E-MAX.sdc"
|
||||
set_location_assignment PIN_88 -to LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
|
||||
set_global_assignment -name SDC_FILE "../RAM2E-MAX.sdc"
|
||||
Binary file not shown.
|
|
@ -1,6 +1,6 @@
|
|||
Assembler report for RAM2E
|
||||
Thu Sep 21 05:34:42 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Thu Dec 28 23:09:48 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
|
@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
|||
2. Assembler Summary
|
||||
3. Assembler Settings
|
||||
4. Assembler Generated Files
|
||||
5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof
|
||||
5. Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof
|
||||
6. Assembler Messages
|
||||
|
||||
|
||||
|
|
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Thu Sep 21 05:34:42 2023 ;
|
||||
; Assembler Status ; Successful - Thu Dec 28 23:09:48 2023 ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
|
|
@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula.
|
|||
+--------+---------+---------------+
|
||||
|
||||
|
||||
+-----------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+-----------------------------------------------+
|
||||
; File Name ;
|
||||
+-----------------------------------------------+
|
||||
; /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
|
||||
+-----------------------------------------------+
|
||||
+-------------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+-------------------------------------------------+
|
||||
; File Name ;
|
||||
+-------------------------------------------------+
|
||||
; Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
|
||||
+-------------------------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------+
|
||||
; Assembler Device Options: /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
|
||||
+----------------+--------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+--------------------------------------------------------+
|
||||
; JTAG usercode ; 0x0016B5DB ;
|
||||
; Checksum ; 0x0016B84B ;
|
||||
+----------------+--------------------------------------------------------+
|
||||
+---------------------------------------------------------------------------+
|
||||
; Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
|
||||
+----------------+----------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+----------------------------------------------------------+
|
||||
; JTAG usercode ; 0x001658EB ;
|
||||
; Checksum ; 0x00165BE3 ;
|
||||
+----------------+----------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------+
|
||||
|
|
@ -77,14 +77,14 @@ https://fpgasoftware.intel.com/eula.
|
|||
+--------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Assembler
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:34:41 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Thu Dec 28 23:09:47 2023
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXV -c RAM2E
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 13092 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:42 2023
|
||||
Info: Peak virtual memory: 13070 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:48 2023
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Thu Sep 21 05:34:47 2023
|
||||
Thu Dec 28 23:09:52 2023
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
Fitter report for RAM2E
|
||||
Thu Sep 21 05:34:38 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Thu Dec 28 23:09:45 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
|
@ -54,21 +54,21 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Fitter Status ; Successful - Thu Sep 21 05:34:38 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
; Device ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 197 / 240 ( 82 % ) ;
|
||||
; Total pins ; 70 / 79 ( 89 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
+-------------------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
; Fitter Status ; Successful - Thu Dec 28 23:09:45 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
; Device ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 238 / 240 ( 99 % ) ;
|
||||
; Total pins ; 70 / 79 ( 89 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
|
@ -134,15 +134,15 @@ https://fpgasoftware.intel.com/eula.
|
|||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 1.2% ;
|
||||
; Processors 3-4 ; 1.1% ;
|
||||
; Processor 2 ; 1.0% ;
|
||||
; Processors 3-4 ; 0.9% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
+--------------+
|
||||
; Pin-Out File ;
|
||||
+--------------+
|
||||
The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
|
||||
The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
|
|
@ -150,27 +150,27 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
|
|||
+---------------------------------------------+-----------------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-----------------------+
|
||||
; Total logic elements ; 197 / 240 ( 82 % ) ;
|
||||
; -- Combinational with no register ; 85 ;
|
||||
; -- Register only ; 19 ;
|
||||
; -- Combinational with a register ; 93 ;
|
||||
; Total logic elements ; 238 / 240 ( 99 % ) ;
|
||||
; -- Combinational with no register ; 115 ;
|
||||
; -- Register only ; 26 ;
|
||||
; -- Combinational with a register ; 97 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 103 ;
|
||||
; -- 3 input functions ; 29 ;
|
||||
; -- 2 input functions ; 42 ;
|
||||
; -- 1 input functions ; 3 ;
|
||||
; -- 4 input functions ; 118 ;
|
||||
; -- 3 input functions ; 41 ;
|
||||
; -- 2 input functions ; 48 ;
|
||||
; -- 1 input functions ; 4 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 183 ;
|
||||
; -- normal mode ; 224 ;
|
||||
; -- arithmetic mode ; 14 ;
|
||||
; -- qfbk mode ; 8 ;
|
||||
; -- qfbk mode ; 6 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 16 ;
|
||||
; -- synchronous clear/load mode ; 20 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 112 / 240 ( 47 % ) ;
|
||||
; Total registers ; 123 / 240 ( 51 % ) ;
|
||||
; Total LABs ; 24 / 24 ( 100 % ) ;
|
||||
; Logic elements in carry chains ; 15 ;
|
||||
; Virtual pins ; 0 ;
|
||||
|
|
@ -185,11 +185,11 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
|
|||
; Global signals ; 1 ;
|
||||
; -- Global clocks ; 1 / 4 ( 25 % ) ;
|
||||
; JTAGs ; 0 / 1 ( 0 % ) ;
|
||||
; Average interconnect usage (total/H/V) ; 24.3% / 25.4% / 23.2% ;
|
||||
; Peak interconnect usage (total/H/V) ; 24.3% / 25.4% / 23.2% ;
|
||||
; Maximum fan-out ; 112 ;
|
||||
; Highest non-global fan-out ; 31 ;
|
||||
; Total fan-out ; 847 ;
|
||||
; Average interconnect usage (total/H/V) ; 26.9% / 27.0% / 26.7% ;
|
||||
; Peak interconnect usage (total/H/V) ; 26.9% / 27.0% / 26.7% ;
|
||||
; Maximum fan-out ; 123 ;
|
||||
; Highest non-global fan-out ; 35 ;
|
||||
; Total fan-out ; 976 ;
|
||||
; Average fan-out ; 3.16 ;
|
||||
+---------------------------------------------+-----------------------+
|
||||
|
||||
|
|
@ -207,69 +207,69 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
|
|||
; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 112 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 14 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 123 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 15 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 12 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nWE80 ; 33 ; 1 ; 3 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nWE80 ; 33 ; 1 ; 3 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Output Pins ;
|
||||
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
|
||||
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
; BA[0] ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; CKE ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[3] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[4] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nCAS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nCS ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nRAS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nRWE ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Output Pins ;
|
||||
+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
|
||||
+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
; BA[0] ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; CKEout ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[3] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[4] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RAout[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nCASout ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nCSout ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nRASout ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nRWEout ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
|
@ -283,7 +283,7 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
|
|||
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[4] ; 91 ; 2 ; 4 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[5] ; 92 ; 2 ; 3 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[7] ; 96 ; 2 ; 3 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
|
||||
|
|
@ -304,35 +304,35 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
|
|||
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
|
||||
+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
|
||||
; 1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; 2 ; 0 ; 1 ; nRWE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 3 ; 1 ; 1 ; nCAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 4 ; 2 ; 1 ; CKE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 5 ; 3 ; 1 ; nRAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 2 ; 0 ; 1 ; nRWEout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 3 ; 1 ; 1 ; nCASout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 4 ; 2 ; 1 ; CKEout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 5 ; 3 ; 1 ; nRASout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 6 ; 4 ; 1 ; BA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 7 ; 5 ; 1 ; RA[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 8 ; 6 ; 1 ; nCS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 7 ; 5 ; 1 ; RAout[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 8 ; 6 ; 1 ; nCSout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
|
||||
; 10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; 11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; 12 ; 7 ; 1 ; C14M ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 13 ; ; ; VCCINT ; power ; ; 1.8V ; -- ; ; -- ; -- ;
|
||||
; 14 ; 8 ; 1 ; BA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 15 ; 9 ; 1 ; RA[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 16 ; 10 ; 1 ; RA[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 17 ; 11 ; 1 ; RA[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 18 ; 12 ; 1 ; RA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 19 ; 13 ; 1 ; RA[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 20 ; 14 ; 1 ; RA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 21 ; 15 ; 1 ; RA[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 15 ; 9 ; 1 ; RAout[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 16 ; 10 ; 1 ; RAout[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 17 ; 11 ; 1 ; RAout[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 18 ; 12 ; 1 ; RAout[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 19 ; 13 ; 1 ; RAout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 20 ; 14 ; 1 ; RAout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 21 ; 15 ; 1 ; RAout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
|
||||
; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
|
||||
; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
|
||||
; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
|
||||
; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
|
||||
; 26 ; 20 ; 1 ; RA[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 27 ; 21 ; 1 ; RA[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 26 ; 20 ; 1 ; RAout[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 27 ; 21 ; 1 ; RAout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 28 ; 22 ; 1 ; nEN80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 29 ; 23 ; 1 ; RA[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 30 ; 24 ; 1 ; RA[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 29 ; 23 ; 1 ; RAout[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 30 ; 24 ; 1 ; RAout[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
|
||||
; 32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; 33 ; 25 ; 1 ; nWE80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
|
|
@ -426,112 +426,119 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
|
|||
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Fitter Resource Utilization by Entity ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 197 (197) ; 112 ; 1 ; 70 ; 0 ; 85 (85) ; 19 (19) ; 93 (93) ; 15 (15) ; 8 (8) ; |RAM2E ; RAM2E ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Fitter Resource Utilization by Entity ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 238 (180) ; 123 ; 1 ; 70 ; 0 ; 115 (90) ; 26 (23) ; 97 (67) ; 15 (15) ; 6 (1) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E_UFM:ram2e_ufm| ; 58 (58) ; 33 ; 1 ; 0 ; 0 ; 25 (25) ; 3 (3) ; 30 (30) ; 0 (0) ; 5 (5) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
|
||||
+------------------------------------+
|
||||
; Delay Chain Summary ;
|
||||
+---------+----------+---------------+
|
||||
; Name ; Pin Type ; Pad to Core 0 ;
|
||||
+---------+----------+---------------+
|
||||
; LED ; Output ; -- ;
|
||||
; Dout[0] ; Output ; -- ;
|
||||
; Dout[1] ; Output ; -- ;
|
||||
; Dout[2] ; Output ; -- ;
|
||||
; Dout[3] ; Output ; -- ;
|
||||
; Dout[4] ; Output ; -- ;
|
||||
; Dout[5] ; Output ; -- ;
|
||||
; Dout[6] ; Output ; -- ;
|
||||
; Dout[7] ; Output ; -- ;
|
||||
; nDOE ; Output ; -- ;
|
||||
; Vout[0] ; Output ; -- ;
|
||||
; Vout[1] ; Output ; -- ;
|
||||
; Vout[2] ; Output ; -- ;
|
||||
; Vout[3] ; Output ; -- ;
|
||||
; Vout[4] ; Output ; -- ;
|
||||
; Vout[5] ; Output ; -- ;
|
||||
; Vout[6] ; Output ; -- ;
|
||||
; Vout[7] ; Output ; -- ;
|
||||
; nVOE ; Output ; -- ;
|
||||
; CKE ; Output ; -- ;
|
||||
; nCS ; Output ; -- ;
|
||||
; nRAS ; Output ; -- ;
|
||||
; nCAS ; Output ; -- ;
|
||||
; nRWE ; Output ; -- ;
|
||||
; BA[0] ; Output ; -- ;
|
||||
; BA[1] ; Output ; -- ;
|
||||
; RA[0] ; Output ; -- ;
|
||||
; RA[1] ; Output ; -- ;
|
||||
; RA[2] ; Output ; -- ;
|
||||
; RA[3] ; Output ; -- ;
|
||||
; RA[4] ; Output ; -- ;
|
||||
; RA[5] ; Output ; -- ;
|
||||
; RA[6] ; Output ; -- ;
|
||||
; RA[7] ; Output ; -- ;
|
||||
; RA[8] ; Output ; -- ;
|
||||
; RA[9] ; Output ; -- ;
|
||||
; RA[10] ; Output ; -- ;
|
||||
; RA[11] ; Output ; -- ;
|
||||
; DQML ; Output ; -- ;
|
||||
; DQMH ; Output ; -- ;
|
||||
; RD[0] ; Bidir ; (0) ;
|
||||
; RD[1] ; Bidir ; (0) ;
|
||||
; RD[2] ; Bidir ; (0) ;
|
||||
; RD[3] ; Bidir ; (0) ;
|
||||
; RD[4] ; Bidir ; (0) ;
|
||||
; RD[5] ; Bidir ; (0) ;
|
||||
; RD[6] ; Bidir ; (0) ;
|
||||
; RD[7] ; Bidir ; (0) ;
|
||||
; nEN80 ; Input ; (0) ;
|
||||
; nWE ; Input ; (0) ;
|
||||
; PHI1 ; Input ; (1) ;
|
||||
; Din[0] ; Input ; (0) ;
|
||||
; C14M ; Input ; (0) ;
|
||||
; nWE80 ; Input ; (0) ;
|
||||
; Ain[0] ; Input ; (0) ;
|
||||
; Ain[1] ; Input ; (0) ;
|
||||
; Ain[2] ; Input ; (0) ;
|
||||
; Ain[3] ; Input ; (0) ;
|
||||
; Ain[4] ; Input ; (0) ;
|
||||
; Ain[5] ; Input ; (0) ;
|
||||
; Ain[6] ; Input ; (0) ;
|
||||
; Ain[7] ; Input ; (0) ;
|
||||
; Din[6] ; Input ; (0) ;
|
||||
; Din[2] ; Input ; (0) ;
|
||||
; Din[1] ; Input ; (0) ;
|
||||
; Din[5] ; Input ; (0) ;
|
||||
; Din[7] ; Input ; (0) ;
|
||||
; Din[4] ; Input ; (0) ;
|
||||
; Din[3] ; Input ; (0) ;
|
||||
; nC07X ; Input ; (0) ;
|
||||
+---------+----------+---------------+
|
||||
+--------------------------------------+
|
||||
; Delay Chain Summary ;
|
||||
+-----------+----------+---------------+
|
||||
; Name ; Pin Type ; Pad to Core 0 ;
|
||||
+-----------+----------+---------------+
|
||||
; LED ; Output ; -- ;
|
||||
; nWE80 ; Input ; (0) ;
|
||||
; Dout[0] ; Output ; -- ;
|
||||
; Dout[1] ; Output ; -- ;
|
||||
; Dout[2] ; Output ; -- ;
|
||||
; Dout[3] ; Output ; -- ;
|
||||
; Dout[4] ; Output ; -- ;
|
||||
; Dout[5] ; Output ; -- ;
|
||||
; Dout[6] ; Output ; -- ;
|
||||
; Dout[7] ; Output ; -- ;
|
||||
; nDOE ; Output ; -- ;
|
||||
; Vout[0] ; Output ; -- ;
|
||||
; Vout[1] ; Output ; -- ;
|
||||
; Vout[2] ; Output ; -- ;
|
||||
; Vout[3] ; Output ; -- ;
|
||||
; Vout[4] ; Output ; -- ;
|
||||
; Vout[5] ; Output ; -- ;
|
||||
; Vout[6] ; Output ; -- ;
|
||||
; Vout[7] ; Output ; -- ;
|
||||
; nVOE ; Output ; -- ;
|
||||
; CKEout ; Output ; -- ;
|
||||
; nCSout ; Output ; -- ;
|
||||
; nRASout ; Output ; -- ;
|
||||
; nCASout ; Output ; -- ;
|
||||
; nRWEout ; Output ; -- ;
|
||||
; BA[0] ; Output ; -- ;
|
||||
; BA[1] ; Output ; -- ;
|
||||
; RAout[0] ; Output ; -- ;
|
||||
; RAout[1] ; Output ; -- ;
|
||||
; RAout[2] ; Output ; -- ;
|
||||
; RAout[3] ; Output ; -- ;
|
||||
; RAout[4] ; Output ; -- ;
|
||||
; RAout[5] ; Output ; -- ;
|
||||
; RAout[6] ; Output ; -- ;
|
||||
; RAout[7] ; Output ; -- ;
|
||||
; RAout[8] ; Output ; -- ;
|
||||
; RAout[9] ; Output ; -- ;
|
||||
; RAout[10] ; Output ; -- ;
|
||||
; RAout[11] ; Output ; -- ;
|
||||
; DQML ; Output ; -- ;
|
||||
; DQMH ; Output ; -- ;
|
||||
; RD[0] ; Bidir ; (0) ;
|
||||
; RD[1] ; Bidir ; (0) ;
|
||||
; RD[2] ; Bidir ; (0) ;
|
||||
; RD[3] ; Bidir ; (0) ;
|
||||
; RD[4] ; Bidir ; (0) ;
|
||||
; RD[5] ; Bidir ; (0) ;
|
||||
; RD[6] ; Bidir ; (0) ;
|
||||
; RD[7] ; Bidir ; (0) ;
|
||||
; nEN80 ; Input ; (0) ;
|
||||
; nWE ; Input ; (0) ;
|
||||
; PHI1 ; Input ; (1) ;
|
||||
; C14M ; Input ; (0) ;
|
||||
; Din[0] ; Input ; (0) ;
|
||||
; Din[6] ; Input ; (0) ;
|
||||
; Din[1] ; Input ; (0) ;
|
||||
; Din[5] ; Input ; (0) ;
|
||||
; Din[7] ; Input ; (0) ;
|
||||
; Din[4] ; Input ; (0) ;
|
||||
; Din[2] ; Input ; (0) ;
|
||||
; Din[3] ; Input ; (0) ;
|
||||
; nC07X ; Input ; (0) ;
|
||||
; Ain[0] ; Input ; (0) ;
|
||||
; Ain[1] ; Input ; (0) ;
|
||||
; Ain[2] ; Input ; (0) ;
|
||||
; Ain[3] ; Input ; (0) ;
|
||||
; Ain[4] ; Input ; (0) ;
|
||||
; Ain[5] ; Input ; (0) ;
|
||||
; Ain[6] ; Input ; (0) ;
|
||||
; Ain[7] ; Input ; (0) ;
|
||||
+-----------+----------+---------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------+
|
||||
; Control Signals ;
|
||||
+------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; C14M ; PIN_12 ; 112 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; CS[0]~2 ; LC_X6_Y1_N1 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal9~1 ; LC_X5_Y3_N0 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal9~2 ; LC_X7_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RA[0]~15 ; LC_X2_Y2_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RDOE ; LC_X2_Y4_N6 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; RWMask~1 ; LC_X4_Y1_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; S[2] ; LC_X7_Y2_N1 ; 22 ; Sync. clear ; no ; -- ; -- ;
|
||||
; UFMD[15]~0 ; LC_X5_Y1_N1 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; always2~8 ; LC_X6_Y1_N2 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
+------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
+---------------------------------------------------------------------------------------------------------------------------+
|
||||
; Control Signals ;
|
||||
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; BA[1]~0 ; LC_X2_Y2_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; C14M ; PIN_12 ; 123 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; CS[0]~2 ; LC_X4_Y3_N0 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; DQML~0 ; LC_X2_Y4_N5 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~1 ; LC_X6_Y3_N2 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~2 ; LC_X6_Y4_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~4 ; LC_X6_Y3_N1 ; 4 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~5 ; LC_X5_Y4_N8 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; Mux14~0 ; LC_X5_Y4_N3 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X6_Y1_N9 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X4_Y1_N6 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X6_Y3_N9 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
; RA[2]~0 ; LC_X2_Y2_N5 ; 6 ; Clock enable ; no ; -- ; -- ;
|
||||
; RDOE ; LC_X3_Y4_N0 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; S[0] ; LC_X7_Y3_N2 ; 35 ; Sync. clear ; no ; -- ; -- ;
|
||||
; S[3] ; LC_X6_Y4_N9 ; 32 ; Sync. clear ; no ; -- ; -- ;
|
||||
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
|
|
@ -539,7 +546,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+------+----------+---------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
; C14M ; PIN_12 ; 112 ; Global Clock ; GCLK0 ;
|
||||
; C14M ; PIN_12 ; 123 ; Global Clock ; GCLK0 ;
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
|
||||
|
||||
|
|
@ -548,118 +555,121 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+-----------------------+--------------------+
|
||||
; Routing Resource Type ; Usage ;
|
||||
+-----------------------+--------------------+
|
||||
; C4s ; 146 / 784 ( 19 % ) ;
|
||||
; Direct links ; 31 / 888 ( 3 % ) ;
|
||||
; C4s ; 171 / 784 ( 22 % ) ;
|
||||
; Direct links ; 55 / 888 ( 6 % ) ;
|
||||
; Global clocks ; 1 / 4 ( 25 % ) ;
|
||||
; LAB clocks ; 6 / 32 ( 19 % ) ;
|
||||
; LUT chains ; 4 / 216 ( 2 % ) ;
|
||||
; Local interconnects ; 279 / 888 ( 31 % ) ;
|
||||
; R4s ; 144 / 704 ( 20 % ) ;
|
||||
; LUT chains ; 6 / 216 ( 3 % ) ;
|
||||
; Local interconnects ; 343 / 888 ( 39 % ) ;
|
||||
; R4s ; 150 / 704 ( 21 % ) ;
|
||||
+-----------------------+--------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Logic Elements ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; Number of Logic Elements (Average = 8.21) ; Number of LABs (Total = 24) ;
|
||||
; Number of Logic Elements (Average = 9.92) ; Number of LABs (Total = 24) ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; 1 ; 2 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 1 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 1 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 14 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 23 ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; LAB-wide Signals ;
|
||||
+------------------------------------+------------------------------+
|
||||
; LAB-wide Signals (Average = 1.38) ; Number of LABs (Total = 24) ;
|
||||
; LAB-wide Signals (Average = 1.58) ; Number of LABs (Total = 24) ;
|
||||
+------------------------------------+------------------------------+
|
||||
; 1 Clock ; 22 ;
|
||||
; 1 Clock enable ; 10 ;
|
||||
; 2 Clock enables ; 1 ;
|
||||
; 1 Clock ; 24 ;
|
||||
; 1 Clock enable ; 9 ;
|
||||
; 1 Sync. clear ; 2 ;
|
||||
; 2 Clock enables ; 3 ;
|
||||
+------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced (Average = 8.54) ; Number of LABs (Total = 24) ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 2 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 13 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 1 ;
|
||||
; 13 ; 1 ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
+-----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced (Average = 10.17) ; Number of LABs (Total = 24) ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 21 ;
|
||||
; 11 ; 1 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 1 ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced Out ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced Out (Average = 6.25) ; Number of LABs (Total = 24) ;
|
||||
; Number of Signals Sourced Out (Average = 7.50) ; Number of LABs (Total = 24) ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 2 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 2 ;
|
||||
; 5 ; 5 ;
|
||||
; 5 ; 3 ;
|
||||
; 6 ; 2 ;
|
||||
; 7 ; 3 ;
|
||||
; 8 ; 5 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 1 ;
|
||||
; 11 ; 1 ;
|
||||
; 7 ; 2 ;
|
||||
; 8 ; 4 ;
|
||||
; 9 ; 6 ;
|
||||
; 10 ; 3 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 1 ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; Number of Distinct Inputs (Average = 10.46) ; Number of LABs (Total = 24) ;
|
||||
; Number of Distinct Inputs (Average = 12.88) ; Number of LABs (Total = 24) ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 4 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 2 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 2 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 1 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 3 ;
|
||||
; 11 ; 3 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 1 ;
|
||||
; 14 ; 1 ;
|
||||
; 15 ; 1 ;
|
||||
; 16 ; 1 ;
|
||||
; 17 ; 0 ;
|
||||
; 18 ; 0 ;
|
||||
; 19 ; 0 ;
|
||||
; 7 ; 2 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 2 ;
|
||||
; 11 ; 1 ;
|
||||
; 12 ; 1 ;
|
||||
; 13 ; 3 ;
|
||||
; 14 ; 3 ;
|
||||
; 15 ; 2 ;
|
||||
; 16 ; 2 ;
|
||||
; 17 ; 1 ;
|
||||
; 18 ; 2 ;
|
||||
; 19 ; 1 ;
|
||||
; 20 ; 0 ;
|
||||
; 21 ; 2 ;
|
||||
; 21 ; 0 ;
|
||||
; 22 ; 0 ;
|
||||
; 23 ; 0 ;
|
||||
; 24 ; 0 ;
|
||||
; 25 ; 1 ;
|
||||
; 24 ; 1 ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
|
|
@ -700,11 +710,11 @@ Info (332129): Detected timing requirements -- optimizing circuit to achieve onl
|
|||
Info (332111): Found 3 clocks
|
||||
Info (332111): Period Clock Name
|
||||
Info (332111): ======== ============
|
||||
Info (332111): 200.000 ARCLK
|
||||
Info (332111): 69.841 C14M
|
||||
Info (332111): 200.000 DRCLK
|
||||
Info (332111): 200.000 ram2e_ufm|ARCLK|regout
|
||||
Info (332111): 200.000 ram2e_ufm|DRCLK|regout
|
||||
Info (186079): Completed User Assigned Global Signals Promotion Operation
|
||||
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 8
|
||||
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8
|
||||
Info (186079): Completed Auto Global Promotion Operation
|
||||
Info (176234): Starting register packing
|
||||
Info (186468): Started processing fast register assignments
|
||||
|
|
@ -718,25 +728,23 @@ Info (170191): Fitter placement operations beginning
|
|||
Info (170137): Fitter placement was successful
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
|
||||
Info (170193): Fitter routing operations beginning
|
||||
Info (170089): 2e+01 ns of routing delay (approximately 1.0% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
|
||||
Info (170195): Router estimated average interconnect usage is 21% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
||||
Info (170201): Optimizations that may affect the design's routability were skipped
|
||||
Info (170195): Router estimated average interconnect usage is 23% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 23% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.58 seconds.
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.67 seconds.
|
||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg
|
||||
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 13770 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:39 2023
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Total CPU time (on all processors): 00:00:03
|
||||
Info: Peak virtual memory: 13748 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:45 2023
|
||||
Info: Elapsed time: 00:00:04
|
||||
Info: Total CPU time (on all processors): 00:00:04
|
||||
|
||||
|
||||
+----------------------------+
|
||||
; Fitter Suppressed Messages ;
|
||||
+----------------------------+
|
||||
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg.
|
||||
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg.
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
Fitter Status : Successful - Thu Sep 21 05:34:38 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Fitter Status : Successful - Thu Dec 28 23:09:45 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
Family : MAX V
|
||||
Device : 5M240ZT100C5
|
||||
Timing Models : Final
|
||||
Total logic elements : 197 / 240 ( 82 % )
|
||||
Total logic elements : 238 / 240 ( 99 % )
|
||||
Total pins : 70 / 79 ( 89 % )
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
Flow report for RAM2E
|
||||
Thu Sep 21 05:34:46 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Thu Dec 28 23:09:52 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
|
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Flow Status ; Successful - Thu Sep 21 05:34:42 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
; Device ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 197 / 240 ( 82 % ) ;
|
||||
; Total pins ; 70 / 79 ( 89 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
+-------------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
; Flow Status ; Successful - Thu Dec 28 23:09:48 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
; Device ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 238 / 240 ( 99 % ) ;
|
||||
; Total pins ; 70 / 79 ( 89 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
|
|
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 09/21/2023 05:34:00 ;
|
||||
; Start date & time ; 12/28/2023 23:09:13 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; RAM2E ;
|
||||
+-------------------+---------------------+
|
||||
|
|
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+-------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.169528883915840 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.170382295304664 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
|
||||
|
|
@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula.
|
|||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:35 ; 1.0 ; 13144 MB ; 00:00:50 ;
|
||||
; Fitter ; 00:00:04 ; 1.0 ; 13770 MB ; 00:00:03 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13091 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:03 ; 1.0 ; 13092 MB ; 00:00:02 ;
|
||||
; Total ; 00:00:43 ; -- ; -- ; 00:00:56 ;
|
||||
; Analysis & Synthesis ; 00:00:28 ; 1.0 ; 13113 MB ; 00:00:41 ;
|
||||
; Fitter ; 00:00:04 ; 1.0 ; 13748 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13069 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:03 ; 1.0 ; 13067 MB ; 00:00:02 ;
|
||||
; Total ; 00:00:36 ; -- ; -- ; 00:00:48 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="ec04ae5d795b1a9f31d1"/>
|
||||
<hash md5_digest_80b="a200c32949da45b33c7d"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="5M240ZT100C5" path="RAM2E.sof" usercode="0xFFFFFFFF"/>
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
Analysis & Synthesis report for RAM2E
|
||||
Thu Sep 21 05:34:33 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Thu Dec 28 23:09:40 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
|
@ -17,7 +17,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
|||
9. General Register Statistics
|
||||
10. Inverted Register Statistics
|
||||
11. Multiplexer Restructuring Statistics (Restructuring Performed)
|
||||
12. Port Connectivity Checks: "UFM:UFM_inst"
|
||||
12. Port Connectivity Checks: "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst"
|
||||
13. Analysis & Synthesis Messages
|
||||
14. Analysis & Synthesis Suppressed Messages
|
||||
|
||||
|
|
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Thu Sep 21 05:34:33 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
; Total logic elements ; 205 ;
|
||||
; Total pins ; 70 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
+-------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+-------------------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Thu Dec 28 23:09:40 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
; Total logic elements ; 244 ;
|
||||
; Total pins ; 70 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------------+-------------------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
|
|
@ -146,15 +146,16 @@ https://fpgasoftware.intel.com/eula.
|
|||
+----------------------------+-------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
|
||||
; ../RAM2E-MAX.v ; yes ; User Verilog HDL File ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v ; ;
|
||||
; UFM.v ; yes ; User Wizard-Generated File ; //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v ; ;
|
||||
; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.mif ; ;
|
||||
+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+----------------------------------+--------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+----------------------------------+--------------------------------+---------+
|
||||
; ../RAM2E.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/RAM2E.v ; ;
|
||||
; ../UFM-MAX.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/UFM-MAX.v ; ;
|
||||
; UFM.v ; yes ; User Wizard-Generated File ; Y:/Repos/RAM2E/CPLD/MAXV/UFM.v ; ;
|
||||
; ../RAM2E.mif ; yes ; User Memory Initialization File ; Y:/Repos/RAM2E/CPLD/RAM2E.mif ; ;
|
||||
+----------------------------------+-----------------+----------------------------------+--------------------------------+---------+
|
||||
|
||||
|
||||
+-----------------------------------------------------+
|
||||
|
|
@ -162,56 +163,57 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------------+-------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-------+
|
||||
; Total logic elements ; 205 ;
|
||||
; -- Combinational with no register ; 93 ;
|
||||
; -- Register only ; 27 ;
|
||||
; -- Combinational with a register ; 85 ;
|
||||
; Total logic elements ; 244 ;
|
||||
; -- Combinational with no register ; 121 ;
|
||||
; -- Register only ; 32 ;
|
||||
; -- Combinational with a register ; 91 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 103 ;
|
||||
; -- 3 input functions ; 29 ;
|
||||
; -- 2 input functions ; 42 ;
|
||||
; -- 1 input functions ; 3 ;
|
||||
; -- 4 input functions ; 118 ;
|
||||
; -- 3 input functions ; 41 ;
|
||||
; -- 2 input functions ; 48 ;
|
||||
; -- 1 input functions ; 4 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 191 ;
|
||||
; -- normal mode ; 230 ;
|
||||
; -- arithmetic mode ; 14 ;
|
||||
; -- qfbk mode ; 0 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 1 ;
|
||||
; -- synchronous clear/load mode ; 3 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 112 ;
|
||||
; Total registers ; 123 ;
|
||||
; Total logic cells in carry chains ; 15 ;
|
||||
; I/O pins ; 70 ;
|
||||
; UFM blocks ; 1 ;
|
||||
; Maximum fan-out node ; C14M ;
|
||||
; Maximum fan-out ; 112 ;
|
||||
; Total fan-out ; 850 ;
|
||||
; Average fan-out ; 3.08 ;
|
||||
; Maximum fan-out ; 123 ;
|
||||
; Total fan-out ; 977 ;
|
||||
; Average fan-out ; 3.10 ;
|
||||
+---------------------------------------------+-------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 205 (205) ; 112 ; 1 ; 70 ; 0 ; 93 (93) ; 27 (27) ; 85 (85) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 244 (181) ; 123 ; 1 ; 70 ; 0 ; 121 (91) ; 32 (24) ; 91 (66) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E_UFM:ram2e_ufm| ; 63 (63) ; 33 ; 1 ; 0 ; 0 ; 30 (30) ; 8 (8) ; 25 (25) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis IP Cores Summary ;
|
||||
+--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+
|
||||
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
|
||||
+--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+
|
||||
; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1 ; N/A ; N/A ; |RAM2E|UFM:UFM_inst ; UFM.v ;
|
||||
+--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis IP Cores Summary ;
|
||||
+--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+
|
||||
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
|
||||
+--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+
|
||||
; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1 ; N/A ; N/A ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM.v ;
|
||||
+--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+
|
||||
|
||||
|
||||
+------------------------------------------------------+
|
||||
|
|
@ -219,12 +221,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 112 ;
|
||||
; Number of registers using Synchronous Clear ; 1 ;
|
||||
; Total registers ; 123 ;
|
||||
; Number of registers using Synchronous Clear ; 3 ;
|
||||
; Number of registers using Synchronous Load ; 0 ;
|
||||
; Number of registers using Asynchronous Clear ; 0 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 60 ;
|
||||
; Number of registers using Clock Enable ; 62 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
|
|
@ -234,30 +236,36 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+----------------------------------------+---------+
|
||||
; Inverted Register ; Fan out ;
|
||||
+----------------------------------------+---------+
|
||||
; nCS~reg0 ; 1 ;
|
||||
; nRAS~reg0 ; 1 ;
|
||||
; nCAS~reg0 ; 1 ;
|
||||
; nRWE~reg0 ; 1 ;
|
||||
; nRASout~reg0 ; 1 ;
|
||||
; nCASout~reg0 ; 1 ;
|
||||
; nRWEout~reg0 ; 1 ;
|
||||
; DQML~reg0 ; 1 ;
|
||||
; DQMH~reg0 ; 1 ;
|
||||
; Total number of inverted registers = 6 ; ;
|
||||
; CKE ; 1 ;
|
||||
; nRAS ; 1 ;
|
||||
; nCAS ; 1 ;
|
||||
; nRWE ; 1 ;
|
||||
; Total number of inverted registers = 9 ; ;
|
||||
+----------------------------------------+---------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |RAM2E|RA[0]~reg0 ;
|
||||
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[2] ;
|
||||
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[0] ;
|
||||
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RWMask[4] ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
|
||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
|
||||
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[0] ;
|
||||
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[0] ;
|
||||
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RAM2E_UFM:ram2e_ufm|RWMask[5] ;
|
||||
; 16:1 ; 2 bits ; 20 LEs ; 2 LEs ; 18 LEs ; Yes ; |RAM2E|BA[1]~reg0 ;
|
||||
; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |RAM2E|RA[4] ;
|
||||
; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |RAM2E|RA[2] ;
|
||||
; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |RAM2E|DQML~reg0 ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "UFM:UFM_inst" ;
|
||||
; Port Connectivity Checks: "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" ;
|
||||
+--------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+--------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
|
|
@ -272,35 +280,50 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:33:58 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Thu Dec 28 23:09:12 2023
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXV -c RAM2E
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2e/cpld/ram2e-max.v
|
||||
Info (12023): Found entity 1: RAM2E File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 1
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e.v
|
||||
Info (12023): Found entity 1: RAM2E File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 1
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ufm-max.v
|
||||
Info (12023): Found entity 1: RAM2E_UFM File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1
|
||||
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
|
||||
Info (12023): Found entity 1: UFM_altufm_none_p8r File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47
|
||||
Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166
|
||||
Info (12023): Found entity 1: UFM_altufm_none_p8r File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47
|
||||
Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166
|
||||
Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
|
||||
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 93
|
||||
Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217
|
||||
Info (21057): Implemented 276 device resources after synthesis - the final resource count might be different
|
||||
Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 112
|
||||
Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 79
|
||||
Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "nCSout" is stuck at GND File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 78
|
||||
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
|
||||
Warning (21074): Design contains 1 input pin(s) that do not drive logic
|
||||
Warning (15610): No output dependent on input pin "nWE80" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 11
|
||||
Info (21057): Implemented 315 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 22 input pins
|
||||
Info (21059): Implemented 40 output pins
|
||||
Info (21060): Implemented 8 bidirectional pins
|
||||
Info (21061): Implemented 205 logic cells
|
||||
Info (21061): Implemented 244 logic cells
|
||||
Info (21070): Implemented 1 User Flash Memory blocks
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 13144 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:33 2023
|
||||
Info: Elapsed time: 00:00:35
|
||||
Info: Total CPU time (on all processors): 00:00:50
|
||||
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
|
||||
Info: Peak virtual memory: 13113 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:40 2023
|
||||
Info: Elapsed time: 00:00:28
|
||||
Info: Total CPU time (on all processors): 00:00:41
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Analysis & Synthesis Suppressed Messages ;
|
||||
+------------------------------------------+
|
||||
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg.
|
||||
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg.
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
Warning (10273): Verilog HDL warning at RAM2E-MAX.v(46): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 46
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189
|
||||
Warning (10273): Verilog HDL warning at RAM2E.v(74): extended using "x" or "z" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 74
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
Analysis & Synthesis Status : Successful - Thu Sep 21 05:34:33 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Analysis & Synthesis Status : Successful - Thu Dec 28 23:09:40 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
Family : MAX V
|
||||
Total logic elements : 205
|
||||
Total logic elements : 244
|
||||
Total pins : 70
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
|
|
|||
|
|
@ -58,41 +58,41 @@
|
|||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
CHIP "RAM2E" ASSIGNED TO AN: 5M240ZT100C5
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
GND : 1 : gnd : : : :
|
||||
nRWE : 2 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nCAS : 3 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
CKE : 4 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nRAS : 5 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nRWEout : 2 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nCASout : 3 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
CKEout : 4 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nRASout : 5 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
BA[0] : 6 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nCS : 8 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nCSout : 8 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
VCCIO1 : 9 : power : : 3.3V : 1 :
|
||||
GND : 10 : gnd : : : :
|
||||
GND : 11 : gnd : : : :
|
||||
C14M : 12 : input : 3.3-V LVCMOS : : 1 : Y
|
||||
VCCINT : 13 : power : : 1.8V : :
|
||||
BA[1] : 14 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[8] : 17 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[0] : 18 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[7] : 19 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[1] : 20 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[6] : 21 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[8] : 17 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[0] : 18 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[7] : 19 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[1] : 20 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[6] : 21 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
TMS : 22 : input : : : 1 :
|
||||
TDI : 23 : input : : : 1 :
|
||||
TCK : 24 : input : : : 1 :
|
||||
TDO : 25 : output : : : 1 :
|
||||
RA[4] : 26 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[3] : 27 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[4] : 26 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[3] : 27 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
nEN80 : 28 : input : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RA[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
RAout[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y
|
||||
VCCIO1 : 31 : power : : 3.3V : 1 :
|
||||
GND : 32 : gnd : : : :
|
||||
nWE80 : 33 : input : 3.3-V LVCMOS : : 1 : Y
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,6 +1,6 @@
|
|||
Timing Analyzer report for RAM2E
|
||||
Thu Sep 21 05:34:46 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Thu Dec 28 23:09:52 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
|
@ -17,11 +17,11 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
|||
9. Recovery Summary
|
||||
10. Removal Summary
|
||||
11. Minimum Pulse Width Summary
|
||||
12. Setup: 'DRCLK'
|
||||
13. Setup: 'ARCLK'
|
||||
12. Setup: 'ram2e_ufm|DRCLK|regout'
|
||||
13. Setup: 'ram2e_ufm|ARCLK|regout'
|
||||
14. Setup: 'C14M'
|
||||
15. Hold: 'ARCLK'
|
||||
16. Hold: 'DRCLK'
|
||||
15. Hold: 'ram2e_ufm|DRCLK|regout'
|
||||
16. Hold: 'ram2e_ufm|ARCLK|regout'
|
||||
17. Hold: 'C14M'
|
||||
18. Setup Transfers
|
||||
19. Hold Transfers
|
||||
|
|
@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------+
|
||||
; Timing Analyzer Summary ;
|
||||
+-----------------------+-----------------------------------------------------+
|
||||
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Timing Analyzer ; Legacy Timing Analyzer ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Device Family ; MAX V ;
|
||||
; Device Name ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Delay Model ; Slow Model ;
|
||||
; Rise/Fall Delays ; Unavailable ;
|
||||
+-----------------------+-----------------------------------------------------+
|
||||
+---------------------------------------------------------------------------------------------+
|
||||
; Timing Analyzer Summary ;
|
||||
+-----------------------+---------------------------------------------------------------------+
|
||||
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Timing Analyzer ; Legacy Timing Analyzer ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Device Family ; MAX V ;
|
||||
; Device Name ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Delay Model ; Slow Model ;
|
||||
; Rise/Fall Delays ; Unavailable ;
|
||||
+-----------------------+---------------------------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
|
|
@ -93,54 +93,54 @@ https://fpgasoftware.intel.com/eula.
|
|||
+------------------+--------+--------------------------+
|
||||
; SDC File Path ; Status ; Read at ;
|
||||
+------------------+--------+--------------------------+
|
||||
; ../RAM2E.sdc ; OK ; Thu Sep 21 05:34:45 2023 ;
|
||||
; ../RAM2E-MAX.sdc ; OK ; Thu Sep 21 05:34:45 2023 ;
|
||||
; ../RAM2E.sdc ; OK ; Thu Dec 28 23:09:51 2023 ;
|
||||
; ../RAM2E-MAX.sdc ; OK ; Thu Dec 28 23:09:51 2023 ;
|
||||
+------------------+--------+--------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Clocks ;
|
||||
+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
|
||||
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
|
||||
+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
|
||||
; ARCLK ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { ARCLK } ;
|
||||
; C14M ; Base ; 69.841 ; 14.32 MHz ; 0.000 ; 34.920 ; ; ; ; ; ; ; ; ; ; ; { C14M } ;
|
||||
; DRCLK ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { DRCLK } ;
|
||||
+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Clocks ;
|
||||
+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
|
||||
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
|
||||
+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
|
||||
; C14M ; Base ; 69.841 ; 14.32 MHz ; 0.000 ; 34.920 ; ; ; ; ; ; ; ; ; ; ; { C14M } ;
|
||||
; ram2e_ufm|ARCLK|regout ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { ram2e_ufm|ARCLK|regout } ;
|
||||
; ram2e_ufm|DRCLK|regout ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { ram2e_ufm|DRCLK|regout } ;
|
||||
+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------+
|
||||
; Fmax Summary ;
|
||||
+-----------+-----------------+------------+------+
|
||||
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
||||
+-----------+-----------------+------------+------+
|
||||
; 10.0 MHz ; 10.0 MHz ; ARCLK ; ;
|
||||
; 10.0 MHz ; 10.0 MHz ; DRCLK ; ;
|
||||
; 25.52 MHz ; 25.52 MHz ; C14M ; ;
|
||||
+-----------+-----------------+------------+------+
|
||||
+-------------------------------------------------------------+
|
||||
; Fmax Summary ;
|
||||
+-----------+-----------------+------------------------+------+
|
||||
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
||||
+-----------+-----------------+------------------------+------+
|
||||
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|ARCLK|regout ; ;
|
||||
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|DRCLK|regout ; ;
|
||||
; 27.71 MHz ; 27.71 MHz ; C14M ; ;
|
||||
+-----------+-----------------+------------------------+------+
|
||||
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
||||
|
||||
|
||||
+---------------------------------+
|
||||
; Setup Summary ;
|
||||
+-------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+---------+---------------+
|
||||
; DRCLK ; -24.019 ; -24.019 ;
|
||||
; ARCLK ; -23.863 ; -23.863 ;
|
||||
; C14M ; -15.767 ; -176.992 ;
|
||||
+-------+---------+---------------+
|
||||
+--------------------------------------------------+
|
||||
; Setup Summary ;
|
||||
+------------------------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+------------------------+---------+---------------+
|
||||
; ram2e_ufm|DRCLK|regout ; -25.451 ; -25.451 ;
|
||||
; ram2e_ufm|ARCLK|regout ; -25.441 ; -25.441 ;
|
||||
; C14M ; -20.081 ; -208.886 ;
|
||||
+------------------------+---------+---------------+
|
||||
|
||||
|
||||
+---------------------------------+
|
||||
; Hold Summary ;
|
||||
+-------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+---------+---------------+
|
||||
; ARCLK ; -16.136 ; -16.136 ;
|
||||
; DRCLK ; -15.980 ; -15.980 ;
|
||||
; C14M ; 2.440 ; 0.000 ;
|
||||
+-------+---------+---------------+
|
||||
+--------------------------------------------------+
|
||||
; Hold Summary ;
|
||||
+------------------------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+------------------------+---------+---------------+
|
||||
; ram2e_ufm|DRCLK|regout ; -14.567 ; -14.567 ;
|
||||
; ram2e_ufm|ARCLK|regout ; -14.558 ; -14.558 ;
|
||||
; C14M ; 3.133 ; 0.000 ;
|
||||
+------------------------+---------+---------------+
|
||||
|
||||
|
||||
--------------------
|
||||
|
|
@ -155,302 +155,302 @@ No paths to report.
|
|||
No paths to report.
|
||||
|
||||
|
||||
+--------------------------------+
|
||||
; Minimum Pulse Width Summary ;
|
||||
+-------+--------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+--------+---------------+
|
||||
; C14M ; 34.581 ; 0.000 ;
|
||||
; ARCLK ; 70.000 ; 0.000 ;
|
||||
; DRCLK ; 70.000 ; 0.000 ;
|
||||
+-------+--------+---------------+
|
||||
+-------------------------------------------------+
|
||||
; Minimum Pulse Width Summary ;
|
||||
+------------------------+--------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+------------------------+--------+---------------+
|
||||
; C14M ; 34.581 ; 0.000 ;
|
||||
; ram2e_ufm|ARCLK|regout ; 70.000 ; 0.000 ;
|
||||
; ram2e_ufm|DRCLK|regout ; 70.000 ; 0.000 ;
|
||||
+------------------------+--------+---------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'DRCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -24.019 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.057 ; 2.963 ;
|
||||
; -24.019 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.057 ; 2.963 ;
|
||||
; 100.000 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'ram2e_ufm|DRCLK|regout' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; -25.451 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -0.970 ; 4.482 ;
|
||||
; -25.432 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -0.970 ; 4.463 ;
|
||||
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'ARCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -23.863 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.001 ; -0.901 ; 2.963 ;
|
||||
; 100.000 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'ram2e_ufm|ARCLK|regout' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; -25.441 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -0.977 ; 4.465 ;
|
||||
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'C14M' ;
|
||||
+---------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
; -15.767 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFMReqErase ; DRCLK ; C14M ; 0.001 ; 1.057 ; 16.504 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[4] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[5] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[7] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[0] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[1] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[2] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[3] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[6] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -14.411 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; LEDEN ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.148 ;
|
||||
; -13.177 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFMInitDone ; DRCLK ; C14M ; 0.001 ; 1.057 ; 13.914 ;
|
||||
; -11.917 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFMD[8] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 12.654 ;
|
||||
; 16.803 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ;
|
||||
; 16.803 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ;
|
||||
; 16.803 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ;
|
||||
; 16.803 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ;
|
||||
; 16.803 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ;
|
||||
; 16.803 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ;
|
||||
; 16.806 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.793 ;
|
||||
; 16.809 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.790 ;
|
||||
; 18.727 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ;
|
||||
; 18.727 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ;
|
||||
; 18.727 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ;
|
||||
; 18.727 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ;
|
||||
; 18.727 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ;
|
||||
; 18.727 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ;
|
||||
; 18.730 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.869 ;
|
||||
; 18.733 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.866 ;
|
||||
; 19.149 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.450 ;
|
||||
; 19.149 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.450 ;
|
||||
; 19.196 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.403 ;
|
||||
; 19.196 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.403 ;
|
||||
; 19.196 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.403 ;
|
||||
; 19.260 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.339 ;
|
||||
; 19.260 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.339 ;
|
||||
; 19.307 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.292 ;
|
||||
; 19.307 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.292 ;
|
||||
; 19.307 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.292 ;
|
||||
; 20.893 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ;
|
||||
; 20.893 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ;
|
||||
; 20.893 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ;
|
||||
; 20.893 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ;
|
||||
; 20.893 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ;
|
||||
; 20.893 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ;
|
||||
; 20.896 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.703 ;
|
||||
; 20.899 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.700 ;
|
||||
; 22.101 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.498 ;
|
||||
; 22.101 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.498 ;
|
||||
; 22.101 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.498 ;
|
||||
; 22.212 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.387 ;
|
||||
; 22.212 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.387 ;
|
||||
; 22.212 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.387 ;
|
||||
; 23.092 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ;
|
||||
; 23.092 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ;
|
||||
; 23.092 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ;
|
||||
; 23.092 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ;
|
||||
; 23.092 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ;
|
||||
; 23.092 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ;
|
||||
; 23.095 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.504 ;
|
||||
; 23.098 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.501 ;
|
||||
; 23.710 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.889 ;
|
||||
; 23.710 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.889 ;
|
||||
; 23.757 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.842 ;
|
||||
; 23.757 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.842 ;
|
||||
; 23.757 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.842 ;
|
||||
; 24.349 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.250 ;
|
||||
; 24.349 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.250 ;
|
||||
; 24.396 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.203 ;
|
||||
; 24.396 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.203 ;
|
||||
; 24.396 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.203 ;
|
||||
; 26.662 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.937 ;
|
||||
; 26.662 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.937 ;
|
||||
; 26.662 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.937 ;
|
||||
; 27.301 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.298 ;
|
||||
; 27.301 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.298 ;
|
||||
; 27.301 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.298 ;
|
||||
; 30.659 ; FS[15] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 38.861 ;
|
||||
; 31.593 ; FS[14] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 37.927 ;
|
||||
; 32.392 ; FS[15] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 37.128 ;
|
||||
; 32.513 ; FS[2] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 37.007 ;
|
||||
; 33.326 ; FS[14] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 36.194 ;
|
||||
; 33.452 ; FS[15] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 36.068 ;
|
||||
; 33.715 ; S[1] ; CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 35.805 ;
|
||||
; 34.111 ; FS[1] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 35.409 ;
|
||||
; 34.246 ; FS[2] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 35.274 ;
|
||||
; 34.386 ; FS[14] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 35.134 ;
|
||||
; 35.112 ; FS[11] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 34.408 ;
|
||||
; 35.288 ; FS[10] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 34.232 ;
|
||||
; 35.392 ; S[1] ; CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 34.128 ;
|
||||
; 35.639 ; S[2] ; CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 33.881 ;
|
||||
; 35.844 ; FS[1] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 33.676 ;
|
||||
; 36.147 ; FS[8] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 33.373 ;
|
||||
; 36.765 ; FS[9] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 32.755 ;
|
||||
; 36.845 ; FS[11] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 32.675 ;
|
||||
; 37.021 ; FS[10] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 32.499 ;
|
||||
; 37.152 ; FS[4] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 32.368 ;
|
||||
; 37.316 ; S[2] ; CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 32.204 ;
|
||||
; 37.805 ; S[0] ; CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 31.715 ;
|
||||
; 37.880 ; FS[8] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 31.640 ;
|
||||
; 37.905 ; FS[11] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 31.615 ;
|
||||
+---------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'C14M' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+-------------+--------------+------------+------------+
|
||||
; -20.081 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 20.731 ;
|
||||
; -18.769 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 19.419 ;
|
||||
; -18.109 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.759 ;
|
||||
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
|
||||
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
|
||||
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
|
||||
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
|
||||
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
|
||||
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
|
||||
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
|
||||
; -16.915 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 17.565 ;
|
||||
; -11.924 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 12.574 ;
|
||||
; 25.780 ; RA[5] ; RAout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.819 ;
|
||||
; 26.401 ; RA[0] ; RAout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.198 ;
|
||||
; 27.872 ; RA[10] ; RAout[10]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.727 ;
|
||||
; 28.323 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.276 ;
|
||||
; 28.531 ; RA[8] ; RAout[8]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.068 ;
|
||||
; 28.539 ; RA[11] ; RAout[11]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.060 ;
|
||||
; 28.589 ; RA[9] ; RAout[9]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.010 ;
|
||||
; 30.107 ; RA[7] ; RAout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.492 ;
|
||||
; 30.133 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.466 ;
|
||||
; 30.360 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.239 ;
|
||||
; 30.365 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.234 ;
|
||||
; 30.369 ; RA[1] ; RAout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.230 ;
|
||||
; 30.392 ; RA[6] ; RAout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.207 ;
|
||||
; 31.173 ; RA[3] ; RAout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.426 ;
|
||||
; 31.207 ; RA[2] ; RAout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.392 ;
|
||||
; 31.456 ; RA[4] ; RAout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.143 ;
|
||||
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
||||
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
||||
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
||||
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
||||
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
||||
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
||||
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
||||
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
|
||||
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
||||
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
||||
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
||||
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
||||
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
||||
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
||||
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
||||
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
|
||||
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
||||
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
||||
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
||||
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
||||
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
||||
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
||||
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
||||
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
|
||||
; 37.521 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 69.841 ; 0.000 ; 31.999 ;
|
||||
; 37.937 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 69.841 ; 0.000 ; 31.583 ;
|
||||
; 39.048 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 69.841 ; 0.000 ; 30.472 ;
|
||||
; 40.235 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 69.841 ; 0.000 ; 29.285 ;
|
||||
; 40.239 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 69.841 ; 0.000 ; 29.281 ;
|
||||
; 40.355 ; S[1] ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 29.165 ;
|
||||
; 40.651 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 69.841 ; 0.000 ; 28.869 ;
|
||||
; 40.655 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 69.841 ; 0.000 ; 28.865 ;
|
||||
; 40.771 ; S[2] ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 28.749 ;
|
||||
; 41.239 ; FS[15] ; nCAS ; C14M ; C14M ; 69.841 ; 0.000 ; 28.281 ;
|
||||
; 41.532 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.988 ;
|
||||
; 41.557 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.963 ;
|
||||
; 41.762 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 69.841 ; 0.000 ; 27.758 ;
|
||||
; 41.766 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 69.841 ; 0.000 ; 27.754 ;
|
||||
; 41.808 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.712 ;
|
||||
; 41.882 ; S[3] ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 27.638 ;
|
||||
; 41.904 ; FS[13] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.616 ;
|
||||
; 42.244 ; CS[0] ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 27.276 ;
|
||||
; 42.246 ; CS[0] ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 27.274 ;
|
||||
; 42.482 ; FS[15] ; nRAS ; C14M ; C14M ; 69.841 ; 0.000 ; 27.038 ;
|
||||
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
|
||||
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
|
||||
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
|
||||
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
|
||||
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
|
||||
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
|
||||
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
|
||||
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
|
||||
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
|
||||
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
|
||||
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
|
||||
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
|
||||
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
|
||||
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
|
||||
; 42.780 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.740 ;
|
||||
; 42.842 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.678 ;
|
||||
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
||||
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
||||
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
||||
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
||||
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
||||
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
||||
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
||||
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
|
||||
; 42.991 ; FS[0] ; nCAS ; C14M ; C14M ; 69.841 ; 0.000 ; 26.529 ;
|
||||
; 42.993 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.527 ;
|
||||
; 42.993 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.527 ;
|
||||
; 42.993 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.527 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'ARCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -16.136 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.000 ; -0.901 ; 2.963 ;
|
||||
; 60.000 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'ram2e_ufm|DRCLK|regout' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; -14.567 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -0.970 ; 4.463 ;
|
||||
; -14.548 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -0.970 ; 4.482 ;
|
||||
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'DRCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -15.980 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.057 ; 2.963 ;
|
||||
; -15.980 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.057 ; 2.963 ;
|
||||
; 60.000 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'ram2e_ufm|ARCLK|regout' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; -14.558 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -0.977 ; 4.465 ;
|
||||
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'C14M' ;
|
||||
+-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+
|
||||
; 2.440 ; UFMBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.479 ;
|
||||
; 3.130 ; UFMD[12] ; UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.169 ;
|
||||
; 3.153 ; UFMD[9] ; UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.192 ;
|
||||
; 3.166 ; UFMD[14] ; UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.205 ;
|
||||
; 3.170 ; UFMD[13] ; UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.209 ;
|
||||
; 3.385 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.424 ;
|
||||
; 3.414 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.453 ;
|
||||
; 3.442 ; CmdEraseMAX ; CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 3.481 ;
|
||||
; 3.443 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.482 ;
|
||||
; 3.451 ; S[2] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 3.490 ;
|
||||
; 3.451 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.490 ;
|
||||
; 3.453 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.492 ;
|
||||
; 3.454 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.493 ;
|
||||
; 3.528 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.567 ;
|
||||
; 3.538 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.577 ;
|
||||
; 3.740 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.779 ;
|
||||
; 3.740 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 3.779 ;
|
||||
; 3.741 ; RTPBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.780 ;
|
||||
; 3.779 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 3.818 ;
|
||||
; 3.810 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.849 ;
|
||||
; 3.827 ; CmdPrgmMAX ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.866 ;
|
||||
; 3.831 ; S[1] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 3.870 ;
|
||||
; 3.833 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.872 ;
|
||||
; 3.839 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.878 ;
|
||||
; 3.843 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.882 ;
|
||||
; 4.011 ; PHI1reg ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.050 ;
|
||||
; 4.210 ; UFMD[8] ; UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.249 ;
|
||||
; 4.278 ; CmdEraseMAX ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 4.317 ;
|
||||
; 4.279 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.318 ;
|
||||
; 5.056 ; RTPBusyReg ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.095 ;
|
||||
; 5.228 ; LEDEN ; LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.267 ;
|
||||
; 5.241 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.280 ;
|
||||
; 5.243 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.282 ;
|
||||
; 5.252 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.291 ;
|
||||
; 5.268 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 5.307 ;
|
||||
; 5.272 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.311 ;
|
||||
; 5.278 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.317 ;
|
||||
; 5.281 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.320 ;
|
||||
; 5.286 ; CmdPrgmMAX ; CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.325 ;
|
||||
; 5.360 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.399 ;
|
||||
; 5.361 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.400 ;
|
||||
; 5.440 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.479 ;
|
||||
; 5.441 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.480 ;
|
||||
; 5.441 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.480 ;
|
||||
; 5.442 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.481 ;
|
||||
; 5.452 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ;
|
||||
; 5.464 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.503 ;
|
||||
; 5.473 ; UFMErase ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.512 ;
|
||||
; 5.474 ; UFMProgram ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.513 ;
|
||||
; 5.475 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.514 ;
|
||||
; 5.476 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.515 ;
|
||||
; 5.476 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.515 ;
|
||||
; 5.478 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 5.517 ;
|
||||
; 5.486 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.525 ;
|
||||
; 5.541 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.580 ;
|
||||
; 5.613 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.652 ;
|
||||
; 5.664 ; RWBank[2] ; RA[10]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.703 ;
|
||||
; 5.753 ; CmdPrgmMAX ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.792 ;
|
||||
; 5.978 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.017 ;
|
||||
; 5.987 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.026 ;
|
||||
; 6.013 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.052 ;
|
||||
; 6.016 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.055 ;
|
||||
; 6.122 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.161 ;
|
||||
; 6.131 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.170 ;
|
||||
; 6.157 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.196 ;
|
||||
; 6.160 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.199 ;
|
||||
; 6.229 ; DRCLKPulse ; DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 6.268 ;
|
||||
; 6.275 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.314 ;
|
||||
; 6.304 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.343 ;
|
||||
; 6.419 ; FS[8] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.458 ;
|
||||
; 6.442 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.481 ;
|
||||
; 6.443 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.482 ;
|
||||
; 6.444 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.483 ;
|
||||
; 6.454 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ;
|
||||
; 6.466 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.505 ;
|
||||
; 6.477 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.516 ;
|
||||
; 6.478 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.517 ;
|
||||
; 6.507 ; RWBank[5] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.546 ;
|
||||
; 6.533 ; CmdBitbangMAX ; DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 6.572 ;
|
||||
; 6.586 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.625 ;
|
||||
; 6.587 ; FS[4] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.626 ;
|
||||
; 6.621 ; FS[13] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.660 ;
|
||||
; 6.651 ; UFMD[11] ; RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.690 ;
|
||||
; 6.724 ; RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.763 ;
|
||||
; 6.730 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.769 ;
|
||||
; 6.731 ; FS[4] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.770 ;
|
||||
; 6.774 ; RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.813 ;
|
||||
; 6.793 ; FS[10] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.832 ;
|
||||
; 6.793 ; FS[10] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.832 ;
|
||||
; 6.793 ; FS[10] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.832 ;
|
||||
; 6.816 ; UFMD[15] ; RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.855 ;
|
||||
; 6.836 ; CS[0] ; CmdRWMaskSet ; C14M ; C14M ; 0.000 ; 0.000 ; 6.875 ;
|
||||
; 6.843 ; CS[0] ; CmdSetRWBankFFLED ; C14M ; C14M ; 0.000 ; 0.000 ; 6.882 ;
|
||||
; 6.874 ; FS[3] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.913 ;
|
||||
; 6.895 ; CmdEraseMAX ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 6.934 ;
|
||||
; 6.940 ; FS[9] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.979 ;
|
||||
; 6.940 ; FS[9] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.979 ;
|
||||
; 6.940 ; FS[9] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.979 ;
|
||||
; 6.998 ; FS[2] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.037 ;
|
||||
; 6.998 ; FS[2] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.037 ;
|
||||
+-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'C14M' ;
|
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; 3.133 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.172 ;
|
||||
; 3.136 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.175 ;
|
||||
; 3.429 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.468 ;
|
||||
; 3.436 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.475 ;
|
||||
; 3.453 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.492 ;
|
||||
; 3.483 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.522 ;
|
||||
; 3.527 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.566 ;
|
||||
; 3.753 ; RWBank[7] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.792 ;
|
||||
; 3.765 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 3.804 ;
|
||||
; 3.767 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.806 ;
|
||||
; 3.803 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.842 ;
|
||||
; 3.833 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.872 ;
|
||||
; 3.879 ; RC[2] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.918 ;
|
||||
; 3.883 ; RC[2] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.922 ;
|
||||
; 3.885 ; RC[2] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.924 ;
|
||||
; 4.002 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.041 ;
|
||||
; 4.318 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.357 ;
|
||||
; 4.629 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 4.668 ;
|
||||
; 4.854 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.893 ;
|
||||
; 4.855 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.894 ;
|
||||
; 4.859 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.898 ;
|
||||
; 4.879 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.918 ;
|
||||
; 5.050 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.089 ;
|
||||
; 5.054 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.093 ;
|
||||
; 5.156 ; S[2] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.195 ;
|
||||
; 5.163 ; S[2] ; VOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.202 ;
|
||||
; 5.217 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ;
|
||||
; 5.217 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ;
|
||||
; 5.228 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 5.267 ;
|
||||
; 5.229 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 5.268 ;
|
||||
; 5.233 ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.272 ;
|
||||
; 5.253 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.292 ;
|
||||
; 5.266 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.305 ;
|
||||
; 5.272 ; RWBank[1] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.311 ;
|
||||
; 5.281 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.320 ;
|
||||
; 5.290 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.329 ;
|
||||
; 5.301 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.340 ;
|
||||
; 5.312 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 5.351 ;
|
||||
; 5.313 ; RC[0] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.352 ;
|
||||
; 5.315 ; RC[0] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.354 ;
|
||||
; 5.316 ; RC[0] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.355 ;
|
||||
; 5.320 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.359 ;
|
||||
; 5.329 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.368 ;
|
||||
; 5.351 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.390 ;
|
||||
; 5.354 ; S[3] ; VOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.393 ;
|
||||
; 5.355 ; S[3] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.394 ;
|
||||
; 5.429 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.468 ;
|
||||
; 5.429 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.468 ;
|
||||
; 5.443 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.482 ;
|
||||
; 5.443 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.482 ;
|
||||
; 5.449 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.488 ;
|
||||
; 5.452 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ;
|
||||
; 5.452 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ;
|
||||
; 5.453 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.492 ;
|
||||
; 5.453 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.492 ;
|
||||
; 5.460 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.499 ;
|
||||
; 5.464 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.503 ;
|
||||
; 5.466 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.505 ;
|
||||
; 5.552 ; RC[1] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.591 ;
|
||||
; 5.559 ; RC[1] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.598 ;
|
||||
; 5.561 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.600 ;
|
||||
; 5.563 ; RC[1] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.602 ;
|
||||
; 5.564 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.603 ;
|
||||
; 5.565 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 5.604 ;
|
||||
; 5.565 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.604 ;
|
||||
; 5.570 ; S[1] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.609 ;
|
||||
; 5.579 ; S[1] ; VOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.618 ;
|
||||
; 5.613 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.652 ;
|
||||
; 5.884 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.923 ;
|
||||
; 5.988 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.027 ;
|
||||
; 6.001 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.040 ;
|
||||
; 6.016 ; S[0] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.055 ;
|
||||
; 6.132 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.171 ;
|
||||
; 6.145 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.184 ;
|
||||
; 6.276 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.315 ;
|
||||
; 6.315 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.354 ;
|
||||
; 6.319 ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.358 ;
|
||||
; 6.338 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.377 ;
|
||||
; 6.365 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.404 ;
|
||||
; 6.445 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.484 ;
|
||||
; 6.451 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.490 ;
|
||||
; 6.454 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ;
|
||||
; 6.454 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ;
|
||||
; 6.455 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.494 ;
|
||||
; 6.462 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.501 ;
|
||||
; 6.466 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.505 ;
|
||||
; 6.516 ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.555 ;
|
||||
; 6.536 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.575 ;
|
||||
; 6.567 ; S[3] ; CKE ; C14M ; C14M ; 0.000 ; 0.000 ; 6.606 ;
|
||||
; 6.598 ; FS[4] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.637 ;
|
||||
; 6.598 ; FS[13] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.637 ;
|
||||
; 6.610 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.649 ;
|
||||
; 6.627 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.666 ;
|
||||
; 6.628 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.667 ;
|
||||
; 6.710 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.749 ;
|
||||
; 6.735 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.774 ;
|
||||
; 6.742 ; FS[4] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.781 ;
|
||||
; 6.754 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.793 ;
|
||||
; 6.771 ; RWBank[4] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.810 ;
|
||||
; 6.787 ; S[0] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.826 ;
|
||||
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; Setup Transfers ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; C14M ; 1607 ; 0 ; 64 ; 0 ;
|
||||
; DRCLK ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; DRCLK ; 2 ; 0 ; 0 ; 0 ;
|
||||
; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
+---------------------------------------------------------------------------------------------+
|
||||
; Setup Transfers ;
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
; C14M ; C14M ; 1625 ; 0 ; 16 ; 0 ;
|
||||
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ram2e_ufm|DRCLK|regout ; 2 ; 0 ; 0 ; 0 ;
|
||||
; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; Hold Transfers ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; C14M ; 1607 ; 0 ; 64 ; 0 ;
|
||||
; DRCLK ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; DRCLK ; 2 ; 0 ; 0 ; 0 ;
|
||||
; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
+---------------------------------------------------------------------------------------------+
|
||||
; Hold Transfers ;
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
; C14M ; C14M ; 1625 ; 0 ; 16 ; 0 ;
|
||||
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ram2e_ufm|DRCLK|regout ; 2 ; 0 ; 0 ; 0 ;
|
||||
; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||||
|
||||
|
||||
|
|
@ -473,22 +473,22 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
+---------------------------------+-------+------+
|
||||
; Illegal Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Input Ports ; 29 ; 29 ;
|
||||
; Unconstrained Input Port Paths ; 169 ; 169 ;
|
||||
; Unconstrained Output Ports ; 48 ; 48 ;
|
||||
; Unconstrained Output Port Paths ; 67 ; 67 ;
|
||||
; Unconstrained Input Ports ; 28 ; 28 ;
|
||||
; Unconstrained Input Port Paths ; 176 ; 176 ;
|
||||
; Unconstrained Output Ports ; 47 ; 47 ;
|
||||
; Unconstrained Output Port Paths ; 76 ; 76 ;
|
||||
+---------------------------------+-------+------+
|
||||
|
||||
|
||||
+-------------------------------------+
|
||||
; Clock Status Summary ;
|
||||
+--------+-------+------+-------------+
|
||||
; Target ; Clock ; Type ; Status ;
|
||||
+--------+-------+------+-------------+
|
||||
; ARCLK ; ARCLK ; Base ; Constrained ;
|
||||
; C14M ; C14M ; Base ; Constrained ;
|
||||
; DRCLK ; DRCLK ; Base ; Constrained ;
|
||||
+--------+-------+------+-------------+
|
||||
+----------------------------------------------------------------------+
|
||||
; Clock Status Summary ;
|
||||
+------------------------+------------------------+------+-------------+
|
||||
; Target ; Clock ; Type ; Status ;
|
||||
+------------------------+------------------------+------+-------------+
|
||||
; C14M ; C14M ; Base ; Constrained ;
|
||||
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; Base ; Constrained ;
|
||||
; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; Base ; Constrained ;
|
||||
+------------------------+------------------------+------+-------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------+
|
||||
|
|
@ -524,7 +524,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
; nC07X ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nEN80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nWE80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
|
@ -535,7 +534,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
+-------------+---------------------------------------------------------------------------------------+
|
||||
; BA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; BA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; CKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; CKEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
|
|
@ -547,18 +546,18 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
|
|
@ -575,11 +574,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRWEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nVOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
|
||||
|
|
@ -617,7 +615,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
; nC07X ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nEN80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nWE80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
|
|
@ -628,7 +625,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
+-------------+---------------------------------------------------------------------------------------+
|
||||
; BA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; BA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; CKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; CKEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
|
|
@ -640,18 +637,18 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RAout[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
|
|
@ -668,11 +665,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRWEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nVOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
|
||||
|
|
@ -682,8 +678,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
+--------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Timing Analyzer
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:34:43 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Thu Dec 28 23:09:49 2023
|
||||
Info: Command: quartus_sta RAM2E-MAXV -c RAM2E
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
|
|
@ -695,37 +691,37 @@ Info (332104): Reading SDC File: '../RAM2E.sdc'
|
|||
Info (332104): Reading SDC File: '../RAM2E-MAX.sdc'
|
||||
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
||||
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ARCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: DRCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Critical Warning (332148): Timing requirements not met
|
||||
Info (332146): Worst-case setup slack is -24.019
|
||||
Info (332146): Worst-case setup slack is -25.451
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= =================== =====================
|
||||
Info (332119): -24.019 -24.019 DRCLK
|
||||
Info (332119): -23.863 -23.863 ARCLK
|
||||
Info (332119): -15.767 -176.992 C14M
|
||||
Info (332146): Worst-case hold slack is -16.136
|
||||
Info (332119): -25.451 -25.451 ram2e_ufm|DRCLK|regout
|
||||
Info (332119): -25.441 -25.441 ram2e_ufm|ARCLK|regout
|
||||
Info (332119): -20.081 -208.886 C14M
|
||||
Info (332146): Worst-case hold slack is -14.567
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= =================== =====================
|
||||
Info (332119): -16.136 -16.136 ARCLK
|
||||
Info (332119): -15.980 -15.980 DRCLK
|
||||
Info (332119): 2.440 0.000 C14M
|
||||
Info (332119): -14.567 -14.567 ram2e_ufm|DRCLK|regout
|
||||
Info (332119): -14.558 -14.558 ram2e_ufm|ARCLK|regout
|
||||
Info (332119): 3.133 0.000 C14M
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Info (332146): Worst-case minimum pulse width slack is 34.581
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= =================== =====================
|
||||
Info (332119): 34.581 0.000 C14M
|
||||
Info (332119): 70.000 0.000 ARCLK
|
||||
Info (332119): 70.000 0.000 DRCLK
|
||||
Info (332119): 70.000 0.000 ram2e_ufm|ARCLK|regout
|
||||
Info (332119): 70.000 0.000 ram2e_ufm|DRCLK|regout
|
||||
Info (332001): The selected device family is not supported by the report_metastability command.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ARCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: DRCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
|
||||
Info: Peak virtual memory: 13092 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:46 2023
|
||||
Info: Peak virtual memory: 13067 megabytes
|
||||
Info: Processing ended: Thu Dec 28 23:09:52 2023
|
||||
Info: Elapsed time: 00:00:03
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
|
||||
|
|
|
|||
|
|
@ -2,39 +2,39 @@
|
|||
Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Setup 'DRCLK'
|
||||
Slack : -24.019
|
||||
TNS : -24.019
|
||||
Type : Setup 'ram2e_ufm|DRCLK|regout'
|
||||
Slack : -25.451
|
||||
TNS : -25.451
|
||||
|
||||
Type : Setup 'ARCLK'
|
||||
Slack : -23.863
|
||||
TNS : -23.863
|
||||
Type : Setup 'ram2e_ufm|ARCLK|regout'
|
||||
Slack : -25.441
|
||||
TNS : -25.441
|
||||
|
||||
Type : Setup 'C14M'
|
||||
Slack : -15.767
|
||||
TNS : -176.992
|
||||
Slack : -20.081
|
||||
TNS : -208.886
|
||||
|
||||
Type : Hold 'ARCLK'
|
||||
Slack : -16.136
|
||||
TNS : -16.136
|
||||
Type : Hold 'ram2e_ufm|DRCLK|regout'
|
||||
Slack : -14.567
|
||||
TNS : -14.567
|
||||
|
||||
Type : Hold 'DRCLK'
|
||||
Slack : -15.980
|
||||
TNS : -15.980
|
||||
Type : Hold 'ram2e_ufm|ARCLK|regout'
|
||||
Slack : -14.558
|
||||
TNS : -14.558
|
||||
|
||||
Type : Hold 'C14M'
|
||||
Slack : 2.440
|
||||
Slack : 3.133
|
||||
TNS : 0.000
|
||||
|
||||
Type : Minimum Pulse Width 'C14M'
|
||||
Slack : 34.581
|
||||
TNS : 0.000
|
||||
|
||||
Type : Minimum Pulse Width 'ARCLK'
|
||||
Type : Minimum Pulse Width 'ram2e_ufm|ARCLK|regout'
|
||||
Slack : 70.000
|
||||
TNS : 0.000
|
||||
|
||||
Type : Minimum Pulse Width 'DRCLK'
|
||||
Type : Minimum Pulse Width 'ram2e_ufm|DRCLK|regout'
|
||||
Slack : 70.000
|
||||
TNS : 0.000
|
||||
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ LOCATE COMP "nWE" SITE "29" ;
|
|||
LOCATE COMP "nWE80" SITE "83" ;
|
||||
LOCATE COMP "BA[0]" SITE "58" ;
|
||||
LOCATE COMP "BA[1]" SITE "60" ;
|
||||
LOCATE COMP "CKE" SITE "53" ;
|
||||
LOCATE COMP "CKEout" SITE "53" ;
|
||||
LOCATE COMP "DQMH" SITE "49" ;
|
||||
LOCATE COMP "DQML" SITE "48" ;
|
||||
LOCATE COMP "Dout[0]" SITE "30" ;
|
||||
|
|
@ -35,18 +35,18 @@ LOCATE COMP "Dout[5]" SITE "21" ;
|
|||
LOCATE COMP "Dout[6]" SITE "31" ;
|
||||
LOCATE COMP "Dout[7]" SITE "32" ;
|
||||
LOCATE COMP "LED" SITE "35" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "RA[1]" SITE "68" ;
|
||||
LOCATE COMP "RA[2]" SITE "70" ;
|
||||
LOCATE COMP "RA[3]" SITE "74" ;
|
||||
LOCATE COMP "RA[4]" SITE "75" ;
|
||||
LOCATE COMP "RA[5]" SITE "71" ;
|
||||
LOCATE COMP "RA[7]" SITE "67" ;
|
||||
LOCATE COMP "RA[6]" SITE "69" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[9]" SITE "63" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RAout[0]" SITE "66" ;
|
||||
LOCATE COMP "RAout[1]" SITE "68" ;
|
||||
LOCATE COMP "RAout[2]" SITE "70" ;
|
||||
LOCATE COMP "RAout[3]" SITE "74" ;
|
||||
LOCATE COMP "RAout[4]" SITE "75" ;
|
||||
LOCATE COMP "RAout[5]" SITE "71" ;
|
||||
LOCATE COMP "RAout[7]" SITE "67" ;
|
||||
LOCATE COMP "RAout[6]" SITE "69" ;
|
||||
LOCATE COMP "RAout[8]" SITE "65" ;
|
||||
LOCATE COMP "RAout[9]" SITE "63" ;
|
||||
LOCATE COMP "RAout[10]" SITE "64" ;
|
||||
LOCATE COMP "RAout[11]" SITE "59" ;
|
||||
LOCATE COMP "Vout[0]" SITE "18" ;
|
||||
LOCATE COMP "Vout[1]" SITE "15" ;
|
||||
LOCATE COMP "Vout[2]" SITE "17" ;
|
||||
|
|
@ -55,11 +55,11 @@ LOCATE COMP "Vout[4]" SITE "19" ;
|
|||
LOCATE COMP "Vout[5]" SITE "16" ;
|
||||
LOCATE COMP "Vout[6]" SITE "14" ;
|
||||
LOCATE COMP "Vout[7]" SITE "12" ;
|
||||
LOCATE COMP "nCAS" SITE "52" ;
|
||||
LOCATE COMP "nCS" SITE "57" ;
|
||||
LOCATE COMP "nCASout" SITE "52" ;
|
||||
LOCATE COMP "nCSout" SITE "57" ;
|
||||
LOCATE COMP "nDOE" SITE "20" ;
|
||||
LOCATE COMP "nRAS" SITE "54" ;
|
||||
LOCATE COMP "nRWE" SITE "51" ;
|
||||
LOCATE COMP "nRASout" SITE "54" ;
|
||||
LOCATE COMP "nRWEout" SITE "51" ;
|
||||
LOCATE COMP "nVOE" SITE "10" ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
|
|
@ -93,30 +93,30 @@ IOBUF PORT "nWE" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
|||
IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
|
||||
IOBUF PORT "BA[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "BA[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "CKE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "CKEout" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "DQMH" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "DQML" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
|
||||
IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
|
||||
IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
|
||||
IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
|
||||
IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
|
||||
IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
|
||||
IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
|
||||
IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ;
|
||||
IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RA[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RA[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RA[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RA[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RA[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RA[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RA[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RA[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RA[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RA[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RA[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RA[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RAout[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RAout[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RAout[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RAout[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RAout[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RAout[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RAout[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RAout[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RAout[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RAout[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RAout[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RAout[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "Vout[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "Vout[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "Vout[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
|
|
@ -125,11 +125,11 @@ IOBUF PORT "Vout[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
|||
IOBUF PORT "Vout[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "Vout[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "Vout[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "nCAS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "nCS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "nCASout" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "nCSout" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "nDOE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "nRAS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "nRWE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "nRASout" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "nRWEout" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "nVOE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ;
|
||||
IOBUF PORT "RD[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 CLAMP=ON ;
|
||||
IOBUF PORT "RD[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 CLAMP=ON ;
|
||||
|
|
@ -142,7 +142,7 @@ IOBUF PORT "RD[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 CLAMP=ON ;
|
|||
OUTPUT PORT "LED" LOAD 100.000000 pF ;
|
||||
OUTPUT PORT "BA[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "BA[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "CKE" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "CKEout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "DQMH" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "DQML" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
|
||||
|
|
@ -153,18 +153,18 @@ OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
|
|||
OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "RA[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[2]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[3]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[4]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[5]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[6]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[7]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[8]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[9]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[10]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[11]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[2]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[3]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[4]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[5]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[6]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[7]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[8]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[9]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[10]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RAout[11]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ;
|
||||
|
|
@ -173,11 +173,11 @@ OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ;
|
|||
OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "nCAS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nCS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nCASout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nCSout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nDOE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRAS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRWE" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRASout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRWEout" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nVOE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;
|
||||
|
|
|
|||
|
|
@ -1,831 +0,0 @@
|
|||
module RAM2E(C14M, PHI1, LED,
|
||||
nWE, nWE80, nEN80, nC07X,
|
||||
Ain, Din, Dout, nDOE, Vout, nVOE,
|
||||
CKE, nCS, nRAS, nCAS, nRWE,
|
||||
BA, RA, RD, DQML, DQMH);
|
||||
|
||||
/* Clocks */
|
||||
input C14M, PHI1;
|
||||
|
||||
/* Control inputs */
|
||||
input nWE, nWE80, nEN80, nC07X;
|
||||
|
||||
/* Delay for EN80 signal */
|
||||
//output DelayOut = 1'b0;
|
||||
//input DelayIn;
|
||||
wire EN80 = !nEN80;
|
||||
|
||||
/* Activity LED */
|
||||
reg LEDEN = 0;
|
||||
output LED;
|
||||
assign LED = !(!nEN80 && LEDEN);
|
||||
|
||||
/* Address Bus */
|
||||
input [7:0] Ain; // Multiplexed DRAM address input
|
||||
|
||||
/* 6502 Data Bus */
|
||||
input [7:0] Din; // 6502 data bus inputs
|
||||
reg DOEEN = 0; // 6502 data bus output enable from state machine
|
||||
output nDOE;
|
||||
assign nDOE = !(EN80 && nWE && DOEEN); // 6502 data bus output enable
|
||||
output reg [7:0] Dout; // 6502 data Bus output
|
||||
|
||||
/* Video Data Bus */
|
||||
output nVOE;
|
||||
assign nVOE = !(!PHI1); /// Video data bus output enable
|
||||
output reg [7:0] Vout; // Video data bus
|
||||
|
||||
/* SDRAM */
|
||||
output reg CKE = 0;
|
||||
output reg nCS = 1, nRAS = 1, nCAS = 1, nRWE = 1;
|
||||
output reg [1:0] BA;
|
||||
output reg [11:0] RA;
|
||||
output reg DQML = 1, DQMH = 1;
|
||||
wire RDOE = EN80 && !nWE80;
|
||||
inout [7:0] RD;
|
||||
assign RD[7:0] = RDOE ? Din[7:0] : 8'bZ;
|
||||
|
||||
/* RAMWorks Bank Register and Capacity Mask */
|
||||
reg [7:0] RWBank = 0; // RAMWorks bank register
|
||||
reg [7:0] RWMask = 0; // RAMWorks bank reg. capacity mask
|
||||
reg RWSel = 0; // RAMWorks bank register select
|
||||
reg CmdRWMaskSet = 0; // RAMWorks Mask register set flag
|
||||
// Causes RWBank to be zeroed next RWSel access
|
||||
//reg CmdSetRWBankFFMAX = 0;
|
||||
//reg CmdSetRWBankFFSPI = 0;
|
||||
reg CmdSetRWBankFFMXO2 = 0;
|
||||
reg CmdSetRWBankFFLED = 0;
|
||||
reg CmdLEDSet = 0;
|
||||
reg CmdLEDGet = 0;
|
||||
|
||||
/* Command Sequence Detector */
|
||||
reg [2:0] CS = 0; // Command sequence state
|
||||
reg [2:0] CmdTout = 0; // Command sequence timeout
|
||||
|
||||
/* UFM Interface */
|
||||
reg wb_rst;
|
||||
reg wb_cyc_stb;
|
||||
reg wb_req;
|
||||
reg wb_we;
|
||||
reg [7:0] wb_adr;
|
||||
reg [7:0] wb_dati;
|
||||
wire wb_ack;
|
||||
wire [7:0] wb_dato;
|
||||
wire ufm_irq;
|
||||
REFB ufmefb(
|
||||
.wb_clk_i(C14M),
|
||||
.wb_rst_i(wb_rst),
|
||||
.wb_cyc_i(wb_cyc_stb),
|
||||
.wb_stb_i(wb_cyc_stb),
|
||||
.wb_we_i(wb_we),
|
||||
.wb_adr_i(wb_adr),
|
||||
.wb_dat_i(wb_dati),
|
||||
.wb_dat_o(wb_dato),
|
||||
.wb_ack_o(wb_ack),
|
||||
.wbc_ufm_irq(ufm_irq));
|
||||
|
||||
/* UFM State and User Command Triggers */
|
||||
//reg CmdBitbangMAX = 0; // Set by user command. Loads UFM outputs next RWSel
|
||||
//reg CmdBitbangSPI = 0;
|
||||
reg CmdBitbangMXO2 = 0;
|
||||
reg CmdExecMXO2 = 0;
|
||||
//reg CmdPrgmMAX = 0; // Set by user command. Programs UFM
|
||||
//reg CmdEraseMAX = 0; // Set by user command. Erases UFM
|
||||
|
||||
/* State Counters */
|
||||
reg PHI1reg = 0; // Saved PHI1 at last rising clock edge
|
||||
reg Ready = 0; // 1 if done with init sequence (S0) and enter S1-S15
|
||||
reg [15:0] FS = 0; // Fast state counter
|
||||
reg [3:0] S = 0; // IIe State counter
|
||||
|
||||
/* State Counters */
|
||||
always @(posedge C14M) begin
|
||||
// Increment fast state counter
|
||||
FS <= FS+16'h0001;
|
||||
// Synchronize Apple state counter to S1 when just entering PHI1
|
||||
PHI1reg <= PHI1; // Save old PHI1
|
||||
S <= (PHI1 && !PHI1reg && Ready) ? 4'h1 :
|
||||
S==4'h0 ? 4'h0 :
|
||||
S==4'hF ? 4'hF : S+4'h1;
|
||||
end
|
||||
|
||||
/* UFM Control */
|
||||
always @(posedge C14M) begin
|
||||
if (S==4'h0) begin
|
||||
if (FS[15:14]==2'b00) wb_rst <= 1'b1;
|
||||
else if (FS[15:14]==2'b01) wb_rst <= 1'b0;
|
||||
else if (FS[15:14]==2'b10) begin
|
||||
wb_rst <= 1'b0;
|
||||
if (wb_ack || (FS[7:0]==0)) wb_cyc_stb <= 0;
|
||||
else if ((FS[7:0]==1) && wb_req) wb_cyc_stb <= 1;
|
||||
case (FS[13:8])
|
||||
0: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_req <= 1;
|
||||
end 1: begin // Enable configuration interface - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h74;
|
||||
wb_req <= 1;
|
||||
end 2: begin // Enable configuration interface - operand 1/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h08;
|
||||
wb_req <= 1;
|
||||
end 3: begin // Enable configuration interface - operand 2/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 4: begin // Enable configuration interface - operand 3/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 5: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
|
||||
end 6: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_req <= 1;
|
||||
end 7: begin // Poll status register - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h3C;
|
||||
wb_req <= 1;
|
||||
end 8: begin // Poll status register - operand 1/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 9: begin // Poll status register - operand 2/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 10: begin // Poll status register - operand 3/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 11, 12, 13, 14: begin // Read status register 1-4
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h73;
|
||||
wb_dati[7:0] <= 8'h3C;
|
||||
wb_req <= 1;
|
||||
end 15: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
|
||||
end 16: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_req <= 1;
|
||||
end 17: begin // Set UFM address - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'hB4;
|
||||
wb_req <= 1;
|
||||
end 18: begin // Set UFM address - operand 1/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 19: begin // Set UFM address - operand 2/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 20: begin // Set UFM address - operand 3/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 21: begin // Set UFM address - data 1/4
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h40;
|
||||
wb_req <= 1;
|
||||
end 22: begin // Set UFM address - data 2/4
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 23: begin // Set UFM address - data 3/4
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 24: begin // Set UFM address - data 4/4
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 190;
|
||||
wb_req <= 1;
|
||||
end 25: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
|
||||
end 26: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_req <= 1;
|
||||
end 27: begin // Read UFM page - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'hCA;
|
||||
wb_req <= 1;
|
||||
end 28: begin // Read UFM page - operand 1/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h10;
|
||||
wb_req <= 1;
|
||||
end 29: begin // Read UFM page - operand 2/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 30: begin // Read UFM page - operand 3/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h01;
|
||||
wb_req <= 1;
|
||||
end 31: begin // Read UFM page - data 0
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h73;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
if (wb_ack) RWMask[7:0] <= wb_dato[7:0];
|
||||
end 32: begin // Read UFM page - data 1
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h73;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
if (wb_ack) LEDEN <= wb_dato[0];
|
||||
end 33, 34,
|
||||
35, 36, 37, 38,
|
||||
39, 40, 41, 42,
|
||||
43, 44, 45, 46: begin // Read UFM page - data 2-15
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h73;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 47: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
|
||||
end 48: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_req <= 1;
|
||||
end 49: begin // Disable configuration interface - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h26;
|
||||
wb_req <= 1;
|
||||
end 50: begin // Disable configuration interface - operand 1/2
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 51: begin // Disable configuration interface - operand 2/2
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 52: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
|
||||
end 53: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_req <= 1;
|
||||
end 54: begin // Bypass - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'hFF;
|
||||
wb_req <= 1;
|
||||
end 55: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end default: begin
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 0;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
wb_rst <= 1'b0;
|
||||
wb_cyc_stb <= 1'b0;
|
||||
wb_req <= 1'b0;
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h00;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
end
|
||||
end else begin
|
||||
// UFM bitbang control
|
||||
wb_rst <= 1'b0;
|
||||
wb_req <= 1'b0;
|
||||
|
||||
if (RWSel && S==4'hC) begin
|
||||
// LED control
|
||||
if (CmdLEDSet) LEDEN <= Din[0];
|
||||
|
||||
// Set capacity mask
|
||||
if (CmdRWMaskSet) RWMask[7:0] <= {Din[7], ~Din[6:0]};
|
||||
|
||||
// Set EFB address
|
||||
if (CmdBitbangMXO2) begin
|
||||
wb_adr[7:0] <= Din[7:0];
|
||||
wb_dati[7:0] <= wb_adr[7:0];
|
||||
end
|
||||
|
||||
// Excecute EFB R/W cycle
|
||||
if (CmdExecMXO2) begin
|
||||
wb_we <= Din[0];
|
||||
wb_cyc_stb <= 1;
|
||||
end else if (wb_ack) wb_cyc_stb <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
/* SDRAM Control */
|
||||
always @(posedge C14M) begin
|
||||
if (S==4'h0) begin
|
||||
// SDRAM initialization
|
||||
if (FS[15:0]==16'hFFC0) begin
|
||||
// Precharge All
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b0;
|
||||
RA[10] <= 1'b1; // "all"
|
||||
end else if (FS[15:4]==16'hFFD && FS[0]==1'b0) begin // Repeat 8x
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA[10] <= 1'b0;
|
||||
end else if (FS[15:0]==16'hFFE8) begin
|
||||
// Set Mode Register
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b0;
|
||||
RA[10] <= 1'b0; // Reserved in mode register
|
||||
end else if (FS[15:4]==12'hFFF && FS[0]==1'b0) begin // Repeat 8x
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA[10] <= 1'b0;
|
||||
end else begin // Otherwise send no-op
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA[10] <= 1'b0;
|
||||
end
|
||||
// Enable SDRAM clock after 65,280 cycles (~4.56ms)
|
||||
CKE <= FS[15:8] == 8'hFF;
|
||||
|
||||
// Mode register contents
|
||||
BA[1:0] <= 2'b00; // Reserved
|
||||
RA[11] <= 1'b0; // Reserved
|
||||
// RA[10] set above ^
|
||||
RA[9] <= 1'b1; // "1" for single write mode
|
||||
RA[8] <= 1'b0; // Reserved
|
||||
RA[7] <= 1'b0; // "0" for not test mode
|
||||
RA[6:4] <= 3'b010; // "2" for CAS latency 2
|
||||
RA[3] <= 1'b0; // "0" for sequential burst (not used)
|
||||
RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
|
||||
// Begin normal operation after 128k init cycles (~9.15ms)
|
||||
if (FS == 16'hFFFF) Ready <= 1'b1;
|
||||
end else if (S==4'h1) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h2) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// Activate
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// SDRAM bank 0, high-order row address is 0
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
// Row address is as previously latched
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h3) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// Read
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// SDRAM bank 0, RA[11,9:8] don't care
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11] <= 1'b0;
|
||||
RA[10] <= 1'b1; // (A10 set to auto-precharge)
|
||||
RA[9] <= 1'b0;
|
||||
RA[8] <= 1'b0;
|
||||
// Latch column address for read command
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Read low byte (high byte is +4MB in ramworks)
|
||||
DQML <= 1'b0;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h4) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h5) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h6) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
if (FS[5:4]==0) begin
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
end else begin
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
end
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h7) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
// Latch row address for activate command
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h8) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= EN80;
|
||||
|
||||
// Activate if '245 output enabled
|
||||
nCS <= nEN80;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// SDRAM bank, RA[11:8] determine by RamWorks bank
|
||||
BA[1:0] <= RWBank[5:4];
|
||||
RA[11:8] <= RWBank[3:0];
|
||||
// Row address is as previously latched
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h9) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= EN80;
|
||||
|
||||
// Read/Write if '245 output enabled
|
||||
nCS <= nEN80;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= nWE80;
|
||||
|
||||
// SDRAM bank still determined by RamWorks, RA[11,9:8] don't care
|
||||
BA[1:0] <= RWBank[5:4];
|
||||
RA[11] <= 1'b0;
|
||||
RA[10] <= 1'b1; // (A10 set to auto-precharge)
|
||||
RA[9] <= 1'b0;
|
||||
RA[8] <= RWBank[7];
|
||||
// Latch column address for R/W command
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Latch RAMWorks low nybble write select using old row address
|
||||
RWSel <= RA[0] && !RA[3] && !nWE && !nC07X;
|
||||
|
||||
// Mask according to RAMWorks bank (high byte is +4MB)
|
||||
DQML <= RWBank[6];
|
||||
DQMH <= !RWBank[6];
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'hA) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= EN80;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'hB) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
end else if (S==4'hC) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
|
||||
// RAMWorks Bank Register Select
|
||||
if (RWSel) begin
|
||||
// Latch RAMWorks bank if accessed
|
||||
if (CmdSetRWBankFFLED ||
|
||||
//CmdSetRWBankFFMAX ||
|
||||
//CmdSetRWBankFFSPI ||
|
||||
CmdSetRWBankFFMXO2 ||
|
||||
(CmdLEDGet && LEDEN)) RWBank <= 8'hFF;
|
||||
else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]};
|
||||
|
||||
// Recognize command sequence and advance CS state
|
||||
if ((CS==3'h0 && Din[7:0]==8'hFF) ||
|
||||
(CS==3'h1 && Din[7:0]==8'h00) ||
|
||||
(CS==3'h2 && Din[7:0]==8'h55) ||
|
||||
(CS==3'h3 && Din[7:0]==8'hAA) ||
|
||||
(CS==3'h4 && Din[7:0]==8'hC1) ||
|
||||
(CS==3'h5 && Din[7:0]==8'hAD) ||
|
||||
CS==3'h6 || CS==3'h7) CS <= CS+3'h1;
|
||||
else CS <= 0; // Back to beginning if it's not right
|
||||
|
||||
if (CS==3'h6) begin // Recognize and submit command in CS6
|
||||
//CmdSetRWBankFFMAX <= Din[7:0]==8'hFF;
|
||||
//CmdSetRWBankFFSPI <= Din[7:0]==8'hFE;
|
||||
CmdSetRWBankFFMXO2 <= Din[7:0]==8'hFD;
|
||||
CmdSetRWBankFFLED <= Din[7:0]==8'hF0;
|
||||
|
||||
CmdRWMaskSet <= Din[7:0]==8'hE0;
|
||||
CmdLEDSet <= Din[7:0]==8'hE2;
|
||||
CmdLEDGet <= Din[7:0]==8'hE3;
|
||||
|
||||
//CmdBitbangMAX <= Din[7:0]==8'hEA;
|
||||
//CmdBitbangSPI <= Din[7:0]==8'hEB;
|
||||
CmdBitbangMXO2 <= Din[7:0]==8'hEC;
|
||||
CmdExecMXO2 <= Din[7:0]==8'hED;
|
||||
|
||||
//if (Din[7:0]==8'hEE) CmdEraseMAX <= 1;
|
||||
//if (Din[7:0]==8'hEF) CmdPrgmMAX <= 1;
|
||||
end else begin // Reset command triggers
|
||||
//CmdSetRWBankFFMAX <= 0;
|
||||
//CmdSetRWBankFFSPI <= 0;
|
||||
CmdSetRWBankFFMXO2 <= 0;
|
||||
CmdSetRWBankFFLED <= 0;
|
||||
CmdRWMaskSet <= 0;
|
||||
CmdLEDSet <= 0;
|
||||
CmdLEDGet <= 0;
|
||||
//CmdBitbangMAX <= 0;
|
||||
//CmdBitbangSPI <= 0;
|
||||
CmdBitbangMXO2 <= 0;
|
||||
CmdExecMXO2 <= 0;
|
||||
end
|
||||
|
||||
CmdTout <= 0; // Reset command timeout if RWSel accessed
|
||||
end else begin
|
||||
CmdTout <= CmdTout+3'h1; // Increment command timeout
|
||||
// If command sequence times out, reset sequence state
|
||||
if (CmdTout==3'h7) CS <= 0;
|
||||
end
|
||||
end else if (S==4'hD) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
end else if (S==4'hE) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
// Latch row address for next video read
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
end else if (S==4'hF) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
// Latch row address for next video read
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
end
|
||||
end
|
||||
always @(negedge C14M) begin
|
||||
// Latch video and read data outputs
|
||||
if (S==4'h6) Vout[7:0] <= RD[7:0];
|
||||
if (S==4'hC) Dout[7:0] <= RD[7:0];
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,2 +1,2 @@
|
|||
create_clock ARCLK -period 200ns
|
||||
create_clock DRCLK -period 200ns
|
||||
create_clock [get_nets RAM2E_UFM:ram2e_ufm\|ARCLK] -period 200ns
|
||||
create_clock [get_nets RAM2E_UFM:ram2e_ufm\|DRCLK] -period 200ns
|
||||
|
|
|
|||
689
CPLD/RAM2E-MAX.v
689
CPLD/RAM2E-MAX.v
|
|
@ -1,689 +0,0 @@
|
|||
module RAM2E(C14M, PHI1, LED,
|
||||
nWE, nWE80, nEN80, nC07X,
|
||||
Ain, Din, Dout, nDOE, Vout, nVOE,
|
||||
CKE, nCS, nRAS, nCAS, nRWE,
|
||||
BA, RA, RD, DQML, DQMH);
|
||||
|
||||
/* Clocks */
|
||||
input C14M, PHI1;
|
||||
|
||||
/* Control inputs */
|
||||
input nWE, nWE80, nEN80, nC07X;
|
||||
|
||||
/* Delay for EN80 signal */
|
||||
//output DelayOut = 1'b0;
|
||||
//input DelayIn;
|
||||
wire EN80 = !nEN80;
|
||||
|
||||
/* Activity LED */
|
||||
reg LEDEN = 0;
|
||||
output LED;
|
||||
assign LED = !(!nEN80 && LEDEN);
|
||||
|
||||
/* Address Bus */
|
||||
input [7:0] Ain; // Multiplexed DRAM address input
|
||||
|
||||
/* 6502 Data Bus */
|
||||
input [7:0] Din; // 6502 data bus inputs
|
||||
reg DOEEN = 0; // 6502 data bus output enable from state machine
|
||||
output nDOE;
|
||||
assign nDOE = !(EN80 && nWE && DOEEN); // 6502 data bus output enable
|
||||
output reg [7:0] Dout; // 6502 data Bus output
|
||||
|
||||
/* Video Data Bus */
|
||||
output nVOE;
|
||||
assign nVOE = !(!PHI1); /// Video data bus output enable
|
||||
output reg [7:0] Vout; // Video data bus
|
||||
|
||||
/* SDRAM */
|
||||
output reg CKE = 0;
|
||||
output reg nCS = 1, nRAS = 1, nCAS = 1, nRWE = 1;
|
||||
output reg [1:0] BA;
|
||||
output reg [11:0] RA;
|
||||
output reg DQML = 1, DQMH = 1;
|
||||
wire RDOE = EN80 && !nWE80;
|
||||
inout [7:0] RD;
|
||||
assign RD[7:0] = RDOE ? Din[7:0] : 8'bZ;
|
||||
|
||||
/* RAMWorks Bank Register and Capacity Mask */
|
||||
reg [7:0] RWBank = 0; // RAMWorks bank register
|
||||
reg [7:0] RWMask = 0; // RAMWorks bank reg. capacity mask
|
||||
reg RWSel = 0; // RAMWorks bank register select
|
||||
reg CmdRWMaskSet = 0; // RAMWorks Mask register set flag
|
||||
// Causes RWBank to be zeroed next RWSel access
|
||||
reg CmdSetRWBankFFMAX = 0;
|
||||
//reg CmdSetRWBankFFSPI = 0;
|
||||
//reg CmdSetRWBankFFMXO2 = 0;
|
||||
reg CmdSetRWBankFFLED = 0;
|
||||
reg CmdLEDSet = 0;
|
||||
reg CmdLEDGet = 0;
|
||||
|
||||
/* Command Sequence Detector */
|
||||
reg [2:0] CS = 0; // Command sequence state
|
||||
reg [2:0] CmdTout = 0; // Command sequence timeout
|
||||
|
||||
/* UFM Interface */
|
||||
reg [15:8] UFMD = 0; // *Parallel* UFM data register
|
||||
reg ARCLK = 0; // UFM address register clock
|
||||
// UFM address register data input tied to 0
|
||||
reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
|
||||
reg DRCLK = 0; // UFM data register clock
|
||||
reg DRDIn = 0; // UFM data register input
|
||||
reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
|
||||
reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
|
||||
reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
|
||||
wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
|
||||
wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
|
||||
wire DRDOut; // UFM data output
|
||||
// UFM oscillator always enabled
|
||||
wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
|
||||
UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
|
||||
.arclk (ARCLK),
|
||||
.ardin (1'b0),
|
||||
.arshft (ARShift),
|
||||
.drclk (DRCLK),
|
||||
.drdin (DRDIn),
|
||||
.drshft (DRShift),
|
||||
.erase (UFMErase),
|
||||
.oscena (1'b1),
|
||||
.program (UFMProgram),
|
||||
.busy (UFMBusy),
|
||||
.drdout (DRDOut),
|
||||
.osc (UFMOsc),
|
||||
.rtpbusy (RTPBusy));
|
||||
reg UFMRTPBusy = 0;
|
||||
always @(posedge C14M) begin UFMRTPBusy <= UFMBusy || RTPBusy;
|
||||
|
||||
/* UFM State and User Command Triggers */
|
||||
reg UFMInitDone = 0; // 1 if UFM initialization finished
|
||||
reg UFMReqErase = 0; // 1 if UFM requires erase
|
||||
reg CmdBitbangMAX = 0; // Set by user command. Loads UFM outputs next RWSel
|
||||
//reg CmdBitbangSPI = 0;
|
||||
//reg CmdBitbangMXO2 = 0;
|
||||
//reg CmdExecMXO2 = 0;
|
||||
reg CmdPrgmMAX = 0; // Set by user command. Programs UFM
|
||||
reg CmdEraseMAX = 0; // Set by user command. Erases UFM
|
||||
reg DRCLKPulse = 0; // Set by user command. Causes DRCLK pulse next C14M
|
||||
|
||||
/* State Counters */
|
||||
reg PHI1reg = 0; // Saved PHI1 at last rising clock edge
|
||||
reg Ready = 0; // 1 if done with init sequence (S0) and enter S1-S15
|
||||
reg [15:0] FS = 0; // Fast state counter
|
||||
reg [3:0] S = 0; // IIe State counter
|
||||
|
||||
/* State Counters */
|
||||
always @(posedge C14M) begin
|
||||
// Increment fast state counter
|
||||
FS <= FS+16'h0001;
|
||||
// Synchronize Apple state counter to S1 when just entering PHI1
|
||||
PHI1reg <= PHI1; // Save old PHI1
|
||||
S <= (PHI1 && !PHI1reg && Ready) ? 4'h1 :
|
||||
S==4'h0 ? 4'h0 :
|
||||
S==4'hF ? 4'hF : S+4'h1;
|
||||
end
|
||||
|
||||
/* UFM Control */
|
||||
reg UFMProgStart;
|
||||
always @(posedge C14M) begin
|
||||
if (S==4'h0) begin
|
||||
if ((FS[15:13]==3'b101) || (FS[15:13]==3'b111 && UFMReqErase)) begin
|
||||
// In states AXXX-BXXX and also EXXX-FXXX if erase/wrap req'd
|
||||
// shift in 0's to address register
|
||||
ARCLK <= FS[0]; // Clock address register
|
||||
DRCLK <= 1'b0; // Don't clock data register
|
||||
ARShift <= 1'b1; // Shift address registers
|
||||
DRDIn <= 1'b0; // Don't care DRDIn
|
||||
DRShift <= 1'b0; // Don't care DRDShift
|
||||
end else if (!UFMInitDone && FS[15:13]==3'b110 && FS[4:1]==4'h4) begin
|
||||
// In states CXXX-DXXX (substep 4)
|
||||
// Xfer to data reg (repeat 256x 1x)
|
||||
ARCLK <= 1'b0; // Don't clock address register
|
||||
DRCLK <= FS[0]; // Clock data register
|
||||
ARShift <= 1'b0; // Don't care ARShift
|
||||
DRDIn <= 1'b0; // Don't care DRDIn
|
||||
DRShift <= 1'b0; // Don't care DRShift
|
||||
end else if (!UFMInitDone && FS[15:13]==3'b110 && (FS[4:1]==4'h7 || FS[4]==1'b1)) begin
|
||||
// In states CXXX-DXXX (substeps 8-F)
|
||||
// Save UFM D15-8, shift out D14-7 (repeat 256x 8x)
|
||||
DRCLK <= FS[0]; // Clock data register
|
||||
ARShift <= 1'b0; // ARShift is 0 because we want to increment
|
||||
DRDIn <= 1'b0; // Don't care what to shift into data register
|
||||
DRShift <= 1'b1; // Shift data register
|
||||
// Shift into UFMD
|
||||
if (FS[0]) UFMD[15:8] <= {UFMD[14:8], DRDOut};
|
||||
|
||||
// Compare and store mask
|
||||
if (FS[4:1]==4'hF) begin
|
||||
ARCLK <= FS[0]; // Clock address register to increment
|
||||
// If byte is erased (0xFF, i.e. all 1's, is erased)...
|
||||
if (UFMD[15:8]==8'hFF && DRDOut==1'b1) begin
|
||||
// Current UFM address is where we want to store
|
||||
UFMInitDone <= 1'b1; // Quit iterating
|
||||
// Otherwise byte is valid setting (i.e. some bit is 0)...
|
||||
end else begin
|
||||
// Set RWMask, but if saved mask is 0x80, store ~0xFF
|
||||
if (UFMD[15:8]==8'b10000000) begin
|
||||
RWMask[7:0] <= {1'b1, ~7'h7F};
|
||||
end else RWMask[7:0] <= {UFMD[15], ~UFMD[14:8]};
|
||||
// Set LED setting
|
||||
LEDEN <= DRDOut ^ UFMD[15];
|
||||
// If last byte in sector...
|
||||
if (FS[12:5]==8'hFF) begin
|
||||
UFMReqErase <= 1'b1; // Mark need to erase
|
||||
end
|
||||
end
|
||||
end else ARCLK <= 1'b0; // Don't clock address register
|
||||
end else begin
|
||||
ARCLK <= 1'b0;
|
||||
DRCLK <= 1'b0;
|
||||
ARShift <= 1'b0;
|
||||
DRDIn <= 1'b0;
|
||||
DRShift <= 1'b0;
|
||||
end
|
||||
|
||||
// Don't erase or program UFM during initialization
|
||||
UFMErase <= 1'b0;
|
||||
UFMProgram <= 1'b0;
|
||||
// Keep DRCLK pulse control disabled during init
|
||||
DRCLKPulse <= 1'b0;
|
||||
// Reset UFMProgStart
|
||||
UFMProgStart <= 1'b0;
|
||||
end else begin
|
||||
// Can only shift UFM data register now
|
||||
ARCLK <= 1'b0;
|
||||
ARShift <= 1'b0;
|
||||
DRShift <= 1'b1;
|
||||
|
||||
// UFM bitbang control
|
||||
if (CmdBitbangMAX && RWSel && S==4'hC) begin
|
||||
DRDIn <= Din[6];
|
||||
DRCLKPulse <= Din[7];
|
||||
DRCLK <= 1'b0;
|
||||
end else begin
|
||||
DRCLKPulse <= 1'b0;
|
||||
DRCLK <= DRCLKPulse;
|
||||
end
|
||||
|
||||
if (RWSel && S==4'hC) begin
|
||||
// LED control
|
||||
if (CmdLEDSet) LEDEN <= Din[0];
|
||||
|
||||
// Set capacity mask
|
||||
if (CmdRWMaskSet) RWMask[7:0] <= {Din[7], ~Din[6:0]};
|
||||
end
|
||||
|
||||
// UFM programming sequence
|
||||
if (S==4'h1) begin
|
||||
if (!UFMProgStart && !UFMRTPBusy) begin
|
||||
if (CmdPrgmMAX) begin
|
||||
UFMErase <= UFMReqErase;
|
||||
UFMProgStart <= 1;
|
||||
end else if (CmdEraseMAX) UFMErase <= 1;
|
||||
end else if (UFMProgStart && !UFMRTPBusy) begin
|
||||
UFMErase <= 0;
|
||||
if (!UFMErase) UFMProgram <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
/* SDRAM Control */
|
||||
always @(posedge C14M) begin
|
||||
if (S==4'h0) begin
|
||||
// SDRAM initialization
|
||||
if (FS[15:0]==16'hFFC0) begin
|
||||
// Precharge All
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b0;
|
||||
RA[10] <= 1'b1; // "all"
|
||||
end else if (FS[15:4]==16'hFFD && FS[0]==1'b0) begin // Repeat 8x
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA[10] <= 1'b0;
|
||||
end else if (FS[15:0]==16'hFFE8) begin
|
||||
// Set Mode Register
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b0;
|
||||
RA[10] <= 1'b0; // Reserved in mode register
|
||||
end else if (FS[15:4]==12'hFFF && FS[0]==1'b0) begin // Repeat 8x
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA[10] <= 1'b0;
|
||||
end else begin // Otherwise send no-op
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA[10] <= 1'b0;
|
||||
end
|
||||
// Enable SDRAM clock after 65,280 cycles (~4.56ms)
|
||||
CKE <= FS[15:8] == 8'hFF;
|
||||
|
||||
// Mode register contents
|
||||
BA[1:0] <= 2'b00; // Reserved
|
||||
RA[11] <= 1'b0; // Reserved
|
||||
// RA[10] set above ^
|
||||
RA[9] <= 1'b1; // "1" for single write mode
|
||||
RA[8] <= 1'b0; // Reserved
|
||||
RA[7] <= 1'b0; // "0" for not test mode
|
||||
RA[6:4] <= 3'b010; // "2" for CAS latency 2
|
||||
RA[3] <= 1'b0; // "0" for sequential burst (not used)
|
||||
RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
|
||||
// Begin normal operation after 128k init cycles (~9.15ms)
|
||||
if (FS == 16'hFFFF) Ready <= 1'b1;
|
||||
end else if (S==4'h1) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h2) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// Activate
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// SDRAM bank 0, high-order row address is 0
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
// Row address is as previously latched
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h3) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// Read
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// SDRAM bank 0, RA[11,9:8] don't care
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11] <= 1'b0;
|
||||
RA[10] <= 1'b1; // (A10 set to auto-precharge)
|
||||
RA[9] <= 1'b0;
|
||||
RA[8] <= 1'b0;
|
||||
// Latch column address for read command
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Read low byte (high byte is +4MB in ramworks)
|
||||
DQML <= 1'b0;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h4) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h5) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h6) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
if (FS[5:4]==0) begin
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
end else begin
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
end
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h7) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
// Latch row address for activate command
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h8) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= EN80;
|
||||
|
||||
// Activate if '245 output enabled
|
||||
nCS <= nEN80;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// SDRAM bank, RA[11:8] determine by RamWorks bank
|
||||
BA[1:0] <= RWBank[5:4];
|
||||
RA[11:8] <= RWBank[3:0];
|
||||
// Row address is as previously latched
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h9) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= EN80;
|
||||
|
||||
// Read/Write if '245 output enabled
|
||||
nCS <= nEN80;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= nWE80;
|
||||
|
||||
// SDRAM bank still determined by RamWorks, RA[11,9:8] don't care
|
||||
BA[1:0] <= RWBank[5:4];
|
||||
RA[11] <= 1'b0;
|
||||
RA[10] <= 1'b1; // (A10 set to auto-precharge)
|
||||
RA[9] <= 1'b0;
|
||||
RA[8] <= RWBank[7];
|
||||
// Latch column address for R/W command
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Latch RAMWorks low nybble write select using old row address
|
||||
RWSel <= RA[0] && !RA[3] && !nWE && !nC07X;
|
||||
|
||||
// Mask according to RAMWorks bank (high byte is +4MB)
|
||||
DQML <= RWBank[6];
|
||||
DQMH <= !RWBank[6];
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'hA) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= EN80;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'hB) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
end else if (S==4'hC) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
|
||||
// RAMWorks Bank Register Select
|
||||
if (RWSel) begin
|
||||
// Latch RAMWorks bank if accessed
|
||||
if (CmdSetRWBankFFLED ||
|
||||
CmdSetRWBankFFMAX ||
|
||||
//CmdSetRWBankFFSPI ||
|
||||
//CmdSetRWBankFFMXO2 ||
|
||||
(CmdLEDGet && LEDEN)) RWBank <= 8'hFF;
|
||||
else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]};
|
||||
|
||||
// Recognize command sequence and advance CS state
|
||||
if ((CS==3'h0 && Din[7:0]==8'hFF) ||
|
||||
(CS==3'h1 && Din[7:0]==8'h00) ||
|
||||
(CS==3'h2 && Din[7:0]==8'h55) ||
|
||||
(CS==3'h3 && Din[7:0]==8'hAA) ||
|
||||
(CS==3'h4 && Din[7:0]==8'hC1) ||
|
||||
(CS==3'h5 && Din[7:0]==8'hAD) ||
|
||||
CS==3'h6 || CS==3'h7) CS <= CS+3'h1;
|
||||
else CS <= 0; // Back to beginning if it's not right
|
||||
|
||||
if (CS==3'h6) begin // Recognize and submit command in CS6
|
||||
CmdSetRWBankFFMAX <= Din[7:0]==8'hFF;
|
||||
//CmdSetRWBankFFSPI <= Din[7:0]==8'hFE;
|
||||
//CmdSetRWBankFFMXO2 <= Din[7:0]==8'hFD;
|
||||
CmdSetRWBankFFLED <= Din[7:0]==8'hF0;
|
||||
|
||||
CmdRWMaskSet <= Din[7:0]==8'hE0;
|
||||
CmdLEDSet <= Din[7:0]==8'hE2;
|
||||
CmdLEDGet <= Din[7:0]==8'hE3;
|
||||
|
||||
CmdBitbangMAX <= Din[7:0]==8'hEA;
|
||||
//CmdBitbangSPI <= Din[7:0]==8'hEB;
|
||||
//CmdBitbangMXO2 <= Din[7:0]==8'hEC;
|
||||
//CmdExecMXO2 <= Din[7:0]==8'hED;
|
||||
|
||||
if (!CmdEraseMAX && !CmdPrgmMAX) begin
|
||||
if (Din[7:0]==8'hEE) CmdEraseMAX <= 1;
|
||||
if (Din[7:0]==8'hEF) CmdPrgmMAX <= 1;
|
||||
end
|
||||
end else begin // Reset command triggers
|
||||
CmdSetRWBankFFMAX <= 0;
|
||||
//CmdSetRWBankFFSPI <= 0;
|
||||
//CmdSetRWBankFFMXO2 <= 0;
|
||||
CmdSetRWBankFFLED <= 0;
|
||||
CmdRWMaskSet <= 0;
|
||||
CmdLEDSet <= 0;
|
||||
CmdLEDGet <= 0;
|
||||
CmdBitbangMAX <= 0;
|
||||
//CmdBitbangSPI <= 0;
|
||||
//CmdBitbangMXO2 <= 0;
|
||||
//CmdExecMXO2 <= 0;
|
||||
end
|
||||
|
||||
CmdTout <= 0; // Reset command timeout if RWSel accessed
|
||||
end else begin
|
||||
CmdTout <= CmdTout+3'h1; // Increment command timeout
|
||||
// If command sequence times out, reset sequence state
|
||||
if (CmdTout==3'h7) CS <= 0;
|
||||
end
|
||||
end else if (S==4'hD) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
end else if (S==4'hE) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
// Latch row address for next video read
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
end else if (S==4'hF) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA[1:0] <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
// Latch row address for next video read
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
end
|
||||
end
|
||||
always @(negedge C14M) begin
|
||||
// Latch video and read data outputs
|
||||
if (S==4'h6) Vout[7:0] <= RD[7:0];
|
||||
if (S==4'hC) Dout[7:0] <= RD[7:0];
|
||||
end
|
||||
endmodule
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue