Merge branch 'dev-GW4201D' of https://github.com/garrettsworkshop/RAM2GS into dev-GW4201D
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485253603 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:53 2020 " "Processing started: Thu Jul 23 02:20:53 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485254775 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485254806 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:55 2020 " "Processing ended: Thu Jul 23 02:20:55 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485255322 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595485244993 ""}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595485245024 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""}
|
||||
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595485245680 ""}
|
||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595485245711 ""}
|
||||
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595485246102 ""}
|
||||
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595485246305 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595485246336 ""}
|
||||
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595485246383 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595485246383 ""}
|
||||
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595485246399 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246415 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246430 ""}
|
||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246446 ""}
|
||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""}
|
||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246461 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""}
|
||||
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246461 ""}
|
||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
|
||||
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""}
|
||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
|
||||
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""}
|
||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595485246493 ""}
|
||||
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595485246555 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595485246555 ""}
|
||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246633 ""}
|
||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246649 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595485246665 ""}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595485246665 ""}
|
||||
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485246712 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595485247071 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485247462 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595485247477 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595485248884 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485248899 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595485248946 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595485249462 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595485249462 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250243 ""}
|
||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485250259 ""}
|
||||
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250275 ""}
|
||||
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485250290 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485250525 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "376 " "Peak virtual memory: 376 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:50 2020 " "Processing ended: Thu Jul 23 02:20:50 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485250759 ""}
|
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|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485235413 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:35 2020 " "Processing started: Thu Jul 23 02:20:35 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485237304 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595485237601 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237632 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595485237632 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595485237804 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595485237804 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595485238085 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595485238195 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" { } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595485238320 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595485240523 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595485240523 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595485240929 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:41 2020 " "Processing ended: Thu Jul 23 02:20:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""}
|
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@ -1 +0,0 @@
|
|||
RAM4GS/done
|
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|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485258541 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:57 2020 " "Processing started: Thu Jul 23 02:20:57 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485258573 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485258791 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485259791 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485260010 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485260010 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485260260 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485260838 ""}
|
||||
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485261042 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485261120 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485261260 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.292 -92.804 PHI2 " " -9.292 -92.804 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.365 -253.063 RCLK " " -8.365 -253.063 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.490 -0.577 nCRAS " " -0.490 -0.577 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.306 -16.306 DRCLK " " -16.306 -16.306 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.272 -16.272 ARCLK " " -16.272 -16.272 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.874 -0.874 RCLK " " -0.874 -0.874 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.396 -0.396 PHI2 " " -0.396 -0.396 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.125 -0.125 nCRAS " " -0.125 -0.125 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485261339 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485261354 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485261854 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485261995 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485261995 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "288 " "Peak virtual memory: 288 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:21:02 2020 " "Processing ended: Thu Jul 23 02:21:02 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""}
|
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|
@ -1,106 +0,0 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484987367 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:27 2020 " "Processing started: Thu Jul 23 02:16:27 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595484989226 ""}
|
||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595484989445 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989617 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989633 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595484989805 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484989883 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" { } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484990008 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
|
||||
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595484991726 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595484991726 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595484992133 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:32 2020 " "Processing ended: Thu Jul 23 02:16:32 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484995336 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:33 2020 " "Processing started: Thu Jul 23 02:16:33 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1595484995351 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1595484995367 ""}
|
||||
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1595484995523 ""}
|
||||
{ "Info" "0" "" "Project = RAM4GS" { } { } 0 0 "Project = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""}
|
||||
{ "Info" "0" "" "Revision = RAM4GS" { } { } 0 0 "Revision = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595484996148 ""}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595484996164 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""}
|
||||
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595484996648 ""}
|
||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595484996679 ""}
|
||||
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595484996992 ""}
|
||||
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595484997164 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595484997179 ""}
|
||||
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595484997210 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595484997210 ""}
|
||||
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595484997210 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997210 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997226 ""}
|
||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997226 ""}
|
||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
|
||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
|
||||
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
|
||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
|
||||
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
|
||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
|
||||
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
|
||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595484997273 ""}
|
||||
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595484997320 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595484997320 ""}
|
||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997382 ""}
|
||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997398 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595484997414 ""}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595484997414 ""}
|
||||
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484997445 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595484997742 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484998117 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595484998132 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595484999460 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484999460 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595484999507 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595484999976 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595484999976 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000632 ""}
|
||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.50 " "Total time spent on timing analysis during the Fitter is 0.50 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485000663 ""}
|
||||
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000679 ""}
|
||||
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485000742 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485001117 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:41 2020 " "Processing ended: Thu Jul 23 02:16:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485001429 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1595485004085 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:43 2020 " "Processing started: Thu Jul 23 02:16:43 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485005116 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485005148 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:45 2020 " "Processing ended: Thu Jul 23 02:16:45 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485005632 ""}
|
||||
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1595485006413 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1595485008366 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:47 2020 " "Processing started: Thu Jul 23 02:16:47 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485008413 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485008601 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485009444 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""}
|
||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485009898 ""}
|
||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485010507 ""}
|
||||
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485010726 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""}
|
||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485010773 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485010851 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.292 -92.804 PHI2 " " -9.292 -92.804 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.365 -253.063 RCLK " " -8.365 -253.063 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.490 -0.577 nCRAS " " -0.490 -0.577 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.306 -16.306 DRCLK " " -16.306 -16.306 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.272 -16.272 ARCLK " " -16.272 -16.272 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.874 -0.874 RCLK " " -0.874 -0.874 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.396 -0.396 PHI2 " " -0.396 -0.396 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.125 -0.125 nCRAS " " -0.125 -0.125 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010913 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010929 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""}
|
||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485011241 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:51 2020 " "Processing ended: Thu Jul 23 02:16:51 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""}
|
||||
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus II Full Compilation was successful. 0 errors, 14 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485012647 ""}
|
|
@ -1,26 +0,0 @@
|
|||
ERASE_TIME=500000000
|
||||
INTENDED_DEVICE_FAMILY="MAX II"
|
||||
LPM_FILE=RAM4GS.mif
|
||||
LPM_HINT=UNUSED
|
||||
LPM_TYPE=altufm_none
|
||||
OSC_FREQUENCY=180000
|
||||
PORT_ARCLKENA=PORT_UNUSED
|
||||
PORT_DRCLKENA=PORT_UNUSED
|
||||
PROGRAM_TIME=1600000
|
||||
WIDTH_UFM_ADDRESS=9
|
||||
DEVICE_FAMILY="MAX II"
|
||||
CBX_AUTO_BLACKBOX=ALL
|
||||
CBX_AUTO_BLACKBOX=ALL
|
||||
arclk
|
||||
ardin
|
||||
arshft
|
||||
busy
|
||||
drclk
|
||||
drdin
|
||||
drdout
|
||||
drshft
|
||||
erase
|
||||
osc
|
||||
oscena
|
||||
program
|
||||
rtpbusy
|
Binary file not shown.
|
@ -1,13 +0,0 @@
|
|||
/* Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */
|
||||
JedecChain;
|
||||
FileRevision(JESD32A);
|
||||
DefaultMfr(6E);
|
||||
|
||||
P ActionCode(Cfg)
|
||||
Device PartName(EPM240T100) Path("Z:/Repos/RAM4GS/cpld/output_files/") File("RAM4GS.pof") MfrSpec(OpMask(3) SEC_Device(EPM240T100) Child_OpMask(2 3 3));
|
||||
|
||||
ChainEnd;
|
||||
|
||||
AlteraBegin;
|
||||
ChainType(JTAG);
|
||||
AlteraEnd;
|
|
@ -1 +0,0 @@
|
|||
Thu Jul 23 02:21:03 2020
|
|
@ -1,11 +0,0 @@
|
|||
Fitter Status : Successful - Thu Jul 23 02:20:50 2020
|
||||
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Revision Name : RAM4GS
|
||||
Top-level Entity Name : RAM4GS
|
||||
Family : MAX II
|
||||
Device : EPM240T100C5
|
||||
Timing Models : Final
|
||||
Total logic elements : 170 / 240 ( 71 % )
|
||||
Total pins : 62 / 80 ( 78 % )
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
|
@ -1,8 +0,0 @@
|
|||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="6d7ef2df313eca11db51"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EPM240T100C5" path="RAM4GS.sof" usercode="0xFFFFFFFF"/>
|
||||
</file_info>
|
||||
</sld_project_info>
|
|
@ -1,9 +0,0 @@
|
|||
Analysis & Synthesis Status : Successful - Thu Jul 23 02:20:40 2020
|
||||
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||
Revision Name : RAM4GS
|
||||
Top-level Entity Name : RAM4GS
|
||||
Family : MAX II
|
||||
Total logic elements : 178
|
||||
Total pins : 62
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,9 @@
|
|||
[Runmanager]
|
||||
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
|
||||
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\x2\xc9\0\0\x2i\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
|
||||
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
|
||||
|
||||
[impl1%3CStrategy1%3E]
|
||||
isChecked=true
|
||||
isHidden=false
|
||||
isExpanded=true
|
|
@ -0,0 +1,4 @@
|
|||
[General]
|
||||
Export.auto_tasks=IBIS, Bitgen
|
||||
Map.auto_tasks=MapEqu, MapTrace
|
||||
PAR.auto_tasks=PARTrace, IOTiming
|
|
@ -0,0 +1,3 @@
|
|||
[General]
|
||||
COLUMN_POS_INFO_NAME_-1_0=Prioritize
|
||||
COLUMN_POS_INFO_NAME_-1_1=PIO Register
|
|
@ -0,0 +1,65 @@
|
|||
[General]
|
||||
pin_sort_type=0
|
||||
pin_sort_ascending=true
|
||||
sig_sort_type=0
|
||||
sig_sort_ascending=true
|
||||
active_Sheet=Timing Preferences
|
||||
|
||||
[Port%20Assignments]
|
||||
Name="166,0"
|
||||
Group%20By="84,1"
|
||||
Pin="63,2"
|
||||
BANK="62,3"
|
||||
IO_TYPE="117,4"
|
||||
PULLMODE="119,5"
|
||||
DRIVE="67,6"
|
||||
SLEWRATE="92,7"
|
||||
OPENDRAIN="97,8"
|
||||
Outload%20%28pF%29="103,9"
|
||||
MaxSkew="87,10"
|
||||
Clock%20Load%20Only="121,11"
|
||||
sort_columns="Name,Ascending"
|
||||
|
||||
[Pin%20Assignments]
|
||||
Pin="90,0"
|
||||
Pad%20Name="89,1"
|
||||
Dual%20Function="109,2"
|
||||
Polarity="77,3"
|
||||
BANK="0,4"
|
||||
IO_TYPE="117,5"
|
||||
Signal%20Name="123,6"
|
||||
Signal%20Type="115,7"
|
||||
sort_columns="Pin,Ascending"
|
||||
|
||||
[Clock%20Resource]
|
||||
Clock%20Type="100,ELLIPSIS"
|
||||
Clock%20Name="100,ELLIPSIS"
|
||||
Selection="100,ELLIPSIS"
|
||||
|
||||
[Global%20Preferences]
|
||||
Preference%20Name="222,ELLIPSIS"
|
||||
Preference%20Value="236,ELLIPSIS"
|
||||
|
||||
[Cell%20Mapping]
|
||||
Type="100,ELLIPSIS"
|
||||
Name="100,ELLIPSIS"
|
||||
Din\Dout="100,ELLIPSIS"
|
||||
PIO%20Register="100,ELLIPSIS"
|
||||
|
||||
[Route%20Priority]
|
||||
Type="100,ELLIPSIS"
|
||||
Name="100,ELLIPSIS"
|
||||
Prioritize="100,ELLIPSIS"
|
||||
|
||||
[Timing%20Preferences]
|
||||
Preference%20Name="246,ELLIPSIS"
|
||||
Preference%20Value="104,ELLIPSIS"
|
||||
Preference%20Unit="1012,ELLIPSIS"
|
||||
|
||||
[Group]
|
||||
Group%20Type\Name="134,ELLIPSIS"
|
||||
Value="1245,ELLIPSIS"
|
||||
|
||||
[Misc%20Preferences]
|
||||
Preference%20Name="117,ELLIPSIS"
|
||||
Preference%20Value="104,ELLIPSIS"
|
0
CPLD/AGM-src/constraints.sdc → CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ccl
Executable file → Normal file
0
CPLD/AGM-src/constraints.sdc → CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ccl
Executable file → Normal file
|
@ -0,0 +1,14 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BaliProject version="3.2" title="RAM2GS_LCMXO256C" device="LCMXO256C-3T100C" default_implementation="impl1">
|
||||
<Options/>
|
||||
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
|
||||
<Options def_top="RAM2GS"/>
|
||||
<Source name="../RAM2GS-LCMXO.v" type="Verilog" type_short="Verilog">
|
||||
<Options top_module="RAM2GS"/>
|
||||
</Source>
|
||||
<Source name="RAM2GS_LCMXO256C.lpf" type="Logic Preference" type_short="LPF">
|
||||
<Options/>
|
||||
</Source>
|
||||
</Implementation>
|
||||
<Strategy name="Strategy1" file="RAM2GS_LCMXO256C1.sty"/>
|
||||
</BaliProject>
|
|
@ -0,0 +1,226 @@
|
|||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
LOCATE COMP "Dout[0]" SITE "1" ;
|
||||
LOCATE COMP "Dout[6]" SITE "2" ;
|
||||
LOCATE COMP "Dout[7]" SITE "3" ;
|
||||
LOCATE COMP "Dout[4]" SITE "4" ;
|
||||
LOCATE COMP "Dout[5]" SITE "5" ;
|
||||
LOCATE COMP "Dout[3]" SITE "6" ;
|
||||
LOCATE COMP "Dout[1]" SITE "7" ;
|
||||
LOCATE COMP "Dout[2]" SITE "8" ;
|
||||
LOCATE COMP "Din[2]" SITE "14" ;
|
||||
LOCATE COMP "Din[1]" SITE "15" ;
|
||||
LOCATE COMP "Din[3]" SITE "16" ;
|
||||
LOCATE COMP "Din[5]" SITE "17" ;
|
||||
LOCATE COMP "Din[4]" SITE "18" ;
|
||||
LOCATE COMP "Din[7]" SITE "19" ;
|
||||
LOCATE COMP "Din[6]" SITE "20" ;
|
||||
LOCATE COMP "Din[0]" SITE "21" ;
|
||||
LOCATE COMP "LED" SITE "57" ;
|
||||
LOCATE COMP "RA[0]" SITE "98" ;
|
||||
LOCATE COMP "RA[1]" SITE "89" ;
|
||||
LOCATE COMP "RA[2]" SITE "94" ;
|
||||
LOCATE COMP "RA[3]" SITE "97" ;
|
||||
LOCATE COMP "RA[4]" SITE "99" ;
|
||||
LOCATE COMP "RA[5]" SITE "95" ;
|
||||
LOCATE COMP "RA[6]" SITE "91" ;
|
||||
LOCATE COMP "RA[7]" SITE "100" ;
|
||||
LOCATE COMP "RA[8]" SITE "96" ;
|
||||
LOCATE COMP "RA[9]" SITE "85" ;
|
||||
LOCATE COMP "RA[10]" SITE "87" ;
|
||||
LOCATE COMP "RA[11]" SITE "79" ;
|
||||
LOCATE COMP "RBA[1]" SITE "83" ;
|
||||
LOCATE COMP "RBA[0]" SITE "63" ;
|
||||
LOCATE COMP "RCKE" SITE "82" ;
|
||||
LOCATE COMP "RDQMH" SITE "76" ;
|
||||
LOCATE COMP "RDQML" SITE "61" ;
|
||||
LOCATE COMP "UFMCLK" SITE "58" ;
|
||||
LOCATE COMP "UFMSDI" SITE "56" ;
|
||||
LOCATE COMP "nUFMCS" SITE "53" ;
|
||||
LOCATE COMP "nRCAS" SITE "78" ;
|
||||
LOCATE COMP "nRCS" SITE "77" ;
|
||||
LOCATE COMP "nRRAS" SITE "73" ;
|
||||
LOCATE COMP "nRWE" SITE "72" ;
|
||||
LOCATE COMP "RD[0]" SITE "64" ;
|
||||
LOCATE COMP "RD[1]" SITE "65" ;
|
||||
LOCATE COMP "RD[2]" SITE "66" ;
|
||||
LOCATE COMP "RD[3]" SITE "67" ;
|
||||
LOCATE COMP "RD[4]" SITE "68" ;
|
||||
LOCATE COMP "RD[5]" SITE "69" ;
|
||||
LOCATE COMP "RD[6]" SITE "70" ;
|
||||
LOCATE COMP "RD[7]" SITE "71" ;
|
||||
LOCATE COMP "PHI2" SITE "39" ;
|
||||
LOCATE COMP "RCLK" SITE "86" ;
|
||||
LOCATE COMP "nCCAS" SITE "27" ;
|
||||
LOCATE COMP "nCRAS" SITE "43" ;
|
||||
LOCATE COMP "CROW[0]" SITE "32" ;
|
||||
LOCATE COMP "CROW[1]" SITE "34" ;
|
||||
LOCATE COMP "UFMSDO" SITE "55" ;
|
||||
LOCATE COMP "nFWE" SITE "22" ;
|
||||
LOCATE COMP "MAin[0]" SITE "23" ;
|
||||
LOCATE COMP "MAin[1]" SITE "38" ;
|
||||
LOCATE COMP "MAin[2]" SITE "37" ;
|
||||
LOCATE COMP "MAin[3]" SITE "47" ;
|
||||
LOCATE COMP "MAin[4]" SITE "46" ;
|
||||
LOCATE COMP "MAin[5]" SITE "45" ;
|
||||
LOCATE COMP "MAin[6]" SITE "49" ;
|
||||
LOCATE COMP "MAin[7]" SITE "44" ;
|
||||
LOCATE COMP "MAin[8]" SITE "50" ;
|
||||
LOCATE COMP "MAin[9]" SITE "51" ;
|
||||
IOBUF PORT "CROW[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "CROW[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "nCRAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "nCCAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "RCLK" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "PHI2" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[8]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[9]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "UFMSDO" PULLMODE=KEEPER IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "nFWE" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVTTL33 DRIVE=16 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "UFMCLK" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "UFMSDI" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "nUFMCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "LED" LOAD 25.000000 pF ;
|
||||
OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
|
||||
USE PRIMARY NET "PHI2_c" ;
|
||||
USE PRIMARY NET "RCLK_c" ;
|
||||
VOLTAGE 3.300 V;
|
||||
VCCIO_DERATE BANK 0 PERCENT -5;
|
||||
VCCIO_DERATE PERCENT -5;
|
||||
VCCIO_DERATE BANK 1 PERCENT -5;
|
||||
PERIOD NET "PHI2_c" 350.000000 ns ;
|
||||
PERIOD NET "nCCAS_c" 350.000000 ns ;
|
||||
PERIOD NET "nCRAS_c" 350.000000 ns ;
|
||||
PERIOD NET "RCLK_c" 16.000000 ns ;
|
||||
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
USE PRIMARY NET "nCCAS_c" ;
|
||||
USE PRIMARY NET "nCRAS_c" ;
|
|
@ -0,0 +1,205 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE strategy>
|
||||
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
|
||||
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
|
||||
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
|
||||
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
|
||||
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
|
||||
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
|
||||
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
|
||||
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
|
||||
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
|
||||
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
|
||||
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
|
||||
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
|
||||
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
|
||||
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
|
||||
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
|
||||
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
|
||||
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
|
||||
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
|
||||
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
|
||||
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
|
||||
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
|
||||
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
|
||||
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
|
||||
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
|
||||
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
|
||||
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
|
||||
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
|
||||
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
|
||||
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
|
||||
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
|
||||
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
|
||||
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
|
||||
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
|
||||
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
|
||||
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
|
||||
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
|
||||
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
|
||||
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
|
||||
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
|
||||
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
|
||||
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
|
||||
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
|
||||
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_parHold" value="On" time="0"/>
|
||||
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
|
||||
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
|
||||
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
|
||||
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
|
||||
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
|
||||
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
|
||||
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
|
||||
<Property name="PROP_SYN_LibPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
|
||||
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
|
||||
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
|
||||
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
|
||||
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
|
||||
</Strategy>
|
|
@ -0,0 +1,91 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn210816194012"></A><B><U><big>pn210816194012</big></U></B>
|
||||
#Start recording tcl command: 8/16/2021 19:02:08
|
||||
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
|
||||
prj_project new -name "RAM2GS_LCMXO256C" -impl "impl1" -dev LCMXO256C-3T100C -synthesis "lse"
|
||||
prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v"
|
||||
prj_project save
|
||||
prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v"
|
||||
prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
|
||||
prj_run PAR -impl impl1
|
||||
prj_run PAR -impl impl1
|
||||
prj_run Map -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run PAR -impl impl1
|
||||
prj_run Map -impl impl1
|
||||
prj_run PAR -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 8/16/2021 19:40:12
|
||||
|
||||
|
||||
|
||||
<A name="pn210816202808"></A><B><U><big>pn210816202808</big></U></B>
|
||||
#Start recording tcl command: 8/16/2021 20:24:10
|
||||
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
|
||||
prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 8/16/2021 20:28:08
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
|
@ -0,0 +1,17 @@
|
|||
#Start recording tcl command: 8/16/2021 19:02:08
|
||||
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
|
||||
prj_project new -name "RAM2GS_LCMXO256C" -impl "impl1" -dev LCMXO256C-3T100C -synthesis "lse"
|
||||
prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v"
|
||||
prj_project save
|
||||
prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v"
|
||||
prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
|
||||
prj_run PAR -impl impl1
|
||||
prj_run PAR -impl impl1
|
||||
prj_run Map -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run PAR -impl impl1
|
||||
prj_run Map -impl impl1
|
||||
prj_run PAR -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 8/16/2021 19:40:12
|
|
@ -0,0 +1,5 @@
|
|||
#Start recording tcl command: 8/16/2021 20:24:10
|
||||
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
|
||||
prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 8/16/2021 20:28:08
|
|
@ -0,0 +1,4 @@
|
|||
#Start recording tcl command: 8/16/2021 21:33:16
|
||||
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
|
||||
prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf"
|
||||
#Stop recording: 8/16/2021 21:33:22
|
|
@ -0,0 +1,6 @@
|
|||
#Start recording tcl command: 8/16/2021 21:32:14
|
||||
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
|
||||
prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceOne
|
||||
#Stop recording: 8/16/2021 21:41:12
|
|
@ -0,0 +1,46 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BuildStatus>
|
||||
<Strategy name="Strategy1">
|
||||
<Milestone name="Export" build_result="0" build_time="0">
|
||||
<Task name="IBIS" build_result="0" update_result="2" update_time="1629164185"/>
|
||||
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="Bitgen" build_result="2" update_result="0" update_time="1629164189"/>
|
||||
</Milestone>
|
||||
<Milestone name="Map" build_result="2" build_time="1629163946">
|
||||
<Task name="Map" build_result="2" update_result="0" update_time="1629163946"/>
|
||||
<Task name="MapEqu" build_result="2" update_result="0" update_time="1629163946"/>
|
||||
<Task name="MapTrace" build_result="2" update_result="0" update_time="1629163947"/>
|
||||
<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
|
||||
</Milestone>
|
||||
<Milestone name="PAR" build_result="2" build_time="1629163954">
|
||||
<Task name="PAR" build_result="2" update_result="0" update_time="1629163954"/>
|
||||
<Task name="PARTrace" build_result="2" update_result="0" update_time="1629163954"/>
|
||||
<Task name="IOTiming" build_result="2" update_result="0" update_time="1629163954"/>
|
||||
</Milestone>
|
||||
<Milestone name="Synthesis" build_result="2" build_time="1629163946">
|
||||
<Task name="Lattice_Synthesis" build_result="2" update_result="0" update_time="1629163946"/>
|
||||
<Task name="LSE_Compile" build_result="2" update_result="0" update_time="1629163959"/>
|
||||
</Milestone>
|
||||
<Milestone name="TOOL_Report" build_result="0" build_time="0">
|
||||
<Task name="HDLE" build_result="2" update_result="0" update_time="1629163934"/>
|
||||
<Task name="BKM" build_result="0" update_result="2" update_time="1629163934"/>
|
||||
<Task name="SSO" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="DEC" build_result="0" update_result="3" update_time="0"/>
|
||||
</Milestone>
|
||||
<Report name=".vdbs/RAM2GS_LCMXO256C_impl1_map.vdb" last_build_time="1629163946" last_build_size="65077"/>
|
||||
<Report name="IBIS/RAM2GS_LCMXO256C_impl1.ibs" last_build_time="0" last_build_size="0"/>
|
||||
<Report name="RAM2GS_LCMXO256C_impl1.bgn" last_build_time="1629164186" last_build_size="2011"/>
|
||||
<Report name="RAM2GS_LCMXO256C_impl1.ior" last_build_time="1629163954" last_build_size="6686"/>
|
||||
<Report name="RAM2GS_LCMXO256C_impl1.jed" last_build_time="1629164189" last_build_size="61054"/>
|
||||
<Report name="RAM2GS_LCMXO256C_impl1.lsedata" last_build_time="1629163945" last_build_size="225954"/>
|
||||
<Report name="RAM2GS_LCMXO256C_impl1.n2e" last_build_time="1629163946" last_build_size="14598"/>
|
||||
<Report name="RAM2GS_LCMXO256C_impl1.ncd" last_build_time="1629163954" last_build_size="154201"/>
|
||||
<Report name="RAM2GS_LCMXO256C_impl1.ngd" last_build_time="1629163946" last_build_size="153868"/>
|
||||
<Report name="RAM2GS_LCMXO256C_impl1.tw1" last_build_time="1629163947" last_build_size="111690"/>
|
||||
<Report name="RAM2GS_LCMXO256C_impl1.twr" last_build_time="1629163954" last_build_size="187578"/>
|
||||
<Report name="RAM2GS_LCMXO256C_impl1_map.ncd" last_build_time="1629163946" last_build_size="104196"/>
|
||||
</Strategy>
|
||||
</BuildStatus>
|
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
@ -0,0 +1 @@
|
|||
RAM2GS_rtl.vdb
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,75 @@
|
|||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Mon Aug 16 21:36:26 2021 *
|
||||
NOTE DESIGN NAME: RAM2GS *
|
||||
NOTE DEVICE NAME: LCMXO256C-3TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS RD[7] : 71 : inout *
|
||||
NOTE PINS RD[6] : 70 : inout *
|
||||
NOTE PINS RD[5] : 69 : inout *
|
||||
NOTE PINS RD[4] : 68 : inout *
|
||||
NOTE PINS RD[3] : 67 : inout *
|
||||
NOTE PINS RD[2] : 66 : inout *
|
||||
NOTE PINS RD[1] : 65 : inout *
|
||||
NOTE PINS RD[0] : 64 : inout *
|
||||
NOTE PINS Dout[7] : 3 : out *
|
||||
NOTE PINS Dout[6] : 2 : out *
|
||||
NOTE PINS Dout[5] : 5 : out *
|
||||
NOTE PINS Dout[4] : 4 : out *
|
||||
NOTE PINS Dout[3] : 6 : out *
|
||||
NOTE PINS Dout[2] : 8 : out *
|
||||
NOTE PINS Dout[1] : 7 : out *
|
||||
NOTE PINS Dout[0] : 1 : out *
|
||||
NOTE PINS LED : 57 : out *
|
||||
NOTE PINS RBA[1] : 83 : out *
|
||||
NOTE PINS RBA[0] : 63 : out *
|
||||
NOTE PINS RA[11] : 79 : out *
|
||||
NOTE PINS RA[10] : 87 : out *
|
||||
NOTE PINS RA[9] : 85 : out *
|
||||
NOTE PINS RA[8] : 96 : out *
|
||||
NOTE PINS RA[7] : 100 : out *
|
||||
NOTE PINS RA[6] : 91 : out *
|
||||
NOTE PINS RA[5] : 95 : out *
|
||||
NOTE PINS RA[4] : 99 : out *
|
||||
NOTE PINS RA[3] : 97 : out *
|
||||
NOTE PINS RA[2] : 94 : out *
|
||||
NOTE PINS RA[1] : 89 : out *
|
||||
NOTE PINS RA[0] : 98 : out *
|
||||
NOTE PINS nRCS : 77 : out *
|
||||
NOTE PINS RCKE : 82 : out *
|
||||
NOTE PINS nRWE : 72 : out *
|
||||
NOTE PINS nRRAS : 73 : out *
|
||||
NOTE PINS nRCAS : 78 : out *
|
||||
NOTE PINS RDQMH : 76 : out *
|
||||
NOTE PINS RDQML : 61 : out *
|
||||
NOTE PINS nUFMCS : 53 : out *
|
||||
NOTE PINS UFMCLK : 58 : out *
|
||||
NOTE PINS UFMSDI : 56 : out *
|
||||
NOTE PINS PHI2 : 39 : in *
|
||||
NOTE PINS MAin[9] : 51 : in *
|
||||
NOTE PINS MAin[8] : 50 : in *
|
||||
NOTE PINS MAin[7] : 44 : in *
|
||||
NOTE PINS MAin[6] : 49 : in *
|
||||
NOTE PINS MAin[5] : 45 : in *
|
||||
NOTE PINS MAin[4] : 46 : in *
|
||||
NOTE PINS MAin[3] : 47 : in *
|
||||
NOTE PINS MAin[2] : 37 : in *
|
||||
NOTE PINS MAin[1] : 38 : in *
|
||||
NOTE PINS MAin[0] : 23 : in *
|
||||
NOTE PINS CROW[1] : 34 : in *
|
||||
NOTE PINS CROW[0] : 32 : in *
|
||||
NOTE PINS Din[7] : 19 : in *
|
||||
NOTE PINS Din[6] : 20 : in *
|
||||
NOTE PINS Din[5] : 17 : in *
|
||||
NOTE PINS Din[4] : 18 : in *
|
||||
NOTE PINS Din[3] : 16 : in *
|
||||
NOTE PINS Din[2] : 14 : in *
|
||||
NOTE PINS Din[1] : 15 : in *
|
||||
NOTE PINS Din[0] : 21 : in *
|
||||
NOTE PINS nCCAS : 27 : in *
|
||||
NOTE PINS nCRAS : 43 : in *
|
||||
NOTE PINS nFWE : 22 : in *
|
||||
NOTE PINS RCLK : 86 : in *
|
||||
NOTE PINS UFMSDO : 55 : in *
|
||||
NOTE CONFIGURATION MODE: NONE *
|
||||
NOTE COMPRESSION: off *
|
|
@ -0,0 +1,24 @@
|
|||
----------------------------------------------------------------------
|
||||
Report for cell RAM2GS.TECH
|
||||
Register bits: 102 of 490 (20.816%)
|
||||
I/O cells: 67
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
CCU2 9 100.0
|
||||
FD1P3AX 28 100.0
|
||||
FD1P3AY 3 100.0
|
||||
FD1P3IX 2 100.0
|
||||
FD1P3JX 1 100.0
|
||||
FD1S3AX 47 100.0
|
||||
FD1S3AY 1 100.0
|
||||
FD1S3IX 16 100.0
|
||||
FD1S3JX 4 100.0
|
||||
GSR 1 100.0
|
||||
IB 26 100.0
|
||||
INV 3 100.0
|
||||
LUT4 114 100.0
|
||||
OB 33 100.0
|
||||
ORCALUT4 2 100.0
|
||||
PFUMX 3 100.0
|
||||
TOTAL 301
|
|
@ -0,0 +1,45 @@
|
|||
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Mon Aug 16 21:36:25 2021
|
||||
|
||||
|
||||
Command: bitgen -w -g ES:No -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO256C
|
||||
Package: TQFP100
|
||||
Performance: 3
|
||||
Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.19.
|
||||
Performance Hardware Data Status: Version 1.124.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
|
||||
|
||||
Preference Summary:
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ES | No** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 44 MB
|
Binary file not shown.
Binary file not shown.
|
@ -0,0 +1,271 @@
|
|||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO256C
|
||||
Performance Grade: 3
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.19
|
||||
|
||||
Mon Aug 16 21:32:33 2021
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+--------------+------+----------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | Properties |
|
||||
+-----------+----------+--------------+------+----------------------------------+
|
||||
| CROW[0] | 32/1 | LVTTL33_IN | PB2C | SLEW:FAST |
|
||||
| CROW[1] | 34/1 | LVTTL33_IN | PB2D | SLEW:FAST |
|
||||
| Din[0] | 21/1 | LVTTL33_IN | PL8A | SLEW:FAST |
|
||||
| Din[1] | 15/1 | LVTTL33_IN | PL6A | SLEW:FAST |
|
||||
| Din[2] | 14/1 | LVTTL33_IN | PL5D | SLEW:FAST |
|
||||
| Din[3] | 16/1 | LVTTL33_IN | PL6B | SLEW:FAST |
|
||||
| Din[4] | 18/1 | LVTTL33_IN | PL7B | SLEW:FAST |
|
||||
| Din[5] | 17/1 | LVTTL33_IN | PL7A | SLEW:FAST |
|
||||
| Din[6] | 20/1 | LVTTL33_IN | PL7D | SLEW:FAST |
|
||||
| Din[7] | 19/1 | LVTTL33_IN | PL7C | SLEW:FAST |
|
||||
| Dout[0] | 1/1 | LVTTL33_OUT | PL2A | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[1] | 7/1 | LVTTL33_OUT | PL4A | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[2] | 8/1 | LVTTL33_OUT | PL4B | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[3] | 6/1 | LVTTL33_OUT | PL3D | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[4] | 4/1 | LVTTL33_OUT | PL3B | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[5] | 5/1 | LVTTL33_OUT | PL3C | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[6] | 2/1 | LVTTL33_OUT | PL2B | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[7] | 3/1 | LVTTL33_OUT | PL3A | DRIVE:4mA SLEW:SLOW |
|
||||
| LED | 57/0 | LVTTL33_OUT | PR7B | DRIVE:16mA SLEW:SLOW |
|
||||
| MAin[0] | 23/1 | LVTTL33_IN | PL9A | SLEW:FAST |
|
||||
| MAin[1] | 38/1 | LVTTL33_IN | PB3C | SLEW:FAST |
|
||||
| MAin[2] | 37/1 | LVTTL33_IN | PB3B | SLEW:FAST |
|
||||
| MAin[3] | 47/1 | LVTTL33_IN | PB5A | SLEW:FAST |
|
||||
| MAin[4] | 46/1 | LVTTL33_IN | PB4D | SLEW:FAST |
|
||||
| MAin[5] | 45/1 | LVTTL33_IN | PB4C | SLEW:FAST |
|
||||
| MAin[6] | 49/1 | LVTTL33_IN | PB5C | SLEW:FAST |
|
||||
| MAin[7] | 44/1 | LVTTL33_IN | PB4B | SLEW:FAST |
|
||||
| MAin[8] | 50/1 | LVTTL33_IN | PB5D | SLEW:FAST |
|
||||
| MAin[9] | 51/0 | LVTTL33_IN | PR9B | SLEW:FAST |
|
||||
| PHI2 | 39/1 | LVTTL33_IN | PB3D | SLEW:FAST |
|
||||
| RA[0] | 98/0 | LVTTL33_OUT | PT2C | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 87/0 | LVTTL33_OUT | PT3D | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 79/0 | LVTTL33_OUT | PT5A | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 89/0 | LVTTL33_OUT | PT3C | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 94/0 | LVTTL33_OUT | PT3A | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 97/0 | LVTTL33_OUT | PT2D | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 99/0 | LVTTL33_OUT | PT2B | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 95/0 | LVTTL33_OUT | PT2F | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 91/0 | LVTTL33_OUT | PT3B | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 100/0 | LVTTL33_OUT | PT2A | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 96/0 | LVTTL33_OUT | PT2E | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 85/0 | LVTTL33_OUT | PT4B | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[0] | 63/0 | LVTTL33_OUT | PR5D | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 83/0 | LVTTL33_OUT | PT4C | DRIVE:4mA SLEW:SLOW |
|
||||
| RCKE | 82/0 | LVTTL33_OUT | PT4D | DRIVE:4mA SLEW:SLOW |
|
||||
| RCLK | 86/0 | LVTTL33_IN | PT4A | SLEW:FAST |
|
||||
| RDQMH | 76/0 | LVTTL33_OUT | PR2A | DRIVE:4mA SLEW:SLOW |
|
||||
| RDQML | 61/0 | LVTTL33_OUT | PR6A | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 64/0 | LVTTL33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| RD[1] | 65/0 | LVTTL33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| RD[2] | 66/0 | LVTTL33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| RD[3] | 67/0 | LVTTL33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| RD[4] | 68/0 | LVTTL33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| RD[5] | 69/0 | LVTTL33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| RD[6] | 70/0 | LVTTL33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| RD[7] | 71/0 | LVTTL33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| UFMCLK | 58/0 | LVTTL33_OUT | PR7A | DRIVE:4mA SLEW:SLOW |
|
||||
| UFMSDI | 56/0 | LVTTL33_OUT | PR7C | DRIVE:4mA SLEW:SLOW |
|
||||
| UFMSDO | 55/0 | LVTTL33_IN | PR7D | SLEW:FAST PULL:KEEPER |
|
||||
| nCCAS | 27/1 | LVTTL33_IN | PL9B | SLEW:FAST |
|
||||
| nCRAS | 43/1 | LVTTL33_IN | PB4A | SLEW:FAST |
|
||||
| nFWE | 22/1 | LVTTL33_IN | PL8B | SLEW:FAST |
|
||||
| nRCAS | 78/0 | LVTTL33_OUT | PT5B | DRIVE:4mA SLEW:SLOW |
|
||||
| nRCS | 77/0 | LVTTL33_OUT | PT5C | DRIVE:4mA SLEW:SLOW |
|
||||
| nRRAS | 73/0 | LVTTL33_OUT | PR2B | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 72/0 | LVTTL33_OUT | PR3A | DRIVE:4mA SLEW:SLOW |
|
||||
| nUFMCS | 53/0 | LVTTL33_OUT | PR8B | DRIVE:4mA SLEW:SLOW |
|
||||
+-----------+----------+--------------+------+----------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+---------------------+------------+--------------+------+---------------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function |
|
||||
+----------+---------------------+------------+--------------+------+---------------+
|
||||
| 1/1 | Dout[0] | LOCATED | LVTTL33_OUT | PL2A | |
|
||||
| 2/1 | Dout[6] | LOCATED | LVTTL33_OUT | PL2B | |
|
||||
| 3/1 | Dout[7] | LOCATED | LVTTL33_OUT | PL3A | |
|
||||
| 4/1 | Dout[4] | LOCATED | LVTTL33_OUT | PL3B | |
|
||||
| 5/1 | Dout[5] | LOCATED | LVTTL33_OUT | PL3C | |
|
||||
| 6/1 | Dout[3] | LOCATED | LVTTL33_OUT | PL3D | |
|
||||
| 7/1 | Dout[1] | LOCATED | LVTTL33_OUT | PL4A | |
|
||||
| 8/1 | Dout[2] | LOCATED | LVTTL33_OUT | PL4B | |
|
||||
| 9/1 | unused, PULL:UP | | | PL5A | |
|
||||
| 11/1 | unused, PULL:UP | | | PL5B | |
|
||||
| 13/1 | unused, PULL:UP | | | PL5C | |
|
||||
| 14/1 | Din[2] | LOCATED | LVTTL33_IN | PL5D | GSR_PADN |
|
||||
| 15/1 | Din[1] | LOCATED | LVTTL33_IN | PL6A | |
|
||||
| 16/1 | Din[3] | LOCATED | LVTTL33_IN | PL6B | TSALLPAD |
|
||||
| 17/1 | Din[5] | LOCATED | LVTTL33_IN | PL7A | |
|
||||
| 18/1 | Din[4] | LOCATED | LVTTL33_IN | PL7B | |
|
||||
| 19/1 | Din[7] | LOCATED | LVTTL33_IN | PL7C | |
|
||||
| 20/1 | Din[6] | LOCATED | LVTTL33_IN | PL7D | |
|
||||
| 21/1 | Din[0] | LOCATED | LVTTL33_IN | PL8A | |
|
||||
| 22/1 | nFWE | LOCATED | LVTTL33_IN | PL8B | |
|
||||
| 23/1 | MAin[0] | LOCATED | LVTTL33_IN | PL9A | |
|
||||
| 27/1 | nCCAS | LOCATED | LVTTL33_IN | PL9B | |
|
||||
| 29/1 | unused, PULL:UP | | | PB2A | |
|
||||
| 30/1 | unused, PULL:UP | | | PB2B | |
|
||||
| 32/1 | CROW[0] | LOCATED | LVTTL33_IN | PB2C | |
|
||||
| 34/1 | CROW[1] | LOCATED | LVTTL33_IN | PB2D | |
|
||||
| 36/1 | unused, PULL:UP | | | PB3A | PCLKT1_1 |
|
||||
| 37/1 | MAin[2] | LOCATED | LVTTL33_IN | PB3B | |
|
||||
| 38/1 | MAin[1] | LOCATED | LVTTL33_IN | PB3C | PCLKT1_0 |
|
||||
| 39/1 | PHI2 | LOCATED | LVTTL33_IN | PB3D | |
|
||||
| 43/1 | nCRAS | LOCATED | LVTTL33_IN | PB4A | |
|
||||
| 44/1 | MAin[7] | LOCATED | LVTTL33_IN | PB4B | |
|
||||
| 45/1 | MAin[5] | LOCATED | LVTTL33_IN | PB4C | |
|
||||
| 46/1 | MAin[4] | LOCATED | LVTTL33_IN | PB4D | |
|
||||
| 47/1 | MAin[3] | LOCATED | LVTTL33_IN | PB5A | |
|
||||
| 49/1 | MAin[6] | LOCATED | LVTTL33_IN | PB5C | |
|
||||
| 50/1 | MAin[8] | LOCATED | LVTTL33_IN | PB5D | |
|
||||
| 51/0 | MAin[9] | LOCATED | LVTTL33_IN | PR9B | |
|
||||
| 52/0 | unused, PULL:UP | | | PR9A | |
|
||||
| 53/0 | nUFMCS | LOCATED | LVTTL33_OUT | PR8B | |
|
||||
| 54/0 | unused, PULL:UP | | | PR8A | |
|
||||
| 55/0 | UFMSDO | LOCATED | LVTTL33_IN | PR7D | |
|
||||
| 56/0 | UFMSDI | LOCATED | LVTTL33_OUT | PR7C | |
|
||||
| 57/0 | LED | LOCATED | LVTTL33_OUT | PR7B | |
|
||||
| 58/0 | UFMCLK | LOCATED | LVTTL33_OUT | PR7A | |
|
||||
| 59/0 | unused, PULL:UP | | | PR6B | |
|
||||
| 61/0 | RDQML | LOCATED | LVTTL33_OUT | PR6A | |
|
||||
| 63/0 | RBA[0] | LOCATED | LVTTL33_OUT | PR5D | |
|
||||
| 64/0 | RD[0] | LOCATED | LVTTL33_BIDI | PR5C | |
|
||||
| 65/0 | RD[1] | LOCATED | LVTTL33_BIDI | PR5B | |
|
||||
| 66/0 | RD[2] | LOCATED | LVTTL33_BIDI | PR5A | |
|
||||
| 67/0 | RD[3] | LOCATED | LVTTL33_BIDI | PR4B | |
|
||||
| 68/0 | RD[4] | LOCATED | LVTTL33_BIDI | PR4A | |
|
||||
| 69/0 | RD[5] | LOCATED | LVTTL33_BIDI | PR3D | |
|
||||
| 70/0 | RD[6] | LOCATED | LVTTL33_BIDI | PR3C | |
|
||||
| 71/0 | RD[7] | LOCATED | LVTTL33_BIDI | PR3B | |
|
||||
| 72/0 | nRWE | LOCATED | LVTTL33_OUT | PR3A | |
|
||||
| 73/0 | nRRAS | LOCATED | LVTTL33_OUT | PR2B | |
|
||||
| 76/0 | RDQMH | LOCATED | LVTTL33_OUT | PR2A | |
|
||||
| 77/0 | nRCS | LOCATED | LVTTL33_OUT | PT5C | |
|
||||
| 78/0 | nRCAS | LOCATED | LVTTL33_OUT | PT5B | |
|
||||
| 79/0 | RA[11] | LOCATED | LVTTL33_OUT | PT5A | |
|
||||
| 80/0 | unused, PULL:UP | | | PT4F | |
|
||||
| 81/0 | unused, PULL:UP | | | PT4E | |
|
||||
| 82/0 | RCKE | LOCATED | LVTTL33_OUT | PT4D | |
|
||||
| 83/0 | RBA[1] | LOCATED | LVTTL33_OUT | PT4C | |
|
||||
| 85/0 | RA[9] | LOCATED | LVTTL33_OUT | PT4B | PCLKT0_1 |
|
||||
| 86/0 | RCLK | LOCATED | LVTTL33_IN | PT4A | PCLKT0_0 |
|
||||
| 87/0 | RA[10] | LOCATED | LVTTL33_OUT | PT3D | |
|
||||
| 89/0 | RA[1] | LOCATED | LVTTL33_OUT | PT3C | |
|
||||
| 91/0 | RA[6] | LOCATED | LVTTL33_OUT | PT3B | |
|
||||
| 94/0 | RA[2] | LOCATED | LVTTL33_OUT | PT3A | |
|
||||
| 95/0 | RA[5] | LOCATED | LVTTL33_OUT | PT2F | |
|
||||
| 96/0 | RA[8] | LOCATED | LVTTL33_OUT | PT2E | |
|
||||
| 97/0 | RA[3] | LOCATED | LVTTL33_OUT | PT2D | |
|
||||
| 98/0 | RA[0] | LOCATED | LVTTL33_OUT | PT2C | |
|
||||
| 99/0 | RA[4] | LOCATED | LVTTL33_OUT | PT2B | |
|
||||
| 100/0 | RA[7] | LOCATED | LVTTL33_OUT | PT2A | |
|
||||
| PB5B/0 | unused, PULL:UP | | | PB5B | |
|
||||
| PT5D/0 | unused, PULL:UP | | | PT5D | |
|
||||
| TCK/1 | | | | TCK | TCK |
|
||||
| TDI/1 | | | | TDI | TDI |
|
||||
| TDO/1 | | | | TDO | TDO |
|
||||
| TMS/1 | | | | TMS | TMS |
|
||||
+----------+---------------------+------------+--------------+------+---------------+
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "32";
|
||||
LOCATE COMP "CROW[1]" SITE "34";
|
||||
LOCATE COMP "Din[0]" SITE "21";
|
||||
LOCATE COMP "Din[1]" SITE "15";
|
||||
LOCATE COMP "Din[2]" SITE "14";
|
||||
LOCATE COMP "Din[3]" SITE "16";
|
||||
LOCATE COMP "Din[4]" SITE "18";
|
||||
LOCATE COMP "Din[5]" SITE "17";
|
||||
LOCATE COMP "Din[6]" SITE "20";
|
||||
LOCATE COMP "Din[7]" SITE "19";
|
||||
LOCATE COMP "Dout[0]" SITE "1";
|
||||
LOCATE COMP "Dout[1]" SITE "7";
|
||||
LOCATE COMP "Dout[2]" SITE "8";
|
||||
LOCATE COMP "Dout[3]" SITE "6";
|
||||
LOCATE COMP "Dout[4]" SITE "4";
|
||||
LOCATE COMP "Dout[5]" SITE "5";
|
||||
LOCATE COMP "Dout[6]" SITE "2";
|
||||
LOCATE COMP "Dout[7]" SITE "3";
|
||||
LOCATE COMP "LED" SITE "57";
|
||||
LOCATE COMP "MAin[0]" SITE "23";
|
||||
LOCATE COMP "MAin[1]" SITE "38";
|
||||
LOCATE COMP "MAin[2]" SITE "37";
|
||||
LOCATE COMP "MAin[3]" SITE "47";
|
||||
LOCATE COMP "MAin[4]" SITE "46";
|
||||
LOCATE COMP "MAin[5]" SITE "45";
|
||||
LOCATE COMP "MAin[6]" SITE "49";
|
||||
LOCATE COMP "MAin[7]" SITE "44";
|
||||
LOCATE COMP "MAin[8]" SITE "50";
|
||||
LOCATE COMP "MAin[9]" SITE "51";
|
||||
LOCATE COMP "PHI2" SITE "39";
|
||||
LOCATE COMP "RA[0]" SITE "98";
|
||||
LOCATE COMP "RA[10]" SITE "87";
|
||||
LOCATE COMP "RA[11]" SITE "79";
|
||||
LOCATE COMP "RA[1]" SITE "89";
|
||||
LOCATE COMP "RA[2]" SITE "94";
|
||||
LOCATE COMP "RA[3]" SITE "97";
|
||||
LOCATE COMP "RA[4]" SITE "99";
|
||||
LOCATE COMP "RA[5]" SITE "95";
|
||||
LOCATE COMP "RA[6]" SITE "91";
|
||||
LOCATE COMP "RA[7]" SITE "100";
|
||||
LOCATE COMP "RA[8]" SITE "96";
|
||||
LOCATE COMP "RA[9]" SITE "85";
|
||||
LOCATE COMP "RBA[0]" SITE "63";
|
||||
LOCATE COMP "RBA[1]" SITE "83";
|
||||
LOCATE COMP "RCKE" SITE "82";
|
||||
LOCATE COMP "RCLK" SITE "86";
|
||||
LOCATE COMP "RDQMH" SITE "76";
|
||||
LOCATE COMP "RDQML" SITE "61";
|
||||
LOCATE COMP "RD[0]" SITE "64";
|
||||
LOCATE COMP "RD[1]" SITE "65";
|
||||
LOCATE COMP "RD[2]" SITE "66";
|
||||
LOCATE COMP "RD[3]" SITE "67";
|
||||
LOCATE COMP "RD[4]" SITE "68";
|
||||
LOCATE COMP "RD[5]" SITE "69";
|
||||
LOCATE COMP "RD[6]" SITE "70";
|
||||
LOCATE COMP "RD[7]" SITE "71";
|
||||
LOCATE COMP "UFMCLK" SITE "58";
|
||||
LOCATE COMP "UFMSDI" SITE "56";
|
||||
LOCATE COMP "UFMSDO" SITE "55";
|
||||
LOCATE COMP "nCCAS" SITE "27";
|
||||
LOCATE COMP "nCRAS" SITE "43";
|
||||
LOCATE COMP "nFWE" SITE "22";
|
||||
LOCATE COMP "nRCAS" SITE "78";
|
||||
LOCATE COMP "nRCS" SITE "77";
|
||||
LOCATE COMP "nRRAS" SITE "73";
|
||||
LOCATE COMP "nRWE" SITE "72";
|
||||
LOCATE COMP "nUFMCS" SITE "53";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Mon Aug 16 21:32:33 2021
|
||||
|
|
@ -0,0 +1,211 @@
|
|||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
|
||||
Mon Aug 16 21:32:27 2021
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
|
||||
Preference file: RAM2GS_LCMXO256C_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO256C
|
||||
Package: TQFP100
|
||||
Performance: 3
|
||||
Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.19.
|
||||
Performance Hardware Data Status: Version 1.124.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 67/79 84% used
|
||||
67/78 85% bonded
|
||||
SLICE 65/128 50% used
|
||||
|
||||
|
||||
|
||||
Number of Signals: 252
|
||||
Number of Connections: 618
|
||||
|
||||
Pin Constraint Summary:
|
||||
67 out of 67 pins locked (100% locked).
|
||||
|
||||
The following 4 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 39)
|
||||
PHI2_c (driver: PHI2, clk load #: 13)
|
||||
nCCAS_c (driver: nCCAS, clk load #: 4)
|
||||
nCRAS_c (driver: nCRAS, clk load #: 7)
|
||||
|
||||
No signal is selected as secondary clock.
|
||||
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
........
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
...............
|
||||
Placer score = 586066.
|
||||
Finished Placer Phase 1. REAL time: 6 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 584668
|
||||
Finished Placer Phase 2. REAL time: 6 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 1 out of 4 (25%)
|
||||
General PIO: 3 out of 80 (3%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 39
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13
|
||||
PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PL9B)", clk load = 4
|
||||
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7
|
||||
|
||||
PRIMARY : 4 out of 4 (100%)
|
||||
SECONDARY: 0 out of 4 (0%)
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
67 out of 79 (84.8%) PIO sites used.
|
||||
67 out of 78 (85.9%) bonded PIO sites used.
|
||||
Number of PIO comps: 67; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+------------+------------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 |
|
||||
+----------+----------------+------------+------------+------------+
|
||||
| 0 | 36 / 41 ( 87%) | 3.3V | - | - |
|
||||
| 1 | 31 / 37 ( 83%) | 3.3V | - | - |
|
||||
+----------+----------------+------------+------------+------------+
|
||||
|
||||
Total placer CPU time: 6 secs
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 618 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
|
||||
|
||||
Completed router resource preassignment. Real time: 6 secs
|
||||
|
||||
Start NBR router at 21:32:33 08/16/21
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 21:32:33 08/16/21
|
||||
|
||||
Start NBR section for initial routing at 21:32:33 08/16/21
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.038ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 21:32:33 08/16/21
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 2
|
||||
4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 3
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21
|
||||
|
||||
Start NBR section for re-routing at 21:32:33 08/16/21
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
||||
|
||||
Start NBR section for post-routing at 21:32:33 08/16/21
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 2.023ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 6 secs
|
||||
Total REAL time: 7 secs
|
||||
Completely routed.
|
||||
End of route. 618 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 2.023
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.339
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 6 secs
|
||||
Total REAL time to completion: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|
@ -0,0 +1,33 @@
|
|||
[ActiveSupport PAR]
|
||||
; Global primary clocks
|
||||
GLOBAL_PRIMARY_USED = 4;
|
||||
; Global primary clock #0
|
||||
GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
|
||||
GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
|
||||
GLOBAL_PRIMARY_0_LOADNUM = 39;
|
||||
; Global primary clock #1
|
||||
GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
|
||||
GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_1_LOADNUM = 13;
|
||||
; Global primary clock #2
|
||||
GLOBAL_PRIMARY_2_SIGNALNAME = nCCAS_c;
|
||||
GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_2_LOADNUM = 4;
|
||||
; Global primary clock #3
|
||||
GLOBAL_PRIMARY_3_SIGNALNAME = nCRAS_c;
|
||||
GLOBAL_PRIMARY_3_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_3_LOADNUM = 7;
|
||||
; # of global secondary clocks
|
||||
GLOBAL_SECONDARY_USED = 0;
|
||||
; I/O Bank 0 Usage
|
||||
BANK_0_USED = 36;
|
||||
BANK_0_AVAIL = 41;
|
||||
BANK_0_VCCIO = 3.3V;
|
||||
BANK_0_VREF1 = NA;
|
||||
BANK_0_VREF2 = NA;
|
||||
; I/O Bank 1 Usage
|
||||
BANK_1_USED = 31;
|
||||
BANK_1_AVAIL = 37;
|
||||
BANK_1_VCCIO = 3.3V;
|
||||
BANK_1_VREF1 = NA;
|
||||
BANK_1_VREF2 = NA;
|
|
@ -0,0 +1,28 @@
|
|||
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Mon Aug 16 21:32:27 2021
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
|
||||
RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
|
||||
RAM2GS_LCMXO256C_impl1.prf -gui -msgset
|
||||
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2GS_LCMXO256C_impl1.prf.
|
||||
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 2.023 0 0.339 0 07 Completed
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
|
@ -0,0 +1 @@
|
|||
DRC detected 0 errors and 0 warnings.
|
|
@ -0,0 +1,977 @@
|
|||
|
||||
*
|
||||
NOTE JEDEC CREATED BY: Lattice Semiconductor Diamond Deployment Tool 3.12*
|
||||
NOTE Version: Diamond (64-bit) 3.12.0.240.2*
|
||||
NOTE Readback: Off*
|
||||
NOTE Security: Off*
|
||||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Mon Aug 16 21:36:26 2021 *
|
||||
NOTE DESIGN NAME: RAM2GS *
|
||||
NOTE DEVICE NAME: LCMXO256C-3TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS RD[7] : 71 : inout *
|
||||
NOTE PINS RD[6] : 70 : inout *
|
||||
NOTE PINS RD[5] : 69 : inout *
|
||||
NOTE PINS RD[4] : 68 : inout *
|
||||
NOTE PINS RD[3] : 67 : inout *
|
||||
NOTE PINS RD[2] : 66 : inout *
|
||||
NOTE PINS RD[1] : 65 : inout *
|
||||
NOTE PINS RD[0] : 64 : inout *
|
||||
NOTE PINS Dout[7] : 3 : out *
|
||||
NOTE PINS Dout[6] : 2 : out *
|
||||
NOTE PINS Dout[5] : 5 : out *
|
||||
NOTE PINS Dout[4] : 4 : out *
|
||||
NOTE PINS Dout[3] : 6 : out *
|
||||
NOTE PINS Dout[2] : 8 : out *
|
||||
NOTE PINS Dout[1] : 7 : out *
|
||||
NOTE PINS Dout[0] : 1 : out *
|
||||
NOTE PINS LED : 57 : out *
|
||||
NOTE PINS RBA[1] : 83 : out *
|
||||
NOTE PINS RBA[0] : 63 : out *
|
||||
NOTE PINS RA[11] : 79 : out *
|
||||
NOTE PINS RA[10] : 87 : out *
|
||||
NOTE PINS RA[9] : 85 : out *
|
||||
NOTE PINS RA[8] : 96 : out *
|
||||
NOTE PINS RA[7] : 100 : out *
|
||||
NOTE PINS RA[6] : 91 : out *
|
||||
NOTE PINS RA[5] : 95 : out *
|
||||
NOTE PINS RA[4] : 99 : out *
|
||||
NOTE PINS RA[3] : 97 : out *
|
||||
NOTE PINS RA[2] : 94 : out *
|
||||
NOTE PINS RA[1] : 89 : out *
|
||||
NOTE PINS RA[0] : 98 : out *
|
||||
NOTE PINS nRCS : 77 : out *
|
||||
NOTE PINS RCKE : 82 : out *
|
||||
NOTE PINS nRWE : 72 : out *
|
||||
NOTE PINS nRRAS : 73 : out *
|
||||
NOTE PINS nRCAS : 78 : out *
|
||||
NOTE PINS RDQMH : 76 : out *
|
||||
NOTE PINS RDQML : 61 : out *
|
||||
NOTE PINS nUFMCS : 53 : out *
|
||||
NOTE PINS UFMCLK : 58 : out *
|
||||
NOTE PINS UFMSDI : 56 : out *
|
||||
NOTE PINS PHI2 : 39 : in *
|
||||
NOTE PINS MAin[9] : 51 : in *
|
||||
NOTE PINS MAin[8] : 50 : in *
|
||||
NOTE PINS MAin[7] : 44 : in *
|
||||
NOTE PINS MAin[6] : 49 : in *
|
||||
NOTE PINS MAin[5] : 45 : in *
|
||||
NOTE PINS MAin[4] : 46 : in *
|
||||
NOTE PINS MAin[3] : 47 : in *
|
||||
NOTE PINS MAin[2] : 37 : in *
|
||||
NOTE PINS MAin[1] : 38 : in *
|
||||
NOTE PINS MAin[0] : 23 : in *
|
||||
NOTE PINS CROW[1] : 34 : in *
|
||||
NOTE PINS CROW[0] : 32 : in *
|
||||
NOTE PINS Din[7] : 19 : in *
|
||||
NOTE PINS Din[6] : 20 : in *
|
||||
NOTE PINS Din[5] : 17 : in *
|
||||
NOTE PINS Din[4] : 18 : in *
|
||||
NOTE PINS Din[3] : 16 : in *
|
||||
NOTE PINS Din[2] : 14 : in *
|
||||
NOTE PINS Din[1] : 15 : in *
|
||||
NOTE PINS Din[0] : 21 : in *
|
||||
NOTE PINS nCCAS : 27 : in *
|
||||
NOTE PINS nCRAS : 43 : in *
|
||||
NOTE PINS nFWE : 22 : in *
|
||||
NOTE PINS RCLK : 86 : in *
|
||||
NOTE PINS UFMSDO : 55 : in *
|
||||
NOTE CONFIGURATION MODE: NONE *
|
||||
NOTE COMPRESSION: off *
|
||||
|
||||
|
||||
QF56640*
|
||||
G0*
|
||||
F0*
|
||||
L00000
|
||||
11111111001011111111011110111100101111111101111011110010111111110111101111001011
|
||||
11111101111011111111111111111111101111001010010011110111011100101001001111011110
|
||||
11001010010011110111101111111111
|
||||
11111111001011111111011110111100101111111101111011110010111111110111101111001011
|
||||
11111101111011111111111111111111101111001010010011110111011100101001001111011101
|
||||
11001010010011110111011111111111
|
||||
11111111111111111111111111111111111111111111111111110010111111110111101111111111
|
||||
11111111111111111111111111111111101111111111111111111111111100101001001111011101
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111110010111111110111101111111111
|
||||
11111111111111110010111111110111101111111111111111111111111100101001001111011101
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111110111111111111111111111111111111111
|
||||
11111111111110111111111111111011111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111011111111111111111111111111111111
|
||||
11111111111110111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111100111111011111111111111111111111111111111011111111111101111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111101111111111111111111111111111111111111111111111111111101111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111101111111111111111111111111111111111111111111111111111111
|
||||
11110111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111011111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111101111111111111111110111111111001111101111111111111111111
|
||||
11011111111111111011111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111011111111101111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111011111111101111111111111111111110111
|
||||
11111111111111111101111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111110111111111111111111111111111111111111111111111111111111111110111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111110001111111111111111111111111101111111111111111111111111111111111
|
||||
11111111111111111110111111111111
|
||||
11111111111111111111111111111111111111111111111111110111111111100101111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111110111111111011
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111110111111111111101111111111111
|
||||
11111111111111111111111111111111111111111110111111111110111111111111111111101111
|
||||
11111111111111111011111111111111
|
||||
11111111111111111111100111111111111111111111111111111111111111001111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111101111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111110111111111111011111111101111111111111111111101111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11110101101111111110111110111011110110111111111111100111111111101111111111010101
|
||||
11111011111111111111111101111001
|
||||
11011111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111001110111110111111111011111011101111111111111101101111101101111111110111011
|
||||
01010011111111111111111111111001
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111110110111110111111111110111111101111111111111111011111111111111111110110111
|
||||
01010111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111110111111110010111111111111111111101111111110111111111110111111
|
||||
11111111111111111111111111111010
|
||||
11111111111111111111111111111111111111111111111111111111111111110111111111111111
|
||||
11111101011010110110111100010110111111111111111011111111111111100111111011111111
|
||||
11010010111111111111111010111111
|
||||
11111111111111111111111111111111111111111111111111111111111111110111111111111111
|
||||
11111111111111111000100111000111011110111111111011111111111110101011111100110111
|
||||
11110010110111111101110111011011
|
||||
11111111111111111111111111111111111111111111111111111111111111101111111111111111
|
||||
11111111110111011100111101111111011101111111111101011101111111001111011111110111
|
||||
01110011110111111111111101011001
|
||||
11111111111111111111111111111111111111111111111111111111111110111111111111111111
|
||||
11111011111101111100111111111111011111111111111111111111111111001101111111111011
|
||||
11110011001111111101111101111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11110101111011111000111111100111111111111111111110001111111110101111111111110001
|
||||
11101111001111111111111111111001
|
||||
11011111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111101111101101000001001110111111111111111111111011111111110101111111111111111
|
||||
11100010110111111111111111111001
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111011111111011111010101111111111111111111111110111111111111001111111111111111
|
||||
01110011111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111000111101101111111111111111111111111111111110111111111111111101
|
||||
11111111111111111101111111111011
|
||||
11111101111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11011111111111111100111111101111111111111111101111011111111111101110011101111111
|
||||
11110011111111111111111111111111
|
||||
11111011111111111111111111111111111111111111111111111111111111111111111111111110
|
||||
11011111111111101100111111110011111111111110010111011111111111101111011111111111
|
||||
11110011111111111111111111111011
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111101
|
||||
00011111111111010111111111111111011111111110111111111111111101001011011111111111
|
||||
11011111111111111101111111111001
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11011111111111111100111111111111111111111111110010111111111111111111011011111111
|
||||
11111111111111111111111111111101
|
||||
01111111111111111111111111111111111111111111111111111111111111111011011111111111
|
||||
11111111111110011101011011111111011101111111111111111101100111001111111110111111
|
||||
11111111111110011110111111111001
|
||||
01011111111111111111111111111111111111111111111111111111111111111111111111011111
|
||||
11111111111011010101101101111111011000011111111111011100110101001111011111111111
|
||||
11111110000111011111011111111001
|
||||
11111111111111111111111111111111111111111111111111111111111111111100111111110011
|
||||
11111111111111111101111101111111111111111111111111111111111111011111111111111111
|
||||
11111111111110111111110011111111
|
||||
01110011111111111111111111111111111111111111111111111111111111111111111111100011
|
||||
11111111111111111001110111111010111111101111111011101011111110011110111111011111
|
||||
11111101110111111111111111111010
|
||||
10111111111111111111111111111111111111111111111111111111111111111111111111111011
|
||||
10011011101111111100111011010111011100111111110010110111111111001111111101111111
|
||||
11111111111011001111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111101010
|
||||
11011101110111111100000101100111111001101011111101011101111111001111111100111111
|
||||
11111111111111001111111111111011
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111011
|
||||
11011111111111111100011101111111111111111111110011001101111111011111111011110111
|
||||
11111111111101110101111111111001
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111011
|
||||
01111111111111111100111101111110111111101111111111111111111110011111101111111111
|
||||
11111111111010111111111101111111
|
||||
01111111111111111111111111111111111111111111111111111111111111111111111111101111
|
||||
11111111111111111011111111100101011001100011111111111111111110011111111111111111
|
||||
11111111111111111111111111111001
|
||||
01011111111111111111111111111111111111111111111111111111111111111111111111101011
|
||||
11111111111111111100111111100011011100100011111111111111111111001111111111111111
|
||||
11111111111111101011111111111001
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111100111111111011011111111111111111111111111111101111111111111111
|
||||
11111111111111101111110011111110
|
||||
01111111111111111111111111111111111111111111111111111111111111111111111111101111
|
||||
11111111111111111111111111111010111111100011111111111111111100111111111111111111
|
||||
11111111111111100101111111111011
|
||||
10111111111111111111111111111111111111111111111111111111111111101111111111111111
|
||||
11110101111111111111011111110111011111110011111011111111100111011111111111111111
|
||||
01111111111011111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111110111111111111111
|
||||
11111001111111111111111101111110111111110011111111111111111111001111111111111111
|
||||
11111100010111111111111111111011
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111011111
|
||||
11111111111111110111111001101111111111011111111001011111111101101111111111111111
|
||||
11111110110111011111111111111001
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111111111110011111111111111111111111111111111111110
|
||||
11111111100101011111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111100111111111111111
|
||||
11111111111111111111111111110111111111111101011111111101111111111110111111111111
|
||||
01111111111111111111111111111001
|
||||
11111111111111111111111111111111111111111111111111111111111111110111111111111111
|
||||
11111111111111110111111001111111111111111110110111111111111111111111011111111011
|
||||
01011011111111111111111111111001
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111101100111111011111111111011111111111110
|
||||
11110011111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111101111111111111110
|
||||
11011111111111111011011101101111111111111111110111111111111111111111011111111111
|
||||
11100111111111111111111111111011
|
||||
11111111111111111111011111111111111111111111111111111111111111111111111111111111
|
||||
11111011111111111111010111111111111111111111111111011111111111111111010101111111
|
||||
11111110011111111111110111111111
|
||||
11111111111111111111011111111111111111111111111111111111111111111111111111111111
|
||||
11111101111111111111101111111111111111111111111111011111111111111001011001111111
|
||||
11101010111111111111110111111011
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111110111101111111111111111111111110111111111111111111011111111111
|
||||
11110011110111111110101111111001
|
||||
11111111111111111010111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111011111111111111111111111111111011111111111111111110111111111111
|
||||
11110111111111111111111111111101
|
||||
11111111111111111111111111111111111111111111111111111111111111111111011111111111
|
||||
11111111111111111001111111111111111111111111111110011111111111111111111111111011
|
||||
11100011101111111111111111111001
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111100011101111111111111111111111111011111111111111111111111111101
|
||||
10100011110111111111111111111001
|
||||
11111111111111111111111111111111111111111111111111111111111111111110111111111111
|
||||
11111111111111111100111001111111111111111111111110111111111111111111111111111111
|
||||
01110110111111111111111101111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111000111111111111111111111111111111111111111111111111111111111111
|
||||
11100111110111111111111101111010
|
||||
11111111111111111111111111111111111111111111111111111111111111010111111111111111
|
||||
11111111111001111100111111111111101100111111111111110100111111111111111011111111
|
||||
11111011111111111110101111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111110111111111111111
|
||||
11111111111101111100111111111111110001111111111111111101111111111111111101111111
|
||||
01111011111111111111111111111011
|
||||
11111111111111111111111111111111111111111111111111111111111111101111111111111111
|
||||
11111111111111010100111111111111111101111111111111111011111111111111111111111011
|
||||
11011111111111111111110111111001
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111100111111111111101111111111111111111111011111111111111111111111
|
||||
11111111111111111111011111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111001101111111111111111111111111111111111111111111111111111
|
||||
11111101011110111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111101101110111100111111111111111111111111111111111111111111010
|
||||
11111110111111011111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111101111111110111111111111111111111111111111111111111111101
|
||||
11111111110111111110111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111010101111111101111111111111111111111111111111111111111111011
|
||||
11111111111111111111110111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111110111111111111110
|
||||
10110101111111111111101111110111111111111110111101011111111111111111101111001111
|
||||
11111111111011111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111110
|
||||
11011001111111111111101111110001111111111110111110011111111111110011011110010111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111101111111111111111
|
||||
11011111111111111111111101111001101111111111110111011111111111110101011100111111
|
||||
11111111111111011111111101111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
01111111111111111111110110101111111101111111011111011111111111111110010101111111
|
||||
11111111111101011111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111110111111111111111
|
||||
11111111111111111111111111101111111111111111111110011111111111111111111111100111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111110111111111111111111111011111111111111111111111110111
|
||||
11111111111111111111111101111111
|
||||
11111111111111111111111111111111111111111111111111111111111111101111111111111111
|
||||
11111111111111111111111111111111111111111111111110111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111101111
|
||||
11111111111111111111111100111111
|
||||
11111111111111111111111111111111111111110111111111111111111111111101011111111111
|
||||
11111111111111111111111110111110111111111111111110011111111111111111101000110111
|
||||
11111101001111111111111111111111
|
||||
11111111111111111111111111111111111111111101111111111111111111111111011111111111
|
||||
11111111111111111111001101111111011111111111111111011111111111110011011101101111
|
||||
11111110110111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111110111111111111
|
||||
11111111111111111111111101110111111111111111111110111111111111110111001001011111
|
||||
11111110110111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111110011010111111111111111111111111111111111111100010111111111
|
||||
11111111110111111111111111011111
|
||||
11111111111111111111111111111110001111111011111111111111111111111111111111011011
|
||||
11101111111111111111111110110100111111111111111010011111111111111111101111111111
|
||||
11111111111110011000111111111001
|
||||
11011111111111111111111111111110111000011101111111111111111111111111111111011011
|
||||
11110111111111110100001101101011011111011011111111011111111111111111110111111111
|
||||
11111111111111001101111011111001
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111011
|
||||
11111101111111110100011100010011111111111011111101111111111111111111111101111111
|
||||
11111111111111101111010111111110
|
||||
11111111111111111111111111111111001111111111111111111111111111111111111111101011
|
||||
11111101111111111111110001111111011111101111111110111111111111111111111101111111
|
||||
11111111111110100101111111111011
|
||||
11111111111111111111111111111111001111111101101111111111111111111111111111110011
|
||||
00111001011011110101111110100110101110111101011011011110010111111111111111111111
|
||||
11111111111111110111111111111111
|
||||
11111111111111111111111111111110111111111111110111111111111111111111111111100000
|
||||
11011101110111001100101101100111011100111110110110011101010111111111111111111111
|
||||
11111111111111111111111111111011
|
||||
11111111111111111111111111111111111111111011110111111111111111111111111111110001
|
||||
11011011110111011100111111111111011101111111110011001110110111111111111111111111
|
||||
11111111111111111101111111111001
|
||||
11111111111111111111111111111111111111111111110111111111111111111111111111110011
|
||||
11011111110101011000110011011111110111101110100001111111101111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
01111111111111111111111111111110001111111111111111111111111111110111111111101111
|
||||
11111111111111001011111110111111001111101111111110011111111111111111101111111111
|
||||
11111111111110011111111111111001
|
||||
01011111111111111111111111111110001111111111111111111111111111111111111111101110
|
||||
10011111111110011011111111110111111111111111111111011111111111111111110111111111
|
||||
11111111111110011111111111111001
|
||||
11111111111111111111111111111111001111111111111111111111111111111111111111111110
|
||||
11111111111111111111101110110111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111110
|
||||
01111111111111111111111111111111111111111111111111111111111111101111111111111111
|
||||
01011111111111111111111100011111010111001111111110111111111111111111111111111111
|
||||
11111111111111111111111111111011
|
||||
10111111111111111111011111111111111111111111110111111111111111111111111111111111
|
||||
10111101111111011111111010111111111101111011111011011011111111111111111111111111
|
||||
11111110111111111111111111111111
|
||||
11111111111111111111011111111111001111111111110111111111111111111111111111110111
|
||||
11011100111110001111100101011111011110111111111101001111111111111111111111111111
|
||||
11111110000111111111111111111011
|
||||
11100111111111111111111111111110001111111111110111111111111111111111111111010111
|
||||
11111011110011010100101111111111011101011111111110111101111111111111111111111111
|
||||
11111110110111111111111111111001
|
||||
11111111111111111010111111111110111111111111101111111111111111111111111111111111
|
||||
11101111111111111111111101111110111011111111111011111101111111111111111111111111
|
||||
11111111110111111111111111111111
|
||||
01111111111111111111111111111111111111111111111111111111111111110111111111111111
|
||||
11111101111111111111110110110110111111111101111010011111111111111111101111111111
|
||||
11111111111011100101111111111001
|
||||
01011111111111111111111111111110001000011111111111111111111111101111111111011111
|
||||
11011011111111110111001110110111011111111111100101011111111111111111110101111111
|
||||
11010011111101110101111111111001
|
||||
11111111111111111111111111111111001111111111111111111111111111111111111111011111
|
||||
11111111111111111111111101100111111111111101110110111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
01111111111111111111111111111111111111111111111111111111111111111111111111011101
|
||||
10011111111111111011101100011111111111111111110111111111111111111111101111111111
|
||||
11101111111111111011111111111011
|
||||
10111111111111111111111111111111111111111001111111111111111111110111111111011111
|
||||
10111101111111011111011111010111101111111111111001011111111111111111110101111111
|
||||
11111110011111001111111111111111
|
||||
11111111111111111111111111111110001111111101111111111111111111100111111111111111
|
||||
11011111111111011011111110110111111111111111111111011111111111111111111101111111
|
||||
11100010111111001111111111111011
|
||||
11111111111111111111111111111111001111111111111111111111111111111111111111111111
|
||||
11111111111010111111111101100111110101111111111010011111111111111111111011111111
|
||||
11110011110111110101111111111001
|
||||
11111111111111111111111111111111001111111011111111111111111110111111111111101101
|
||||
11011011111111111101111111111111111101111111111101111111111111111111111111111111
|
||||
11110011111010111111111111111101
|
||||
01111111111111111111111111111110001111111111111111111111111111110111111111101111
|
||||
11101000011111011011111101010111111111111111111011011111110111111111101001111111
|
||||
11101111111111011111111101011001
|
||||
01011111111111111111111111111110001111111111111111111111111111101111111111100111
|
||||
11111000110111011011101101100111111111111111111010111111110111111111110101111111
|
||||
11100011111111111111111111111001
|
||||
11111111111111111111111111111111001111111111111111111111111111111111111111111111
|
||||
11110110111010111110111101111111111111111111111111011110100111111111111111111111
|
||||
11111011111111111111111110111110
|
||||
01111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111110100111111010010001111111111111111111111101111111110111111111111011111111
|
||||
11101011111110111111111111111011
|
||||
10111111111111111111111111111111111111111001111110011111111111111101011111111111
|
||||
10111001010111111111111110110111111001111111111101011110110111111111101111111111
|
||||
11111111111111011110011101111111
|
||||
11111111111111111111111111111111001111111101111011011111111111111111011111111110
|
||||
11011101110111111111001101111111101101111111111011011100110111111111100101111111
|
||||
11110011111110111111111111111011
|
||||
11111111111111111111111111111110001111111111111111111111111111111110111111011101
|
||||
01111111111111110110111100110111111111111111111110011111111111111111111101111111
|
||||
11011011111111111111110111111001
|
||||
11111111111111111111111111111110111111111011111111111111111111111111111111111111
|
||||
11011011101111111110100001001111111111111111111111101111001111111111101111111111
|
||||
11111011111111111111110111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111110111111111111011
|
||||
11111101111111111111011111101111101111111111111010011111111011111111101111111111
|
||||
11111110111111111111111111111111
|
||||
11111111111111111111111111111110001000011111111111111111111111101111111111011111
|
||||
11011111111111110111100111110111111110111111111111011111110111111111111111111111
|
||||
11111110011111111111111111111111
|
||||
11111111111111111111111111111111001111111111111111111111111111111111111111111101
|
||||
11111011111111110100111100110111111101111111111100011111111111111111110101111111
|
||||
11111111110111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111101111
|
||||
10011111111111111100111111111111110111111111111111011111111111111111111101111111
|
||||
11111110110111111111111111111111
|
||||
11111111111111111111111111111111111111111001111111111111111111100111111111110001
|
||||
00111111111111010100111100110110111111111111111011111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111110001111111101111111111111111111110111111111111110
|
||||
11011111111011011000101111110001011111111110010111111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111001111111111111111111111111111101111111111111111
|
||||
11011111111111111100111100000011111111111110111011011111111111111111101101111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111001111111011111111111111111111111111111111101110
|
||||
11011111111110111000110110111101111111111111100101111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111110001111111011111111111111111111110111111111101011
|
||||
01111111111011111011111010111111101101111111111011111111110111111111111111110111
|
||||
11111111111011111111111101111111
|
||||
11111111111111111111111111111110001111111101111111111111111111101111111111110000
|
||||
11011111111101101011101101011111111111111111111101111101100111111111111111111111
|
||||
11111111111101111111110111111111
|
||||
11111111111111111111111101111111001111111111111111111111111111111111111111111111
|
||||
10011111111111011111110111110111111111111111111111111110111111111111111111101111
|
||||
11111111111111011111111111111111
|
||||
11111111111111111111111101111111111111111111111111111111111111111111111111101111
|
||||
11111111111111111111011101110111110011111111111111101111111111111111111111111111
|
||||
11111111111111011111110111111111
|
||||
11111011111111111111111111111111111111111001111111111111111111110111111111111111
|
||||
11110111111111111110110010010111110111111111111011011111111111111111110101111111
|
||||
11111111111111111111111111111111
|
||||
11110111111111111111111111111111001111111101111111111111111111100111111111110111
|
||||
11111101111111111111001101110111111111111111111100111111111111111111111001111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111110001111111011111111111111111111111111111111011111
|
||||
11111111111111110111011101101111111101111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111110111111111111111111111111111110111111111111111111
|
||||
11111111111111111111111101011111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111110111111111111111
|
||||
11111111111111111111111010111111101111111111111011111111111011111111101111111111
|
||||
11111111111010011111111111111111
|
||||
11111111111111111111111111111110001000011111111111111111111111101111111111111110
|
||||
11011111111111100111111101111111111111111111111101111111111111111111100111111111
|
||||
11111111111101011111111111111111
|
||||
11111100111111111111111111111111001111111111111111111111111111111111111111111101
|
||||
01111101111111111111101110010111101111111111111011011110111111111111111101111111
|
||||
11111111111111011111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
10011101111011111001111101111111111111111111111111111111111111111111111111111111
|
||||
11111111111110011111111111111111
|
||||
11111111111111111110011111111111111111111001111111111111111111110111111111111111
|
||||
10111100111111111111111001111111111111111111111110011111111111111111111111111111
|
||||
11111111101111111111111111111111
|
||||
11111111111111111110011111111110001111111101111111111111111111100111111111111111
|
||||
11011111111111011011100101111111111111111111111111011101111111111111111111111111
|
||||
11111111110111111111111111111111
|
||||
11111111111111111111111111111111001111111111111111111111111111111111111111111111
|
||||
11111111111010111111011101111111111111111111111111101001111111111111111111111111
|
||||
11111111111111011111111111111111
|
||||
11111111111111111111111111111111001111111011111111111111111110111111111111111111
|
||||
11111010111111011101111101111111111111111111111110111111111111111111111111111111
|
||||
11111110110111011111111111111111
|
||||
11111111111111111111111111111110001111111011111111111111111111111101011111111111
|
||||
11101111111111011011111111111111111111111111111111011111111111111111111111111111
|
||||
11111111111111111111111101111111
|
||||
11111111111111111111111111111110001111111101111111111111111111111111011111111111
|
||||
11110111111101011011111111111111101111111111111110111111111111111111111111111111
|
||||
11111111111111111111111101111111
|
||||
11111111111111111111111111111111001111111111111111111111111111111110111111111111
|
||||
11111101111111011110111111111111110101111111111111111111111111111111111111111111
|
||||
11111111111111111111111111011111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111101111110011011111111111111101111111111111111111111111111111111111111111111
|
||||
11111111111111111111111100111111
|
||||
11111111111111111111111111111111111111111111111111111111111111101111111111111111
|
||||
11111111111111111111101110010111111101111111111011011111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111001111111101111111111111111111110111111111111111
|
||||
11111111111111111111101101100111101101111111111111011111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111110001111111111111111111111111111111111111111111111
|
||||
11111111111111110110111101111111100101111110111110111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111110111111101111111111111111111111111111111111111111
|
||||
11111111111111111111100001011111101011111111110001111111111111111111111111111111
|
||||
11111111111111111111111111011111
|
||||
01111111111111111111111111111111111111111111111111111100101111010101011111110111
|
||||
11111111111111001100100111111101001100111110111111111000110011111111101101101011
|
||||
00110011111111011111110111011011
|
||||
01011110111111111111111111111110001000011111111111110100100101110011111111010111
|
||||
11111111111110010100101111111001011000011110110111000101110001001111111011100111
|
||||
00010011111111111111110011111010
|
||||
11111111111111111111111111111111001111111111111111111100101001101011111101111111
|
||||
11111111111111110100111101111010111101111110000111101111010101001111110111111110
|
||||
01111011111110111110100101111111
|
||||
01111110111111111111111111111111111111111111111111111000111101111011001111101111
|
||||
11111111111111111100111111111011110111101111110011100111101111111111111110111101
|
||||
11101011111111111111111111111011
|
||||
10111111111111111111111111111111111111111101101111111100100111110110101110111101
|
||||
00110101101011000100111110111101111111111111111110011011011101001111110101011011
|
||||
01110011111111111010100110111101
|
||||
11111111111111111111111111111110001111111011110111111000101111111111010101111110
|
||||
11011001110100001000111001011111011101101110100111011101110111000000011001110111
|
||||
01100011111111111101110111111111
|
||||
11111111111111111111111111111111001111111111110111111100111101111111011101111111
|
||||
11011110110111011100111111110111011111110110111111111101110111000111001101110011
|
||||
01111011111011011100100101111111
|
||||
11111111111111111111111111111111001111111111110111111110111111101111001111101110
|
||||
11011111111111111100101101110111011101111111010110111101110111001111011111110000
|
||||
11101011111111111111011111111111
|
||||
01111111111111111111111111111110001111111111111111111000100111110111111101101111
|
||||
00110101111111111011111111111111100111100010111101011111111110001111111101111111
|
||||
11101110111111111100101111111001
|
||||
01011111111111111111111111111110001111111111111111111000101101101111101101111110
|
||||
11011101111111111011111111111111111111100010111110011111111111001111111011111111
|
||||
11100010000111111111111111111001
|
||||
11111111111111111111111111111111001111111111111111111100011001111111111111111110
|
||||
11111011111111111110111111111111111101110011110111111111111111001111111111111111
|
||||
11111010110111111111110111111111
|
||||
01111111111111111111111111111111111111111111111111111010111101111111111011101111
|
||||
11011111111111111111111111111111110111100011011111111101111111001111111111111111
|
||||
11111011110111111111011111111011
|
||||
10111111111111111111111111111111111111111001110111111100011111111111011111111111
|
||||
10111101110111111111101111110111111111110001001111011111111111001111101101111011
|
||||
11111101111111111101111111111111
|
||||
11111111111111111111111111111111001111111101110111111100111101111111011110111110
|
||||
01011101111111111111111101110111011101110010110111111100110111000011011111111111
|
||||
10110010111111111111111111111011
|
||||
11111111111111111111111111111110001111111111110111110100111001111111011101011111
|
||||
11111111110111110111111001111111111111010011110111111101111101001111011111111101
|
||||
01011011110111111101111111111001
|
||||
11111111111111111111111111111110111111111011101111111110111111111110111111110110
|
||||
11001011111111111111111110101110111101111010110110111011111111101100110011111111
|
||||
11111011011111111111111111111101
|
||||
01111111111111111111111111111111111111111010111111111111101111111111111101111111
|
||||
11101111111110011111111110100111111101110110101010011111111111001110111000100001
|
||||
11111011111010111111111111111001
|
||||
01011111111111111111111111111110001000011100111011010110111001110111101001010111
|
||||
11010101111111000111111101100111111100010010110100011111111101001001011101110111
|
||||
11010011111011011111111111111001
|
||||
11111111111111111111111111111111001111111111110111111111011101111111111111011110
|
||||
11111111111111111111111011010111111001110010010111111111111111001011111010000111
|
||||
00010011111111011111111111111111
|
||||
01111111111111111111111111111111111111111111011111111011111100111111111111111111
|
||||
10001111111111111011101101110111111101100011110111111111111110111111011111111111
|
||||
11010010110101111111111111111010
|
||||
10111111111111111111111111111111111111110111111110011111111011100010111100010011
|
||||
11010111111111111111011110110111111111110111101010010100111111001111111101111111
|
||||
01010011011111111111111111111111
|
||||
11111111111111111111111111111110001111111101111011011011100101110111011001100110
|
||||
10011101111111111011100111110111111111100011110110011101111110001111111001111111
|
||||
00110010111111111111111111111011
|
||||
11111111111111111111111111111111001111111111111111111111011111101111111111110001
|
||||
11011111111111111111111100100111111111110001111111011111010111001111111111111111
|
||||
11110011111111111111111111111001
|
||||
11111111111111111111111111111111001111111111111111111111111101111101111111110011
|
||||
01011111111111111010111110011111111111110011110101011011111010111111101111111110
|
||||
11110011111111111111111111111111
|
||||
01111111111111111111111111111110001111111111111110011000111111110111011101100011
|
||||
11111111111111011000111110100111111111101110001111011111111110001111101101111110
|
||||
01100011111110011111111111111001
|
||||
01011111111111111111111111111110001111111111111111001011011111101101011000100011
|
||||
11111111111110001000101110110111111111101110110111011111111110001111111101111111
|
||||
11110111111111011111111111111001
|
||||
11111111111111111111111111111111001111111111111111111111011101111011111101110011
|
||||
11111111111111111110111111100111111111111110110111111111111111111111110101111111
|
||||
11110111111110111111111111111110
|
||||
01111111111111111111111111111111111111111111111111111011111101111010111110110011
|
||||
11111111111111111010110111011111111111101011110010111111111111001111101001111111
|
||||
11110011111111111111111111111011
|
||||
10111111111111111111101101111111111111111000110111111111101110110011111111111011
|
||||
11101111110111111100111110100111111001111101111111111110011111001111101111110111
|
||||
01110011101111111110010111111111
|
||||
11111111111111111111110111111111001111111101110111111111100111110101111111111011
|
||||
11010111110111111100111111000111111100111110110111011111111111001111100101111111
|
||||
00110110110111111111110011111011
|
||||
11111111111111111111101001111110001111111111010111110111111101111011011111010001
|
||||
10111111101111110110111111110111111111011110010111111111110001111111111101101111
|
||||
11010111011111111111110011111001
|
||||
11111111111111111111111111111110111111111010100111111111111110001111111111110011
|
||||
11011110111111111110111111110111111111111111100011111111111111001111101111111110
|
||||
11110010110111111111101111111111
|
||||
11111111111111111111111111111111111111111011111111110111111011101111111101111110
|
||||
11111111111111111111011111111111101111110011001111111110101111111011111110111111
|
||||
11110011001111011111111111111111
|
||||
11111101111111111111111111111110001000011101111111110111001101110111111111011010
|
||||
11111111111111111111101111111111110110011000110111111111111111111011011111111111
|
||||
11011110110110111111111111111110
|
||||
11111111111111111111111111111111001111111111111111111111010101111111111111011011
|
||||
11011111111111111111110100110111111101011001110111111111110111111000011111111111
|
||||
11010010111011011111111111111111
|
||||
11111101111111111111111111111111111111111111111111111011111101111111111011111111
|
||||
01111111111111111111111111111111111111111011110111111111011111111111011111011111
|
||||
11010011110111111111111111111111
|
||||
11111111111111111111111111111111111111111101111111111111111111011101111111010101
|
||||
11101111111111111111111010100111111111011110111111011011111111111111101101111111
|
||||
11010110111111111111111111111111
|
||||
11111111111111111111111111111110001111111101111111111011100001110010011101100011
|
||||
11100111111111011111111100000010011111101011111111010101110111111110011101111111
|
||||
11101110110111111111111111111111
|
||||
11111111111111111111111111111111001111111111111111111110011111111010001111110011
|
||||
11011101111111111111101111110001011111111011110011001111111111111111101001111111
|
||||
11110011010111111111111111111111
|
||||
11111111111111111111111111111111001111101011111111111111111101111011111111110110
|
||||
11011111111111011111111101111010111111101010110010111111110111111111100111111111
|
||||
11110110100111111111111111111111
|
||||
11111111111111111111111111111110001111111011010111111000100111101111111101100011
|
||||
11111101010111111111111110010111011111100011110010011100110111111111101001100111
|
||||
11100011111111111111111011111111
|
||||
11111111111111111111111111111110001111111101110111111000101101110111101101100000
|
||||
00011001110111111111111111010110111111100010110110011001111011111111100101110111
|
||||
11100100100111111111110111111110
|
||||
11111111111111111111111111111111001111111111101111111100101001111111111011111101
|
||||
11011111101111111111111111111111111111110011100101111111110111111111111001101111
|
||||
11110001010111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111000111101111111111111111111
|
||||
11001111111111111111111111101111111111110010010111101111001111111111111111111111
|
||||
11110011110111111111111111111111
|
||||
11111111111111111111111111111111111111111101111111111110100011110111111111111011
|
||||
11111101111011111111111111100111111111111101111111011110110111111111111101010111
|
||||
11110011111111101111110011111111
|
||||
11111111111111111111111111111111001111111011111111111110101101110111111111111111
|
||||
11111101111111111111111111110111111111110011110111111110110111111111111101110111
|
||||
11111111111011111111110111111111
|
||||
11111111111111111111111111111110001111111111111111110110101101111111111111011111
|
||||
11111111111111111111111111111111111111010011100111111111110111111111111111111111
|
||||
11011011111111011111101111111111
|
||||
11111111111111111111111111111110111111111111111111111110111100101111111111111011
|
||||
11101011111101111111111111101111111111110010110110111110001111111111101011101111
|
||||
11110011111111110111111111111111
|
||||
11111111111111111111111111111111111111111111111111111100101110111111111111111111
|
||||
11101111111111101111111111111111111111111110111111011111111111111111111001111111
|
||||
10111111011111111111111111111111
|
||||
11111111111111111111111111111110001000011111111111110110101111011111111111111100
|
||||
01000111111111110100111111110111111111011011100111011111111111111111111001111111
|
||||
11111110110111111111111011111111
|
||||
11111111111111111111111111111111001111111111111111111100111101110111111111111110
|
||||
10011101111011111100111111110111111111111110110110111111111111111111111111111011
|
||||
11111110111111111111111111111111
|
||||
11110011111111111111111111111111111111111111111111111000110111110111111111111111
|
||||
11011111111111111011111110110111111111101111110011111111111111111111111111111111
|
||||
11111111100111111110111111111111
|
||||
11111111111111111111011111111111111111111001111111111100101111110111111111111111
|
||||
10101111100111111101111100100111111111111110101111110011111111111111101111111111
|
||||
11111110101011111011111111111111
|
||||
11111111111111111110011111111110001111111101111111111000101111100110111111111100
|
||||
11011110110111111001101101100111111111101110110111101001111111111111111111111111
|
||||
11111110010001111101111111111111
|
||||
11111111111111111111111111111111001111111111111111111100110101111011011111111110
|
||||
01001100110111111101111101110111111111111110010111101101111111111111111101111111
|
||||
11111110110111011111111101111111
|
||||
11111111111111111011111111111111001111111011111111111100111110111011111111111111
|
||||
11010110011111111101110011010111111111111111110111101111111111111111110101111111
|
||||
11111111110111111111111111111111
|
||||
11111111111111111111111111111110001111111111111111111011100011010111101101111111
|
||||
11111111010111111011111111110101010001101110101111011101110011111111111111111101
|
||||
11111111111111011110110111111111
|
||||
11111111111111111111111111111110001111111111111111111011101101110111100101111111
|
||||
11111111110011111011101111110111000101101110010110111110110011111111111111111001
|
||||
11111111111110111111111111111111
|
||||
11111111111111111111111111111111001111111111111111111111101101111111111101111111
|
||||
11111101111101111111110111101111101101111111110111111011000111111111111111111111
|
||||
01111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111011111101101111110011111111
|
||||
11111101101111111011111110111110111111101101110111111111111111111111111111111111
|
||||
11111111111111111111111100111111
|
||||
11111111111111111111111111111111111111111101111111111101101111110111111111111110
|
||||
00101111111010011111111110100111111111111101111111011101110111111111101101111111
|
||||
11111101111111110101110111111111
|
||||
11111111111111111111111111111111001111111011111111111101111001111111111111111110
|
||||
11011111111111011111111101000111110111111110111111011000110011111111011101111111
|
||||
11111110000111111101110111111111
|
||||
11111111111111111111111111111110001111111111111111110110011101111111111111111110
|
||||
11001101111111110111111110110111111101010111010111111111000111111111111011111111
|
||||
11111111110111111010101111111111
|
||||
11111111111111111111111111111110111111111111111111111111111101101111111111111111
|
||||
11010111111111111111111011111111111111111110110010101111110111111110100111111111
|
||||
11111110110111111111111111111111
|
||||
01111111111111111111111111111111111111100101111111111111101111111111111001111011
|
||||
11111111111111111100111111100110101101111011011111111010110111111111101101111101
|
||||
01111011111011111101111111111001
|
||||
01011111111111111111111111111110001111111101111111110101101101111111111101011011
|
||||
11111111111111110100111111100011011000010010110111101001010101000111111111111111
|
||||
01011111111111111101111111111001
|
||||
11111111111111111111111111111111001111110011111111110100110100110111101001111011
|
||||
11111101111111110100111111111001101101010011111111100110100111001111010111111111
|
||||
01011111111101111011111111111111
|
||||
01111111111111111111111111111111111111111111111111111110111011111111111111101010
|
||||
11011101111111111100111111111111010111011011101111101100111110001011011011111110
|
||||
01111011111111101111111111111011
|
||||
10111111111111111111111111111111111111111101111111110111110011110110101101110001
|
||||
11101111101001110100111111100111111111011111100011011111111111111111101111101111
|
||||
01010101111011111011111111111111
|
||||
11111111111111111111111111111110001111111101110111111111001101110111010100110010
|
||||
01111111110111111000111111110111011101100010110100111101110010001111011111110111
|
||||
01110010111101111101111111111011
|
||||
11111111111111111111111111111111001111111111111111111110011101111111001001110011
|
||||
11011100110111011100111111101111001111110001110011011101110111000111110101110011
|
||||
11110011110111111101111111111001
|
||||
11111111111111111111111111111111001111101011110111111110111100101111011111100011
|
||||
11110101111101111000111111111111111111110011010111111101110110001110011100111110
|
||||
11110111011111111111111111111101
|
||||
11111111111111111111111111111110001111111111111111111011110010111111111100100011
|
||||
11101111111101111010111111111011011111100001111111101111111110001010111101111111
|
||||
01101011111111111101111111111001
|
||||
11011111111111111111111111111110001111111111111111111000101101011111111001111111
|
||||
11110111111111111011111111111111111111100010111111111111110110001001011011111110
|
||||
01110011111111111111111111111001
|
||||
11111111111111111111111111111111001111111111111111111100101111111111111111111111
|
||||
11111111111111011111111111111111111111110011010111111111111111001111011111111011
|
||||
11110011111111111111111111111110
|
||||
11111111111111111111111111111111111111111111111111111111111101111111111111101111
|
||||
11111111111111111111111111111111111111100010110111111111110110101111111111111111
|
||||
11111011111111111111111111111011
|
||||
11111101111111111111111111111111111111111111111111111111111111010111001100110011
|
||||
11100101111111011110111010110111111111111010111101011110110011001111101111111011
|
||||
01111010111111111111111111111111
|
||||
11111011111111111111111111111111001111111101111111111111100101100111011101111110
|
||||
01111101110111011111100100110111111111110010111111011111110111001001011110110101
|
||||
00110010110111111111111111111011
|
||||
11111111111111111111111111111110001111111111111111110111101011111111010001011101
|
||||
11111011111010110111101111010111111111010011010110111111111101001111110101110010
|
||||
01010010000111111111111111111001
|
||||
11111111111111111111111111111110111111101111111111111111111101111110101111111111
|
||||
11010111101111111111111100101111111111011011111111111111001111001010011101101111
|
||||
11111011110111111111111111111111
|
||||
01111111111111111111111111111111111111111111111111111111011111111111111111111111
|
||||
11101111111111011100111110111111111111110001101111111111100111010111111111111011
|
||||
11110010011111111111111111111001
|
||||
01011111111111111111111111111111111000011111111011010111100001111111111111011011
|
||||
10011111111111010111111101011111111111010011110111111110110101011111011111111111
|
||||
11010010110111111111111111111001
|
||||
11111111111111111111111111111111111111111111111111110111101101111111111111010010
|
||||
11110111111010111100111111110111111111110011110111111111111101001110011111111101
|
||||
11100011110111111111111111111111
|
||||
01111111111111111111111111111111111111111111111111111100111101111111111111010111
|
||||
11011111111111111000101001110111111111101111111111111111111101001111111111111111
|
||||
11010010100111111111111111111011
|
||||
10111111111111111111111111111111111111111101111111110111100111100111111111011111
|
||||
10111001111111111100101110110110111111110011111011011011111101111011111101110011
|
||||
11010010001111011111111111111111
|
||||
11111111111111111111111111111111111111111011111111111100101001110111111111111011
|
||||
11011001111111111000101101101111011111100011111010011101111110011011011001111101
|
||||
11100010110110111111111111111011
|
||||
11111111111111111111111111111111111111111111111111111100111101111111111111110011
|
||||
11111111111111111100101000110111111111110011111111011111111111001111011111101111
|
||||
01110010110011011111111111111001
|
||||
11111111111111111111111111111111111111111111111111111100101101101111111111110111
|
||||
11111111111111111000110101011111111111101110110001111111111111101100101111111111
|
||||
10110111110111111111111111111101
|
||||
01111111111111111111111111111111111111111111111111111011100111111110011101101111
|
||||
11111111111111011000111111010111111111100010101111111011111110001111111111101111
|
||||
01101111111111111111111111111111
|
||||
01011111111111111111111111111111111111111111111111111011101111111101011111101011
|
||||
11011111111111001010111111100111111111100010110111111001111110001111011110100110
|
||||
11101111111111111111111111111110
|
||||
11111111111111111111111111111111111111111111111111111101011101111011111011111110
|
||||
11111111111110111100111111111111111111110011110111111111110111111010111100011111
|
||||
00110111111111111111111111111111
|
||||
01111111111111111111111111111111111111111111111111111111111101111011111111111111
|
||||
10011111111111111000111111111111111111100001010111101111110111001111011100110111
|
||||
11110111111111111111111111111111
|
||||
10111111111111111111111111111111111111111111111111111111101111100111111111111111
|
||||
11111111111111111100111111110110011001111010111001011111111111011100101101111011
|
||||
11110011111011111111111111111111
|
||||
11111111111111111111111111111111111111111101111111111111101101110111111111111111
|
||||
11111111111111111100111111110111001101111010011111011111111111000011010011111101
|
||||
11111111111101111111111111111111
|
||||
11111111111111111111111111111111111111111111111111110111111001111111111111011111
|
||||
11111111111111110100111111111110111111011011110010011111111101110111011111111111
|
||||
00011111111111111111111111111111
|
||||
11111111111111111111111111111111111111101111111111111111110111101111111111111111
|
||||
11111111111111111100111110101111111111111011111101111111111111011111011111111111
|
||||
11110011111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111110110110111111111011111111111
|
||||
01111111111111111111011010111011111111111111011011111111111101001011111111111111
|
||||
11111110111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111110100001101111110111111111100
|
||||
11011111110111111111101100111111011111011100111101111101111101101111011111111111
|
||||
11111110110111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111100111001111111111111111111
|
||||
11011101111111111111110101110101111111111111110111111111111111001010011101111111
|
||||
11111110010011011111111111111111
|
||||
11111111111111111111111111111111111111111111111111111000111111111111111111111110
|
||||
10011100111111111111111111011011111111110011111111101111111110001111011101111111
|
||||
11111111100111111111111111111111
|
||||
11111111111111111111111111111111111111111101111111111100111111110110111111111110
|
||||
11101111111111111111111110010111111111111010111010011001111111001111101111111111
|
||||
11111101001111111110111111111111
|
||||
11111111111111111111111111111111111111111011111111111000001111101100011111111110
|
||||
11111111111111111111111101010111111111111110110101011101111110101111111111111111
|
||||
01111110110111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111100111101111011111111111111
|
||||
01011101111111111111111111101111111111101101010110111111111111001111111101111111
|
||||
11111111110111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111100110111111011111111111111
|
||||
11110101111111111111101001111111111111110011100111101111111110001011010101111111
|
||||
01111110110111111111011111111111
|
||||
11111111111111111111111111111111111111111111111111111000100111111111101101111111
|
||||
11111111111011001111111111111111111111110011111111111111010110001111111111111011
|
||||
00111111111011101111111111111111
|
||||
11111111111111111111111111111111111111111111111111111000101111111111111100111111
|
||||
11111111111111001111111111111111111111111110111111111111100110001111111111111111
|
||||
01111111111101111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111100011101111111101001111111
|
||||
11111111111101011111111111111111111111111111011111111111110111011111111111111101
|
||||
01111111111111110111111111111111
|
||||
11111111111111111111111111111111111111111111111111111000111101111111110111111111
|
||||
11111111111110111111111111111111111111110010110111111111110110001011011111111010
|
||||
11111111111111111111111111111111
|
||||
11110011111111111111111111111111111111111101111111111100101111111001111001111111
|
||||
11101111111111111111111111110111101111110001111110011110110011001111111101110011
|
||||
00111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111011111111111100101111111101011101111111
|
||||
11011111111111101111111111110111111110110111111111011101110011001111011111111111
|
||||
00111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111110100111101111111101001111110
|
||||
11111111111111011111111111111111110101010111110110111111010101001011111111101101
|
||||
01111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111110100101111111111111111111
|
||||
10010111111111111111111110101111111111110010110111101111101101001110011011111110
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111101010111111111110110011
|
||||
11111111111111101111111111111111111111110010111011111111111111111101111111111111
|
||||
11111111111010011111110111111111
|
||||
11111111111111111111111111111111111111111111111111110111101101011111111110010011
|
||||
11111111111010111111111111111111111111010010110011111111111101111011011101111111
|
||||
11111111111010011111110111111111
|
||||
11111111111111111111111111111111111111111111111111111111100101111111101111010011
|
||||
11111111111001111111111111111111111111110010010111011111111101111111111111111111
|
||||
11111111111101011110101111111111
|
||||
11111111111111111111111111111111111111111111111111111011111101111111101111110011
|
||||
11111111111011111111111111111111111111110011100101111111111111111010001111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111001111111111111111111100111111111010001
|
||||
10101101101111111111111110110111111111110111111010010111111101001111101101011111
|
||||
11111110111011111111111111111111
|
||||
11111111111111111111111111111111111111111101111111111011111111110111111111100011
|
||||
11010110100111111111111101101111111111110011111101001111111111110011010010101011
|
||||
11111111110101111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111110111111101111111111110011
|
||||
11011110110111111111111011110111111111100111111111101101111111111010011111111111
|
||||
11111110110111011111111111111111
|
||||
11111111111111111111111111111111111111111011111111111111101101111111111111110010
|
||||
11011010011111111111101101010111111111110110110110111111111111001101011110111101
|
||||
11111111100111011111111111111111
|
||||
11111111111111111111111111111111111111111111111111111000100111111111110001100011
|
||||
10101111110111111111111111111111001101111110101101011111111110110111111111111101
|
||||
11111111111011111001111101111111
|
||||
11111111111111111111111111111111111111111111111111111000101001111111101101100111
|
||||
11000111101111111111111111111111011111111110110110011111111111111011011111111001
|
||||
11111111111101111100101111111111
|
||||
11111111111111111111111111111111111111111111111111111100111101111111101101111101
|
||||
11111101111111111111111111111110111111111001110111111111111111111011011111111111
|
||||
01111111111111111111110100111111
|
||||
11111111111111111111111111111111111111111111111111111000111111111111101111110011
|
||||
11011111111111111111111111111011111111111011010111111111111111101100011111111111
|
||||
11111111111111111011011111111111
|
||||
11111111111111111111111111111111111111111001111111111110111111110111111111110011
|
||||
11101101111101111111111110110111111111110001011001001101111111111101101101111111
|
||||
11111111111011111111111111111111
|
||||
11111111111111111111111111111111111111111101111111111100101111111111111111111111
|
||||
11010111111010111111111101101111111111111110111111011011111111111011111011111111
|
||||
11111111111101111111111111111111
|
||||
11111111111111111111111111111111111111111111111111110100111111111111111111011111
|
||||
11101101111111011111111111111111111111011011110110010101111101000111111101111111
|
||||
11111111111111111111111111011111
|
||||
11111111111111111111111111111111111111111011111111111100110111101111111111110001
|
||||
10011011111111111111111011011111111111111011111101011101111111101111010101111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111101111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111101111111111111111111111111111111111111110111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111101111111101111
|
||||
11111111111111011111111111111111
|
||||
11111111111111111111111110111111111111111111111111111111111111111111111111111111
|
||||
11111111111111110101110011111111111111111111111111111111111101111110111111101111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111110101111111111111111111011111111111111111
|
||||
11111111111111110101111111010111111111111111111101111111111111111111110101111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111011111111111111111111111111111111111111111110111111110011111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111011111111111111111111101111111111111111
|
||||
11111111111111111011111111101111111111111111111110111111111111111111111011111111
|
||||
11001111111100111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111110111111111111111111111111111111111111111111111111111110111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111110111111111111111111111011111111111111110
|
||||
10111111111111110111101011011110111111111111111101011111111111111111110111111111
|
||||
11111111111101111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
01111111111111111111110111111110001111111110011111111001111111111111111111100111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111001111111100111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111101111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111101111111111111111111
|
||||
11111111111111111111111111110111111111111111111111011111111111111111111001111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111110
|
||||
11111111111111111111111111101111111111111111111110111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111101111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111110111111111111111111111011110010100100111100111111001010
|
||||
01001111011101110011000100111101100111001100010011110010111100101001001111001111
|
||||
11001010010011110111101111111111
|
||||
11111111001011111111011110111100101001001111011110110010110011011101111011111111
|
||||
11111111111011110011000100111101100111001100010011110110101100110001001111011010
|
||||
11001010010011110111101111111111
|
||||
11111111111111111111111111111111111111111111111111110010100100111100111111111111
|
||||
11111111111111110011000100111100100111111111111111111111111100110001001111011010
|
||||
11111111111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111110011011111110111101111111111
|
||||
11111111111111110010100100111100111111111111111111111111111100110001001111011010
|
||||
11111111111111111111111111111111
|
||||
*
|
||||
CA8D9*
|
||||
N User Electronic Signature Data*
|
||||
U00000000000000000000000000000000*
|
||||
2290
|
|
@ -0,0 +1,4 @@
|
|||
---- MParTrce Tool Log File ----
|
||||
|
||||
==== Par Standard Out ====
|
||||
==== End of Par Standard Out ====
|
|
@ -0,0 +1,4 @@
|
|||
#BLOCK ASYNCPATHS;
|
||||
#BLOCK RESETPATHS;
|
||||
|
||||
#FREQUENCY 200.000000 MHz;
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,402 @@
|
|||
|
||||
Lattice Mapping Report File for Design Module 'RAM2GS'
|
||||
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
|
||||
Command line: map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial
|
||||
RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr
|
||||
RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf C:/Users/Dog
|
||||
/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.
|
||||
lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_L
|
||||
CMXO256C.lpf -c 0 -gui -msgset
|
||||
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO256CTQFP100
|
||||
Target Performance: 3
|
||||
Mapper: mj5g00, version: Diamond (64-bit) 3.12.0.240.2
|
||||
Mapped on: 08/16/21 21:32:26
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of PFU registers: 102 out of 256 (40%)
|
||||
Number of SLICEs: 65 out of 128 (51%)
|
||||
SLICEs as Logic/ROM: 65 out of 128 (51%)
|
||||
SLICEs as RAM: 0 out of 64 (0%)
|
||||
SLICEs as Carry: 9 out of 128 (7%)
|
||||
Number of LUT4s: 129 out of 256 (50%)
|
||||
Number used as logic LUTs: 111
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
Number of external PIOs: 67 out of 78 (86%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
Number of TSALL: 0 out of 1 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 4
|
||||
Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
|
||||
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
|
||||
Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
|
||||
Number of Clock Enables: 13
|
||||
Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs
|
||||
Net RCLK_c_enable_6: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
|
||||
Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
|
||||
Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_7: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
|
||||
Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs
|
||||
Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/16/21 21:32:26
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
|
||||
Net Ready_N_268: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 9
|
||||
Net RASr2: 1 loads, 1 LSLICEs
|
||||
Net C1Submitted_N_225: 2 loads, 2 LSLICEs
|
||||
Net n2299: 1 loads, 1 LSLICEs
|
||||
Net nRowColSel_N_35: 1 loads, 1 LSLICEs
|
||||
Net nRowColSel_N_34: 1 loads, 1 LSLICEs
|
||||
Net LEDEN_N_88: 1 loads, 1 LSLICEs
|
||||
Net n2291: 2 loads, 2 LSLICEs
|
||||
Net Ready: 7 loads, 7 LSLICEs
|
||||
Net nRWE_N_173: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net Ready: 19 loads
|
||||
Net InitReady: 17 loads
|
||||
Net RASr2: 16 loads
|
||||
Net nRowColSel_N_35: 14 loads
|
||||
Net nRowColSel: 13 loads
|
||||
Net Din_c_6: 9 loads
|
||||
Net MAin_c_1: 9 loads
|
||||
Net Din_c_5: 8 loads
|
||||
Net FS_11: 8 loads
|
||||
Net MAin_c_0: 8 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 0
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
Design Errors/Warnings
|
||||
----------------------
|
||||
|
||||
No errors or warnings present.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| IO Name | Direction | Levelmode | IO | FIXEDDELAY |
|
||||
| | | IO_TYPE | Register | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RD[7] | BIDIR | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RD[6] | BIDIR | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RD[5] | BIDIR | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RD[4] | BIDIR | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RD[3] | BIDIR | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RD[2] | BIDIR | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/16/21 21:32:26
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| RD[1] | BIDIR | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RD[0] | BIDIR | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Dout[7] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Dout[6] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Dout[5] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Dout[4] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Dout[3] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Dout[2] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Dout[1] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Dout[0] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| LED | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RBA[1] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RBA[0] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RA[11] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RA[10] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RA[9] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RA[8] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RA[7] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RA[6] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RA[5] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RA[4] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RA[3] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RA[2] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RA[1] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RA[0] | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| nRCS | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RCKE | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| nRWE | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/16/21 21:32:26
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| nRRAS | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| nRCAS | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RDQMH | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RDQML | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| nUFMCS | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| UFMCLK | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| UFMSDI | OUTPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| PHI2 | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| MAin[9] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| MAin[8] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| MAin[7] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| MAin[6] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| MAin[5] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| MAin[4] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| MAin[3] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| MAin[2] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| MAin[1] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| MAin[0] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| CROW[1] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| CROW[0] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Din[7] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Din[6] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Din[5] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Din[4] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Din[3] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Din[2] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Din[1] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Din[0] | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/16/21 21:32:26
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| nCCAS | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| nCRAS | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| nFWE | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RCLK | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| UFMSDO | INPUT | LVTTL33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
|
||||
Removed logic
|
||||
-------------
|
||||
|
||||
Block i2 undriven or does not drive anything - clipped.
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal PHI2_N_114 was merged into signal PHI2_c
|
||||
Signal nCRAS_N_9 was merged into signal nCRAS_c
|
||||
Signal nCCAS_N_3 was merged into signal nCCAS_c
|
||||
Signal n2302 was merged into signal nRowColSel_N_35
|
||||
Signal nRWE_N_172 was merged into signal nRWE_N_173
|
||||
Signal n2307 was merged into signal Ready
|
||||
Signal RASr2_N_63 was merged into signal RASr2
|
||||
Signal n1377 was merged into signal nRowColSel_N_34
|
||||
Signal n2306 was merged into signal nFWE_c
|
||||
Signal UFMSDO_N_74 was merged into signal UFMSDO_c
|
||||
Signal GND_net undriven or does not drive anything - clipped.
|
||||
Signal VCC_net undriven or does not drive anything - clipped.
|
||||
Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped.
|
||||
Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped.
|
||||
Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped.
|
||||
Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped.
|
||||
Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped.
|
||||
Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped.
|
||||
Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped.
|
||||
Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped.
|
||||
Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped.
|
||||
Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped.
|
||||
Block i1962 was optimized away.
|
||||
Block i1961 was optimized away.
|
||||
Block i1963 was optimized away.
|
||||
Block i1070_1_lut_rep_25 was optimized away.
|
||||
Block nRWE_I_49_1_lut was optimized away.
|
||||
Block i604_1_lut_rep_30 was optimized away.
|
||||
Block RASr2_I_0_1_lut was optimized away.
|
||||
Block i1069_1_lut was optimized away.
|
||||
Block i1_1_lut_rep_29 was optimized away.
|
||||
Block UFMSDO_I_0_1_lut was optimized away.
|
||||
Block i1 was optimized away.
|
||||
|
||||
Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 29 MB
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/16/21 21:32:26
|
||||
|
||||
Run Time and Memory Usage (cont)
|
||||
--------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
|
@ -0,0 +1,9 @@
|
|||
-v
|
||||
1
|
||||
|
||||
|
||||
-gt
|
||||
|
||||
|
||||
-mapchkpnt 0
|
||||
-sethld
|
|
@ -0,0 +1,574 @@
|
|||
|
||||
comp 0: SLICE_0 (FSLICE)
|
||||
|
||||
comp 1: SLICE_1 (FSLICE)
|
||||
|
||||
comp 2: SLICE_2 (FSLICE)
|
||||
|
||||
comp 3: SLICE_3 (FSLICE)
|
||||
|
||||
comp 4: SLICE_4 (FSLICE)
|
||||
|
||||
comp 5: SLICE_5 (FSLICE)
|
||||
|
||||
comp 6: SLICE_6 (FSLICE)
|
||||
|
||||
comp 7: SLICE_7 (FSLICE)
|
||||
|
||||
comp 8: SLICE_8 (FSLICE)
|
||||
|
||||
comp 9: SLICE_9 (FSLICE)
|
||||
n1361 = ((ADSubmitted*(~MAin_c_1+n2290))+ADSubmitted_N_234)
|
||||
ADSubmitted.D = n1361
|
||||
ADSubmitted.CLK = ~PHI2_c
|
||||
ADSubmitted.SP = VCC
|
||||
ADSubmitted.LSR = C1Submitted_N_225
|
||||
n2080 = (~MAin_c_0*(~ADSubmitted*n2122))
|
||||
|
||||
comp 10: SLICE_14 (FSLICE)
|
||||
n2386 = GND
|
||||
C1Submitted.D = n2386
|
||||
C1Submitted.CLK = ~PHI2_c
|
||||
C1Submitted.SP = PHI2_N_114_enable_1
|
||||
C1Submitted.LSR = C1Submitted_N_225
|
||||
n2098 = (MAin_c_0*(~C1Submitted*(MAin_c_1*n2108)))
|
||||
|
||||
comp 11: SLICE_18 (FSLICE)
|
||||
CmdEnable_N_236 = (ADSubmitted_N_234+C1Submitted_N_225)
|
||||
CmdEnable.D = CmdEnable_N_236
|
||||
CmdEnable.CLK = ~PHI2_c
|
||||
CmdEnable.SP = PHI2_N_114_enable_8
|
||||
CmdEnable.LSR = GND
|
||||
XOR8MEG_N_112 = (~n2290*(CmdEnable*(MAin_c_0*~MAin_c_1)))
|
||||
|
||||
comp 12: SLICE_19 (FSLICE)
|
||||
n2387\000/BUF1 = VCC
|
||||
CmdSubmitted.D = n2387\000/BUF1
|
||||
CmdSubmitted.CLK = ~PHI2_c
|
||||
CmdSubmitted.SP = PHI2_N_114_enable_6
|
||||
CmdSubmitted.LSR = GND
|
||||
n2308 = (~PHI2r2*(CmdSubmitted*PHI2r3))
|
||||
|
||||
comp 13: SLICE_23 (FSLICE)
|
||||
Cmdn8MEGEN_N_248 = (~n2296*(~Din_c_5*~Din_c_0+Din_c_5*n8MEGEN)+n2296*n8MEGEN)
|
||||
Cmdn8MEGEN.D = Cmdn8MEGEN_N_248
|
||||
Cmdn8MEGEN.CLK = ~PHI2_c
|
||||
Cmdn8MEGEN.SP = PHI2_N_114_enable_6
|
||||
Cmdn8MEGEN.LSR = GND
|
||||
n2296 = (~Din_c_4+(Din_c_6+Din_c_7))
|
||||
|
||||
comp 14: SLICE_25 (FSLICE)
|
||||
n2387 = VCC
|
||||
InitReady.D = n2387
|
||||
InitReady.CLK = RCLK_c
|
||||
InitReady.SP = RCLK_c_enable_6
|
||||
InitReady.LSR = GND
|
||||
RCLK_c_enable_24 = (~InitReady+(~PHI2r2*(CmdSubmitted*PHI2r3)))
|
||||
|
||||
comp 15: SLICE_31 (FSLICE)
|
||||
RA11_N_180 = (~n8MEGEN*(XOR8MEG@Din_c_6)+n8MEGEN*XOR8MEG)
|
||||
RA_c.D = RA11_N_180
|
||||
RA_c.CLK = PHI2_c
|
||||
RA_c.SP = VCC
|
||||
RA_c.LSR = ~Ready
|
||||
n2385 = (Din_c_6+Din_c_7)
|
||||
|
||||
comp 16: SLICE_33 (FSLICE)
|
||||
RCKEEN_N_115 = (~Ready*InitReady+Ready*RCKEEN_N_116)
|
||||
RCKEEN.D = RCKEEN_N_115
|
||||
RCKEEN.CLK = RCLK_c
|
||||
RCKEEN.SP = RCLK_c_enable_4
|
||||
RCKEEN.LSR = GND
|
||||
RCLK_c_enable_7 = (~n2119*(InitReady*n2308)+n2119*(~InitReady*~FS_5+InitReady*n2308))
|
||||
|
||||
comp 17: SLICE_34 (FSLICE)
|
||||
RCKE_N_128 = (~RASr3*(~RASr2*(RCKEEN*RASr)+RASr2*RCKEEN)+RASr3*(~RASr2+RCKEEN))
|
||||
RCKE_c.D = RCKE_N_128
|
||||
RCKE_c.CLK = RCLK_c
|
||||
RCKE_c.SP = VCC
|
||||
RCKE_c.LSR = GND
|
||||
nRWE_N_178 = (~RCKE_c+RASr2)
|
||||
CASr2.D = CASr
|
||||
CASr2.CLK = RCLK_c
|
||||
CASr2.SP = VCC
|
||||
CASr2.LSR = GND
|
||||
|
||||
comp 18: SLICE_35 (FSLICE)
|
||||
n2387\001/BUF1 = VCC
|
||||
Ready.D = n2387\001/BUF1
|
||||
Ready.CLK = RCLK_c
|
||||
Ready.SP = Ready_N_268
|
||||
Ready.LSR = GND
|
||||
RCLK_c_enable_23 = (InitReady*(RASr2*(nRowColSel_N_35*~Ready)))
|
||||
|
||||
comp 19: SLICE_42 (FSLICE)
|
||||
UFMCLK_N_212 = (~n2076*(~InitReady*FS_4+InitReady*CmdUFMCLK)+n2076*(InitReady*CmdUFMCLK))
|
||||
UFMCLK_c.D = UFMCLK_N_212
|
||||
UFMCLK_c.CLK = RCLK_c
|
||||
UFMCLK_c.SP = RCLK_c_enable_24
|
||||
UFMCLK_c.LSR = n2291
|
||||
RCLK_c_enable_6 = (n2076*FS_10)
|
||||
|
||||
comp 20: SLICE_43 (FSLICE)
|
||||
UFMSDI_N_219 = (~InitReady*n1895+InitReady*CmdUFMSDI)
|
||||
UFMSDI_c.D = UFMSDI_N_219
|
||||
UFMSDI_c.CLK = RCLK_c
|
||||
UFMSDI_c.SP = RCLK_c_enable_24
|
||||
UFMSDI_c.LSR = n2291
|
||||
n1895 = (~FS_10*(n2103*(~n2293*FS_6)))
|
||||
|
||||
comp 21: SLICE_55 (FSLICE)
|
||||
n2128 = (((n2297+n2301)+nRCAS_N_161)+Ready)
|
||||
n980.D = n2128
|
||||
n980.CLK = RCLK_c
|
||||
n980.SP = VCC
|
||||
n980.LSR = ~nRWE_N_173
|
||||
n2301 = (~InitReady+~RASr2)
|
||||
|
||||
comp 22: SLICE_56 (FSLICE)
|
||||
n8MEGEN_N_94 = (~n4*(~FS_10*Cmdn8MEGEN+FS_10*~UFMSDO_c)+n4*Cmdn8MEGEN)
|
||||
n8MEGEN.D = n8MEGEN_N_94
|
||||
n8MEGEN.CLK = RCLK_c
|
||||
n8MEGEN.SP = RCLK_c_enable_7
|
||||
n8MEGEN.LSR = GND
|
||||
n4 = ((~FS_11+n2300)+InitReady)
|
||||
|
||||
comp 23: SLICE_58 (FSLICE)
|
||||
nRCAS_N_157 = (~nRowColSel_N_35*(~n2117+~Ready)+nRowColSel_N_35*n2287)
|
||||
nRCAS_c.D = nRCAS_N_157
|
||||
nRCAS_c.CLK = RCLK_c
|
||||
nRCAS_c.SP = RCLK_c_enable_4
|
||||
nRCAS_c.LSR = GND
|
||||
n2287 = (~n2248*(~Ready*~RASr2+Ready*(~RASr2+~CBR))+n2248*(~Ready+(~RASr2+~CBR)))
|
||||
|
||||
comp 24: SLICE_60 (FSLICE)
|
||||
nRCS_N_132 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~n2117*~nRowColSel_N_35))*Ready)+((~InitReady+nRCS_N_135+~RASr2+~nRowColSel_N_35)*~Ready)
|
||||
nRCS_c.D = nRCS_N_132
|
||||
nRCS_c.CLK = RCLK_c
|
||||
nRCS_c.SP = RCLK_c_enable_4
|
||||
nRCS_c.LSR = GND
|
||||
|
||||
comp 25: SLICE_61 (FSLICE)
|
||||
n33 = (~Ready*(n2244+n2297)+Ready*(n2244+n18))
|
||||
nRRAS_c.D = n33
|
||||
nRRAS_c.CLK = RCLK_c
|
||||
nRRAS_c.SP = VCC
|
||||
nRRAS_c.LSR = GND
|
||||
n50 = ((nRowColSel_N_33+nRRAS_c)+nRowColSel_N_32)
|
||||
RASr.D = ~nCRAS_c
|
||||
RASr.CLK = RCLK_c
|
||||
RASr.SP = VCC
|
||||
RASr.LSR = GND
|
||||
|
||||
comp 26: SLICE_62 (FSLICE)
|
||||
n1369 = (~n2308*nUFMCS_c+n2308*~CmdUFMCS)
|
||||
nRWE_N_173.D = n705
|
||||
nRWE_N_173.CLK = RCLK_c
|
||||
nRWE_N_173.SP = RCLK_c_enable_23
|
||||
nRWE_N_173.LSR = GND
|
||||
nRCS_N_135.D = Ready_N_272
|
||||
nRCS_N_135.CLK = RCLK_c
|
||||
nRCS_N_135.SP = RCLK_c_enable_23
|
||||
nRCS_N_135.LSR = GND
|
||||
|
||||
comp 27: SLICE_63 (FSLICE)
|
||||
nRWE_N_167 = (~n2292*(~Ready*~n2164+Ready*nRWE_N_174)+n2292*(~Ready+nRWE_N_174))
|
||||
nRWE_c.D = nRWE_N_167
|
||||
nRWE_c.CLK = RCLK_c
|
||||
nRWE_c.SP = RCLK_c_enable_3
|
||||
nRWE_c.LSR = GND
|
||||
nRWE_N_174 = (~nRowColSel_N_35*(~n1+n1627)+nRowColSel_N_35*nRWE_N_178)
|
||||
|
||||
comp 28: SLICE_64 (FSLICE)
|
||||
n1368 = (~nRowColSel_N_32*(nRowColSel+n1627)+nRowColSel_N_32*(~nRowColSel_N_28+n1627))
|
||||
nRowColSel.D = n1368
|
||||
nRowColSel.CLK = RCLK_c
|
||||
nRowColSel.SP = VCC
|
||||
nRowColSel.LSR = n2299
|
||||
RA_c_4 = (~nRowColSel*RowA_4+nRowColSel*MAin_c_4)
|
||||
|
||||
comp 29: SLICE_65 (FSLICE)
|
||||
n1628 = (nRowColSel_N_32+nRowColSel_N_33)
|
||||
nRowColSel_N_32.D = n1628
|
||||
nRowColSel_N_32.CLK = RCLK_c
|
||||
nRowColSel_N_32.SP = VCC
|
||||
nRowColSel_N_32.LSR = ~RASr2
|
||||
RCLK_c_enable_4 = (((nRowColSel_N_32+n2299)+nRowColSel_N_34)+nRowColSel_N_33)
|
||||
|
||||
comp 30: SLICE_66 (FSLICE)
|
||||
n1135 = (RASr2*~nRowColSel_N_32)
|
||||
nRowColSel_N_33.D = n1135
|
||||
nRowColSel_N_33.CLK = RCLK_c
|
||||
nRowColSel_N_33.SP = VCC
|
||||
nRowColSel_N_33.LSR = ~nRowColSel_N_34
|
||||
n2117 = (~nRowColSel_N_33*(n1*~nRowColSel_N_34)+nRowColSel_N_33*(~n2304*~nRowColSel_N_34))
|
||||
|
||||
comp 31: SLICE_67 (FSLICE)
|
||||
LED_N_90 = (~LEDEN+nCRAS_c)
|
||||
nRowColSel_N_34.D = n1135
|
||||
nRowColSel_N_34.CLK = RCLK_c
|
||||
nRowColSel_N_34.SP = VCC
|
||||
nRowColSel_N_34.LSR = ~nRowColSel_N_35
|
||||
n2154 = (MAin_c_4*Bank_7)
|
||||
|
||||
comp 32: SLICE_68 (FSLICE)
|
||||
n2168 = (FS_3*(FS_2*(FS_0*FS_1)))
|
||||
nRowColSel_N_35.D = ~RASr2
|
||||
nRowColSel_N_35.CLK = RCLK_c
|
||||
nRowColSel_N_35.SP = VCC
|
||||
nRowColSel_N_35.LSR = GND
|
||||
n962 = (nCCAS_c+nFWE_c)
|
||||
CASr3.D = CASr2
|
||||
CASr3.CLK = RCLK_c
|
||||
CASr3.SP = VCC
|
||||
CASr3.LSR = GND
|
||||
|
||||
comp 33: SLICE_69 (FSLICE)
|
||||
n1348 = (~InitReady*n2076+InitReady*n1369)
|
||||
nUFMCS_c.D = n1348
|
||||
nUFMCS_c.CLK = RCLK_c
|
||||
nUFMCS_c.SP = VCC
|
||||
nUFMCS_c.LSR = LEDEN_N_88
|
||||
n2076 = (FS_17*(FS_11*(n12_adj_2*FS_15)))
|
||||
|
||||
comp 34: i1912/SLICE_70 (FSLICE)
|
||||
n2244 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~nRowColSel_N_35*n50))*Ready)+(((~nRowColSel_N_35*n50)+~InitReady+~RASr2)*~Ready)
|
||||
|
||||
comp 35: RCKEEN_I_0_419/SLICE_71 (FSLICE)
|
||||
RCKEEN_N_116 = (((~FWEr*~CBR)+~RASr2)*nRowColSel_N_35)+(((FWEr*n11_adj_3*~CBR)+(nRowColSel_N_34*~CBR))*~nRowColSel_N_35)
|
||||
|
||||
comp 36: SLICE_72 (FSLICE)
|
||||
PHI2_N_114_enable_7 = (Din_c_5*(~n2296*(n2298*XOR8MEG_N_112)))
|
||||
n702.D = n703
|
||||
n702.CLK = RCLK_c
|
||||
n702.SP = RCLK_c_enable_23
|
||||
n702.LSR = GND
|
||||
n2298 = (((Din_c_6+Din_c_7)+Din_c_5)+Din_c_4)
|
||||
n701.D = n702
|
||||
n701.CLK = RCLK_c
|
||||
n701.SP = RCLK_c_enable_23
|
||||
n701.LSR = GND
|
||||
|
||||
comp 37: SLICE_73 (FSLICE)
|
||||
n11 = (~n2168+((~FS_11+n2300)+FS_6))
|
||||
n706.D = n707
|
||||
n706.CLK = RCLK_c
|
||||
n706.SP = RCLK_c_enable_23
|
||||
n706.LSR = GND
|
||||
n2300 = ((FS_16+n10)+FS_17)
|
||||
n705.D = n706
|
||||
n705.CLK = RCLK_c
|
||||
n705.SP = RCLK_c_enable_23
|
||||
n705.LSR = GND
|
||||
|
||||
comp 38: SLICE_74 (FSLICE)
|
||||
C1Submitted_N_225 = (~n2131*(~Din_c_2*(n2295*n2122)))
|
||||
n710.D = n711
|
||||
n710.CLK = RCLK_c
|
||||
n710.SP = RCLK_c_enable_23
|
||||
n710.LSR = GND
|
||||
n2295 = (n2114*~nFWE_c)
|
||||
n709.D = n710
|
||||
n709.CLK = RCLK_c
|
||||
n709.SP = RCLK_c_enable_23
|
||||
n709.LSR = GND
|
||||
|
||||
comp 39: SLICE_75 (FSLICE)
|
||||
n2119 = (~n12*(~n11*(FS_10*n2294)))
|
||||
n708.D = n709
|
||||
n708.CLK = RCLK_c
|
||||
n708.SP = RCLK_c_enable_23
|
||||
n708.LSR = GND
|
||||
RCLK_c_enable_25 = (n2119*(FS_5*~InitReady))
|
||||
n707.D = n708
|
||||
n707.CLK = RCLK_c
|
||||
n707.SP = RCLK_c_enable_23
|
||||
n707.LSR = GND
|
||||
|
||||
comp 40: SLICE_76 (FSLICE)
|
||||
n2131 = ((~MAin_c_1+n1285)+MAin_c_0)
|
||||
WRD_0.D = Din_c_0
|
||||
WRD_0.CLK = ~nCCAS_c
|
||||
WRD_0.SP = VCC
|
||||
WRD_0.LSR = GND
|
||||
n1285 = (~MAin_c_5+(~n2170+(~Bank_3+n26)))
|
||||
WRD_1.D = Din_c_1
|
||||
WRD_1.CLK = ~nCCAS_c
|
||||
WRD_1.SP = VCC
|
||||
WRD_1.LSR = GND
|
||||
|
||||
comp 41: SLICE_77 (FSLICE)
|
||||
PHI2_N_114_enable_8 = (~MAin_c_1*(~n2286*(~n2290*MAin_c_0))+MAin_c_1*(~n2286*~n2290))
|
||||
RowA_2.D = MAin_c_2
|
||||
RowA_2.CLK = ~nCRAS_c
|
||||
RowA_2.SP = VCC
|
||||
RowA_2.LSR = ~Ready
|
||||
n2286 = (n2114*(~Din_c_2*n2080+Din_c_2*n2098))
|
||||
RowA_3.D = MAin_c_3
|
||||
RowA_3.CLK = ~nCRAS_c
|
||||
RowA_3.SP = VCC
|
||||
RowA_3.LSR = ~Ready
|
||||
|
||||
comp 42: SLICE_78 (FSLICE)
|
||||
n10 = (((FS_14+FS_13)+FS_12)+FS_15)
|
||||
CASr.D = ~nCCAS_c
|
||||
CASr.CLK = RCLK_c
|
||||
CASr.SP = VCC
|
||||
CASr.LSR = GND
|
||||
n2294 = (((FS_16+n10)+FS_17)+FS_11)
|
||||
PHI2r2.D = PHI2r
|
||||
PHI2r2.CLK = RCLK_c
|
||||
PHI2r2.SP = VCC
|
||||
PHI2r2.LSR = GND
|
||||
|
||||
comp 43: SLICE_79 (FSLICE)
|
||||
n1627 = (nRowColSel_N_34+nRowColSel_N_33)
|
||||
WRD_2.D = Din_c_2
|
||||
WRD_2.CLK = ~nCCAS_c
|
||||
WRD_2.SP = VCC
|
||||
WRD_2.LSR = GND
|
||||
RCLK_c_enable_3 = (((~Ready+nRowColSel_N_32)+n1627)+nRowColSel_N_35)
|
||||
WRD_3.D = Din_c_3
|
||||
WRD_3.CLK = ~nCCAS_c
|
||||
WRD_3.SP = VCC
|
||||
WRD_3.LSR = GND
|
||||
|
||||
comp 44: SLICE_80 (FSLICE)
|
||||
ADSubmitted_N_234 = (~n2289*(n4_adj_1*(MAin_c_0*n2108)))
|
||||
WRD_6.D = Din_c_6
|
||||
WRD_6.CLK = ~nCCAS_c
|
||||
WRD_6.SP = VCC
|
||||
WRD_6.LSR = GND
|
||||
n2289 = (~MAin_c_1+n1285)
|
||||
WRD_7.D = Din_c_7
|
||||
WRD_7.CLK = ~nCCAS_c
|
||||
WRD_7.SP = VCC
|
||||
WRD_7.LSR = GND
|
||||
|
||||
comp 45: SLICE_81 (FSLICE)
|
||||
n4_adj_1 = (n2114*(Din_c_2*~nFWE_c))
|
||||
RowA_8.D = MAin_c_8
|
||||
RowA_8.CLK = ~nCRAS_c
|
||||
RowA_8.SP = VCC
|
||||
RowA_8.LSR = ~Ready
|
||||
n2114 = (Din_c_7*(~Din_c_4*(~Din_c_1*Din_c_0)))
|
||||
RowA_9.D = MAin_c_9
|
||||
RowA_9.CLK = ~nCRAS_c
|
||||
RowA_9.SP = VCC
|
||||
RowA_9.LSR = ~Ready
|
||||
|
||||
comp 46: SLICE_82 (FSLICE)
|
||||
n2166 = (Bank_6*(MAin_c_2*(Bank_5*Bank_0)))
|
||||
RowA_0.D = MAin_c_0
|
||||
RowA_0.CLK = ~nCRAS_c
|
||||
RowA_0.SP = VCC
|
||||
RowA_0.LSR = ~Ready
|
||||
n26 = (~MAin_c_6+(~n2154+(~n2166+Bank_2)))
|
||||
RowA_1.D = MAin_c_1
|
||||
RowA_1.CLK = ~nCRAS_c
|
||||
RowA_1.SP = VCC
|
||||
RowA_1.LSR = ~Ready
|
||||
|
||||
comp 47: SLICE_83 (FSLICE)
|
||||
n2245 = (InitReady*(Ready_N_272*(~RASr2*nRowColSel_N_32)))
|
||||
CmdUFMCLK.D = Din_c_1
|
||||
CmdUFMCLK.CLK = ~PHI2_c
|
||||
CmdUFMCLK.SP = PHI2_N_114_enable_7
|
||||
CmdUFMCLK.LSR = GND
|
||||
Ready_N_268 = (n2245+Ready)
|
||||
CmdUFMCS.D = Din_c_2
|
||||
CmdUFMCS.CLK = ~PHI2_c
|
||||
CmdUFMCS.SP = PHI2_N_114_enable_7
|
||||
CmdUFMCS.LSR = GND
|
||||
|
||||
comp 48: SLICE_84 (FSLICE)
|
||||
nRowColSel_N_28 = ((~FWEr+CASr3)+CBR)
|
||||
nRCAS_N_161.D = nRCS_N_135
|
||||
nRCAS_N_161.CLK = RCLK_c
|
||||
nRCAS_N_161.SP = RCLK_c_enable_23
|
||||
nRCAS_N_161.LSR = GND
|
||||
n1 = (~CASr3*(CASr2*(FWEr*~CBR)))
|
||||
n703.D = nRWE_N_173
|
||||
n703.CLK = RCLK_c
|
||||
n703.SP = RCLK_c_enable_23
|
||||
n703.LSR = GND
|
||||
|
||||
comp 49: SLICE_85 (FSLICE)
|
||||
n12 = (((~FS_4+FS_9)+FS_8)+FS_7)
|
||||
PHI2r3.D = PHI2r2
|
||||
PHI2r3.CLK = RCLK_c
|
||||
PHI2r3.SP = VCC
|
||||
PHI2r3.LSR = GND
|
||||
n2103 = (~FS_9*(FS_7*~FS_8)+FS_9*(FS_5*(~FS_7*~FS_8)))
|
||||
PHI2r.D = PHI2_c
|
||||
PHI2r.CLK = RCLK_c
|
||||
PHI2r.SP = VCC
|
||||
PHI2r.LSR = GND
|
||||
|
||||
comp 50: SLICE_86 (FSLICE)
|
||||
n2291 = (~InitReady*(~n2300*~FS_11))
|
||||
RowA_6.D = MAin_c_6
|
||||
RowA_6.CLK = ~nCRAS_c
|
||||
RowA_6.SP = VCC
|
||||
RowA_6.LSR = ~Ready
|
||||
LEDEN_N_88 = (~InitReady*(~FS_10*(~n2300*~FS_11)))
|
||||
RowA_7.D = MAin_c_7
|
||||
RowA_7.CLK = ~nCRAS_c
|
||||
RowA_7.SP = VCC
|
||||
RowA_7.LSR = ~Ready
|
||||
|
||||
comp 51: SLICE_87 (FSLICE)
|
||||
n2122 = (~Din_c_5*(Din_c_6*~Din_c_3))
|
||||
Ready_N_272.D = n699
|
||||
Ready_N_272.CLK = RCLK_c
|
||||
Ready_N_272.SP = RCLK_c_enable_23
|
||||
Ready_N_272.LSR = GND
|
||||
n2108 = (Din_c_3*(Din_c_5*~Din_c_6))
|
||||
n711.D = nRCAS_N_161
|
||||
n711.CLK = RCLK_c
|
||||
n711.SP = RCLK_c_enable_23
|
||||
n711.LSR = GND
|
||||
|
||||
comp 52: SLICE_88 (FSLICE)
|
||||
RDQMH_c = (~nRowColSel+MAin_c_9)
|
||||
CmdUFMSDI.D = Din_c_0
|
||||
CmdUFMSDI.CLK = ~PHI2_c
|
||||
CmdUFMSDI.SP = PHI2_N_114_enable_7
|
||||
CmdUFMSDI.LSR = GND
|
||||
RA_c_9 = (~nRowColSel*RowA_9+nRowColSel*MAin_c_9)
|
||||
|
||||
comp 53: SLICE_89 (FSLICE)
|
||||
n2290 = (nFWE_c+n1285)
|
||||
LEDEN.D = ~UFMSDO_c
|
||||
LEDEN.CLK = RCLK_c
|
||||
LEDEN.SP = RCLK_c_enable_25
|
||||
LEDEN.LSR = GND
|
||||
PHI2_N_114_enable_1 = (MAin_c_1*(~n1285*~nFWE_c))
|
||||
|
||||
comp 54: SLICE_90 (FSLICE)
|
||||
PHI2_N_114_enable_6 = (Din_c_4*(XOR8MEG_N_112*(~Din_c_7*~Din_c_6)))
|
||||
n700.D = n701
|
||||
n700.CLK = RCLK_c
|
||||
n700.SP = RCLK_c_enable_23
|
||||
n700.LSR = GND
|
||||
PHI2_N_114_enable_2 = (XOR8MEG_N_112*(~Din_c_5*(~Din_c_4*~n2385)))
|
||||
n699.D = n700
|
||||
n699.CLK = RCLK_c
|
||||
n699.SP = RCLK_c_enable_23
|
||||
n699.LSR = GND
|
||||
|
||||
comp 55: SLICE_91 (FSLICE)
|
||||
n2248 = (~InitReady+(nRCAS_N_161+nRCS_N_135))
|
||||
CBR.D = ~nCCAS_c
|
||||
CBR.CLK = ~nCRAS_c
|
||||
CBR.SP = VCC
|
||||
CBR.LSR = GND
|
||||
n2292 = (~RASr2+(~InitReady+(~nRowColSel_N_35+nRCS_N_135)))
|
||||
FWEr.D = ~nFWE_c
|
||||
FWEr.CLK = ~nCRAS_c
|
||||
FWEr.SP = VCC
|
||||
FWEr.LSR = GND
|
||||
|
||||
comp 56: SLICE_92 (FSLICE)
|
||||
RDQML_c = (~nRowColSel+~MAin_c_9)
|
||||
RowA_4.D = MAin_c_4
|
||||
RowA_4.CLK = ~nCRAS_c
|
||||
RowA_4.SP = VCC
|
||||
RowA_4.LSR = ~Ready
|
||||
RA_c_0 = (~nRowColSel*RowA_0+nRowColSel*MAin_c_0)
|
||||
RowA_5.D = MAin_c_5
|
||||
RowA_5.CLK = ~nCRAS_c
|
||||
RowA_5.SP = VCC
|
||||
RowA_5.LSR = ~Ready
|
||||
|
||||
comp 57: SLICE_93 (FSLICE)
|
||||
n12_adj_2 = (FS_12*(FS_13*(FS_16*FS_14)))
|
||||
RASr2.D = RASr
|
||||
RASr2.CLK = RCLK_c
|
||||
RASr2.SP = VCC
|
||||
RASr2.LSR = GND
|
||||
n2293 = (~FS_11+((FS_16+n10)+FS_17))
|
||||
RASr3.D = RASr2
|
||||
RASr3.CLK = RCLK_c
|
||||
RASr3.SP = VCC
|
||||
RASr3.LSR = GND
|
||||
|
||||
comp 58: SLICE_94 (FSLICE)
|
||||
RA_c_1 = (~nRowColSel*RowA_1+nRowColSel*MAin_c_1)
|
||||
Bank_0.D = Din_c_0
|
||||
Bank_0.CLK = PHI2_c
|
||||
Bank_0.SP = VCC
|
||||
Bank_0.LSR = GND
|
||||
RA_c_3 = (~nRowColSel*RowA_3+nRowColSel*MAin_c_3)
|
||||
Bank_1.D = Din_c_1
|
||||
Bank_1.CLK = PHI2_c
|
||||
Bank_1.SP = VCC
|
||||
Bank_1.LSR = GND
|
||||
|
||||
comp 59: SLICE_95 (FSLICE)
|
||||
RA_c_8 = (~nRowColSel*RowA_8+nRowColSel*MAin_c_8)
|
||||
Bank_6.D = Din_c_6
|
||||
Bank_6.CLK = PHI2_c
|
||||
Bank_6.SP = VCC
|
||||
Bank_6.LSR = GND
|
||||
RA_c_2 = (~nRowColSel*RowA_2+nRowColSel*MAin_c_2)
|
||||
Bank_7.D = Din_c_7
|
||||
Bank_7.CLK = PHI2_c
|
||||
Bank_7.SP = VCC
|
||||
Bank_7.LSR = GND
|
||||
|
||||
comp 60: SLICE_96 (FSLICE)
|
||||
n2299 = (~Ready+nRowColSel_N_35)
|
||||
XOR8MEG.D = Din_c_0
|
||||
XOR8MEG.CLK = ~PHI2_c
|
||||
XOR8MEG.SP = PHI2_N_114_enable_2
|
||||
XOR8MEG.LSR = GND
|
||||
n2297 = (~nRowColSel_N_35+nRCS_N_135)
|
||||
|
||||
comp 61: SLICE_97 (FSLICE)
|
||||
RA_c_7 = (~nRowColSel*RowA_7+nRowColSel*MAin_c_7)
|
||||
Bank_4.D = Din_c_4
|
||||
Bank_4.CLK = PHI2_c
|
||||
Bank_4.SP = VCC
|
||||
Bank_4.LSR = GND
|
||||
n2170 = (Bank_1*(Bank_4*(MAin_c_3*MAin_c_7)))
|
||||
Bank_5.D = Din_c_5
|
||||
Bank_5.CLK = PHI2_c
|
||||
Bank_5.SP = VCC
|
||||
Bank_5.LSR = GND
|
||||
|
||||
comp 62: SLICE_98 (FSLICE)
|
||||
RA_c_6 = (~nRowColSel*RowA_6+nRowColSel*MAin_c_6)
|
||||
Bank_2.D = Din_c_2
|
||||
Bank_2.CLK = PHI2_c
|
||||
Bank_2.SP = VCC
|
||||
Bank_2.LSR = GND
|
||||
RA_c_5 = (~nRowColSel*RowA_5+nRowColSel*MAin_c_5)
|
||||
Bank_3.D = Din_c_3
|
||||
Bank_3.CLK = PHI2_c
|
||||
Bank_3.SP = VCC
|
||||
Bank_3.LSR = GND
|
||||
|
||||
comp 63: SLICE_99 (FSLICE)
|
||||
n2164 = (nRCAS_N_161+nRWE_N_173)
|
||||
RBA_c_0.D = CROW_c_0
|
||||
RBA_c_0.CLK = ~nCRAS_c
|
||||
RBA_c_0.SP = VCC
|
||||
RBA_c_0.LSR = ~Ready
|
||||
n18 = (nRowColSel_N_34*~nRowColSel_N_35)
|
||||
RBA_c_1.D = CROW_c_1
|
||||
RBA_c_1.CLK = ~nCRAS_c
|
||||
RBA_c_1.SP = VCC
|
||||
RBA_c_1.LSR = ~Ready
|
||||
|
||||
comp 64: SLICE_100 (FSLICE)
|
||||
n11_adj_3 = (~CASr2+nRowColSel_N_33)
|
||||
WRD_4.D = Din_c_4
|
||||
WRD_4.CLK = ~nCCAS_c
|
||||
WRD_4.SP = VCC
|
||||
WRD_4.LSR = GND
|
||||
n2304 = (FWEr+CBR)
|
||||
WRD_5.D = Din_c_5
|
||||
WRD_5.CLK = ~nCCAS_c
|
||||
WRD_5.SP = VCC
|
||||
WRD_5.LSR = GND
|
Binary file not shown.
Binary file not shown.
|
@ -0,0 +1,9 @@
|
|||
-w
|
||||
-l 5
|
||||
-i 6
|
||||
-n 1
|
||||
-t 1
|
||||
-s 1
|
||||
-c 0
|
||||
-e 0
|
||||
-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1
|
|
@ -0,0 +1,9 @@
|
|||
-w
|
||||
-l 5
|
||||
-i 6
|
||||
-n 1
|
||||
-t 1
|
||||
-s 1
|
||||
-c 0
|
||||
-e 0
|
||||
-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1
|
|
@ -0,0 +1,5 @@
|
|||
-rem
|
||||
-distrce
|
||||
-log "RAM2GS_LCMXO256C_impl1.log"
|
||||
-o "RAM2GS_LCMXO256C_impl1.csv"
|
||||
-pr "RAM2GS_LCMXO256C_impl1.prf"
|
|
@ -0,0 +1,271 @@
|
|||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO256C
|
||||
Performance Grade: 3
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.19
|
||||
|
||||
Mon Aug 16 21:32:33 2021
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+--------------+------+----------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | Properties |
|
||||
+-----------+----------+--------------+------+----------------------------------+
|
||||
| CROW[0] | 32/1 | LVTTL33_IN | PB2C | SLEW:FAST |
|
||||
| CROW[1] | 34/1 | LVTTL33_IN | PB2D | SLEW:FAST |
|
||||
| Din[0] | 21/1 | LVTTL33_IN | PL8A | SLEW:FAST |
|
||||
| Din[1] | 15/1 | LVTTL33_IN | PL6A | SLEW:FAST |
|
||||
| Din[2] | 14/1 | LVTTL33_IN | PL5D | SLEW:FAST |
|
||||
| Din[3] | 16/1 | LVTTL33_IN | PL6B | SLEW:FAST |
|
||||
| Din[4] | 18/1 | LVTTL33_IN | PL7B | SLEW:FAST |
|
||||
| Din[5] | 17/1 | LVTTL33_IN | PL7A | SLEW:FAST |
|
||||
| Din[6] | 20/1 | LVTTL33_IN | PL7D | SLEW:FAST |
|
||||
| Din[7] | 19/1 | LVTTL33_IN | PL7C | SLEW:FAST |
|
||||
| Dout[0] | 1/1 | LVTTL33_OUT | PL2A | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[1] | 7/1 | LVTTL33_OUT | PL4A | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[2] | 8/1 | LVTTL33_OUT | PL4B | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[3] | 6/1 | LVTTL33_OUT | PL3D | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[4] | 4/1 | LVTTL33_OUT | PL3B | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[5] | 5/1 | LVTTL33_OUT | PL3C | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[6] | 2/1 | LVTTL33_OUT | PL2B | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[7] | 3/1 | LVTTL33_OUT | PL3A | DRIVE:4mA SLEW:SLOW |
|
||||
| LED | 57/0 | LVTTL33_OUT | PR7B | DRIVE:16mA SLEW:SLOW |
|
||||
| MAin[0] | 23/1 | LVTTL33_IN | PL9A | SLEW:FAST |
|
||||
| MAin[1] | 38/1 | LVTTL33_IN | PB3C | SLEW:FAST |
|
||||
| MAin[2] | 37/1 | LVTTL33_IN | PB3B | SLEW:FAST |
|
||||
| MAin[3] | 47/1 | LVTTL33_IN | PB5A | SLEW:FAST |
|
||||
| MAin[4] | 46/1 | LVTTL33_IN | PB4D | SLEW:FAST |
|
||||
| MAin[5] | 45/1 | LVTTL33_IN | PB4C | SLEW:FAST |
|
||||
| MAin[6] | 49/1 | LVTTL33_IN | PB5C | SLEW:FAST |
|
||||
| MAin[7] | 44/1 | LVTTL33_IN | PB4B | SLEW:FAST |
|
||||
| MAin[8] | 50/1 | LVTTL33_IN | PB5D | SLEW:FAST |
|
||||
| MAin[9] | 51/0 | LVTTL33_IN | PR9B | SLEW:FAST |
|
||||
| PHI2 | 39/1 | LVTTL33_IN | PB3D | SLEW:FAST |
|
||||
| RA[0] | 98/0 | LVTTL33_OUT | PT2C | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 87/0 | LVTTL33_OUT | PT3D | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 79/0 | LVTTL33_OUT | PT5A | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 89/0 | LVTTL33_OUT | PT3C | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 94/0 | LVTTL33_OUT | PT3A | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 97/0 | LVTTL33_OUT | PT2D | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 99/0 | LVTTL33_OUT | PT2B | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 95/0 | LVTTL33_OUT | PT2F | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 91/0 | LVTTL33_OUT | PT3B | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 100/0 | LVTTL33_OUT | PT2A | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 96/0 | LVTTL33_OUT | PT2E | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 85/0 | LVTTL33_OUT | PT4B | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[0] | 63/0 | LVTTL33_OUT | PR5D | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 83/0 | LVTTL33_OUT | PT4C | DRIVE:4mA SLEW:SLOW |
|
||||
| RCKE | 82/0 | LVTTL33_OUT | PT4D | DRIVE:4mA SLEW:SLOW |
|
||||
| RCLK | 86/0 | LVTTL33_IN | PT4A | SLEW:FAST |
|
||||
| RDQMH | 76/0 | LVTTL33_OUT | PR2A | DRIVE:4mA SLEW:SLOW |
|
||||
| RDQML | 61/0 | LVTTL33_OUT | PR6A | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 64/0 | LVTTL33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| RD[1] | 65/0 | LVTTL33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| RD[2] | 66/0 | LVTTL33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| RD[3] | 67/0 | LVTTL33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| RD[4] | 68/0 | LVTTL33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| RD[5] | 69/0 | LVTTL33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| RD[6] | 70/0 | LVTTL33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| RD[7] | 71/0 | LVTTL33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
|
||||
| UFMCLK | 58/0 | LVTTL33_OUT | PR7A | DRIVE:4mA SLEW:SLOW |
|
||||
| UFMSDI | 56/0 | LVTTL33_OUT | PR7C | DRIVE:4mA SLEW:SLOW |
|
||||
| UFMSDO | 55/0 | LVTTL33_IN | PR7D | SLEW:FAST PULL:KEEPER |
|
||||
| nCCAS | 27/1 | LVTTL33_IN | PL9B | SLEW:FAST |
|
||||
| nCRAS | 43/1 | LVTTL33_IN | PB4A | SLEW:FAST |
|
||||
| nFWE | 22/1 | LVTTL33_IN | PL8B | SLEW:FAST |
|
||||
| nRCAS | 78/0 | LVTTL33_OUT | PT5B | DRIVE:4mA SLEW:SLOW |
|
||||
| nRCS | 77/0 | LVTTL33_OUT | PT5C | DRIVE:4mA SLEW:SLOW |
|
||||
| nRRAS | 73/0 | LVTTL33_OUT | PR2B | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 72/0 | LVTTL33_OUT | PR3A | DRIVE:4mA SLEW:SLOW |
|
||||
| nUFMCS | 53/0 | LVTTL33_OUT | PR8B | DRIVE:4mA SLEW:SLOW |
|
||||
+-----------+----------+--------------+------+----------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+---------------------+------------+--------------+------+---------------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function |
|
||||
+----------+---------------------+------------+--------------+------+---------------+
|
||||
| 1/1 | Dout[0] | LOCATED | LVTTL33_OUT | PL2A | |
|
||||
| 2/1 | Dout[6] | LOCATED | LVTTL33_OUT | PL2B | |
|
||||
| 3/1 | Dout[7] | LOCATED | LVTTL33_OUT | PL3A | |
|
||||
| 4/1 | Dout[4] | LOCATED | LVTTL33_OUT | PL3B | |
|
||||
| 5/1 | Dout[5] | LOCATED | LVTTL33_OUT | PL3C | |
|
||||
| 6/1 | Dout[3] | LOCATED | LVTTL33_OUT | PL3D | |
|
||||
| 7/1 | Dout[1] | LOCATED | LVTTL33_OUT | PL4A | |
|
||||
| 8/1 | Dout[2] | LOCATED | LVTTL33_OUT | PL4B | |
|
||||
| 9/1 | unused, PULL:UP | | | PL5A | |
|
||||
| 11/1 | unused, PULL:UP | | | PL5B | |
|
||||
| 13/1 | unused, PULL:UP | | | PL5C | |
|
||||
| 14/1 | Din[2] | LOCATED | LVTTL33_IN | PL5D | GSR_PADN |
|
||||
| 15/1 | Din[1] | LOCATED | LVTTL33_IN | PL6A | |
|
||||
| 16/1 | Din[3] | LOCATED | LVTTL33_IN | PL6B | TSALLPAD |
|
||||
| 17/1 | Din[5] | LOCATED | LVTTL33_IN | PL7A | |
|
||||
| 18/1 | Din[4] | LOCATED | LVTTL33_IN | PL7B | |
|
||||
| 19/1 | Din[7] | LOCATED | LVTTL33_IN | PL7C | |
|
||||
| 20/1 | Din[6] | LOCATED | LVTTL33_IN | PL7D | |
|
||||
| 21/1 | Din[0] | LOCATED | LVTTL33_IN | PL8A | |
|
||||
| 22/1 | nFWE | LOCATED | LVTTL33_IN | PL8B | |
|
||||
| 23/1 | MAin[0] | LOCATED | LVTTL33_IN | PL9A | |
|
||||
| 27/1 | nCCAS | LOCATED | LVTTL33_IN | PL9B | |
|
||||
| 29/1 | unused, PULL:UP | | | PB2A | |
|
||||
| 30/1 | unused, PULL:UP | | | PB2B | |
|
||||
| 32/1 | CROW[0] | LOCATED | LVTTL33_IN | PB2C | |
|
||||
| 34/1 | CROW[1] | LOCATED | LVTTL33_IN | PB2D | |
|
||||
| 36/1 | unused, PULL:UP | | | PB3A | PCLKT1_1 |
|
||||
| 37/1 | MAin[2] | LOCATED | LVTTL33_IN | PB3B | |
|
||||
| 38/1 | MAin[1] | LOCATED | LVTTL33_IN | PB3C | PCLKT1_0 |
|
||||
| 39/1 | PHI2 | LOCATED | LVTTL33_IN | PB3D | |
|
||||
| 43/1 | nCRAS | LOCATED | LVTTL33_IN | PB4A | |
|
||||
| 44/1 | MAin[7] | LOCATED | LVTTL33_IN | PB4B | |
|
||||
| 45/1 | MAin[5] | LOCATED | LVTTL33_IN | PB4C | |
|
||||
| 46/1 | MAin[4] | LOCATED | LVTTL33_IN | PB4D | |
|
||||
| 47/1 | MAin[3] | LOCATED | LVTTL33_IN | PB5A | |
|
||||
| 49/1 | MAin[6] | LOCATED | LVTTL33_IN | PB5C | |
|
||||
| 50/1 | MAin[8] | LOCATED | LVTTL33_IN | PB5D | |
|
||||
| 51/0 | MAin[9] | LOCATED | LVTTL33_IN | PR9B | |
|
||||
| 52/0 | unused, PULL:UP | | | PR9A | |
|
||||
| 53/0 | nUFMCS | LOCATED | LVTTL33_OUT | PR8B | |
|
||||
| 54/0 | unused, PULL:UP | | | PR8A | |
|
||||
| 55/0 | UFMSDO | LOCATED | LVTTL33_IN | PR7D | |
|
||||
| 56/0 | UFMSDI | LOCATED | LVTTL33_OUT | PR7C | |
|
||||
| 57/0 | LED | LOCATED | LVTTL33_OUT | PR7B | |
|
||||
| 58/0 | UFMCLK | LOCATED | LVTTL33_OUT | PR7A | |
|
||||
| 59/0 | unused, PULL:UP | | | PR6B | |
|
||||
| 61/0 | RDQML | LOCATED | LVTTL33_OUT | PR6A | |
|
||||
| 63/0 | RBA[0] | LOCATED | LVTTL33_OUT | PR5D | |
|
||||
| 64/0 | RD[0] | LOCATED | LVTTL33_BIDI | PR5C | |
|
||||
| 65/0 | RD[1] | LOCATED | LVTTL33_BIDI | PR5B | |
|
||||
| 66/0 | RD[2] | LOCATED | LVTTL33_BIDI | PR5A | |
|
||||
| 67/0 | RD[3] | LOCATED | LVTTL33_BIDI | PR4B | |
|
||||
| 68/0 | RD[4] | LOCATED | LVTTL33_BIDI | PR4A | |
|
||||
| 69/0 | RD[5] | LOCATED | LVTTL33_BIDI | PR3D | |
|
||||
| 70/0 | RD[6] | LOCATED | LVTTL33_BIDI | PR3C | |
|
||||
| 71/0 | RD[7] | LOCATED | LVTTL33_BIDI | PR3B | |
|
||||
| 72/0 | nRWE | LOCATED | LVTTL33_OUT | PR3A | |
|
||||
| 73/0 | nRRAS | LOCATED | LVTTL33_OUT | PR2B | |
|
||||
| 76/0 | RDQMH | LOCATED | LVTTL33_OUT | PR2A | |
|
||||
| 77/0 | nRCS | LOCATED | LVTTL33_OUT | PT5C | |
|
||||
| 78/0 | nRCAS | LOCATED | LVTTL33_OUT | PT5B | |
|
||||
| 79/0 | RA[11] | LOCATED | LVTTL33_OUT | PT5A | |
|
||||
| 80/0 | unused, PULL:UP | | | PT4F | |
|
||||
| 81/0 | unused, PULL:UP | | | PT4E | |
|
||||
| 82/0 | RCKE | LOCATED | LVTTL33_OUT | PT4D | |
|
||||
| 83/0 | RBA[1] | LOCATED | LVTTL33_OUT | PT4C | |
|
||||
| 85/0 | RA[9] | LOCATED | LVTTL33_OUT | PT4B | PCLKT0_1 |
|
||||
| 86/0 | RCLK | LOCATED | LVTTL33_IN | PT4A | PCLKT0_0 |
|
||||
| 87/0 | RA[10] | LOCATED | LVTTL33_OUT | PT3D | |
|
||||
| 89/0 | RA[1] | LOCATED | LVTTL33_OUT | PT3C | |
|
||||
| 91/0 | RA[6] | LOCATED | LVTTL33_OUT | PT3B | |
|
||||
| 94/0 | RA[2] | LOCATED | LVTTL33_OUT | PT3A | |
|
||||
| 95/0 | RA[5] | LOCATED | LVTTL33_OUT | PT2F | |
|
||||
| 96/0 | RA[8] | LOCATED | LVTTL33_OUT | PT2E | |
|
||||
| 97/0 | RA[3] | LOCATED | LVTTL33_OUT | PT2D | |
|
||||
| 98/0 | RA[0] | LOCATED | LVTTL33_OUT | PT2C | |
|
||||
| 99/0 | RA[4] | LOCATED | LVTTL33_OUT | PT2B | |
|
||||
| 100/0 | RA[7] | LOCATED | LVTTL33_OUT | PT2A | |
|
||||
| PB5B/0 | unused, PULL:UP | | | PB5B | |
|
||||
| PT5D/0 | unused, PULL:UP | | | PT5D | |
|
||||
| TCK/1 | | | | TCK | TCK |
|
||||
| TDI/1 | | | | TDI | TDI |
|
||||
| TDO/1 | | | | TDO | TDO |
|
||||
| TMS/1 | | | | TMS | TMS |
|
||||
+----------+---------------------+------------+--------------+------+---------------+
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "32";
|
||||
LOCATE COMP "CROW[1]" SITE "34";
|
||||
LOCATE COMP "Din[0]" SITE "21";
|
||||
LOCATE COMP "Din[1]" SITE "15";
|
||||
LOCATE COMP "Din[2]" SITE "14";
|
||||
LOCATE COMP "Din[3]" SITE "16";
|
||||
LOCATE COMP "Din[4]" SITE "18";
|
||||
LOCATE COMP "Din[5]" SITE "17";
|
||||
LOCATE COMP "Din[6]" SITE "20";
|
||||
LOCATE COMP "Din[7]" SITE "19";
|
||||
LOCATE COMP "Dout[0]" SITE "1";
|
||||
LOCATE COMP "Dout[1]" SITE "7";
|
||||
LOCATE COMP "Dout[2]" SITE "8";
|
||||
LOCATE COMP "Dout[3]" SITE "6";
|
||||
LOCATE COMP "Dout[4]" SITE "4";
|
||||
LOCATE COMP "Dout[5]" SITE "5";
|
||||
LOCATE COMP "Dout[6]" SITE "2";
|
||||
LOCATE COMP "Dout[7]" SITE "3";
|
||||
LOCATE COMP "LED" SITE "57";
|
||||
LOCATE COMP "MAin[0]" SITE "23";
|
||||
LOCATE COMP "MAin[1]" SITE "38";
|
||||
LOCATE COMP "MAin[2]" SITE "37";
|
||||
LOCATE COMP "MAin[3]" SITE "47";
|
||||
LOCATE COMP "MAin[4]" SITE "46";
|
||||
LOCATE COMP "MAin[5]" SITE "45";
|
||||
LOCATE COMP "MAin[6]" SITE "49";
|
||||
LOCATE COMP "MAin[7]" SITE "44";
|
||||
LOCATE COMP "MAin[8]" SITE "50";
|
||||
LOCATE COMP "MAin[9]" SITE "51";
|
||||
LOCATE COMP "PHI2" SITE "39";
|
||||
LOCATE COMP "RA[0]" SITE "98";
|
||||
LOCATE COMP "RA[10]" SITE "87";
|
||||
LOCATE COMP "RA[11]" SITE "79";
|
||||
LOCATE COMP "RA[1]" SITE "89";
|
||||
LOCATE COMP "RA[2]" SITE "94";
|
||||
LOCATE COMP "RA[3]" SITE "97";
|
||||
LOCATE COMP "RA[4]" SITE "99";
|
||||
LOCATE COMP "RA[5]" SITE "95";
|
||||
LOCATE COMP "RA[6]" SITE "91";
|
||||
LOCATE COMP "RA[7]" SITE "100";
|
||||
LOCATE COMP "RA[8]" SITE "96";
|
||||
LOCATE COMP "RA[9]" SITE "85";
|
||||
LOCATE COMP "RBA[0]" SITE "63";
|
||||
LOCATE COMP "RBA[1]" SITE "83";
|
||||
LOCATE COMP "RCKE" SITE "82";
|
||||
LOCATE COMP "RCLK" SITE "86";
|
||||
LOCATE COMP "RDQMH" SITE "76";
|
||||
LOCATE COMP "RDQML" SITE "61";
|
||||
LOCATE COMP "RD[0]" SITE "64";
|
||||
LOCATE COMP "RD[1]" SITE "65";
|
||||
LOCATE COMP "RD[2]" SITE "66";
|
||||
LOCATE COMP "RD[3]" SITE "67";
|
||||
LOCATE COMP "RD[4]" SITE "68";
|
||||
LOCATE COMP "RD[5]" SITE "69";
|
||||
LOCATE COMP "RD[6]" SITE "70";
|
||||
LOCATE COMP "RD[7]" SITE "71";
|
||||
LOCATE COMP "UFMCLK" SITE "58";
|
||||
LOCATE COMP "UFMSDI" SITE "56";
|
||||
LOCATE COMP "UFMSDO" SITE "55";
|
||||
LOCATE COMP "nCCAS" SITE "27";
|
||||
LOCATE COMP "nCRAS" SITE "43";
|
||||
LOCATE COMP "nFWE" SITE "22";
|
||||
LOCATE COMP "nRCAS" SITE "78";
|
||||
LOCATE COMP "nRCS" SITE "77";
|
||||
LOCATE COMP "nRRAS" SITE "73";
|
||||
LOCATE COMP "nRWE" SITE "72";
|
||||
LOCATE COMP "nUFMCS" SITE "53";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Mon Aug 16 21:32:33 2021
|
||||
|
|
@ -0,0 +1,239 @@
|
|||
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Mon Aug 16 21:32:27 2021
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
|
||||
RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
|
||||
RAM2GS_LCMXO256C_impl1.prf -gui -msgset
|
||||
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2GS_LCMXO256C_impl1.prf.
|
||||
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 2.023 0 0.339 0 07 Completed
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
|
||||
Mon Aug 16 21:32:27 2021
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
|
||||
Preference file: RAM2GS_LCMXO256C_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO256C
|
||||
Package: TQFP100
|
||||
Performance: 3
|
||||
Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.19.
|
||||
Performance Hardware Data Status: Version 1.124.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 67/79 84% used
|
||||
67/78 85% bonded
|
||||
SLICE 65/128 50% used
|
||||
|
||||
|
||||
|
||||
Number of Signals: 252
|
||||
Number of Connections: 618
|
||||
|
||||
Pin Constraint Summary:
|
||||
67 out of 67 pins locked (100% locked).
|
||||
|
||||
The following 4 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 39)
|
||||
PHI2_c (driver: PHI2, clk load #: 13)
|
||||
nCCAS_c (driver: nCCAS, clk load #: 4)
|
||||
nCRAS_c (driver: nCRAS, clk load #: 7)
|
||||
|
||||
No signal is selected as secondary clock.
|
||||
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
........
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
...............
|
||||
Placer score = 586066.
|
||||
Finished Placer Phase 1. REAL time: 6 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 584668
|
||||
Finished Placer Phase 2. REAL time: 6 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 1 out of 4 (25%)
|
||||
General PIO: 3 out of 80 (3%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 39
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13
|
||||
PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PL9B)", clk load = 4
|
||||
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7
|
||||
|
||||
PRIMARY : 4 out of 4 (100%)
|
||||
SECONDARY: 0 out of 4 (0%)
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
67 out of 79 (84.8%) PIO sites used.
|
||||
67 out of 78 (85.9%) bonded PIO sites used.
|
||||
Number of PIO comps: 67; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+------------+------------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 |
|
||||
+----------+----------------+------------+------------+------------+
|
||||
| 0 | 36 / 41 ( 87%) | 3.3V | - | - |
|
||||
| 1 | 31 / 37 ( 83%) | 3.3V | - | - |
|
||||
+----------+----------------+------------+------------+------------+
|
||||
|
||||
Total placer CPU time: 6 secs
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 618 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
|
||||
|
||||
Completed router resource preassignment. Real time: 6 secs
|
||||
|
||||
Start NBR router at 21:32:33 08/16/21
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 21:32:33 08/16/21
|
||||
|
||||
Start NBR section for initial routing at 21:32:33 08/16/21
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.038ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 21:32:33 08/16/21
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 2
|
||||
4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 3
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21
|
||||
|
||||
Start NBR section for re-routing at 21:32:33 08/16/21
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
|
||||
|
||||
Start NBR section for post-routing at 21:32:33 08/16/21
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 2.023ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 6 secs
|
||||
Total REAL time: 7 secs
|
||||
Completely routed.
|
||||
End of route. 618 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 2.023
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.339
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 6 secs
|
||||
Total REAL time to completion: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|
@ -0,0 +1,165 @@
|
|||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:32:26 2021
|
||||
|
||||
SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
|
||||
LOCATE COMP "RD[7]" SITE "71" ;
|
||||
LOCATE COMP "RD[6]" SITE "70" ;
|
||||
LOCATE COMP "RD[5]" SITE "69" ;
|
||||
LOCATE COMP "RD[4]" SITE "68" ;
|
||||
LOCATE COMP "RD[3]" SITE "67" ;
|
||||
LOCATE COMP "RD[2]" SITE "66" ;
|
||||
LOCATE COMP "RD[1]" SITE "65" ;
|
||||
LOCATE COMP "RD[0]" SITE "64" ;
|
||||
LOCATE COMP "Dout[7]" SITE "3" ;
|
||||
LOCATE COMP "Dout[6]" SITE "2" ;
|
||||
LOCATE COMP "Dout[5]" SITE "5" ;
|
||||
LOCATE COMP "Dout[4]" SITE "4" ;
|
||||
LOCATE COMP "Dout[3]" SITE "6" ;
|
||||
LOCATE COMP "Dout[2]" SITE "8" ;
|
||||
LOCATE COMP "Dout[1]" SITE "7" ;
|
||||
LOCATE COMP "Dout[0]" SITE "1" ;
|
||||
LOCATE COMP "LED" SITE "57" ;
|
||||
LOCATE COMP "RBA[1]" SITE "83" ;
|
||||
LOCATE COMP "RBA[0]" SITE "63" ;
|
||||
LOCATE COMP "RA[11]" SITE "79" ;
|
||||
LOCATE COMP "RA[10]" SITE "87" ;
|
||||
LOCATE COMP "RA[9]" SITE "85" ;
|
||||
LOCATE COMP "RA[8]" SITE "96" ;
|
||||
LOCATE COMP "RA[7]" SITE "100" ;
|
||||
LOCATE COMP "RA[6]" SITE "91" ;
|
||||
LOCATE COMP "RA[5]" SITE "95" ;
|
||||
LOCATE COMP "RA[4]" SITE "99" ;
|
||||
LOCATE COMP "RA[3]" SITE "97" ;
|
||||
LOCATE COMP "RA[2]" SITE "94" ;
|
||||
LOCATE COMP "RA[1]" SITE "89" ;
|
||||
LOCATE COMP "RA[0]" SITE "98" ;
|
||||
LOCATE COMP "nRCS" SITE "77" ;
|
||||
LOCATE COMP "RCKE" SITE "82" ;
|
||||
LOCATE COMP "nRWE" SITE "72" ;
|
||||
LOCATE COMP "nRRAS" SITE "73" ;
|
||||
LOCATE COMP "nRCAS" SITE "78" ;
|
||||
LOCATE COMP "RDQMH" SITE "76" ;
|
||||
LOCATE COMP "RDQML" SITE "61" ;
|
||||
LOCATE COMP "nUFMCS" SITE "53" ;
|
||||
LOCATE COMP "UFMCLK" SITE "58" ;
|
||||
LOCATE COMP "UFMSDI" SITE "56" ;
|
||||
LOCATE COMP "PHI2" SITE "39" ;
|
||||
LOCATE COMP "MAin[9]" SITE "51" ;
|
||||
LOCATE COMP "MAin[8]" SITE "50" ;
|
||||
LOCATE COMP "MAin[7]" SITE "44" ;
|
||||
LOCATE COMP "MAin[6]" SITE "49" ;
|
||||
LOCATE COMP "MAin[5]" SITE "45" ;
|
||||
LOCATE COMP "MAin[4]" SITE "46" ;
|
||||
LOCATE COMP "MAin[3]" SITE "47" ;
|
||||
LOCATE COMP "MAin[2]" SITE "37" ;
|
||||
LOCATE COMP "MAin[1]" SITE "38" ;
|
||||
LOCATE COMP "MAin[0]" SITE "23" ;
|
||||
LOCATE COMP "CROW[1]" SITE "34" ;
|
||||
LOCATE COMP "CROW[0]" SITE "32" ;
|
||||
LOCATE COMP "Din[7]" SITE "19" ;
|
||||
LOCATE COMP "Din[6]" SITE "20" ;
|
||||
LOCATE COMP "Din[5]" SITE "17" ;
|
||||
LOCATE COMP "Din[4]" SITE "18" ;
|
||||
LOCATE COMP "Din[3]" SITE "16" ;
|
||||
LOCATE COMP "Din[2]" SITE "14" ;
|
||||
LOCATE COMP "Din[1]" SITE "15" ;
|
||||
LOCATE COMP "Din[0]" SITE "21" ;
|
||||
LOCATE COMP "nCCAS" SITE "27" ;
|
||||
LOCATE COMP "nCRAS" SITE "43" ;
|
||||
LOCATE COMP "nFWE" SITE "22" ;
|
||||
LOCATE COMP "RCLK" SITE "86" ;
|
||||
LOCATE COMP "UFMSDO" SITE "55" ;
|
||||
PERIOD NET "PHI2_c" 350.000000 ns ;
|
||||
USE PRIMARY NET "RCLK_c" ;
|
||||
PERIOD NET "nCCAS_c" 350.000000 ns ;
|
||||
USE PRIMARY NET "PHI2_c" ;
|
||||
PERIOD NET "nCRAS_c" 350.000000 ns ;
|
||||
USE PRIMARY NET "nCCAS_c" ;
|
||||
PERIOD NET "RCLK_c" 16.000000 ns ;
|
||||
USE PRIMARY NET "nCRAS_c" ;
|
||||
SCHEMATIC END ;
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "LED" LOAD 25.000000 pF ;
|
||||
OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
|
||||
VOLTAGE 3.300 V;
|
||||
VCCIO_DERATE BANK 0 PERCENT -5;
|
||||
VCCIO_DERATE PERCENT -5;
|
||||
VCCIO_DERATE BANK 1 PERCENT -5;
|
||||
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
COMMERCIAL ;
|
|
@ -0,0 +1,10 @@
|
|||
-v
|
||||
10
|
||||
|
||||
|
||||
|
||||
|
||||
-gt
|
||||
-sethld
|
||||
-sp 3
|
||||
-sphld m
|
|
@ -0,0 +1,2 @@
|
|||
|
||||
-g ES:No
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,111 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Bitgen Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Mon Aug 16 21:36:25 2021
|
||||
|
||||
|
||||
Command: bitgen -w -g ES:No -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO256C
|
||||
Package: TQFP100
|
||||
Performance: 3
|
||||
Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.19.
|
||||
Performance Hardware Data Status: Version 1.124.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
|
||||
|
||||
<A name="bgn_ps"></A>
|
||||
<B><U><big>Preference Summary:</big></U></B>
|
||||
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ES | No** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 44 MB
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
|
@ -0,0 +1,202 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>I/O Timing Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Top"></A><B><U><big>I/O Timing Report</big></U></B>
|
||||
Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO256C
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Package Status: Final Version 1.19.
|
||||
Performance Hardware Data Status: Version 1.124.
|
||||
Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO256C
|
||||
Package: TQFP100
|
||||
Performance: 5
|
||||
Package Status: Final Version 1.19.
|
||||
Performance Hardware Data Status: Version 1.124.
|
||||
Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO256C
|
||||
Package: TQFP100
|
||||
Performance: M
|
||||
Package Status: Final Version 1.19.
|
||||
Performance Hardware Data Status: Version 1.124.
|
||||
// Design: RAM2GS
|
||||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo256c_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.0.240.2
|
||||
// Written on Mon Aug 16 21:32:34 2021
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
Worst Case Results across Performance Grades (M, 5, 4, 3):
|
||||
|
||||
// Input Setup and Hold Times
|
||||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F 0.215 3 1.805 3
|
||||
CROW[1] nCRAS F -0.050 M 2.105 3
|
||||
Din[0] PHI2 F 5.083 3 2.097 3
|
||||
Din[0] nCCAS F -0.020 M 2.133 3
|
||||
Din[1] PHI2 F 3.519 3 2.454 3
|
||||
Din[1] nCCAS F -0.146 M 2.462 3
|
||||
Din[2] PHI2 F 4.416 3 2.660 3
|
||||
Din[2] nCCAS F 0.272 3 1.853 3
|
||||
Din[3] PHI2 F 5.627 3 2.084 3
|
||||
Din[3] nCCAS F -0.024 M 2.144 3
|
||||
Din[4] PHI2 F 4.808 3 2.117 3
|
||||
Din[4] nCCAS F 0.350 3 1.766 3
|
||||
Din[5] PHI2 F 5.446 3 2.212 3
|
||||
Din[5] nCCAS F 0.435 3 1.708 3
|
||||
Din[6] PHI2 F 5.339 3 1.487 3
|
||||
Din[6] nCCAS F -0.140 M 2.452 3
|
||||
Din[7] PHI2 F 4.546 3 1.555 3
|
||||
Din[7] nCCAS F -0.016 M 2.122 3
|
||||
MAin[0] PHI2 F 4.027 3 0.711 3
|
||||
MAin[0] nCRAS F 1.132 3 0.987 3
|
||||
MAin[1] PHI2 F 4.032 3 1.734 3
|
||||
MAin[1] nCRAS F 0.704 3 1.373 3
|
||||
MAin[2] PHI2 F 10.358 3 -0.773 M
|
||||
MAin[2] nCRAS F -0.202 M 2.529 3
|
||||
MAin[3] PHI2 F 10.442 3 -0.829 M
|
||||
MAin[3] nCRAS F 0.186 3 1.819 3
|
||||
MAin[4] PHI2 F 10.311 3 -0.765 M
|
||||
MAin[4] nCRAS F 0.569 3 1.506 3
|
||||
MAin[5] PHI2 F 7.007 3 0.178 3
|
||||
MAin[5] nCRAS F 0.186 3 1.819 3
|
||||
MAin[6] PHI2 F 9.786 3 -0.641 M
|
||||
MAin[6] nCRAS F 0.177 3 1.829 3
|
||||
MAin[7] PHI2 F 10.008 3 -0.718 M
|
||||
MAin[7] nCRAS F -0.092 M 2.222 3
|
||||
MAin[8] nCRAS F -0.202 M 2.532 3
|
||||
MAin[9] nCRAS F 0.228 3 1.797 3
|
||||
PHI2 RCLK R 5.091 3 -0.759 M
|
||||
UFMSDO RCLK R 2.219 3 -0.104 M
|
||||
nCCAS RCLK R 3.820 3 -0.611 M
|
||||
nCCAS nCRAS F 1.538 3 0.708 3
|
||||
nCRAS RCLK R 4.749 3 -0.670 M
|
||||
nFWE PHI2 F 5.301 3 1.647 3
|
||||
nFWE nCRAS F 1.049 3 1.128 3
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 11.669 3 3.051 M
|
||||
RA[0] RCLK R 9.674 3 2.492 M
|
||||
RA[0] nCRAS F 12.127 3 3.067 M
|
||||
RA[10] RCLK R 8.596 3 2.220 M
|
||||
RA[11] PHI2 R 9.987 3 2.559 M
|
||||
RA[1] RCLK R 8.766 3 2.284 M
|
||||
RA[1] nCRAS F 11.652 3 2.982 M
|
||||
RA[2] RCLK R 10.062 3 2.599 M
|
||||
RA[2] nCRAS F 12.947 3 3.306 M
|
||||
RA[3] RCLK R 9.933 3 2.555 M
|
||||
RA[3] nCRAS F 12.783 3 3.240 M
|
||||
RA[4] RCLK R 8.504 3 2.219 M
|
||||
RA[4] nCRAS F 11.513 3 2.948 M
|
||||
RA[5] RCLK R 9.609 3 2.481 M
|
||||
RA[5] nCRAS F 11.870 3 3.010 M
|
||||
RA[6] RCLK R 10.001 3 2.579 M
|
||||
RA[6] nCRAS F 12.947 3 3.292 M
|
||||
RA[7] RCLK R 10.255 3 2.652 M
|
||||
RA[7] nCRAS F 12.177 3 3.089 M
|
||||
RA[8] RCLK R 8.896 3 2.316 M
|
||||
RA[8] nCRAS F 11.417 3 2.920 M
|
||||
RA[9] RCLK R 8.766 3 2.284 M
|
||||
RA[9] nCRAS F 11.617 3 2.957 M
|
||||
RBA[0] nCRAS F 9.698 3 2.483 M
|
||||
RBA[1] nCRAS F 11.425 3 2.916 M
|
||||
RCKE RCLK R 9.080 3 2.363 M
|
||||
RDQMH RCLK R 9.475 3 2.443 M
|
||||
RDQML RCLK R 10.477 3 2.713 M
|
||||
RD[0] nCCAS F 11.252 3 2.942 M
|
||||
RD[1] nCCAS F 11.963 3 3.100 M
|
||||
RD[2] nCCAS F 12.880 3 3.336 M
|
||||
RD[3] nCCAS F 12.422 3 3.224 M
|
||||
RD[4] nCCAS F 11.252 3 2.942 M
|
||||
RD[5] nCCAS F 12.423 3 3.212 M
|
||||
RD[6] nCCAS F 12.979 3 3.375 M
|
||||
RD[7] nCCAS F 12.914 3 3.350 M
|
||||
UFMCLK RCLK R 8.007 3 2.126 M
|
||||
UFMSDI RCLK R 8.007 3 2.126 M
|
||||
nRCAS RCLK R 8.595 3 2.232 M
|
||||
nRCS RCLK R 7.429 3 1.949 M
|
||||
nRRAS RCLK R 8.615 3 2.236 M
|
||||
nRWE RCLK R 7.429 3 1.949 M
|
||||
nUFMCS RCLK R 9.193 3 2.413 M
|
||||
WARNING: you must also run trce with hold speed: 3
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
|
@ -0,0 +1,41 @@
|
|||
-a "MachXO"
|
||||
-d LCMXO256C
|
||||
-t TQFP100
|
||||
-s 3
|
||||
-frequency 200
|
||||
-optimization_goal Balanced
|
||||
-bram_utilization 100
|
||||
-ramstyle Auto
|
||||
-romstyle auto
|
||||
-dsp_utilization 100
|
||||
-use_dsp 1
|
||||
-use_carry_chain 1
|
||||
-carry_chain_length 0
|
||||
-force_gsr Auto
|
||||
-resource_sharing 1
|
||||
-propagate_constants 1
|
||||
-remove_duplicate_regs 1
|
||||
-mux_style Auto
|
||||
-max_fanout 1000
|
||||
-fsm_encoding_style Auto
|
||||
-twr_paths 3
|
||||
-fix_gated_clocks 1
|
||||
-loop_limit 1950
|
||||
|
||||
|
||||
|
||||
-use_io_insertion 1
|
||||
-resolve_mixed_drivers 0
|
||||
-use_io_reg auto
|
||||
|
||||
|
||||
-lpf 1
|
||||
-p "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C"
|
||||
-ver "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
|
||||
-top RAM2GS
|
||||
|
||||
|
||||
-p "C:/lscc/diamond/3.12/ispfpga/mj5g00/data" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C"
|
||||
|
||||
-ngd "RAM2GS_LCMXO256C_impl1.ngd"
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
[ActiveSupport MAP]
|
||||
Device = LCMXO256C;
|
||||
Package = TQFP100;
|
||||
Performance = 3;
|
||||
LUTS_avail = 256;
|
||||
LUTS_used = 129;
|
||||
FF_avail = 256;
|
||||
FF_used = 102;
|
||||
INPUT_LVTTL33 = 26;
|
||||
OUTPUT_LVTTL33 = 33;
|
||||
BIDI_LVTTL33 = 8;
|
||||
IO_avail = 78;
|
||||
IO_used = 67;
|
|
@ -0,0 +1,108 @@
|
|||
[ START MERGED ]
|
||||
nCRAS_N_9 nCRAS_c
|
||||
nCCAS_N_3 nCCAS_c
|
||||
n2307 Ready
|
||||
n2306 nFWE_c
|
||||
PHI2_N_114 PHI2_c
|
||||
n2302 nRowColSel_N_35
|
||||
nRWE_N_172 nRWE_N_173
|
||||
UFMSDO_N_74 UFMSDO_c
|
||||
n1377 nRowColSel_N_34
|
||||
RASr2_N_63 RASr2
|
||||
[ END MERGED ]
|
||||
[ START CLIPPED ]
|
||||
GND_net
|
||||
VCC_net
|
||||
FS_577_add_4_14/CO0
|
||||
FS_577_add_4_16/CO0
|
||||
FS_577_add_4_12/CO0
|
||||
FS_577_add_4_2/CO0
|
||||
FS_577_add_4_4/CO0
|
||||
FS_577_add_4_6/CO0
|
||||
FS_577_add_4_18/CO1
|
||||
FS_577_add_4_18/CO0
|
||||
FS_577_add_4_8/CO0
|
||||
FS_577_add_4_10/CO0
|
||||
[ END CLIPPED ]
|
||||
[ START DESIGN PREFS ]
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:32:26 2021
|
||||
|
||||
SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
|
||||
LOCATE COMP "RD[7]" SITE "71" ;
|
||||
LOCATE COMP "RD[6]" SITE "70" ;
|
||||
LOCATE COMP "RD[5]" SITE "69" ;
|
||||
LOCATE COMP "RD[4]" SITE "68" ;
|
||||
LOCATE COMP "RD[3]" SITE "67" ;
|
||||
LOCATE COMP "RD[2]" SITE "66" ;
|
||||
LOCATE COMP "RD[1]" SITE "65" ;
|
||||
LOCATE COMP "RD[0]" SITE "64" ;
|
||||
LOCATE COMP "Dout[7]" SITE "3" ;
|
||||
LOCATE COMP "Dout[6]" SITE "2" ;
|
||||
LOCATE COMP "Dout[5]" SITE "5" ;
|
||||
LOCATE COMP "Dout[4]" SITE "4" ;
|
||||
LOCATE COMP "Dout[3]" SITE "6" ;
|
||||
LOCATE COMP "Dout[2]" SITE "8" ;
|
||||
LOCATE COMP "Dout[1]" SITE "7" ;
|
||||
LOCATE COMP "Dout[0]" SITE "1" ;
|
||||
LOCATE COMP "LED" SITE "57" ;
|
||||
LOCATE COMP "RBA[1]" SITE "83" ;
|
||||
LOCATE COMP "RBA[0]" SITE "63" ;
|
||||
LOCATE COMP "RA[11]" SITE "79" ;
|
||||
LOCATE COMP "RA[10]" SITE "87" ;
|
||||
LOCATE COMP "RA[9]" SITE "85" ;
|
||||
LOCATE COMP "RA[8]" SITE "96" ;
|
||||
LOCATE COMP "RA[7]" SITE "100" ;
|
||||
LOCATE COMP "RA[6]" SITE "91" ;
|
||||
LOCATE COMP "RA[5]" SITE "95" ;
|
||||
LOCATE COMP "RA[4]" SITE "99" ;
|
||||
LOCATE COMP "RA[3]" SITE "97" ;
|
||||
LOCATE COMP "RA[2]" SITE "94" ;
|
||||
LOCATE COMP "RA[1]" SITE "89" ;
|
||||
LOCATE COMP "RA[0]" SITE "98" ;
|
||||
LOCATE COMP "nRCS" SITE "77" ;
|
||||
LOCATE COMP "RCKE" SITE "82" ;
|
||||
LOCATE COMP "nRWE" SITE "72" ;
|
||||
LOCATE COMP "nRRAS" SITE "73" ;
|
||||
LOCATE COMP "nRCAS" SITE "78" ;
|
||||
LOCATE COMP "RDQMH" SITE "76" ;
|
||||
LOCATE COMP "RDQML" SITE "61" ;
|
||||
LOCATE COMP "nUFMCS" SITE "53" ;
|
||||
LOCATE COMP "UFMCLK" SITE "58" ;
|
||||
LOCATE COMP "UFMSDI" SITE "56" ;
|
||||
LOCATE COMP "PHI2" SITE "39" ;
|
||||
LOCATE COMP "MAin[9]" SITE "51" ;
|
||||
LOCATE COMP "MAin[8]" SITE "50" ;
|
||||
LOCATE COMP "MAin[7]" SITE "44" ;
|
||||
LOCATE COMP "MAin[6]" SITE "49" ;
|
||||
LOCATE COMP "MAin[5]" SITE "45" ;
|
||||
LOCATE COMP "MAin[4]" SITE "46" ;
|
||||
LOCATE COMP "MAin[3]" SITE "47" ;
|
||||
LOCATE COMP "MAin[2]" SITE "37" ;
|
||||
LOCATE COMP "MAin[1]" SITE "38" ;
|
||||
LOCATE COMP "MAin[0]" SITE "23" ;
|
||||
LOCATE COMP "CROW[1]" SITE "34" ;
|
||||
LOCATE COMP "CROW[0]" SITE "32" ;
|
||||
LOCATE COMP "Din[7]" SITE "19" ;
|
||||
LOCATE COMP "Din[6]" SITE "20" ;
|
||||
LOCATE COMP "Din[5]" SITE "17" ;
|
||||
LOCATE COMP "Din[4]" SITE "18" ;
|
||||
LOCATE COMP "Din[3]" SITE "16" ;
|
||||
LOCATE COMP "Din[2]" SITE "14" ;
|
||||
LOCATE COMP "Din[1]" SITE "15" ;
|
||||
LOCATE COMP "Din[0]" SITE "21" ;
|
||||
LOCATE COMP "nCCAS" SITE "27" ;
|
||||
LOCATE COMP "nCRAS" SITE "43" ;
|
||||
LOCATE COMP "nFWE" SITE "22" ;
|
||||
LOCATE COMP "RCLK" SITE "86" ;
|
||||
LOCATE COMP "UFMSDO" SITE "55" ;
|
||||
PERIOD NET "PHI2_c" 350.000000 ns ;
|
||||
USE PRIMARY NET "RCLK_c" ;
|
||||
PERIOD NET "nCCAS_c" 350.000000 ns ;
|
||||
USE PRIMARY NET "PHI2_c" ;
|
||||
PERIOD NET "nCRAS_c" 350.000000 ns ;
|
||||
USE PRIMARY NET "nCCAS_c" ;
|
||||
PERIOD NET "RCLK_c" 16.000000 ns ;
|
||||
USE PRIMARY NET "nCRAS_c" ;
|
||||
SCHEMATIC END ;
|
||||
[ END DESIGN PREFS ]
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue