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# -------------------------------------------------------------------------- #
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#
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||||||
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# Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
|
# Your use of Intel Corporation's design tools, logic functions
|
||||||
|
# and other software and tools, and any partner logic
|
||||||
|
# functions, and any output files from any of the foregoing
|
||||||
|
# (including device programming or simulation files), and any
|
||||||
|
# associated documentation or information are expressly subject
|
||||||
|
# to the terms and conditions of the Intel Program License
|
||||||
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
# the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
# agreement, including, without limitation, that your use is for
|
||||||
|
# the sole purpose of programming logic devices manufactured by
|
||||||
|
# Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
# refer to the applicable agreement for further details, at
|
||||||
|
# https://fpgasoftware.intel.com/eula.
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||||||
|
#
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||||||
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# -------------------------------------------------------------------------- #
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||||||
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#
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||||||
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# Quartus Prime
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||||||
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# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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||||||
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# Date created = 18:27:39 August 12, 2023
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||||||
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#
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||||||
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# -------------------------------------------------------------------------- #
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||||||
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QUARTUS_VERSION = "19.1"
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DATE = "18:27:39 August 12, 2023"
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# Revisions
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||||||
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PROJECT_REVISION = "RAM2GS"
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@ -0,0 +1,55 @@
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||||||
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# -------------------------------------------------------------------------- #
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||||||
|
#
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||||||
|
# Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
|
# Your use of Intel Corporation's design tools, logic functions
|
||||||
|
# and other software and tools, and any partner logic
|
||||||
|
# functions, and any output files from any of the foregoing
|
||||||
|
# (including device programming or simulation files), and any
|
||||||
|
# associated documentation or information are expressly subject
|
||||||
|
# to the terms and conditions of the Intel Program License
|
||||||
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
# the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
# agreement, including, without limitation, that your use is for
|
||||||
|
# the sole purpose of programming logic devices manufactured by
|
||||||
|
# Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
# refer to the applicable agreement for further details, at
|
||||||
|
# https://fpgasoftware.intel.com/eula.
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||||||
|
#
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||||||
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# -------------------------------------------------------------------------- #
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||||||
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#
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||||||
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# Quartus Prime
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||||||
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# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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# Date created = 18:27:39 August 12, 2023
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# RAM2GS_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "MAX II"
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set_global_assignment -name DEVICE EPM240T100C5
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set_global_assignment -name TOP_LEVEL_ENTITY RAM2GS
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:27:39 AUGUST 12, 2023"
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set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
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set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
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set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v"
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
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Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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Version_Index = 503488000
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Creation_Time = Sat Aug 12 18:39:09 2023
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691880040587 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691880040587 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 18:40:40 2023 " "Processing started: Sat Aug 12 18:40:40 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691880040587 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880040587 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880040587 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691880041058 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691880041058 ""}
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{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(52) " "Verilog HDL warning at RAM2GS-MAX.v(52): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691880053292 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691880053292 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880053292 ""}
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{ "Error" "ESGN_TOP_ENTITY_IS_MISSING" "RAM2GS " "Top-level design entity \"RAM2GS\" is undefined" { } { } 0 12007 "Top-level design entity \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1691880053355 ""}
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|
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4688 " "Peak virtual memory: 4688 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880053389 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sat Aug 12 18:40:53 2023 " "Processing ended: Sat Aug 12 18:40:53 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880053389 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880053389 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:29 " "Total CPU time (on all processors): 00:00:29" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880053389 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880053389 ""}
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SOURCE
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Flow report for RAM2GS
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Sat Aug 12 18:40:53 2023
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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||||||
|
---------------------
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|
; Table of Contents ;
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||||||
|
---------------------
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||||||
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1. Legal Notice
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2. Flow Summary
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||||||
|
3. Flow Settings
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|
4. Flow Non-Default Global Settings
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||||||
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5. Flow Elapsed Time
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6. Flow OS Summary
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7. Flow Log
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8. Flow Messages
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9. Flow Suppressed Messages
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||||||
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||||||
|
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||||||
|
----------------
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||||||
|
; Legal Notice ;
|
||||||
|
----------------
|
||||||
|
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
|
Your use of Intel Corporation's design tools, logic functions
|
||||||
|
and other software and tools, and any partner logic
|
||||||
|
functions, and any output files from any of the foregoing
|
||||||
|
(including device programming or simulation files), and any
|
||||||
|
associated documentation or information are expressly subject
|
||||||
|
to the terms and conditions of the Intel Program License
|
||||||
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
agreement, including, without limitation, that your use is for
|
||||||
|
the sole purpose of programming logic devices manufactured by
|
||||||
|
Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
refer to the applicable agreement for further details, at
|
||||||
|
https://fpgasoftware.intel.com/eula.
|
||||||
|
|
||||||
|
|
||||||
|
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|
+---------------------------------------------------------------------+
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||||||
|
; Flow Summary ;
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||||||
|
+-----------------------+---------------------------------------------+
|
||||||
|
; Flow Status ; Flow Failed - Sat Aug 12 18:40:53 2023 ;
|
||||||
|
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||||
|
; Revision Name ; RAM2GS ;
|
||||||
|
; Top-level Entity Name ; RAM2GS ;
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; Family ; MAX II ;
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; Device ; EPM240T100C5 ;
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|
; Timing Models ; Final ;
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|
+-----------------------+---------------------------------------------+
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||||||
|
|
||||||
|
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||||||
|
+-----------------------------------------+
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||||||
|
; Flow Settings ;
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||||||
|
+-------------------+---------------------+
|
||||||
|
; Option ; Setting ;
|
||||||
|
+-------------------+---------------------+
|
||||||
|
; Start date & time ; 08/12/2023 18:40:40 ;
|
||||||
|
; Main task ; Compilation ;
|
||||||
|
; Revision Name ; RAM2GS ;
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||||||
|
+-------------------+---------------------+
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||||||
|
|
||||||
|
|
||||||
|
+--------------------------------------------------------------------------------------------------------------------+
|
||||||
|
; Flow Non-Default Global Settings ;
|
||||||
|
+---------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||||
|
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||||
|
+---------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||||
|
; COMPILER_SIGNATURE_ID ; 207120313862967.169188004013584 ; -- ; -- ; -- ;
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||||||
|
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||||
|
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
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|
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
|
||||||
|
; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
|
||||||
|
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||||
|
+---------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||||
|
|
||||||
|
|
||||||
|
+--------------------------------------------------------------------------------------------------------------------------+
|
||||||
|
; Flow Elapsed Time ;
|
||||||
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||||
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
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; Analysis & Synthesis ; 00:00:13 ; 1.0 ; 4688 MB ; 00:00:29 ;
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||||||
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; Total ; 00:00:13 ; -- ; -- ; 00:00:29 ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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||||||
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||||||
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+------------------------------------------------------------------------------------+
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||||||
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; Flow OS Summary ;
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||||||
|
+----------------------+------------------+------------+------------+----------------+
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||||||
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; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
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||||||
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+----------------------+------------------+------------+------------+----------------+
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||||||
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; Analysis & Synthesis ; ZanePC ; Windows 10 ; 10.0 ; x86_64 ;
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||||||
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+----------------------+------------------+------------+------------+----------------+
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------------
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; Flow Log ;
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||||||
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------------
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||||||
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quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
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Analysis & Synthesis report for RAM2GS
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||||||
|
Sat Aug 12 18:40:53 2023
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||||||
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
|
||||||
|
|
||||||
|
---------------------
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||||||
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; Table of Contents ;
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||||||
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---------------------
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1. Legal Notice
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||||||
|
2. Analysis & Synthesis Summary
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||||||
|
3. Analysis & Synthesis Settings
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4. Parallel Compilation
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5. Analysis & Synthesis Messages
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||||||
|
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||||||
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||||||
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|
||||||
|
----------------
|
||||||
|
; Legal Notice ;
|
||||||
|
----------------
|
||||||
|
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
|
Your use of Intel Corporation's design tools, logic functions
|
||||||
|
and other software and tools, and any partner logic
|
||||||
|
functions, and any output files from any of the foregoing
|
||||||
|
(including device programming or simulation files), and any
|
||||||
|
associated documentation or information are expressly subject
|
||||||
|
to the terms and conditions of the Intel Program License
|
||||||
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
agreement, including, without limitation, that your use is for
|
||||||
|
the sole purpose of programming logic devices manufactured by
|
||||||
|
Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
refer to the applicable agreement for further details, at
|
||||||
|
https://fpgasoftware.intel.com/eula.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
+---------------------------------------------------------------------------+
|
||||||
|
; Analysis & Synthesis Summary ;
|
||||||
|
+-----------------------------+---------------------------------------------+
|
||||||
|
; Analysis & Synthesis Status ; Failed - Sat Aug 12 18:40:53 2023 ;
|
||||||
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; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||||
|
; Revision Name ; RAM2GS ;
|
||||||
|
; Top-level Entity Name ; RAM2GS ;
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||||||
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; Family ; MAX II ;
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||||||
|
+-----------------------------+---------------------------------------------+
|
||||||
|
|
||||||
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||||||
|
+------------------------------------------------------------------------------------------------------------+
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||||||
|
; Analysis & Synthesis Settings ;
|
||||||
|
+------------------------------------------------------------------+--------------------+--------------------+
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||||||
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; Option ; Setting ; Default Value ;
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||||||
|
+------------------------------------------------------------------+--------------------+--------------------+
|
||||||
|
; Device ; EPM240T100C5 ; ;
|
||||||
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; Top-level entity name ; RAM2GS ; RAM2GS ;
|
||||||
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; Family name ; MAX II ; Cyclone V ;
|
||||||
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; Use smart compilation ; Off ; Off ;
|
||||||
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; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
|
||||||
|
; Enable compact report table ; Off ; Off ;
|
||||||
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; Restructure Multiplexers ; Auto ; Auto ;
|
||||||
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; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
||||||
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; Preserve fewer node names ; On ; On ;
|
||||||
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; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
|
||||||
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; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
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||||||
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; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
||||||
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; State Machine Processing ; Auto ; Auto ;
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||||||
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; Safe State Machine ; Off ; Off ;
|
||||||
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; Extract Verilog State Machines ; On ; On ;
|
||||||
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; Extract VHDL State Machines ; On ; On ;
|
||||||
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; Ignore Verilog initial constructs ; Off ; Off ;
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||||||
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; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
|
||||||
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; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
|
||||||
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; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
|
||||||
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; Infer RAMs from Raw Logic ; On ; On ;
|
||||||
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; Parallel Synthesis ; On ; On ;
|
||||||
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; NOT Gate Push-Back ; On ; On ;
|
||||||
|
; Power-Up Don't Care ; On ; On ;
|
||||||
|
; Remove Redundant Logic Cells ; Off ; Off ;
|
||||||
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; Remove Duplicate Registers ; On ; On ;
|
||||||
|
; Ignore CARRY Buffers ; Off ; Off ;
|
||||||
|
; Ignore CASCADE Buffers ; Off ; Off ;
|
||||||
|
; Ignore GLOBAL Buffers ; Off ; Off ;
|
||||||
|
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
|
||||||
|
; Ignore LCELL Buffers ; Off ; Off ;
|
||||||
|
; Ignore SOFT Buffers ; On ; On ;
|
||||||
|
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
||||||
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; Optimization Technique ; Balanced ; Balanced ;
|
||||||
|
; Carry Chain Length ; 70 ; 70 ;
|
||||||
|
; Auto Carry Chains ; On ; On ;
|
||||||
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; Auto Open-Drain Pins ; On ; On ;
|
||||||
|
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
|
||||||
|
; Auto Shift Register Replacement ; Auto ; Auto ;
|
||||||
|
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
|
||||||
|
; Auto Clock Enable Replacement ; On ; On ;
|
||||||
|
; Allow Synchronous Control Signals ; On ; On ;
|
||||||
|
; Force Use of Synchronous Clear Signals ; Off ; Off ;
|
||||||
|
; Auto Resource Sharing ; Off ; Off ;
|
||||||
|
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
||||||
|
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
||||||
|
; Report Parameter Settings ; On ; On ;
|
||||||
|
; Report Source Assignments ; On ; On ;
|
||||||
|
; Report Connectivity Checks ; On ; On ;
|
||||||
|
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
||||||
|
; Synchronization Register Chain Length ; 2 ; 2 ;
|
||||||
|
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
|
||||||
|
; HDL message level ; Level2 ; Level2 ;
|
||||||
|
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
||||||
|
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||||
|
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||||
|
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
|
||||||
|
; Clock MUX Protection ; On ; On ;
|
||||||
|
; Block Design Naming ; Auto ; Auto ;
|
||||||
|
; Synthesis Effort ; Auto ; Auto ;
|
||||||
|
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
||||||
|
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
||||||
|
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
||||||
|
+------------------------------------------------------------------+--------------------+--------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+------------------------------------------+
|
||||||
|
; Parallel Compilation ;
|
||||||
|
+----------------------------+-------------+
|
||||||
|
; Processors ; Number ;
|
||||||
|
+----------------------------+-------------+
|
||||||
|
; Number detected on machine ; 8 ;
|
||||||
|
; Maximum allowed ; 4 ;
|
||||||
|
; ; ;
|
||||||
|
; Average used ; 1.00 ;
|
||||||
|
; Maximum used ; 1 ;
|
||||||
|
; ; ;
|
||||||
|
; Usage by Processor ; % Time Used ;
|
||||||
|
; Processor 1 ; 100.0% ;
|
||||||
|
+----------------------------+-------------+
|
||||||
|
|
||||||
|
|
||||||
|
+-------------------------------+
|
||||||
|
; Analysis & Synthesis Messages ;
|
||||||
|
+-------------------------------+
|
||||||
|
Info: *******************************************************************
|
||||||
|
Info: Running Quartus Prime Analysis & Synthesis
|
||||||
|
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
Info: Processing started: Sat Aug 12 18:40:40 2023
|
||||||
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
|
||||||
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
|
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||||||
|
Info (12021): Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v
|
||||||
|
Info (12023): Found entity 1: RAM4GS File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1
|
||||||
|
Error (12007): Top-level design entity "RAM2GS" is undefined
|
||||||
|
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning
|
||||||
|
Error: Peak virtual memory: 4688 megabytes
|
||||||
|
Error: Processing ended: Sat Aug 12 18:40:53 2023
|
||||||
|
Error: Elapsed time: 00:00:13
|
||||||
|
Error: Total CPU time (on all processors): 00:00:29
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1,5 @@
|
||||||
|
Analysis & Synthesis Status : Failed - Sat Aug 12 18:40:53 2023
|
||||||
|
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
Revision Name : RAM2GS
|
||||||
|
Top-level Entity Name : RAM2GS
|
||||||
|
Family : MAX II
|
|
@ -0,0 +1,31 @@
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
|
# Your use of Intel Corporation's design tools, logic functions
|
||||||
|
# and other software and tools, and any partner logic
|
||||||
|
# functions, and any output files from any of the foregoing
|
||||||
|
# (including device programming or simulation files), and any
|
||||||
|
# associated documentation or information are expressly subject
|
||||||
|
# to the terms and conditions of the Intel Program License
|
||||||
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
# the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
# agreement, including, without limitation, that your use is for
|
||||||
|
# the sole purpose of programming logic devices manufactured by
|
||||||
|
# Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
# refer to the applicable agreement for further details, at
|
||||||
|
# https://fpgasoftware.intel.com/eula.
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Quartus Prime
|
||||||
|
# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
# Date created = 18:28:29 August 12, 2023
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
|
||||||
|
QUARTUS_VERSION = "19.1"
|
||||||
|
DATE = "18:28:29 August 12, 2023"
|
||||||
|
|
||||||
|
# Revisions
|
||||||
|
|
||||||
|
PROJECT_REVISION = "RAM2GS"
|
|
@ -0,0 +1,53 @@
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
|
# Your use of Intel Corporation's design tools, logic functions
|
||||||
|
# and other software and tools, and any partner logic
|
||||||
|
# functions, and any output files from any of the foregoing
|
||||||
|
# (including device programming or simulation files), and any
|
||||||
|
# associated documentation or information are expressly subject
|
||||||
|
# to the terms and conditions of the Intel Program License
|
||||||
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
# the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
# agreement, including, without limitation, that your use is for
|
||||||
|
# the sole purpose of programming logic devices manufactured by
|
||||||
|
# Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
# refer to the applicable agreement for further details, at
|
||||||
|
# https://fpgasoftware.intel.com/eula.
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Quartus Prime
|
||||||
|
# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
# Date created = 18:28:29 August 12, 2023
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Notes:
|
||||||
|
#
|
||||||
|
# 1) The default values for assignments are stored in the file:
|
||||||
|
# RAM2GS_assignment_defaults.qdf
|
||||||
|
# If this file doesn't exist, see file:
|
||||||
|
# assignment_defaults.qdf
|
||||||
|
#
|
||||||
|
# 2) Altera recommends that you do not modify this file. This
|
||||||
|
# file is updated automatically by the Quartus Prime software
|
||||||
|
# and any changes you make may be lost or overwritten.
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
|
||||||
|
|
||||||
|
set_global_assignment -name FAMILY "MAX V"
|
||||||
|
set_global_assignment -name DEVICE 5M240ZT100C5
|
||||||
|
set_global_assignment -name TOP_LEVEL_ENTITY RAM2GS
|
||||||
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
|
||||||
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:28:29 AUGUST 12, 2023"
|
||||||
|
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
|
||||||
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||||
|
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||||
|
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
|
||||||
|
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
|
||||||
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||||
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||||
|
set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v"
|
||||||
|
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
|
Binary file not shown.
Binary file not shown.
|
@ -0,0 +1,3 @@
|
||||||
|
Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
Version_Index = 503488000
|
||||||
|
Creation_Time = Sat Aug 12 18:39:26 2023
|
Binary file not shown.
Binary file not shown.
|
@ -0,0 +1,9 @@
|
||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691880041624 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691880041639 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 12 18:40:41 2023 " "Processing started: Sat Aug 12 18:40:41 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691880041639 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880041639 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880041639 ""}
|
||||||
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691880042186 ""}
|
||||||
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691880042186 ""}
|
||||||
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(52) " "Verilog HDL warning at RAM2GS-MAX.v(52): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691880054014 ""}
|
||||||
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691880054014 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880054014 ""}
|
||||||
|
{ "Error" "ESGN_TOP_ENTITY_IS_MISSING" "RAM2GS " "Top-level design entity \"RAM2GS\" is undefined" { } { } 0 12007 "Top-level design entity \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1691880054045 ""}
|
||||||
|
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4687 " "Peak virtual memory: 4687 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691880054092 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sat Aug 12 18:40:54 2023 " "Processing ended: Sat Aug 12 18:40:54 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691880054092 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691880054092 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:29 " "Total CPU time (on all processors): 00:00:29" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691880054092 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691880054092 ""}
|
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
@ -0,0 +1 @@
|
||||||
|
SOURCE
|
Binary file not shown.
|
@ -0,0 +1,103 @@
|
||||||
|
Flow report for RAM2GS
|
||||||
|
Sat Aug 12 18:40:54 2023
|
||||||
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
|
||||||
|
|
||||||
|
---------------------
|
||||||
|
; Table of Contents ;
|
||||||
|
---------------------
|
||||||
|
1. Legal Notice
|
||||||
|
2. Flow Summary
|
||||||
|
3. Flow Settings
|
||||||
|
4. Flow Non-Default Global Settings
|
||||||
|
5. Flow Elapsed Time
|
||||||
|
6. Flow OS Summary
|
||||||
|
7. Flow Log
|
||||||
|
8. Flow Messages
|
||||||
|
9. Flow Suppressed Messages
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
----------------
|
||||||
|
; Legal Notice ;
|
||||||
|
----------------
|
||||||
|
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
|
Your use of Intel Corporation's design tools, logic functions
|
||||||
|
and other software and tools, and any partner logic
|
||||||
|
functions, and any output files from any of the foregoing
|
||||||
|
(including device programming or simulation files), and any
|
||||||
|
associated documentation or information are expressly subject
|
||||||
|
to the terms and conditions of the Intel Program License
|
||||||
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
agreement, including, without limitation, that your use is for
|
||||||
|
the sole purpose of programming logic devices manufactured by
|
||||||
|
Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
refer to the applicable agreement for further details, at
|
||||||
|
https://fpgasoftware.intel.com/eula.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
+---------------------------------------------------------------------+
|
||||||
|
; Flow Summary ;
|
||||||
|
+-----------------------+---------------------------------------------+
|
||||||
|
; Flow Status ; Flow Failed - Sat Aug 12 18:40:54 2023 ;
|
||||||
|
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||||
|
; Revision Name ; RAM2GS ;
|
||||||
|
; Top-level Entity Name ; RAM2GS ;
|
||||||
|
; Family ; MAX V ;
|
||||||
|
; Device ; 5M240ZT100C5 ;
|
||||||
|
; Timing Models ; Final ;
|
||||||
|
+-----------------------+---------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+-----------------------------------------+
|
||||||
|
; Flow Settings ;
|
||||||
|
+-------------------+---------------------+
|
||||||
|
; Option ; Setting ;
|
||||||
|
+-------------------+---------------------+
|
||||||
|
; Start date & time ; 08/12/2023 18:40:42 ;
|
||||||
|
; Main task ; Compilation ;
|
||||||
|
; Revision Name ; RAM2GS ;
|
||||||
|
+-------------------+---------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+------------------------------------------------------------------------------------------------------------+
|
||||||
|
; Flow Non-Default Global Settings ;
|
||||||
|
+-------------------------------+---------------------------------+---------------+-------------+------------+
|
||||||
|
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||||
|
+-------------------------------+---------------------------------+---------------+-------------+------------+
|
||||||
|
; COMPILER_SIGNATURE_ID ; 207120313862967.169188004113676 ; -- ; -- ; -- ;
|
||||||
|
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||||
|
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||||
|
; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
|
||||||
|
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||||
|
+-------------------------------+---------------------------------+---------------+-------------+------------+
|
||||||
|
|
||||||
|
|
||||||
|
+--------------------------------------------------------------------------------------------------------------------------+
|
||||||
|
; Flow Elapsed Time ;
|
||||||
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||||
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
|
; Analysis & Synthesis ; 00:00:13 ; 1.0 ; 4687 MB ; 00:00:29 ;
|
||||||
|
; Total ; 00:00:13 ; -- ; -- ; 00:00:29 ;
|
||||||
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+------------------------------------------------------------------------------------+
|
||||||
|
; Flow OS Summary ;
|
||||||
|
+----------------------+------------------+------------+------------+----------------+
|
||||||
|
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||||
|
+----------------------+------------------+------------+------------+----------------+
|
||||||
|
; Analysis & Synthesis ; ZanePC ; Windows 10 ; 10.0 ; x86_64 ;
|
||||||
|
+----------------------+------------------+------------+------------+----------------+
|
||||||
|
|
||||||
|
|
||||||
|
------------
|
||||||
|
; Flow Log ;
|
||||||
|
------------
|
||||||
|
quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1,154 @@
|
||||||
|
Analysis & Synthesis report for RAM2GS
|
||||||
|
Sat Aug 12 18:40:54 2023
|
||||||
|
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
|
||||||
|
|
||||||
|
---------------------
|
||||||
|
; Table of Contents ;
|
||||||
|
---------------------
|
||||||
|
1. Legal Notice
|
||||||
|
2. Analysis & Synthesis Summary
|
||||||
|
3. Analysis & Synthesis Settings
|
||||||
|
4. Parallel Compilation
|
||||||
|
5. Analysis & Synthesis Messages
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
----------------
|
||||||
|
; Legal Notice ;
|
||||||
|
----------------
|
||||||
|
Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||||
|
Your use of Intel Corporation's design tools, logic functions
|
||||||
|
and other software and tools, and any partner logic
|
||||||
|
functions, and any output files from any of the foregoing
|
||||||
|
(including device programming or simulation files), and any
|
||||||
|
associated documentation or information are expressly subject
|
||||||
|
to the terms and conditions of the Intel Program License
|
||||||
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
agreement, including, without limitation, that your use is for
|
||||||
|
the sole purpose of programming logic devices manufactured by
|
||||||
|
Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
refer to the applicable agreement for further details, at
|
||||||
|
https://fpgasoftware.intel.com/eula.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
+---------------------------------------------------------------------------+
|
||||||
|
; Analysis & Synthesis Summary ;
|
||||||
|
+-----------------------------+---------------------------------------------+
|
||||||
|
; Analysis & Synthesis Status ; Failed - Sat Aug 12 18:40:54 2023 ;
|
||||||
|
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||||
|
; Revision Name ; RAM2GS ;
|
||||||
|
; Top-level Entity Name ; RAM2GS ;
|
||||||
|
; Family ; MAX V ;
|
||||||
|
+-----------------------------+---------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+------------------------------------------------------------------------------------------------------------+
|
||||||
|
; Analysis & Synthesis Settings ;
|
||||||
|
+------------------------------------------------------------------+--------------------+--------------------+
|
||||||
|
; Option ; Setting ; Default Value ;
|
||||||
|
+------------------------------------------------------------------+--------------------+--------------------+
|
||||||
|
; Device ; 5M240ZT100C5 ; ;
|
||||||
|
; Top-level entity name ; RAM2GS ; RAM2GS ;
|
||||||
|
; Family name ; MAX V ; Cyclone V ;
|
||||||
|
; Use smart compilation ; Off ; Off ;
|
||||||
|
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
|
||||||
|
; Enable compact report table ; Off ; Off ;
|
||||||
|
; Restructure Multiplexers ; Auto ; Auto ;
|
||||||
|
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
||||||
|
; Preserve fewer node names ; On ; On ;
|
||||||
|
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
|
||||||
|
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
||||||
|
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
||||||
|
; State Machine Processing ; Auto ; Auto ;
|
||||||
|
; Safe State Machine ; Off ; Off ;
|
||||||
|
; Extract Verilog State Machines ; On ; On ;
|
||||||
|
; Extract VHDL State Machines ; On ; On ;
|
||||||
|
; Ignore Verilog initial constructs ; Off ; Off ;
|
||||||
|
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
|
||||||
|
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
|
||||||
|
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
|
||||||
|
; Infer RAMs from Raw Logic ; On ; On ;
|
||||||
|
; Parallel Synthesis ; On ; On ;
|
||||||
|
; NOT Gate Push-Back ; On ; On ;
|
||||||
|
; Power-Up Don't Care ; On ; On ;
|
||||||
|
; Remove Redundant Logic Cells ; Off ; Off ;
|
||||||
|
; Remove Duplicate Registers ; On ; On ;
|
||||||
|
; Ignore CARRY Buffers ; Off ; Off ;
|
||||||
|
; Ignore CASCADE Buffers ; Off ; Off ;
|
||||||
|
; Ignore GLOBAL Buffers ; Off ; Off ;
|
||||||
|
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
|
||||||
|
; Ignore LCELL Buffers ; Off ; Off ;
|
||||||
|
; Ignore SOFT Buffers ; On ; On ;
|
||||||
|
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
||||||
|
; Optimization Technique ; Balanced ; Balanced ;
|
||||||
|
; Carry Chain Length ; 70 ; 70 ;
|
||||||
|
; Auto Carry Chains ; On ; On ;
|
||||||
|
; Auto Open-Drain Pins ; On ; On ;
|
||||||
|
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
|
||||||
|
; Auto Shift Register Replacement ; Auto ; Auto ;
|
||||||
|
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
|
||||||
|
; Auto Clock Enable Replacement ; On ; On ;
|
||||||
|
; Allow Synchronous Control Signals ; On ; On ;
|
||||||
|
; Force Use of Synchronous Clear Signals ; Off ; Off ;
|
||||||
|
; Auto Resource Sharing ; Off ; Off ;
|
||||||
|
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
||||||
|
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
||||||
|
; Report Parameter Settings ; On ; On ;
|
||||||
|
; Report Source Assignments ; On ; On ;
|
||||||
|
; Report Connectivity Checks ; On ; On ;
|
||||||
|
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
||||||
|
; Synchronization Register Chain Length ; 2 ; 2 ;
|
||||||
|
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
|
||||||
|
; HDL message level ; Level2 ; Level2 ;
|
||||||
|
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
||||||
|
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||||
|
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||||
|
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
|
||||||
|
; Clock MUX Protection ; On ; On ;
|
||||||
|
; Block Design Naming ; Auto ; Auto ;
|
||||||
|
; Synthesis Effort ; Auto ; Auto ;
|
||||||
|
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
||||||
|
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
||||||
|
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
||||||
|
+------------------------------------------------------------------+--------------------+--------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+------------------------------------------+
|
||||||
|
; Parallel Compilation ;
|
||||||
|
+----------------------------+-------------+
|
||||||
|
; Processors ; Number ;
|
||||||
|
+----------------------------+-------------+
|
||||||
|
; Number detected on machine ; 8 ;
|
||||||
|
; Maximum allowed ; 4 ;
|
||||||
|
; ; ;
|
||||||
|
; Average used ; 1.00 ;
|
||||||
|
; Maximum used ; 1 ;
|
||||||
|
; ; ;
|
||||||
|
; Usage by Processor ; % Time Used ;
|
||||||
|
; Processor 1 ; 100.0% ;
|
||||||
|
+----------------------------+-------------+
|
||||||
|
|
||||||
|
|
||||||
|
+-------------------------------+
|
||||||
|
; Analysis & Synthesis Messages ;
|
||||||
|
+-------------------------------+
|
||||||
|
Info: *******************************************************************
|
||||||
|
Info: Running Quartus Prime Analysis & Synthesis
|
||||||
|
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
Info: Processing started: Sat Aug 12 18:40:41 2023
|
||||||
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
|
||||||
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
|
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||||||
|
Info (12021): Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v
|
||||||
|
Info (12023): Found entity 1: RAM4GS File: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1
|
||||||
|
Error (12007): Top-level design entity "RAM2GS" is undefined
|
||||||
|
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning
|
||||||
|
Error: Peak virtual memory: 4687 megabytes
|
||||||
|
Error: Processing ended: Sat Aug 12 18:40:54 2023
|
||||||
|
Error: Elapsed time: 00:00:13
|
||||||
|
Error: Total CPU time (on all processors): 00:00:29
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1,5 @@
|
||||||
|
Analysis & Synthesis Status : Failed - Sat Aug 12 18:40:54 2023
|
||||||
|
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||||
|
Revision Name : RAM2GS
|
||||||
|
Top-level Entity Name : RAM2GS
|
||||||
|
Family : MAX V
|
|
@ -0,0 +1,436 @@
|
||||||
|
module RAM4GS(PHI2, MAin, CROW, Din, Dout,
|
||||||
|
nCCAS, nCRAS, nFWE,
|
||||||
|
RBA, RA, RD, nRCS, RCLK, RCKE,
|
||||||
|
nRWE, nRRAS, nRCAS, RDQMH, RDQML);
|
||||||
|
|
||||||
|
/* 65816 Phase 2 Clock */
|
||||||
|
input PHI2;
|
||||||
|
|
||||||
|
/* Async. DRAM Control Inputs */
|
||||||
|
input nCCAS, nCRAS;
|
||||||
|
|
||||||
|
/* Synchronized PHI2 and DRAM signals */
|
||||||
|
reg PHI2r, PHI2r2, PHI2r3;
|
||||||
|
reg RASr, RASr2, RASr3;
|
||||||
|
reg CASr, CASr2, CASr3;
|
||||||
|
reg FWEr;
|
||||||
|
reg CBR;
|
||||||
|
|
||||||
|
/* 65816 Data */
|
||||||
|
input [7:0] Din;
|
||||||
|
output [7:0] Dout = RD[7:0];
|
||||||
|
|
||||||
|
/* Latched 65816 Bank Address */
|
||||||
|
reg [7:0] Bank;
|
||||||
|
|
||||||
|
/* Async. DRAM Address Bus */
|
||||||
|
input [1:0] CROW;
|
||||||
|
input [9:0] MAin;
|
||||||
|
input nFWE;
|
||||||
|
reg n8MEGEN = 0;
|
||||||
|
reg XOR8MEG = 0;
|
||||||
|
|
||||||
|
/* SDRAM Clock */
|
||||||
|
input RCLK;
|
||||||
|
|
||||||
|
/* SDRAM */
|
||||||
|
reg RCKEEN;
|
||||||
|
output reg RCKE = 0;
|
||||||
|
output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
|
||||||
|
output reg [1:0] RBA;
|
||||||
|
reg nRowColSel;
|
||||||
|
reg RA11;
|
||||||
|
reg RA10;
|
||||||
|
reg [9:0] RowA;
|
||||||
|
output [11:0] RA;
|
||||||
|
assign RA[11] = RA11;
|
||||||
|
assign RA[10] = RA10;
|
||||||
|
assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
|
||||||
|
output RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
|
||||||
|
output RDQMH = ~nRowColSel ? 1'b1 : MAin[9];
|
||||||
|
reg [7:0] WRD;
|
||||||
|
inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
|
||||||
|
|
||||||
|
/* UFM Interface */
|
||||||
|
reg UFMD = 0; // UFM data register bit 15
|
||||||
|
reg ARCLK = 0; // UFM address register clock
|
||||||
|
// UFM address register data input tied to 0
|
||||||
|
reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
|
||||||
|
reg DRCLK = 0; // UFM data register clock
|
||||||
|
reg DRDIn = 0; // UFM data register input
|
||||||
|
reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
|
||||||
|
reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
|
||||||
|
reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
|
||||||
|
reg UFMOscEN = 0; // UFM oscillator enable
|
||||||
|
wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
|
||||||
|
wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
|
||||||
|
wire DRDOut; // UFM data output
|
||||||
|
// UFM oscillator always enabled
|
||||||
|
wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
|
||||||
|
UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
|
||||||
|
.arclk (ARCLK),
|
||||||
|
.ardin (1'b0),
|
||||||
|
.arshft (ARShift),
|
||||||
|
.drclk (DRCLK),
|
||||||
|
.drdin (DRDIn),
|
||||||
|
.drshft (DRShift),
|
||||||
|
.erase (UFMErase),
|
||||||
|
.oscena (UFMOscEN),
|
||||||
|
.program (UFMProgram),
|
||||||
|
.busy (UFMBusy),
|
||||||
|
.drdout (DRDOut),
|
||||||
|
.osc (UFMOsc),
|
||||||
|
.rtpbusy (RTPBusy));
|
||||||
|
reg UFMBusyReg = 0; // UFMBusy registered to sync with RCLK
|
||||||
|
reg RTPBusyReg = 0; // RTPBusy registered to sync with RCLK
|
||||||
|
|
||||||
|
/* UFM State */
|
||||||
|
reg UFMInitDone = 0; // 1 if UFM initialization finished
|
||||||
|
reg UFMReqErase = 0; // 1 if UFM requires erase
|
||||||
|
|
||||||
|
/* UFM Command Interface */
|
||||||
|
reg C1Submitted = 0;
|
||||||
|
reg ADSubmitted = 0;
|
||||||
|
reg CmdEnable = 0;
|
||||||
|
reg CmdSubmitted = 0;
|
||||||
|
reg Cmdn8MEGEN = 0;
|
||||||
|
reg CmdDRCLK = 0;
|
||||||
|
reg CmdDRDIn = 0;
|
||||||
|
reg CmdUFMErase = 0; // Set by user command. Programs UFM
|
||||||
|
reg CmdUFMPrgm = 0; // Set by user command. Erases UFM
|
||||||
|
wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
|
||||||
|
wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
|
||||||
|
wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
|
||||||
|
|
||||||
|
/* State Counters */
|
||||||
|
reg InitReady = 0; // 1 if ready for init sequence
|
||||||
|
reg Ready = 0; // 1 if done with init sequence
|
||||||
|
reg [1:0] S = 0; // post-RAS State counter
|
||||||
|
reg [17:0] FS = 0; // Fast init state counter
|
||||||
|
reg [3:0] IS = 0; // Init state counter
|
||||||
|
reg WriteDone;
|
||||||
|
|
||||||
|
/* Synchronize PHI2, RAS, CAS */
|
||||||
|
always @(posedge RCLK) begin
|
||||||
|
PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
|
||||||
|
RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
|
||||||
|
CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
|
||||||
|
end
|
||||||
|
|
||||||
|
/* Latch 65816 bank when PHI2 rises */
|
||||||
|
always @(posedge PHI2) begin
|
||||||
|
if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
|
||||||
|
else RA11 <= 1'b0; // Reserved in mode register
|
||||||
|
Bank[7:0] <= Din[7:0]; // Latch bank
|
||||||
|
end
|
||||||
|
|
||||||
|
/* Latch bank address, row address, WE, and CAS when RAS falls */
|
||||||
|
always @(negedge nCRAS) begin
|
||||||
|
if (Ready) begin
|
||||||
|
RBA[1:0] <= CROW[1:0];
|
||||||
|
RowA[9:0] <= MAin[9:0];
|
||||||
|
end else begin
|
||||||
|
RBA[1:0] <= 2'b00; // Reserved in mode register
|
||||||
|
RowA[9] <= 1'b1; // "1" for single write mode
|
||||||
|
RowA[8] <= 1'b0; // Reserved
|
||||||
|
RowA[7] <= 1'b0; // "0" for not test mode
|
||||||
|
RowA[6:4] <= 3'b010; // "2" for CAS latency 2
|
||||||
|
RowA[3] <= 1'b0; // "0" for sequential burst (not used)
|
||||||
|
RowA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
|
||||||
|
end
|
||||||
|
FWEr <= ~nFWE;
|
||||||
|
CBR <= ~nCCAS;
|
||||||
|
end
|
||||||
|
|
||||||
|
/* Latch write data when CAS falls */
|
||||||
|
always @(negedge nCCAS) begin
|
||||||
|
WRD[7:0] <= Din[7:0];
|
||||||
|
end
|
||||||
|
|
||||||
|
/* State counter from RAS */
|
||||||
|
always @(posedge RCLK) begin
|
||||||
|
if (~RASr2) S <= 0;
|
||||||
|
else if (S==2'h3) S <= 2'h3;
|
||||||
|
else S <= S+1;
|
||||||
|
end
|
||||||
|
/* Init state counter */
|
||||||
|
always @(posedge RCLK) begin
|
||||||
|
// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
|
||||||
|
FS <= FS+1;
|
||||||
|
if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
/* SDRAM CKE */
|
||||||
|
always @(posedge RCLK) begin
|
||||||
|
// Only 1 LUT4 allowed for this function!
|
||||||
|
RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
|
||||||
|
end
|
||||||
|
|
||||||
|
/* SDRAM command */
|
||||||
|
always @(posedge RCLK) begin
|
||||||
|
if (Ready) begin
|
||||||
|
if (S==0) begin
|
||||||
|
if (RASr2) begin
|
||||||
|
if (CBR) begin
|
||||||
|
// AREF
|
||||||
|
nRCS <= 1'b0;
|
||||||
|
nRRAS <= 1'b0;
|
||||||
|
nRCAS <= 1'b0;
|
||||||
|
nRWE <= 1'b1;
|
||||||
|
RA10 <= 1'b1; // RA10 is don't care
|
||||||
|
end else begin
|
||||||
|
// ACT
|
||||||
|
nRCS <= 1'b0;
|
||||||
|
nRRAS <= 1'b0;
|
||||||
|
nRCAS <= 1'b1;
|
||||||
|
nRWE <= 1'b1;
|
||||||
|
RA10 <= 1'b1; // Bank RA10 consistently "1"
|
||||||
|
end
|
||||||
|
// Enable clock only for reads
|
||||||
|
RCKEEN <= ~CBR & ~FWEr;
|
||||||
|
end else if (RCKE) begin
|
||||||
|
// PCall
|
||||||
|
nRCS <= 1'b0;
|
||||||
|
nRRAS <= 1'b0;
|
||||||
|
nRCAS <= 1'b1;
|
||||||
|
nRWE <= 1'b0;
|
||||||
|
RA10 <= 1'b1; // "all"
|
||||||
|
RCKEEN <= 1'b1;
|
||||||
|
end else begin
|
||||||
|
// NOP
|
||||||
|
nRCS <= 1'b1;
|
||||||
|
nRRAS <= 1'b1;
|
||||||
|
nRCAS <= 1'b1;
|
||||||
|
nRWE <= 1'b1;
|
||||||
|
RA10 <= 1'b1; // RA10 is don't care
|
||||||
|
RCKEEN <= 1'b1;
|
||||||
|
end
|
||||||
|
nRowColSel <= 1'b0; // Select registered row addres
|
||||||
|
end else if (S==1) begin
|
||||||
|
// NOP
|
||||||
|
nRCS <= 1'b1;
|
||||||
|
nRRAS <= 1'b1;
|
||||||
|
nRCAS <= 1'b1;
|
||||||
|
nRWE <= 1'b1;
|
||||||
|
RA10 <= 1'b1; // RA10 is don't care
|
||||||
|
nRowColSel <= 1'b1; // Select asynchronous column address
|
||||||
|
RCKEEN <= ~CBR; // Disable clock if refresh cycle
|
||||||
|
end else if (S==2) begin
|
||||||
|
if (~FWEr & ~CBR) begin
|
||||||
|
// RD
|
||||||
|
nRCS <= 1'b0;
|
||||||
|
nRRAS <= 1'b1;
|
||||||
|
nRCAS <= 1'b0;
|
||||||
|
nRWE <= 1'b1;
|
||||||
|
RA10 <= 1'b1; // Auto-precharge
|
||||||
|
end else begin
|
||||||
|
// NOP
|
||||||
|
nRCS <= 1'b1;
|
||||||
|
nRRAS <= 1'b1;
|
||||||
|
nRCAS <= 1'b1;
|
||||||
|
nRWE <= 1'b1;
|
||||||
|
RA10 <= 1'b1; // RA10 is don't care
|
||||||
|
end
|
||||||
|
nRowColSel <= 1'b1; // Select asynchronous column address
|
||||||
|
RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
|
||||||
|
end else if (S==3) begin
|
||||||
|
if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
|
||||||
|
// WR
|
||||||
|
nRCS <= 1'b0;
|
||||||
|
nRRAS <= 1'b1;
|
||||||
|
nRCAS <= 1'b0;
|
||||||
|
nRWE <= 1'b0;
|
||||||
|
RA10 <= 1'b1; // Auto-precharge
|
||||||
|
end else begin
|
||||||
|
// NOP
|
||||||
|
nRCS <= 1'b1;
|
||||||
|
nRRAS <= 1'b1;
|
||||||
|
nRCAS <= 1'b1;
|
||||||
|
nRWE <= 1'b1;
|
||||||
|
RA10 <= 1'b1; // RA10 is don't care
|
||||||
|
end
|
||||||
|
nRowColSel <= ~(~FWEr | CASr3 | CBR);
|
||||||
|
RCKEEN <= ~(~FWEr | CASr2 | CBR);
|
||||||
|
end
|
||||||
|
end else if (InitReady) begin
|
||||||
|
if (S==0 & RASr2) begin
|
||||||
|
if (IS==0) begin
|
||||||
|
// NOP
|
||||||
|
nRCS <= 1'b1;
|
||||||
|
nRRAS <= 1'b1;
|
||||||
|
nRCAS <= 1'b1;
|
||||||
|
nRWE <= 1'b1;
|
||||||
|
RA10 <= 1'b1; // RA10 is don't care
|
||||||
|
end else if (IS==1) begin
|
||||||
|
// PC all
|
||||||
|
nRCS <= 1'b0;
|
||||||
|
nRRAS <= 1'b0;
|
||||||
|
nRCAS <= 1'b1;
|
||||||
|
nRWE <= 1'b0;
|
||||||
|
RA10 <= 1'b1; // "all"
|
||||||
|
end else if (IS==9) begin
|
||||||
|
// Load mode register
|
||||||
|
nRCS <= 1'b0;
|
||||||
|
nRRAS <= 1'b0;
|
||||||
|
nRCAS <= 1'b0;
|
||||||
|
nRWE <= 1'b0;
|
||||||
|
RA10 <= 1'b0; // Reserved in mode register
|
||||||
|
end else begin
|
||||||
|
// AREF
|
||||||
|
nRCS <= 1'b0;
|
||||||
|
nRRAS <= 1'b0;
|
||||||
|
nRCAS <= 1'b0;
|
||||||
|
nRWE <= 1'b1;
|
||||||
|
RA10 <= 1'b1; // RA10 is don't care
|
||||||
|
end
|
||||||
|
IS <= IS+1;
|
||||||
|
end else begin
|
||||||
|
// NOP
|
||||||
|
nRCS <= 1'b1;
|
||||||
|
nRRAS <= 1'b1;
|
||||||
|
nRCAS <= 1'b1;
|
||||||
|
nRWE <= 1'b1;
|
||||||
|
RA10 <= 1'b1; // RA10 is don't care
|
||||||
|
end
|
||||||
|
if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
|
||||||
|
nRowColSel <= 1'b0; // Select registered row address
|
||||||
|
RCKEEN <= 1'b1;
|
||||||
|
end else begin
|
||||||
|
// NOP
|
||||||
|
nRCS <= 1'b1;
|
||||||
|
nRRAS <= 1'b1;
|
||||||
|
nRCAS <= 1'b1;
|
||||||
|
nRWE <= 1'b1;
|
||||||
|
RA10 <= 1'b1; // RA10 is don't care
|
||||||
|
nRowColSel <= 1'b0; // Select registered row address
|
||||||
|
RCKEEN <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
/* Submit command when PHI2 falls */
|
||||||
|
always @(negedge PHI2) begin
|
||||||
|
// Magic number check
|
||||||
|
if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
|
||||||
|
if (ADSubmitted) begin
|
||||||
|
CmdEnable <= 1'b1;
|
||||||
|
UFMOscEN <= 1'b1;
|
||||||
|
end
|
||||||
|
C1Submitted <= 1'b1;
|
||||||
|
ADSubmitted <= 1'b0;
|
||||||
|
end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
|
||||||
|
if (C1Submitted) begin
|
||||||
|
CmdEnable <= 1'b1;
|
||||||
|
UFMOscEN <= 1'b1;
|
||||||
|
end
|
||||||
|
ADSubmitted <= 1'b1;
|
||||||
|
C1Submitted <= 1'b0;
|
||||||
|
end else if (C1WR | ADWR) begin // wrong magic number submitted
|
||||||
|
CmdEnable <= 1'b0;
|
||||||
|
C1Submitted <= 1'b0;
|
||||||
|
ADSubmitted <= 1'b0;
|
||||||
|
end else if (CMDWR) CmdEnable <= 1'b0;
|
||||||
|
|
||||||
|
// Submit command
|
||||||
|
if (CMDWR & CmdEnable) begin
|
||||||
|
if (Din[7:4]==4'h0) begin
|
||||||
|
XOR8MEG <= Din[0];
|
||||||
|
end else if (Din[7:4]==4'h1) begin
|
||||||
|
Cmdn8MEGEN <= ~Din[0];
|
||||||
|
CmdSubmitted <= 1'b1;
|
||||||
|
end else if (Din[7:4]==4'h2) begin
|
||||||
|
Cmdn8MEGEN <= n8MEGEN;
|
||||||
|
CmdUFMErase <= Din[3];
|
||||||
|
CmdUFMPrgm <= Din[2];
|
||||||
|
CmdDRCLK <= Din[1];
|
||||||
|
CmdDRDIn <= Din[0];
|
||||||
|
CmdSubmitted <= 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
/* UFM Control */
|
||||||
|
always @(posedge RCLK) begin
|
||||||
|
if (~Ready) begin
|
||||||
|
if (~UFMInitDone & FS[17:16]==2'b00) begin
|
||||||
|
// Shift 0 into address register
|
||||||
|
ARCLK <= FS[3]; // Clock address register
|
||||||
|
ARShift <= 1'b1; // Shift 0 into address register
|
||||||
|
DRCLK <= 1'b0; // Don't clock data register
|
||||||
|
DRDIn <= 1'b0; // DRDIn is don't care
|
||||||
|
DRShift <= 1'b0; // DRShift is don't care
|
||||||
|
end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h0) begin
|
||||||
|
// Parallel transfer UFM data to shift register
|
||||||
|
ARCLK <= 1'b0; // Don't clock address register
|
||||||
|
ARShift <= 1'b0; // ARShift is don't care
|
||||||
|
DRCLK <= FS[3]; // Clock data register
|
||||||
|
DRDIn <= 1'b0; // DRDIn is don't care
|
||||||
|
DRShift <= 1'b0; // Parallel transfer to data register
|
||||||
|
end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h4) begin
|
||||||
|
// Shift UFM
|
||||||
|
ARCLK <= 1'b0; // Don't clock address register
|
||||||
|
ARShift <= 1'b0; // ARShift is don't care
|
||||||
|
DRCLK <= FS[3]; // Clock data register
|
||||||
|
DRDIn <= 1'b0; // DRDIn is don't care
|
||||||
|
DRShift <= 1'b1; // Shift data register
|
||||||
|
// Capture bit 15 of this UFM word in UFMD register
|
||||||
|
if (FS[3:0]==4'h7) UFMD <= DRDOut;
|
||||||
|
end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h5) begin
|
||||||
|
// Check saved capacity entry
|
||||||
|
if (UFMD) UFMInitDone <= 1'b1; // If erased, quit iterating
|
||||||
|
else begin // If valid setting here
|
||||||
|
n8MEGEN <= ~DRDOut; // Set capacity setting
|
||||||
|
// If last byte in sector, mark need to erase
|
||||||
|
if (FS[15:8]==8'hFF) begin
|
||||||
|
UFMReqErase <= 1'b1; // Mark need to wrap around
|
||||||
|
UFMInitDone <= 1'b1; // Quit iterating
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h6) begin
|
||||||
|
// Increment UFM address
|
||||||
|
ARCLK <= FS[3]; // Clock address register
|
||||||
|
ARShift <= 1'b0; // Increment UFM address
|
||||||
|
DRCLK <= 1'b0; // Don't clock data register
|
||||||
|
DRDIn <= 1'b0; // DRDIn is don't care
|
||||||
|
DRShift <= 1'b0; // DRShift is don't care
|
||||||
|
end else if (FS[17:16]==2'b10 & UFMReqErase) begin
|
||||||
|
// Shift 0 into address register
|
||||||
|
ARCLK <= FS[3]; // Clock address register
|
||||||
|
ARShift <= 1'b1; // Shift 0 into address register
|
||||||
|
DRCLK <= 1'b0; // Don't clock data register
|
||||||
|
DRDIn <= 1'b0; // DRDIn is don't care
|
||||||
|
DRShift <= 1'b0; // DRShift is don't care
|
||||||
|
end else begin
|
||||||
|
// Don't do anything with UFM
|
||||||
|
ARCLK <= 1'b0; // Don't clock address register
|
||||||
|
ARShift <= 1'b0; // ARShift is don't care
|
||||||
|
DRCLK <= 1'b0; // Don't clock data register
|
||||||
|
DRDIn <= 1'b0; // DRDIn is don't care
|
||||||
|
DRShift <= 1'b0; // DRShift is don't care
|
||||||
|
end
|
||||||
|
|
||||||
|
// Don't erase or program UFM during initialization
|
||||||
|
UFMErase <= 1'b0;
|
||||||
|
UFMProgram <= 1'b0;
|
||||||
|
end else begin
|
||||||
|
// Can only shift UFM data register now
|
||||||
|
ARCLK <= 1'b0;
|
||||||
|
ARShift <= 1'b0;
|
||||||
|
DRShift <= 1'b1;
|
||||||
|
|
||||||
|
// Set user command signals after PHI2 falls
|
||||||
|
if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
|
||||||
|
n8MEGEN <= Cmdn8MEGEN;
|
||||||
|
DRCLK <= CmdDRCLK;
|
||||||
|
DRDIn <= CmdDRDIn;
|
||||||
|
end
|
||||||
|
|
||||||
|
// UFM programming sequence
|
||||||
|
if (CmdUFMPrgm | CmdUFMErase) begin
|
||||||
|
if (~UFMBusyReg & ~RTPBusyReg) begin
|
||||||
|
if (UFMReqErase | CmdUFMErase) UFMErase <= 1'b1;
|
||||||
|
else if (CmdUFMPrgm) UFMProgram <= 1'b1;
|
||||||
|
end else if (UFMBusyReg) UFMReqErase <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
|
@ -0,0 +1,213 @@
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Copyright (C) 1991-2013 Altera Corporation
|
||||||
|
# Your use of Altera Corporation's design tools, logic functions
|
||||||
|
# and other software and tools, and its AMPP partner logic
|
||||||
|
# functions, and any output files from any of the foregoing
|
||||||
|
# (including device programming or simulation files), and any
|
||||||
|
# associated documentation or information are expressly subject
|
||||||
|
# to the terms and conditions of the Altera Program License
|
||||||
|
# Subscription Agreement, Altera MegaCore Function License
|
||||||
|
# Agreement, or other applicable license agreement, including,
|
||||||
|
# without limitation, that your use is for the sole purpose of
|
||||||
|
# programming logic devices manufactured by Altera and sold by
|
||||||
|
# Altera or its authorized distributors. Please refer to the
|
||||||
|
# applicable agreement for further details.
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Quartus II 32-bit
|
||||||
|
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
|
||||||
|
# Date created = 21:16:34 March 08, 2020
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Notes:
|
||||||
|
#
|
||||||
|
# 1) The default values for assignments are stored in the file:
|
||||||
|
# RAM4GS_assignment_defaults.qdf
|
||||||
|
# If this file doesn't exist, see file:
|
||||||
|
# assignment_defaults.qdf
|
||||||
|
#
|
||||||
|
# 2) Altera recommends that you do not modify this file. This
|
||||||
|
# file is updated automatically by the Quartus II software
|
||||||
|
# and any changes you make may be lost or overwritten.
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
|
||||||
|
|
||||||
|
set_global_assignment -name FAMILY "MAX II"
|
||||||
|
set_global_assignment -name DEVICE EPM240T100C5
|
||||||
|
set_global_assignment -name TOP_LEVEL_ENTITY RAM4GS
|
||||||
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||||
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:34 MARCH 08, 2020"
|
||||||
|
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||||
|
set_global_assignment -name SDC_FILE constraints.sdc
|
||||||
|
set_global_assignment -name VERILOG_FILE RAM4GS.v
|
||||||
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||||
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||||
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||||
|
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||||
|
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
|
||||||
|
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
|
||||||
|
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
|
||||||
|
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED
|
||||||
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
|
||||||
|
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
|
||||||
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||||
|
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||||
|
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
|
||||||
|
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF
|
||||||
|
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
|
||||||
|
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
|
||||||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
|
||||||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
|
||||||
|
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
|
||||||
|
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
|
||||||
|
set_global_assignment -name SMART_RECOMPILE OFF
|
||||||
|
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10
|
||||||
|
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 10
|
||||||
|
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
|
||||||
|
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON
|
||||||
|
set_global_assignment -name SAFE_STATE_MACHINE ON
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
set_location_assignment PIN_12 -to RCLK
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK
|
||||||
|
|
||||||
|
set_location_assignment PIN_52 -to PHI2
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI2
|
||||||
|
|
||||||
|
set_location_assignment PIN_67 -to nCRAS
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCRAS
|
||||||
|
|
||||||
|
set_location_assignment PIN_53 -to nCCAS
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCCAS
|
||||||
|
|
||||||
|
set_location_assignment PIN_48 -to nFWE
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nFWE
|
||||||
|
|
||||||
|
set_location_assignment PIN_49 -to MAin[0]
|
||||||
|
set_location_assignment PIN_51 -to MAin[1]
|
||||||
|
set_location_assignment PIN_50 -to MAin[2]
|
||||||
|
set_location_assignment PIN_71 -to MAin[3]
|
||||||
|
set_location_assignment PIN_70 -to MAin[4]
|
||||||
|
set_location_assignment PIN_69 -to MAin[5]
|
||||||
|
set_location_assignment PIN_72 -to MAin[6]
|
||||||
|
set_location_assignment PIN_68 -to MAin[7]
|
||||||
|
set_location_assignment PIN_73 -to MAin[8]
|
||||||
|
set_location_assignment PIN_74 -to MAin[9]
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MAin
|
||||||
|
|
||||||
|
set_location_assignment PIN_54 -to CROW[0]
|
||||||
|
set_location_assignment PIN_55 -to CROW[1]
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CROW
|
||||||
|
|
||||||
|
set_location_assignment PIN_35 -to Din[2]
|
||||||
|
set_location_assignment PIN_36 -to Din[1]
|
||||||
|
set_location_assignment PIN_37 -to Din[3]
|
||||||
|
set_location_assignment PIN_38 -to Din[5]
|
||||||
|
set_location_assignment PIN_39 -to Din[4]
|
||||||
|
set_location_assignment PIN_40 -to Din[7]
|
||||||
|
set_location_assignment PIN_41 -to Din[6]
|
||||||
|
set_location_assignment PIN_42 -to Din[0]
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din
|
||||||
|
|
||||||
|
set_location_assignment PIN_33 -to Dout[0]
|
||||||
|
set_location_assignment PIN_57 -to Dout[1]
|
||||||
|
set_location_assignment PIN_56 -to Dout[2]
|
||||||
|
set_location_assignment PIN_47 -to Dout[3]
|
||||||
|
set_location_assignment PIN_44 -to Dout[4]
|
||||||
|
set_location_assignment PIN_28 -to Dout[5]
|
||||||
|
set_location_assignment PIN_34 -to Dout[6]
|
||||||
|
set_location_assignment PIN_43 -to Dout[7]
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
|
||||||
|
|
||||||
|
set_location_assignment PIN_8 -to RCKE
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCKE
|
||||||
|
|
||||||
|
set_location_assignment PIN_3 -to nRCS
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCS
|
||||||
|
|
||||||
|
set_location_assignment PIN_100 -to nRWE
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
|
||||||
|
|
||||||
|
set_location_assignment PIN_6 -to nRRAS
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRRAS
|
||||||
|
|
||||||
|
set_location_assignment PIN_4 -to nRCAS
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCAS
|
||||||
|
|
||||||
|
set_location_assignment PIN_5 -to RBA[0]
|
||||||
|
set_location_assignment PIN_14 -to RBA[1]
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RBA
|
||||||
|
|
||||||
|
set_location_assignment PIN_18 -to RA[0]
|
||||||
|
set_location_assignment PIN_20 -to RA[1]
|
||||||
|
set_location_assignment PIN_30 -to RA[2]
|
||||||
|
set_location_assignment PIN_27 -to RA[3]
|
||||||
|
set_location_assignment PIN_26 -to RA[4]
|
||||||
|
set_location_assignment PIN_29 -to RA[5]
|
||||||
|
set_location_assignment PIN_21 -to RA[6]
|
||||||
|
set_location_assignment PIN_19 -to RA[7]
|
||||||
|
set_location_assignment PIN_17 -to RA[8]
|
||||||
|
set_location_assignment PIN_15 -to RA[9]
|
||||||
|
set_location_assignment PIN_16 -to RA[10]
|
||||||
|
set_location_assignment PIN_7 -to RA[11]
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
|
||||||
|
|
||||||
|
set_location_assignment PIN_2 -to RDQMH
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQMH
|
||||||
|
|
||||||
|
set_location_assignment PIN_98 -to RDQML
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQML
|
||||||
|
|
||||||
|
set_location_assignment PIN_96 -to RD[0]
|
||||||
|
set_location_assignment PIN_90 -to RD[1]
|
||||||
|
set_location_assignment PIN_89 -to RD[2]
|
||||||
|
set_location_assignment PIN_99 -to RD[3]
|
||||||
|
set_location_assignment PIN_92 -to RD[4]
|
||||||
|
set_location_assignment PIN_91 -to RD[5]
|
||||||
|
set_location_assignment PIN_95 -to RD[6]
|
||||||
|
set_location_assignment PIN_97 -to RD[7]
|
||||||
|
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
|
||||||
|
|
||||||
|
set_global_assignment -name MIF_FILE RAM4GS.mif
|
||||||
|
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS
|
||||||
|
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS
|
||||||
|
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE
|
||||||
|
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to MAin
|
||||||
|
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to CROW
|
||||||
|
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to Din
|
||||||
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to Dout
|
||||||
|
set_instance_assignment -name SLOW_SLEW_RATE OFF -to Dout
|
||||||
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE
|
||||||
|
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RCKE
|
||||||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RCKE
|
||||||
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS
|
||||||
|
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCS
|
||||||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCS
|
||||||
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
|
||||||
|
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRWE
|
||||||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
|
||||||
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRRAS
|
||||||
|
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRRAS
|
||||||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRRAS
|
||||||
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCAS
|
||||||
|
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCAS
|
||||||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCAS
|
||||||
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RBA
|
||||||
|
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RBA
|
||||||
|
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RBA
|
||||||
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RA
|
||||||
|
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RA
|
||||||
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQMH
|
||||||
|
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQMH
|
||||||
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQML
|
||||||
|
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML
|
||||||
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD
|
||||||
|
set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
|
||||||
|
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
|
||||||
|
set_global_assignment -name QIP_FILE UFM.qip
|
Loading…
Reference in New Issue