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3 Commits
926fac8bbe
...
c103137bfc
Author | SHA1 | Date |
---|---|---|
Zane Kaminski | c103137bfc | |
Zane Kaminski | 84f33af9c0 | |
Zane Kaminski | 97fe10f40a |
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@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EPM240T100C5
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set_global_assignment -name TOP_LEVEL_ENTITY RAM2GS
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:27:39 AUGUST 12, 2023"
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set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
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set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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Binary file not shown.
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@ -1,6 +1,6 @@
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Assembler report for RAM2GS
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Thu Sep 21 05:38:25 2023
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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Sat Sep 30 04:44:05 2023
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
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---------------------
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@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
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+---------------------------------------------------------------+
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; Assembler Summary ;
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+-----------------------+---------------------------------------+
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; Assembler Status ; Successful - Thu Sep 21 05:38:25 2023 ;
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; Assembler Status ; Successful - Sat Sep 30 04:44:05 2023 ;
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; Revision Name ; RAM2GS ;
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; Top-level Entity Name ; RAM2GS ;
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; Family ; MAX II ;
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@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula.
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+----------------+-----------------------------------------------------------+
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; Option ; Setting ;
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+----------------+-----------------------------------------------------------+
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; JTAG usercode ; 0x00172E3B ;
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; Checksum ; 0x0017312B ;
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; JTAG usercode ; 0x00171B9B ;
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; Checksum ; 0x00171E13 ;
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+----------------+-----------------------------------------------------------+
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@ -77,14 +77,14 @@ https://fpgasoftware.intel.com/eula.
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+--------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime Assembler
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Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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Info: Processing started: Thu Sep 21 05:38:24 2023
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Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
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Info: Processing started: Sat Sep 30 04:44:04 2023
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Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
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Info (115031): Writing out detailed assembly data for power analysis
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Info (115030): Assembler is generating device programming files
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Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
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Info: Peak virtual memory: 13095 megabytes
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Info: Processing ended: Thu Sep 21 05:38:25 2023
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Info: Processing ended: Sat Sep 30 04:44:05 2023
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
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@ -1 +1 @@
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Thu Sep 21 05:38:31 2023
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Sat Sep 30 04:44:09 2023
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@ -1,6 +1,6 @@
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Fitter report for RAM2GS
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Thu Sep 21 05:38:22 2023
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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Sat Sep 30 04:44:02 2023
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
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---------------------
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@ -56,21 +56,21 @@ https://fpgasoftware.intel.com/eula.
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+---------------------------------------------------------------------+
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; Fitter Summary ;
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+-----------------------+---------------------------------------------+
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; Fitter Status ; Successful - Thu Sep 21 05:38:22 2023 ;
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; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
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; Revision Name ; RAM2GS ;
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; Top-level Entity Name ; RAM2GS ;
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; Family ; MAX II ;
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; Device ; EPM240T100C5 ;
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; Timing Models ; Final ;
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; Total logic elements ; 175 / 240 ( 73 % ) ;
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; Total pins ; 63 / 80 ( 79 % ) ;
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; Total virtual pins ; 0 ;
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; UFM blocks ; 1 / 1 ( 100 % ) ;
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+-----------------------+---------------------------------------------+
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+-------------------------------------------------------------------------------------+
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; Fitter Summary ;
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+-----------------------+-------------------------------------------------------------+
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; Fitter Status ; Successful - Sat Sep 30 04:44:02 2023 ;
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; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
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; Revision Name ; RAM2GS ;
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; Top-level Entity Name ; RAM2GS ;
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; Family ; MAX II ;
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; Device ; EPM240T100C5 ;
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; Timing Models ; Final ;
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; Total logic elements ; 184 / 240 ( 77 % ) ;
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; Total pins ; 63 / 80 ( 79 % ) ;
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; Total virtual pins ; 0 ;
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; UFM blocks ; 1 / 1 ( 100 % ) ;
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+-----------------------+-------------------------------------------------------------+
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+--------------------------------------------------------------------------------------------------------------------------------------+
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@ -131,13 +131,13 @@ https://fpgasoftware.intel.com/eula.
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; Number detected on machine ; 4 ;
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; Maximum allowed ; 4 ;
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; ; ;
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; Average used ; 1.03 ;
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; Average used ; 1.04 ;
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; Maximum used ; 4 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processor 2 ; 1.2% ;
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; Processors 3-4 ; 1.1% ;
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; Processor 2 ; 1.5% ;
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; Processors 3-4 ; 1.2% ;
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+----------------------------+-------------+
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@ -152,27 +152,27 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
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+---------------------------------------------+-----------------------+
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; Resource ; Usage ;
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+---------------------------------------------+-----------------------+
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; Total logic elements ; 175 / 240 ( 73 % ) ;
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; -- Combinational with no register ; 77 ;
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; -- Register only ; 21 ;
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; -- Combinational with a register ; 77 ;
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; Total logic elements ; 184 / 240 ( 77 % ) ;
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; -- Combinational with no register ; 80 ;
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; -- Register only ; 22 ;
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; -- Combinational with a register ; 82 ;
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; ; ;
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; Logic element usage by number of LUT inputs ; ;
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; -- 4 input functions ; 57 ;
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; -- 4 input functions ; 64 ;
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; -- 3 input functions ; 46 ;
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; -- 2 input functions ; 42 ;
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; -- 2 input functions ; 43 ;
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; -- 1 input functions ; 8 ;
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; -- 0 input functions ; 1 ;
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; ; ;
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; Logic elements by mode ; ;
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; -- normal mode ; 159 ;
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; -- normal mode ; 168 ;
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; -- arithmetic mode ; 16 ;
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; -- qfbk mode ; 8 ;
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; -- qfbk mode ; 11 ;
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; -- register cascade mode ; 0 ;
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; -- synchronous clear/load mode ; 27 ;
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; -- synchronous clear/load mode ; 35 ;
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; -- asynchronous clear/load mode ; 0 ;
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; ; ;
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; Total registers ; 98 / 240 ( 41 % ) ;
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; Total registers ; 104 / 240 ( 43 % ) ;
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; Total LABs ; 21 / 24 ( 88 % ) ;
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; Logic elements in carry chains ; 17 ;
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; Virtual pins ; 0 ;
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@ -187,12 +187,12 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
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; Global signals ; 4 ;
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; -- Global clocks ; 4 / 4 ( 100 % ) ;
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; JTAGs ; 0 / 1 ( 0 % ) ;
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; Average interconnect usage (total/H/V) ; 19.4% / 20.4% / 18.3% ;
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; Peak interconnect usage (total/H/V) ; 19.4% / 20.4% / 18.3% ;
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; Maximum fan-out ; 55 ;
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; Highest non-global fan-out ; 41 ;
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; Total fan-out ; 661 ;
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; Average fan-out ; 2.77 ;
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; Average interconnect usage (total/H/V) ; 23.0% / 24.7% / 21.2% ;
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; Peak interconnect usage (total/H/V) ; 23.0% / 24.7% / 21.2% ;
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; Maximum fan-out ; 61 ;
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; Highest non-global fan-out ; 43 ;
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; Total fan-out ; 699 ;
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; Average fan-out ; 2.82 ;
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+---------------------------------------------+-----------------------+
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@ -203,12 +203,12 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
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+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
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; CROW[0] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; CROW[1] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[6] ; 41 ; 1 ; 5 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[7] ; 40 ; 1 ; 5 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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@ -222,7 +222,7 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
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; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 22 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 55 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 61 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; nCCAS ; 53 ; 2 ; 8 ; 1 ; 3 ; 11 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; nCRAS ; 67 ; 2 ; 8 ; 3 ; 2 ; 16 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; nFWE ; 48 ; 1 ; 6 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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@ -243,7 +243,7 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
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; Dout[6] ; 34 ; 1 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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; Dout[7] ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
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; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
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; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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@ -251,8 +251,8 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
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; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
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; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
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; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
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; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
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@ -263,7 +263,7 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
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; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
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; nRCS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
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; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
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; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
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@ -273,7 +273,7 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
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; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
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+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
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; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
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; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; RD~16 ; - ;
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; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
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; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
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; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
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; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
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@ -423,7 +423,7 @@ Note: User assignments will override these defaults. The user specified values a
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+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
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; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
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+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
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; |RAM2GS ; 175 (175) ; 98 ; 1 ; 63 ; 0 ; 77 (77) ; 21 (21) ; 77 (77) ; 17 (17) ; 8 (8) ; |RAM2GS ; RAM2GS ; work ;
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; |RAM2GS ; 184 (184) ; 104 ; 1 ; 63 ; 0 ; 80 (80) ; 22 (22) ; 82 (82) ; 17 (17) ; 11 (11) ; |RAM2GS ; RAM2GS ; work ;
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; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ;
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; |UFM_altufm_none_unv:UFM_altufm_none_unv_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component ; UFM_altufm_none_unv ; work ;
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+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
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@ -491,32 +491,33 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
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; PHI2 ; Input ; (0) ;
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; Din[6] ; Input ; (1) ;
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; nFWE ; Input ; (1) ;
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; Din[0] ; Input ; (1) ;
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||||
; Din[7] ; Input ; (1) ;
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||||
; Din[1] ; Input ; (1) ;
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||||
; Din[4] ; Input ; (1) ;
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; Din[2] ; Input ; (1) ;
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; Din[3] ; Input ; (1) ;
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||||
; Din[5] ; Input ; (1) ;
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||||
; Din[0] ; Input ; (1) ;
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||||
; Din[2] ; Input ; (1) ;
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+---------+----------+---------------+
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||||
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||||
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+-----------------------------------------------------------------------------------------------------------------+
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; Control Signals ;
|
||||
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
; CmdDRDIn~1 ; LC_X4_Y1_N0 ; 4 ; Clock enable ; no ; -- ; -- ;
|
||||
; CmdLEDEN~1 ; LC_X4_Y1_N8 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; DRDIn~1 ; LC_X3_Y1_N4 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK3 ;
|
||||
; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; RD~16 ; LC_X3_Y4_N0 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; Ready ; LC_X3_Y2_N8 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ;
|
||||
; always8~6 ; LC_X4_Y2_N7 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK1 ;
|
||||
; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK2 ;
|
||||
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
+--------------------------------------------------------------------------------------------------------------------+
|
||||
; Control Signals ;
|
||||
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
; CmdDRDIn~1 ; LC_X5_Y2_N5 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; CmdLEDEN~1 ; LC_X4_Y2_N2 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; CmdUFMErase~0 ; LC_X7_Y3_N4 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; DRDIn~1 ; LC_X3_Y1_N4 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK3 ;
|
||||
; RCLK ; PIN_12 ; 61 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; RD~16 ; LC_X4_Y4_N7 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; Ready ; LC_X3_Y2_N8 ; 42 ; Sync. clear, Sync. load ; no ; -- ; -- ;
|
||||
; always11~7 ; LC_X6_Y2_N2 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK1 ;
|
||||
; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK2 ;
|
||||
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
|
@ -525,7 +526,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
||||
+-------+----------+---------+----------------------+------------------+
|
||||
; PHI2 ; PIN_52 ; 22 ; Global Clock ; GCLK3 ;
|
||||
; RCLK ; PIN_12 ; 55 ; Global Clock ; GCLK0 ;
|
||||
; RCLK ; PIN_12 ; 61 ; Global Clock ; GCLK0 ;
|
||||
; nCCAS ; PIN_53 ; 11 ; Global Clock ; GCLK1 ;
|
||||
; nCRAS ; PIN_67 ; 16 ; Global Clock ; GCLK2 ;
|
||||
+-------+----------+---------+----------------------+------------------+
|
||||
|
@ -536,113 +537,111 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+-----------------------+--------------------+
|
||||
; Routing Resource Type ; Usage ;
|
||||
+-----------------------+--------------------+
|
||||
; C4s ; 120 / 784 ( 15 % ) ;
|
||||
; Direct links ; 34 / 888 ( 4 % ) ;
|
||||
; C4s ; 134 / 784 ( 17 % ) ;
|
||||
; Direct links ; 53 / 888 ( 6 % ) ;
|
||||
; Global clocks ; 4 / 4 ( 100 % ) ;
|
||||
; LAB clocks ; 12 / 32 ( 38 % ) ;
|
||||
; LUT chains ; 11 / 216 ( 5 % ) ;
|
||||
; Local interconnects ; 232 / 888 ( 26 % ) ;
|
||||
; R4s ; 117 / 704 ( 17 % ) ;
|
||||
; LAB clocks ; 17 / 32 ( 53 % ) ;
|
||||
; LUT chains ; 13 / 216 ( 6 % ) ;
|
||||
; Local interconnects ; 259 / 888 ( 29 % ) ;
|
||||
; R4s ; 137 / 704 ( 19 % ) ;
|
||||
+-----------------------+--------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Logic Elements ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; Number of Logic Elements (Average = 8.33) ; Number of LABs (Total = 21) ;
|
||||
; Number of Logic Elements (Average = 8.76) ; Number of LABs (Total = 21) ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 3 ;
|
||||
; 2 ; 1 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 2 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 15 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 2 ;
|
||||
; 7 ; 1 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 3 ;
|
||||
; 10 ; 12 ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; LAB-wide Signals ;
|
||||
+------------------------------------+------------------------------+
|
||||
; LAB-wide Signals (Average = 1.24) ; Number of LABs (Total = 21) ;
|
||||
; LAB-wide Signals (Average = 1.29) ; Number of LABs (Total = 21) ;
|
||||
+------------------------------------+------------------------------+
|
||||
; 1 Clock ; 12 ;
|
||||
; 1 Clock enable ; 3 ;
|
||||
; 1 Sync. clear ; 3 ;
|
||||
; 2 Clocks ; 8 ;
|
||||
; 2 Clocks ; 9 ;
|
||||
+------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced (Average = 8.57) ; Number of LABs (Total = 21) ;
|
||||
; Number of Signals Sourced (Average = 9.10) ; Number of LABs (Total = 21) ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 3 ;
|
||||
; 2 ; 1 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 2 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 12 ;
|
||||
; 11 ; 1 ;
|
||||
; 12 ; 2 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 2 ;
|
||||
; 7 ; 1 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 3 ;
|
||||
; 10 ; 9 ;
|
||||
; 11 ; 3 ;
|
||||
; 12 ; 1 ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced Out ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced Out (Average = 5.62) ; Number of LABs (Total = 21) ;
|
||||
; Number of Signals Sourced Out (Average = 5.95) ; Number of LABs (Total = 21) ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 1 ;
|
||||
; 2 ; 2 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 1 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 2 ;
|
||||
; 4 ; 4 ;
|
||||
; 5 ; 2 ;
|
||||
; 6 ; 5 ;
|
||||
; 7 ; 5 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 0 ;
|
||||
; 11 ; 1 ;
|
||||
; 6 ; 4 ;
|
||||
; 7 ; 4 ;
|
||||
; 8 ; 3 ;
|
||||
; 9 ; 2 ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; Number of Distinct Inputs (Average = 9.43) ; Number of LABs (Total = 21) ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 2 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 2 ;
|
||||
; 11 ; 2 ;
|
||||
; 12 ; 3 ;
|
||||
; 13 ; 2 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 0 ;
|
||||
; 16 ; 0 ;
|
||||
; 17 ; 1 ;
|
||||
; 18 ; 0 ;
|
||||
; 19 ; 1 ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
+-----------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; Number of Distinct Inputs (Average = 10.33) ; Number of LABs (Total = 21) ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 2 ;
|
||||
; 7 ; 2 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 1 ;
|
||||
; 10 ; 1 ;
|
||||
; 11 ; 3 ;
|
||||
; 12 ; 2 ;
|
||||
; 13 ; 1 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 4 ;
|
||||
; 16 ; 1 ;
|
||||
; 17 ; 0 ;
|
||||
; 18 ; 0 ;
|
||||
; 19 ; 1 ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------+
|
||||
|
@ -665,7 +664,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
|
||||
+-----------------+----------------------+-------------------+
|
||||
; I/O ; RCLK ; 4.0 ;
|
||||
; I/O ; nCRAS ; 3.0 ;
|
||||
; I/O ; nCRAS ; 2.5 ;
|
||||
+-----------------+----------------------+-------------------+
|
||||
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
|
||||
This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
|
||||
|
@ -676,7 +675,7 @@ This will disable optimization of problematic paths and expose them for further
|
|||
+-----------------+----------------------+-------------------+
|
||||
; Source Register ; Destination Register ; Delay Added in ns ;
|
||||
+-----------------+----------------------+-------------------+
|
||||
; nCCAS ; CBR ; 3.041 ;
|
||||
; nCCAS ; CBR ; 2.469 ;
|
||||
; PHI2 ; PHI2r ; 1.523 ;
|
||||
; nCRAS ; RASr ; 1.214 ;
|
||||
+-----------------+----------------------+-------------------+
|
||||
|
@ -737,17 +736,17 @@ Info (170191): Fitter placement operations beginning
|
|||
Info (170137): Fitter placement was successful
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
|
||||
Info (170193): Fitter routing operations beginning
|
||||
Info (170195): Router estimated average interconnect usage is 17% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170195): Router estimated average interconnect usage is 20% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
||||
Info (170201): Optimizations that may affect the design's routability were skipped
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 1.10 seconds.
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.54 seconds.
|
||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 13770 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:38:23 2023
|
||||
Info: Peak virtual memory: 13771 megabytes
|
||||
Info: Processing ended: Sat Sep 30 04:44:02 2023
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Total CPU time (on all processors): 00:00:04
|
||||
|
||||
|
|
|
@ -1,11 +1,11 @@
|
|||
Fitter Status : Successful - Thu Sep 21 05:38:22 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Fitter Status : Successful - Sat Sep 30 04:44:02 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Revision Name : RAM2GS
|
||||
Top-level Entity Name : RAM2GS
|
||||
Family : MAX II
|
||||
Device : EPM240T100C5
|
||||
Timing Models : Final
|
||||
Total logic elements : 175 / 240 ( 73 % )
|
||||
Total logic elements : 184 / 240 ( 77 % )
|
||||
Total pins : 63 / 80 ( 79 % )
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
Flow report for RAM2GS
|
||||
Thu Sep 21 05:38:29 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Sat Sep 30 04:44:08 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Flow Status ; Successful - Thu Sep 21 05:38:25 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 175 / 240 ( 73 % ) ;
|
||||
; Total pins ; 63 / 80 ( 79 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
+-------------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
; Flow Status ; Successful - Sat Sep 30 04:44:05 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 184 / 240 ( 77 % ) ;
|
||||
; Total pins ; 63 / 80 ( 79 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
|
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 09/21/2023 05:37:46 ;
|
||||
; Start date & time ; 09/30/2023 04:43:31 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
+-------------------+---------------------+
|
||||
|
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.169528906604732 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.169606341108100 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
|
||||
|
@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula.
|
|||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:31 ; 1.0 ; 13149 MB ; 00:00:47 ;
|
||||
; Fitter ; 00:00:04 ; 1.0 ; 13770 MB ; 00:00:04 ;
|
||||
; Analysis & Synthesis ; 00:00:26 ; 1.0 ; 13133 MB ; 00:00:44 ;
|
||||
; Fitter ; 00:00:05 ; 1.0 ; 13771 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13095 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13089 MB ; 00:00:02 ;
|
||||
; Total ; 00:00:38 ; -- ; -- ; 00:00:54 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13092 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:34 ; -- ; -- ; 00:00:50 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
Analysis & Synthesis report for RAM2GS
|
||||
Thu Sep 21 05:38:17 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Sat Sep 30 04:43:56 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Thu Sep 21 05:38:17 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX II ;
|
||||
; Total logic elements ; 184 ;
|
||||
; Total pins ; 63 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
+-------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+-------------------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Sat Sep 30 04:43:56 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX II ;
|
||||
; Total logic elements ; 196 ;
|
||||
; Total pins ; 63 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------------+-------------------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
|
@ -162,34 +162,34 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------------+-------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-------+
|
||||
; Total logic elements ; 184 ;
|
||||
; -- Combinational with no register ; 86 ;
|
||||
; -- Register only ; 30 ;
|
||||
; -- Combinational with a register ; 68 ;
|
||||
; Total logic elements ; 196 ;
|
||||
; -- Combinational with no register ; 92 ;
|
||||
; -- Register only ; 34 ;
|
||||
; -- Combinational with a register ; 70 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 57 ;
|
||||
; -- 4 input functions ; 64 ;
|
||||
; -- 3 input functions ; 46 ;
|
||||
; -- 2 input functions ; 42 ;
|
||||
; -- 2 input functions ; 43 ;
|
||||
; -- 1 input functions ; 8 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 168 ;
|
||||
; -- normal mode ; 180 ;
|
||||
; -- arithmetic mode ; 16 ;
|
||||
; -- qfbk mode ; 0 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 10 ;
|
||||
; -- synchronous clear/load mode ; 11 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 98 ;
|
||||
; Total registers ; 104 ;
|
||||
; Total logic cells in carry chains ; 17 ;
|
||||
; I/O pins ; 63 ;
|
||||
; UFM blocks ; 1 ;
|
||||
; Maximum fan-out node ; RCLK ;
|
||||
; Maximum fan-out ; 55 ;
|
||||
; Total fan-out ; 662 ;
|
||||
; Average fan-out ; 2.67 ;
|
||||
; Maximum fan-out ; 61 ;
|
||||
; Total fan-out ; 703 ;
|
||||
; Average fan-out ; 2.70 ;
|
||||
+---------------------------------------------+-------+
|
||||
|
||||
|
||||
|
@ -198,7 +198,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2GS ; 184 (184) ; 98 ; 1 ; 63 ; 0 ; 86 (86) ; 30 (30) ; 68 (68) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ;
|
||||
; |RAM2GS ; 196 (196) ; 104 ; 1 ; 63 ; 0 ; 92 (92) ; 34 (34) ; 70 (70) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_unv:UFM_altufm_none_unv_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component ; UFM_altufm_none_unv ; work ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
|
@ -219,8 +219,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 98 ;
|
||||
; Number of registers using Synchronous Clear ; 6 ;
|
||||
; Total registers ; 104 ;
|
||||
; Number of registers using Synchronous Clear ; 7 ;
|
||||
; Number of registers using Synchronous Load ; 4 ;
|
||||
; Number of registers using Asynchronous Clear ; 0 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
|
@ -253,16 +253,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "UFM:UFM_inst" ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; ardin ; Input ; Info ; Stuck at GND ;
|
||||
; busy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
; rtpbusy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
+-----------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "UFM:UFM_inst" ;
|
||||
+-------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+-------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; ardin ; Input ; Info ; Stuck at GND ;
|
||||
; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
+-------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
|
@ -270,8 +268,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:37:46 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Sat Sep 30 04:43:30 2023
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2gs/cpld/ram2gs-max.v
|
||||
|
@ -290,18 +288,18 @@ Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot
|
|||
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
|
||||
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
|
||||
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
|
||||
Info (21057): Implemented 248 device resources after synthesis - the final resource count might be different
|
||||
Info (21057): Implemented 260 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 25 input pins
|
||||
Info (21059): Implemented 30 output pins
|
||||
Info (21060): Implemented 8 bidirectional pins
|
||||
Info (21061): Implemented 184 logic cells
|
||||
Info (21061): Implemented 196 logic cells
|
||||
Info (21070): Implemented 1 User Flash Memory blocks
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings
|
||||
Info: Peak virtual memory: 13149 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:38:17 2023
|
||||
Info: Elapsed time: 00:00:31
|
||||
Info: Total CPU time (on all processors): 00:00:47
|
||||
Info: Peak virtual memory: 13133 megabytes
|
||||
Info: Processing ended: Sat Sep 30 04:43:56 2023
|
||||
Info: Elapsed time: 00:00:26
|
||||
Info: Total CPU time (on all processors): 00:00:44
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
Analysis & Synthesis Status : Successful - Thu Sep 21 05:38:17 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Analysis & Synthesis Status : Successful - Sat Sep 30 04:43:56 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Revision Name : RAM2GS
|
||||
Top-level Entity Name : RAM2GS
|
||||
Family : MAX II
|
||||
Total logic elements : 184
|
||||
Total logic elements : 196
|
||||
Total pins : 63
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
|
|
@ -58,7 +58,7 @@
|
|||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
CHIP "RAM2GS" ASSIGNED TO AN: EPM240T100C5
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
|
|
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
@ -2,44 +2,44 @@
|
|||
Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Setup 'DRCLK'
|
||||
Slack : -15.744
|
||||
TNS : -15.744
|
||||
|
||||
Type : Setup 'ARCLK'
|
||||
Slack : -15.723
|
||||
TNS : -15.723
|
||||
Slack : -15.739
|
||||
TNS : -15.739
|
||||
|
||||
Type : Setup 'DRCLK'
|
||||
Slack : -15.716
|
||||
TNS : -15.716
|
||||
|
||||
Type : Setup 'RCLK'
|
||||
Slack : -7.153
|
||||
TNS : -69.927
|
||||
Slack : -7.070
|
||||
TNS : -66.746
|
||||
|
||||
Type : Setup 'nCRAS'
|
||||
Slack : 0.358
|
||||
Slack : 0.330
|
||||
TNS : 0.000
|
||||
|
||||
Type : Setup 'PHI2'
|
||||
Slack : 0.545
|
||||
Slack : 0.519
|
||||
TNS : 0.000
|
||||
|
||||
Type : Hold 'ARCLK'
|
||||
Slack : -16.277
|
||||
TNS : -16.277
|
||||
|
||||
Type : Hold 'DRCLK'
|
||||
Slack : -16.276
|
||||
TNS : -16.276
|
||||
Slack : -16.296
|
||||
TNS : -16.296
|
||||
|
||||
Type : Hold 'ARCLK'
|
||||
Slack : -16.261
|
||||
TNS : -16.261
|
||||
|
||||
Type : Hold 'PHI2'
|
||||
Slack : -0.517
|
||||
TNS : -1.433
|
||||
Slack : -0.480
|
||||
TNS : -1.135
|
||||
|
||||
Type : Hold 'nCRAS'
|
||||
Slack : 0.177
|
||||
Slack : 0.160
|
||||
TNS : 0.000
|
||||
|
||||
Type : Hold 'RCLK'
|
||||
Slack : 1.111
|
||||
Slack : 1.109
|
||||
TNS : 0.000
|
||||
|
||||
Type : Minimum Pulse Width 'RCLK'
|
||||
|
|
|
@ -42,7 +42,7 @@ set_global_assignment -name DEVICE 5M240ZT100C5
|
|||
set_global_assignment -name TOP_LEVEL_ENTITY RAM2GS
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:28:29 AUGUST 12, 2023"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
|
Binary file not shown.
|
@ -1,6 +1,6 @@
|
|||
Assembler report for RAM2GS
|
||||
Thu Sep 21 05:38:26 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Sat Sep 30 04:44:05 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Thu Sep 21 05:38:26 2023 ;
|
||||
; Assembler Status ; Successful - Sat Sep 30 04:44:05 2023 ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX V ;
|
||||
|
@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula.
|
|||
+----------------+----------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+----------------------------------------------------------+
|
||||
; JTAG usercode ; 0x00174623 ;
|
||||
; Checksum ; 0x00174A1B ;
|
||||
; JTAG usercode ; 0x00172723 ;
|
||||
; Checksum ; 0x00172A9B ;
|
||||
+----------------+----------------------------------------------------------+
|
||||
|
||||
|
||||
|
@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula.
|
|||
+--------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Assembler
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:38:25 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Sat Sep 30 04:44:04 2023
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 13096 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:38:27 2023
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Processing ended: Sat Sep 30 04:44:05 2023
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
|
|
|
@ -1 +1 @@
|
|||
Thu Sep 21 05:38:32 2023
|
||||
Sat Sep 30 04:44:09 2023
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
Fitter report for RAM2GS
|
||||
Thu Sep 21 05:38:24 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Sat Sep 30 04:44:02 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
@ -56,21 +56,21 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Fitter Status ; Successful - Thu Sep 21 05:38:24 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX V ;
|
||||
; Device ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 175 / 240 ( 73 % ) ;
|
||||
; Total pins ; 63 / 79 ( 80 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
+-------------------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
; Fitter Status ; Successful - Sat Sep 30 04:44:02 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX V ;
|
||||
; Device ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 184 / 240 ( 77 % ) ;
|
||||
; Total pins ; 63 / 79 ( 80 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
@ -131,13 +131,13 @@ https://fpgasoftware.intel.com/eula.
|
|||
; Number detected on machine ; 4 ;
|
||||
; Maximum allowed ; 4 ;
|
||||
; ; ;
|
||||
; Average used ; 1.03 ;
|
||||
; Average used ; 1.04 ;
|
||||
; Maximum used ; 4 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 1.0% ;
|
||||
; Processors 3-4 ; 0.8% ;
|
||||
; Processor 2 ; 1.7% ;
|
||||
; Processors 3-4 ; 1.3% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
|
@ -152,28 +152,28 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin
|
|||
+---------------------------------------------+-----------------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-----------------------+
|
||||
; Total logic elements ; 175 / 240 ( 73 % ) ;
|
||||
; -- Combinational with no register ; 77 ;
|
||||
; -- Register only ; 21 ;
|
||||
; -- Combinational with a register ; 77 ;
|
||||
; Total logic elements ; 184 / 240 ( 77 % ) ;
|
||||
; -- Combinational with no register ; 80 ;
|
||||
; -- Register only ; 22 ;
|
||||
; -- Combinational with a register ; 82 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 57 ;
|
||||
; -- 4 input functions ; 64 ;
|
||||
; -- 3 input functions ; 46 ;
|
||||
; -- 2 input functions ; 42 ;
|
||||
; -- 2 input functions ; 43 ;
|
||||
; -- 1 input functions ; 8 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 159 ;
|
||||
; -- normal mode ; 168 ;
|
||||
; -- arithmetic mode ; 16 ;
|
||||
; -- qfbk mode ; 8 ;
|
||||
; -- qfbk mode ; 11 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 29 ;
|
||||
; -- synchronous clear/load mode ; 33 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 98 / 240 ( 41 % ) ;
|
||||
; Total LABs ; 22 / 24 ( 92 % ) ;
|
||||
; Total registers ; 104 / 240 ( 43 % ) ;
|
||||
; Total LABs ; 24 / 24 ( 100 % ) ;
|
||||
; Logic elements in carry chains ; 17 ;
|
||||
; Virtual pins ; 0 ;
|
||||
; I/O pins ; 63 / 79 ( 80 % ) ;
|
||||
|
@ -187,12 +187,12 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin
|
|||
; Global signals ; 4 ;
|
||||
; -- Global clocks ; 4 / 4 ( 100 % ) ;
|
||||
; JTAGs ; 0 / 1 ( 0 % ) ;
|
||||
; Average interconnect usage (total/H/V) ; 20.2% / 22.0% / 18.3% ;
|
||||
; Peak interconnect usage (total/H/V) ; 20.2% / 22.0% / 18.3% ;
|
||||
; Maximum fan-out ; 55 ;
|
||||
; Highest non-global fan-out ; 41 ;
|
||||
; Total fan-out ; 661 ;
|
||||
; Average fan-out ; 2.77 ;
|
||||
; Average interconnect usage (total/H/V) ; 23.0% / 25.2% / 20.7% ;
|
||||
; Peak interconnect usage (total/H/V) ; 23.0% / 25.2% / 20.7% ;
|
||||
; Maximum fan-out ; 61 ;
|
||||
; Highest non-global fan-out ; 43 ;
|
||||
; Total fan-out ; 699 ;
|
||||
; Average fan-out ; 2.82 ;
|
||||
+---------------------------------------------+-----------------------+
|
||||
|
||||
|
||||
|
@ -203,12 +203,12 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin
|
|||
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
|
||||
; CROW[0] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; CROW[1] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[6] ; 41 ; 1 ; 5 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[7] ; 40 ; 1 ; 5 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
|
@ -222,7 +222,7 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin
|
|||
; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 22 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 55 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 61 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nCCAS ; 53 ; 2 ; 8 ; 1 ; 3 ; 11 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nCRAS ; 67 ; 2 ; 8 ; 3 ; 2 ; 16 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nFWE ; 48 ; 1 ; 6 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
|
@ -245,7 +245,7 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin
|
|||
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
|
@ -253,14 +253,14 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin
|
|||
; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RBA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RDQMH ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RDQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nRCS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
|
@ -273,7 +273,7 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin
|
|||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
|
||||
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
|
||||
; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
|
||||
; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; RD~16 ; - ;
|
||||
; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
|
||||
; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
|
||||
; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
|
||||
|
@ -426,7 +426,7 @@ Note: User assignments will override these defaults. The user specified values a
|
|||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2GS ; 175 (175) ; 98 ; 1 ; 63 ; 0 ; 77 (77) ; 21 (21) ; 77 (77) ; 17 (17) ; 8 (8) ; |RAM2GS ; RAM2GS ; work ;
|
||||
; |RAM2GS ; 184 (184) ; 104 ; 1 ; 63 ; 0 ; 80 (80) ; 22 (22) ; 82 (82) ; 17 (17) ; 11 (11) ; |RAM2GS ; RAM2GS ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_38r:UFM_altufm_none_38r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component ; UFM_altufm_none_38r ; work ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
|
@ -494,32 +494,33 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
; PHI2 ; Input ; (0) ;
|
||||
; Din[6] ; Input ; (1) ;
|
||||
; nFWE ; Input ; (1) ;
|
||||
; Din[0] ; Input ; (1) ;
|
||||
; Din[7] ; Input ; (1) ;
|
||||
; Din[1] ; Input ; (1) ;
|
||||
; Din[4] ; Input ; (1) ;
|
||||
; Din[2] ; Input ; (1) ;
|
||||
; Din[3] ; Input ; (1) ;
|
||||
; Din[5] ; Input ; (1) ;
|
||||
; Din[0] ; Input ; (1) ;
|
||||
; Din[2] ; Input ; (1) ;
|
||||
+---------+----------+---------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------+
|
||||
; Control Signals ;
|
||||
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
; CmdDRDIn~1 ; LC_X5_Y1_N5 ; 4 ; Clock enable ; no ; -- ; -- ;
|
||||
; CmdLEDEN~1 ; LC_X5_Y1_N3 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; DRDIn~1 ; LC_X7_Y1_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK3 ;
|
||||
; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; RD~16 ; LC_X3_Y4_N5 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; Ready ; LC_X3_Y2_N8 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ;
|
||||
; always8~6 ; LC_X4_Y2_N2 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ;
|
||||
; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK1 ;
|
||||
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
+--------------------------------------------------------------------------------------------------------------------+
|
||||
; Control Signals ;
|
||||
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
; CmdDRDIn~1 ; LC_X4_Y2_N3 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; CmdLEDEN~1 ; LC_X4_Y1_N7 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; CmdUFMErase~0 ; LC_X4_Y2_N6 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; DRDIn~1 ; LC_X3_Y1_N6 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK3 ;
|
||||
; RCLK ; PIN_12 ; 61 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; RD~16 ; LC_X4_Y4_N4 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; Ready ; LC_X3_Y3_N6 ; 42 ; Sync. clear, Sync. load ; no ; -- ; -- ;
|
||||
; always11~7 ; LC_X7_Y4_N3 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ;
|
||||
; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK1 ;
|
||||
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
|
@ -528,7 +529,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
||||
+-------+----------+---------+----------------------+------------------+
|
||||
; PHI2 ; PIN_52 ; 22 ; Global Clock ; GCLK3 ;
|
||||
; RCLK ; PIN_12 ; 55 ; Global Clock ; GCLK0 ;
|
||||
; RCLK ; PIN_12 ; 61 ; Global Clock ; GCLK0 ;
|
||||
; nCCAS ; PIN_53 ; 11 ; Global Clock ; GCLK2 ;
|
||||
; nCRAS ; PIN_67 ; 16 ; Global Clock ; GCLK1 ;
|
||||
+-------+----------+---------+----------------------+------------------+
|
||||
|
@ -539,109 +540,106 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+-----------------------+--------------------+
|
||||
; Routing Resource Type ; Usage ;
|
||||
+-----------------------+--------------------+
|
||||
; C4s ; 128 / 784 ( 16 % ) ;
|
||||
; Direct links ; 37 / 888 ( 4 % ) ;
|
||||
; C4s ; 138 / 784 ( 18 % ) ;
|
||||
; Direct links ; 41 / 888 ( 5 % ) ;
|
||||
; Global clocks ; 4 / 4 ( 100 % ) ;
|
||||
; LAB clocks ; 15 / 32 ( 47 % ) ;
|
||||
; LUT chains ; 15 / 216 ( 7 % ) ;
|
||||
; Local interconnects ; 239 / 888 ( 27 % ) ;
|
||||
; R4s ; 117 / 704 ( 17 % ) ;
|
||||
; LAB clocks ; 17 / 32 ( 53 % ) ;
|
||||
; LUT chains ; 18 / 216 ( 8 % ) ;
|
||||
; Local interconnects ; 262 / 888 ( 30 % ) ;
|
||||
; R4s ; 139 / 704 ( 20 % ) ;
|
||||
+-----------------------+--------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Logic Elements ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; Number of Logic Elements (Average = 7.95) ; Number of LABs (Total = 22) ;
|
||||
; Number of Logic Elements (Average = 7.67) ; Number of LABs (Total = 24) ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; 1 ; 1 ;
|
||||
; 2 ; 1 ;
|
||||
; 1 ; 2 ;
|
||||
; 2 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 2 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 1 ;
|
||||
; 8 ; 4 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 10 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 4 ;
|
||||
; 10 ; 11 ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; LAB-wide Signals ;
|
||||
+------------------------------------+------------------------------+
|
||||
; LAB-wide Signals (Average = 1.50) ; Number of LABs (Total = 22) ;
|
||||
; LAB-wide Signals (Average = 1.21) ; Number of LABs (Total = 24) ;
|
||||
+------------------------------------+------------------------------+
|
||||
; 1 Clock ; 13 ;
|
||||
; 1 Clock enable ; 6 ;
|
||||
; 1 Clock ; 18 ;
|
||||
; 1 Clock enable ; 2 ;
|
||||
; 1 Sync. clear ; 3 ;
|
||||
; 1 Sync. load ; 2 ;
|
||||
; 2 Clocks ; 9 ;
|
||||
; 2 Clocks ; 6 ;
|
||||
+------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced (Average = 8.18) ; Number of LABs (Total = 22) ;
|
||||
; Number of Signals Sourced (Average = 7.96) ; Number of LABs (Total = 24) ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 1 ;
|
||||
; 2 ; 1 ;
|
||||
; 1 ; 2 ;
|
||||
; 2 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 2 ;
|
||||
; 8 ; 3 ;
|
||||
; 9 ; 3 ;
|
||||
; 10 ; 7 ;
|
||||
; 11 ; 3 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 4 ;
|
||||
; 10 ; 11 ;
|
||||
; 11 ; 2 ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced Out ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced Out (Average = 5.45) ; Number of LABs (Total = 22) ;
|
||||
; Number of Signals Sourced Out (Average = 5.21) ; Number of LABs (Total = 24) ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 1 ;
|
||||
; 1 ; 3 ;
|
||||
; 2 ; 1 ;
|
||||
; 3 ; 2 ;
|
||||
; 4 ; 2 ;
|
||||
; 5 ; 4 ;
|
||||
; 6 ; 4 ;
|
||||
; 7 ; 5 ;
|
||||
; 8 ; 3 ;
|
||||
; 3 ; 3 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 3 ;
|
||||
; 6 ; 3 ;
|
||||
; 7 ; 7 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 1 ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; Number of Distinct Inputs (Average = 9.32) ; Number of LABs (Total = 22) ;
|
||||
; Number of Distinct Inputs (Average = 8.79) ; Number of LABs (Total = 24) ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 3 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 1 ;
|
||||
; 2 ; 4 ;
|
||||
; 3 ; 2 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 1 ;
|
||||
; 8 ; 4 ;
|
||||
; 9 ; 3 ;
|
||||
; 10 ; 0 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 3 ;
|
||||
; 11 ; 2 ;
|
||||
; 12 ; 1 ;
|
||||
; 13 ; 3 ;
|
||||
; 14 ; 1 ;
|
||||
; 15 ; 0 ;
|
||||
; 12 ; 3 ;
|
||||
; 13 ; 1 ;
|
||||
; 14 ; 2 ;
|
||||
; 15 ; 1 ;
|
||||
; 16 ; 1 ;
|
||||
; 17 ; 0 ;
|
||||
; 18 ; 0 ;
|
||||
; 19 ; 1 ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
|
@ -731,7 +729,7 @@ Info (176234): Starting register packing
|
|||
Info (186468): Started processing fast register assignments
|
||||
Info (186469): Finished processing fast register assignments
|
||||
Info (176235): Finished register packing
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
|
||||
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
|
||||
Info (170189): Fitter placement preparation operations beginning
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
|
||||
|
@ -739,18 +737,18 @@ Info (170191): Fitter placement operations beginning
|
|||
Info (170137): Fitter placement was successful
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
|
||||
Info (170193): Fitter routing operations beginning
|
||||
Info (170195): Router estimated average interconnect usage is 16% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 16% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170195): Router estimated average interconnect usage is 19% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
||||
Info (170201): Optimizations that may affect the design's routability were skipped
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.78 seconds.
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.58 seconds.
|
||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 13770 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:38:24 2023
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Peak virtual memory: 13772 megabytes
|
||||
Info: Processing ended: Sat Sep 30 04:44:02 2023
|
||||
Info: Elapsed time: 00:00:04
|
||||
Info: Total CPU time (on all processors): 00:00:04
|
||||
|
||||
|
||||
|
|
|
@ -1,11 +1,11 @@
|
|||
Fitter Status : Successful - Thu Sep 21 05:38:24 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Fitter Status : Successful - Sat Sep 30 04:44:02 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Revision Name : RAM2GS
|
||||
Top-level Entity Name : RAM2GS
|
||||
Family : MAX V
|
||||
Device : 5M240ZT100C5
|
||||
Timing Models : Final
|
||||
Total logic elements : 175 / 240 ( 73 % )
|
||||
Total logic elements : 184 / 240 ( 77 % )
|
||||
Total pins : 63 / 79 ( 80 % )
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
Flow report for RAM2GS
|
||||
Thu Sep 21 05:38:31 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Sat Sep 30 04:44:08 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Flow Status ; Successful - Thu Sep 21 05:38:26 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX V ;
|
||||
; Device ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 175 / 240 ( 73 % ) ;
|
||||
; Total pins ; 63 / 79 ( 80 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
+-------------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
; Flow Status ; Successful - Sat Sep 30 04:44:05 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX V ;
|
||||
; Device ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 184 / 240 ( 77 % ) ;
|
||||
; Total pins ; 63 / 79 ( 80 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
|
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 09/21/2023 05:37:48 ;
|
||||
; Start date & time ; 09/30/2023 04:43:33 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
+-------------------+---------------------+
|
||||
|
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.169528906810556 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.169606341306136 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
|
||||
|
@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula.
|
|||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:31 ; 1.0 ; 13149 MB ; 00:00:46 ;
|
||||
; Fitter ; 00:00:05 ; 1.0 ; 13770 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13092 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:03 ; 1.0 ; 13090 MB ; 00:00:02 ;
|
||||
; Total ; 00:00:40 ; -- ; -- ; 00:00:53 ;
|
||||
; Analysis & Synthesis ; 00:00:25 ; 1.0 ; 13138 MB ; 00:00:41 ;
|
||||
; Fitter ; 00:00:04 ; 1.0 ; 13772 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13094 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13092 MB ; 00:00:02 ;
|
||||
; Total ; 00:00:32 ; -- ; -- ; 00:00:48 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
Analysis & Synthesis report for RAM2GS
|
||||
Thu Sep 21 05:38:18 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Sat Sep 30 04:43:57 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
|
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Thu Sep 21 05:38:18 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX V ;
|
||||
; Total logic elements ; 184 ;
|
||||
; Total pins ; 63 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
+-------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+-------------------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Sat Sep 30 04:43:57 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX V ;
|
||||
; Total logic elements ; 196 ;
|
||||
; Total pins ; 63 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------------+-------------------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
|
@ -162,34 +162,34 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------------+-------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-------+
|
||||
; Total logic elements ; 184 ;
|
||||
; -- Combinational with no register ; 86 ;
|
||||
; -- Register only ; 30 ;
|
||||
; -- Combinational with a register ; 68 ;
|
||||
; Total logic elements ; 196 ;
|
||||
; -- Combinational with no register ; 92 ;
|
||||
; -- Register only ; 34 ;
|
||||
; -- Combinational with a register ; 70 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 57 ;
|
||||
; -- 4 input functions ; 64 ;
|
||||
; -- 3 input functions ; 46 ;
|
||||
; -- 2 input functions ; 42 ;
|
||||
; -- 2 input functions ; 43 ;
|
||||
; -- 1 input functions ; 8 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 168 ;
|
||||
; -- normal mode ; 180 ;
|
||||
; -- arithmetic mode ; 16 ;
|
||||
; -- qfbk mode ; 0 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 10 ;
|
||||
; -- synchronous clear/load mode ; 11 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 98 ;
|
||||
; Total registers ; 104 ;
|
||||
; Total logic cells in carry chains ; 17 ;
|
||||
; I/O pins ; 63 ;
|
||||
; UFM blocks ; 1 ;
|
||||
; Maximum fan-out node ; RCLK ;
|
||||
; Maximum fan-out ; 55 ;
|
||||
; Total fan-out ; 662 ;
|
||||
; Average fan-out ; 2.67 ;
|
||||
; Maximum fan-out ; 61 ;
|
||||
; Total fan-out ; 703 ;
|
||||
; Average fan-out ; 2.70 ;
|
||||
+---------------------------------------------+-------+
|
||||
|
||||
|
||||
|
@ -198,7 +198,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2GS ; 184 (184) ; 98 ; 1 ; 63 ; 0 ; 86 (86) ; 30 (30) ; 68 (68) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ;
|
||||
; |RAM2GS ; 196 (196) ; 104 ; 1 ; 63 ; 0 ; 92 (92) ; 34 (34) ; 70 (70) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_38r:UFM_altufm_none_38r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component ; UFM_altufm_none_38r ; work ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
|
@ -219,8 +219,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 98 ;
|
||||
; Number of registers using Synchronous Clear ; 6 ;
|
||||
; Total registers ; 104 ;
|
||||
; Number of registers using Synchronous Clear ; 7 ;
|
||||
; Number of registers using Synchronous Load ; 4 ;
|
||||
; Number of registers using Asynchronous Clear ; 0 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
|
@ -253,16 +253,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "UFM:UFM_inst" ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; ardin ; Input ; Info ; Stuck at GND ;
|
||||
; busy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
; rtpbusy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
+-----------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "UFM:UFM_inst" ;
|
||||
+-------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+-------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; ardin ; Input ; Info ; Stuck at GND ;
|
||||
; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
+-------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
|
@ -270,8 +268,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:37:47 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Sat Sep 30 04:43:32 2023
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2gs/cpld/ram2gs-max.v
|
||||
|
@ -290,18 +288,18 @@ Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot
|
|||
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
|
||||
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
|
||||
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
|
||||
Info (21057): Implemented 248 device resources after synthesis - the final resource count might be different
|
||||
Info (21057): Implemented 260 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 25 input pins
|
||||
Info (21059): Implemented 30 output pins
|
||||
Info (21060): Implemented 8 bidirectional pins
|
||||
Info (21061): Implemented 184 logic cells
|
||||
Info (21061): Implemented 196 logic cells
|
||||
Info (21070): Implemented 1 User Flash Memory blocks
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings
|
||||
Info: Peak virtual memory: 13149 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:38:18 2023
|
||||
Info: Elapsed time: 00:00:31
|
||||
Info: Total CPU time (on all processors): 00:00:46
|
||||
Info: Peak virtual memory: 13138 megabytes
|
||||
Info: Processing ended: Sat Sep 30 04:43:57 2023
|
||||
Info: Elapsed time: 00:00:25
|
||||
Info: Total CPU time (on all processors): 00:00:41
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
Analysis & Synthesis Status : Successful - Thu Sep 21 05:38:18 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Analysis & Synthesis Status : Successful - Sat Sep 30 04:43:57 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Revision Name : RAM2GS
|
||||
Top-level Entity Name : RAM2GS
|
||||
Family : MAX V
|
||||
Total logic elements : 184
|
||||
Total logic elements : 196
|
||||
Total pins : 63
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
|
|
@ -58,7 +58,7 @@
|
|||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
CHIP "RAM2GS" ASSIGNED TO AN: 5M240ZT100C5
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
|
|
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
@ -2,44 +2,44 @@
|
|||
Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Setup 'RCLK'
|
||||
Slack : -19.199
|
||||
TNS : -193.279
|
||||
|
||||
Type : Setup 'DRCLK'
|
||||
Slack : -17.454
|
||||
TNS : -17.454
|
||||
|
||||
Type : Setup 'ARCLK'
|
||||
Slack : -17.440
|
||||
TNS : -17.440
|
||||
|
||||
Type : Setup 'ARCLK'
|
||||
Slack : -17.423
|
||||
TNS : -17.423
|
||||
|
||||
Type : Setup 'RCLK'
|
||||
Slack : -15.806
|
||||
TNS : -201.988
|
||||
|
||||
Type : Setup 'nCRAS'
|
||||
Slack : -0.922
|
||||
TNS : -0.922
|
||||
Slack : -1.413
|
||||
TNS : -2.367
|
||||
|
||||
Type : Setup 'PHI2'
|
||||
Slack : 0.616
|
||||
Slack : 2.092
|
||||
TNS : 0.000
|
||||
|
||||
Type : Hold 'DRCLK'
|
||||
Slack : -14.753
|
||||
TNS : -14.753
|
||||
|
||||
Type : Hold 'ARCLK'
|
||||
Slack : -14.577
|
||||
TNS : -14.577
|
||||
|
||||
Type : Hold 'DRCLK'
|
||||
Slack : -14.560
|
||||
TNS : -14.560
|
||||
|
||||
Type : Hold 'PHI2'
|
||||
Slack : -2.450
|
||||
TNS : -5.440
|
||||
Slack : -1.628
|
||||
TNS : -4.762
|
||||
|
||||
Type : Hold 'nCRAS'
|
||||
Slack : -0.233
|
||||
TNS : -0.929
|
||||
Slack : 0.169
|
||||
TNS : 0.000
|
||||
|
||||
Type : Hold 'RCLK'
|
||||
Slack : 2.155
|
||||
Slack : 2.126
|
||||
TNS : 0.000
|
||||
|
||||
Type : Minimum Pulse Width 'RCLK'
|
||||
|
|
|
@ -18,9 +18,9 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
reg CBR;
|
||||
|
||||
/* Activity LED */
|
||||
reg LEDEN = 0;
|
||||
reg LEDEN;
|
||||
output LED;
|
||||
assign LED = !(!nCRAS && !CBR && LEDEN);
|
||||
assign LED = !(!nCRAS && !CBR && LEDEN && Ready);
|
||||
|
||||
/* 65816 Data */
|
||||
input [7:0] Din;
|
||||
|
@ -71,8 +71,8 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
|
||||
reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
|
||||
reg UFMOscEN = 0; // UFM oscillator enable
|
||||
wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
|
||||
wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
|
||||
wire UFMBusyAsync; // 1 if UFM is doing user operation. Asynchronous
|
||||
wire RTPBusyAsync; // 1 if real-time programming in progress. Asynchronous
|
||||
wire DRDOut; // UFM data output
|
||||
// UFM oscillator always enabled
|
||||
wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
|
||||
|
@ -86,12 +86,16 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
.erase (UFMErase),
|
||||
.oscena (UFMOscEN),
|
||||
.program (UFMProgram),
|
||||
.busy (UFMBusy),
|
||||
.busy (UFMBusyAsync),
|
||||
.drdout (DRDOut),
|
||||
.osc (UFMOsc),
|
||||
.rtpbusy (RTPBusy));
|
||||
reg UFMBusyReg = 0; // UFMBusy registered to sync with RCLK
|
||||
reg RTPBusyReg = 0; // RTPBusy registered to sync with RCLK
|
||||
.rtpbusy (RTPBusyAsync));
|
||||
// UFMBusy registered to sync with RCLK
|
||||
reg UFMBusyReg; always @(posedge RCLK) UFMBusyReg <= UFMBusyAsync;
|
||||
// RTPBusy registered to sync with RCLK
|
||||
reg RTPBusyReg; always @(posedge RCLK) RTPBusyReg <= RTPBusyAsync;
|
||||
// UFMRTPBusy ORs both
|
||||
reg UFMRTPBusy; always @(posedge RCLK) UFMRTPBusy <= UFMBusyReg || RTPBusyReg;
|
||||
|
||||
/* UFM State */
|
||||
reg UFMInitDone = 0; // 1 if UFM initialization finished
|
||||
|
@ -166,7 +170,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
always @(posedge RCLK) begin
|
||||
// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
|
||||
FS <= FS+18'h1;
|
||||
if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
|
||||
if (FS[17:10]==8'hFF) InitReady <= 1'b1;
|
||||
end
|
||||
|
||||
/* SDRAM CKE */
|
||||
|
@ -356,8 +360,10 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
// MAX commands
|
||||
CmdLEDEN <= LEDEN;
|
||||
Cmdn8MEGEN <= n8MEGEN;
|
||||
CmdUFMErase <= Din[3];
|
||||
CmdUFMPrgm <= Din[2];
|
||||
if (!CmdUFMPrgm && !CmdUFMErase) begin
|
||||
CmdUFMErase <= Din[3];
|
||||
CmdUFMPrgm <= Din[2];
|
||||
end
|
||||
CmdDRCLK <= Din[1];
|
||||
CmdDRDIn <= Din[0];
|
||||
CmdSubmitted <= 1'b1;
|
||||
|
@ -374,7 +380,12 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
end
|
||||
end
|
||||
|
||||
/* UFM command synchronization */
|
||||
reg CmdUFMPrgmSync; always @(posedge RCLK) CmdUFMPrgmSync <= CmdUFMPrgm;
|
||||
reg CmdUFMEraseSync; always @(posedge RCLK) CmdUFMEraseSync <= CmdUFMErase;
|
||||
|
||||
/* UFM Control */
|
||||
reg UFMProgStart;
|
||||
always @(posedge RCLK) begin
|
||||
if (!Ready) begin
|
||||
if (!UFMInitDone && FS[17:16]==2'b00) begin
|
||||
|
@ -445,6 +456,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
// Don't erase or program UFM during initialization
|
||||
UFMErase <= 1'b0;
|
||||
UFMProgram <= 1'b0;
|
||||
UFMProgStart <= 1'b0;
|
||||
end else begin
|
||||
// Can only shift UFM data register now
|
||||
ARCLK <= 1'b0;
|
||||
|
@ -460,11 +472,16 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
end
|
||||
|
||||
// UFM programming sequence
|
||||
if (CmdUFMPrgm || CmdUFMErase) begin
|
||||
if (!UFMBusyReg && !RTPBusyReg) begin
|
||||
if (UFMReqErase || CmdUFMErase) UFMErase <= 1'b1;
|
||||
else if (CmdUFMPrgm) UFMProgram <= 1'b1;
|
||||
end else if (UFMBusyReg) UFMReqErase <= 1'b0;
|
||||
if (FS[6:0]==0) begin
|
||||
if (!UFMProgStart && !UFMRTPBusy) begin
|
||||
if (CmdUFMPrgmSync) begin
|
||||
UFMErase <= UFMReqErase || CmdUFMEraseSync;
|
||||
UFMProgStart <= 1'b1;
|
||||
end else if (CmdUFMEraseSync) UFMErase <= 1'b1;
|
||||
end else if (UFMProgStart && !UFMRTPBusy) begin
|
||||
UFMErase <= 1'b0;
|
||||
if (!UFMErase) UFMProgram <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
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Reference in New Issue