symboldumps

added paypal sponsor link

.github/FUNDING.yml

@@ -2,7 +2,7 @@
 
 #github: # Replace with up to 4 GitHub Sponsors-enabled usernames e.g., [user1, user2]
 #patreon: # Replace with a single Patreon username
-open_collective: # Replace with a single Open Collective username
+#open_collective: # Replace with a single Open Collective username
 ko_fi: irmen
 #tidelift: # Replace with a single Tidelift platform-name/package-name e.g., npm/babel
 #community_bridge: # Replace with a single Community Bridge project-name e.g., cloud-foundry
@@ -11,3 +11,4 @@ ko_fi: irmen
 #otechie: # Replace with a single Otechie username
 #lfx_crowdfunding: # Replace with a single LFX Crowdfunding project-name e.g., cloud-foundry
 #custom: # Replace with up to 4 custom sponsorship URLs e.g., ['link1', 'link2']
+custom: ['https://paypal.me/irmendejong']

.idea/kotlinc.xml

@@ -14,6 +14,6 @@
     <option name="additionalArguments" value="-Xwhen-guards" />
   </component>
   <component name="KotlinJpsPluginSettings">
-    <option name="version" value="2.1.0" />
+    <option name="version" value="2.1.10" />
   </component>
 </project>

.idea/libraries/KotlinJavaRuntime.xml

@@ -1,23 +1,23 @@
 <component name="libraryTable">
   <library name="KotlinJavaRuntime" type="repository">
-    <properties maven-id="org.jetbrains.kotlin:kotlin-stdlib-jdk8:2.1.0" />
+    <properties maven-id="org.jetbrains.kotlin:kotlin-stdlib-jdk8:2.1.10" />
     <CLASSES>
-      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib-jdk8/2.1.0/kotlin-stdlib-jdk8-2.1.0.jar!/" />
-      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib/2.1.0/kotlin-stdlib-2.1.0.jar!/" />
+      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib-jdk8/2.1.10/kotlin-stdlib-jdk8-2.1.10.jar!/" />
+      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib/2.1.10/kotlin-stdlib-2.1.10.jar!/" />
       <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/annotations/13.0/annotations-13.0.jar!/" />
-      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib-jdk7/2.1.0/kotlin-stdlib-jdk7-2.1.0.jar!/" />
+      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib-jdk7/2.1.10/kotlin-stdlib-jdk7-2.1.10.jar!/" />
     </CLASSES>
     <JAVADOC>
-      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib-jdk8/2.1.0/kotlin-stdlib-jdk8-2.1.0-javadoc.jar!/" />
-      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib/2.1.0/kotlin-stdlib-2.1.0-javadoc.jar!/" />
+      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib-jdk8/2.1.10/kotlin-stdlib-jdk8-2.1.10-javadoc.jar!/" />
+      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib/2.1.10/kotlin-stdlib-2.1.10-javadoc.jar!/" />
       <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/annotations/13.0/annotations-13.0-javadoc.jar!/" />
-      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib-jdk7/2.1.0/kotlin-stdlib-jdk7-2.1.0-javadoc.jar!/" />
+      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib-jdk7/2.1.10/kotlin-stdlib-jdk7-2.1.10-javadoc.jar!/" />
     </JAVADOC>
     <SOURCES>
-      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib-jdk8/2.1.0/kotlin-stdlib-jdk8-2.1.0-sources.jar!/" />
-      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib/2.1.0/kotlin-stdlib-2.1.0-sources.jar!/" />
+      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib-jdk8/2.1.10/kotlin-stdlib-jdk8-2.1.10-sources.jar!/" />
+      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib/2.1.10/kotlin-stdlib-2.1.10-sources.jar!/" />
       <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/annotations/13.0/annotations-13.0-sources.jar!/" />
-      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib-jdk7/2.1.0/kotlin-stdlib-jdk7-2.1.0-sources.jar!/" />
+      <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib-jdk7/2.1.10/kotlin-stdlib-jdk7-2.1.10-sources.jar!/" />
     </SOURCES>
   </library>
 </component>

.idea/libraries/michael_bull_kotlin_result_jvm.xml

@@ -1,18 +1,18 @@
 <component name="libraryTable">
   <library name="michael.bull.kotlin.result.jvm" type="repository">
-    <properties maven-id="com.michael-bull.kotlin-result:kotlin-result-jvm:2.0.0" />
+    <properties maven-id="com.michael-bull.kotlin-result:kotlin-result-jvm:2.0.1" />
     <CLASSES>
-      <root url="jar://$MAVEN_REPOSITORY$/com/michael-bull/kotlin-result/kotlin-result-jvm/2.0.0/kotlin-result-jvm-2.0.0.jar!/" />
+      <root url="jar://$MAVEN_REPOSITORY$/com/michael-bull/kotlin-result/kotlin-result-jvm/2.0.1/kotlin-result-jvm-2.0.1.jar!/" />
       <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib/1.9.22/kotlin-stdlib-1.9.22.jar!/" />
       <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/annotations/13.0/annotations-13.0.jar!/" />
     </CLASSES>
     <JAVADOC>
-      <root url="jar://$MAVEN_REPOSITORY$/com/michael-bull/kotlin-result/kotlin-result-jvm/2.0.0/kotlin-result-jvm-2.0.0-javadoc.jar!/" />
+      <root url="jar://$MAVEN_REPOSITORY$/com/michael-bull/kotlin-result/kotlin-result-jvm/2.0.1/kotlin-result-jvm-2.0.1-javadoc.jar!/" />
       <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib/1.9.22/kotlin-stdlib-1.9.22-javadoc.jar!/" />
       <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/annotations/13.0/annotations-13.0-javadoc.jar!/" />
     </JAVADOC>
     <SOURCES>
-      <root url="jar://$MAVEN_REPOSITORY$/com/michael-bull/kotlin-result/kotlin-result-jvm/2.0.0/kotlin-result-jvm-2.0.0-sources.jar!/" />
+      <root url="jar://$MAVEN_REPOSITORY$/com/michael-bull/kotlin-result/kotlin-result-jvm/2.0.1/kotlin-result-jvm-2.0.1-sources.jar!/" />
       <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/kotlin/kotlin-stdlib/1.9.22/kotlin-stdlib-1.9.22-sources.jar!/" />
       <root url="jar://$MAVEN_REPOSITORY$/org/jetbrains/annotations/13.0/annotations-13.0-sources.jar!/" />
     </SOURCES>

.idea/misc.xml

@@ -22,7 +22,7 @@
   <component name="FrameworkDetectionExcludesConfiguration">
     <type id="Python" />
   </component>
-  <component name="ProjectRootManager" version="2" languageLevel="JDK_17" default="true" project-jdk-name="openjdk-17" project-jdk-type="JavaSDK">
+  <component name="ProjectRootManager" version="2" languageLevel="JDK_11" default="true" project-jdk-name="openjdk-11" project-jdk-type="JavaSDK">
     <output url="file://$PROJECT_DIR$/out" />
   </component>
 </project>

README.md

@@ -1,4 +1,7 @@
 [![ko-fi](https://ko-fi.com/img/githubbutton_sm.svg)](https://ko-fi.com/H2H6S0FFF)
+
+PayPal: [![PayPal](https://www.paypalobjects.com/en_US/i/btn/btn_donate_LG.gif)](https://paypal.me/irmendejong)
+
 [![Documentation](https://readthedocs.org/projects/prog8/badge/?version=latest)](https://prog8.readthedocs.io/)
 
 Prog8 - Structured Programming Language for 8-bit 6502/65c02 microprocessors
@@ -14,7 +17,7 @@ which aims to provide many conveniences over raw assembly code (even when using
 
 This project was created over the last couple of years by dedicating thousands of hours of my free time to it, to make it the best I possibly can.
 If you like Prog8, and think it's worth a nice cup of hot coffee or a delicious pizza, 
-you can help me out a little bit over at [ko-fi.com/irmen](https://ko-fi.com/irmen). 
+you can help me out a little bit over at [ko-fi.com/irmen](https://ko-fi.com/irmen) or [PayPal](https://paypal.me/irmendejong)
 
 
 Documentation
@@ -70,6 +73,7 @@ What does Prog8 provide?
 - ``defer`` statement to help write concise and robust subroutine cleanup logic
 - several specialized built-in functions such as ``lsb``, ``msb``, ``min``, ``max``, ``rol``, ``ror``
 - various powerful built-in libraries to do I/O, number conversions, graphics and more  
+- subroutines can return more than one result value
 - inline assembly allows you to have full control when every cycle or byte matters
 - supports the sixteen 'virtual' 16-bit registers R0 - R15 from the Commander X16 (also available on other targets)
 - encode strings and characters into petscii or screencodes or even other encodings

build.gradle.kts

@@ -1,7 +1,9 @@
 import org.jetbrains.kotlin.gradle.dsl.JvmTarget
+import org.jetbrains.kotlin.gradle.internal.config.LanguageFeature
+
 
 plugins {
-    kotlin("jvm") version "2.1.0"
+    kotlin("jvm") version "2.1.10"
 }
 
 allprojects {
@@ -17,6 +19,12 @@ allprojects {
             freeCompilerArgs = listOf("-Xwhen-guards")
             jvmTarget = JvmTarget.JVM_11
         }
+        sourceSets.all {
+            languageSettings {
+                // enable language features like so:
+                // enableLanguageFeature(LanguageFeature.WhenGuards.name)
+            }
+        }
     }
 
     java {

codeCore/build.gradle.kts

@@ -7,7 +7,7 @@ plugins {
 dependencies {
     // should have no dependencies to other modules
     // implementation("org.jetbrains.kotlin:kotlin-stdlib-jdk8")
-    implementation("com.michael-bull.kotlin-result:kotlin-result-jvm:2.0.0")
+    implementation("com.michael-bull.kotlin-result:kotlin-result-jvm:2.0.1")
 }
 
 sourceSets {
@@ -21,4 +21,4 @@ sourceSets {
     }
 }
 
-// note: there are no unit tests in this module!
+// note: there are no unit tests in this module!

codeCore/src/prog8/code/SymbolTable.kt

@@ -259,7 +259,7 @@ class StMemorySlab(
     StNode(name, StNodeType.MEMORYSLAB, astNode)
 
 
-class StSub(name: String, val parameters: List<StSubroutineParameter>, val returnType: DataType?, astNode: PtNode) :
+class StSub(name: String, val parameters: List<StSubroutineParameter>, val returns: List<DataType>, astNode: PtNode) :
         StNode(name, StNodeType.SUBROUTINE, astNode)
 
 

codeCore/src/prog8/code/SymbolTableMaker.kt

@@ -23,10 +23,10 @@ class SymbolTableMaker(private val program: PtProgram, private val options: Comp
 
         if(options.compTarget.name != VMTarget.NAME) {
             listOf(
-                PtMemMapped("P8ZP_SCRATCH_B1", DataType.forDt(BaseDataType.UBYTE), options.compTarget.machine.zeropage.SCRATCH_B1, null, Position.DUMMY),
-                PtMemMapped("P8ZP_SCRATCH_REG", DataType.forDt(BaseDataType.UBYTE), options.compTarget.machine.zeropage.SCRATCH_REG, null, Position.DUMMY),
-                PtMemMapped("P8ZP_SCRATCH_W1", DataType.forDt(BaseDataType.UWORD), options.compTarget.machine.zeropage.SCRATCH_W1, null, Position.DUMMY),
-                PtMemMapped("P8ZP_SCRATCH_W2", DataType.forDt(BaseDataType.UWORD), options.compTarget.machine.zeropage.SCRATCH_W2, null, Position.DUMMY),
+                PtMemMapped("P8ZP_SCRATCH_B1", DataType.forDt(BaseDataType.UBYTE), options.compTarget.zeropage.SCRATCH_B1, null, Position.DUMMY),
+                PtMemMapped("P8ZP_SCRATCH_REG", DataType.forDt(BaseDataType.UBYTE), options.compTarget.zeropage.SCRATCH_REG, null, Position.DUMMY),
+                PtMemMapped("P8ZP_SCRATCH_W1", DataType.forDt(BaseDataType.UWORD), options.compTarget.zeropage.SCRATCH_W1, null, Position.DUMMY),
+                PtMemMapped("P8ZP_SCRATCH_W2", DataType.forDt(BaseDataType.UWORD), options.compTarget.zeropage.SCRATCH_W2, null, Position.DUMMY),
             ).forEach {
                 it.parent = program
                 st.add(StMemVar(it.name, it.type, it.address, it.arraySize?.toInt(), it))
@@ -58,7 +58,7 @@ class SymbolTableMaker(private val program: PtProgram, private val options: Comp
             }
             is PtSub -> {
                 val params = node.parameters.map {StSubroutineParameter(it.name, it.type, it.register) }
-                StSub(node.name, params, node.returntype, node)
+                StSub(node.name, params, node.returns, node)
             }
             is PtVariable -> {
                 val initialNumeric: Double?

codeCore/src/prog8/code/ast/AstExpressions.kt

@@ -98,7 +98,7 @@ sealed class PtExpression(val type: DataType, position: Position) : PtNode(posit
             is PtFunctionCall -> false
             is PtIdentifier -> true
             is PtIrRegister -> true
-            is PtMemoryByte -> address is PtNumber || address is PtIdentifier
+            is PtMemoryByte -> address is PtNumber
             is PtBool -> true
             is PtNumber -> true
             is PtPrefix -> value.isSimple()
@@ -242,7 +242,7 @@ class PtFunctionCall(val name: String,
         if(void) require(type.isUndefined) {
             "void fcall should have undefined datatype"
         }
-        // note: non-void calls can have UNDEFINED type: is if they return more than 1 value
+        // note: non-void calls can have UNDEFINED type: if they return more than 1 value
     }
 }
 
@@ -379,6 +379,16 @@ class PtString(val value: String, val encoding: Encoding, position: Position) :
 class PtTypeCast(type: BaseDataType, position: Position) : PtExpression(DataType.forDt(type), position) {
     val value: PtExpression
         get() = children.single() as PtExpression
+
+    fun copy(): PtTypeCast {
+        val copy = PtTypeCast(type.base, position)
+        if(children[0] is PtIdentifier) {
+            copy.add((children[0] as PtIdentifier).copy())
+        } else {
+            TODO("cannot copy node ${children[0]}")
+        }
+        return copy
+    }
 }
 
 

codeCore/src/prog8/code/ast/AstPrinter.kt

@@ -125,8 +125,8 @@ fun printAst(root: PtNode, skipLibraries: Boolean, output: (text: String) -> Uni
                     "${it.type} ${it.name} $reg"
                 }
                 var str = "sub ${node.name}($params) "
-                if(node.returntype!=null)
-                    str += "-> ${node.returntype}"
+                if(node.returns.isNotEmpty())
+                    str += "-> ${node.returns.joinToString(",")}"
                 str
             }
             is PtVariable -> {
@@ -171,6 +171,7 @@ fun printAst(root: PtNode, skipLibraries: Boolean, output: (text: String) -> Uni
             }
             is PtDefer -> "<defer>"
             is PtIfExpression -> "<ifexpr>"
+            is PtJmpTable -> "<jmptable>"
         }
     }
 

codeCore/src/prog8/code/ast/AstStatements.kt

@@ -25,15 +25,15 @@ class PtAsmSub(
 class PtSub(
     name: String,
     val parameters: List<PtSubroutineParameter>,
-    val returntype: DataType?,
+    val returns: List<DataType>,
     position: Position
 ) : PtNamedNode(name, position), IPtSubroutine, IPtStatementContainer {
     init {
-        // params and return value should not be str
+        // params and return values should not be str
         if(parameters.any{ !it.type.isNumericOrBool })
             throw AssemblyError("non-numeric/non-bool parameter")
-        if(returntype!=null && !returntype.isNumericOrBool)
-            throw AssemblyError("non-numeric/non-bool returntype $returntype")
+        if(returns.any { !it.isNumericOrBool })
+            throw AssemblyError("non-numeric/non-bool returntype")
         parameters.forEach { it.parent=this }
     }
 }
@@ -59,7 +59,7 @@ sealed interface IPtAssignment {
         get() = children.size>2
 }
 
-class PtAssignment(position: Position) : PtNode(position), IPtAssignment
+class PtAssignment(position: Position, val isVarInitializer: Boolean=false) : PtNode(position), IPtAssignment
 
 class PtAugmentedAssign(val operator: String, position: Position) : PtNode(position), IPtAssignment
 
@@ -130,17 +130,7 @@ class PtRepeatLoop(position: Position) : PtNode(position) {
 }
 
 
-class PtReturn(position: Position) : PtNode(position) {
-    val hasValue: Boolean
-        get() = children.any()
-    val value: PtExpression?
-        get() {
-            return if(children.any())
-                children.single() as PtExpression
-            else
-                null
-        }
-}
+class PtReturn(position: Position) : PtNode(position)  // children are all expressions
 
 
 sealed interface IPtVariable {
@@ -159,6 +149,18 @@ class PtVariable(
     position: Position
 ) : PtNamedNode(name, position), IPtVariable {
     init {
+
+        if(value!=null) {
+            require(value is PtArray || value is PtString) { "variable initializer value must only be array or string" }
+            // NOTE: the 6502 code generator expects numerical variables to not have an initialization value,
+            // because that is done via assignment statements. There are no "inline" variables with a given value.
+            // All variables are put into zeropage or into the BSS section and initialized afterwards during program
+            // startup or at the start of the subroutine.
+            // The IR codegen however is different it has a special section <VARIABLESWITHINIT> for all variables
+            // that have a non-zero initialization value, regardless of the datatype. It removes the initialization
+            // assignment and puts the value back into the variable (but only in the symboltable).
+        }
+
         value?.let {it.parent=this}
     }
 }
@@ -191,3 +193,6 @@ class PtWhenChoice(val isElse: Boolean, position: Position) : PtNode(position) {
 
 
 class PtDefer(position: Position): PtNode(position), IPtStatementContainer
+
+
+class PtJmpTable(position: Position) : PtNode(position)     // contains only PtIdentifier nodes

codeCore/src/prog8/code/core/BuiltinFunctions.kt

@@ -27,8 +27,6 @@ class FParam(val name: String, vararg val possibleDatatypes: BaseDataType)
 private val IterableDatatypes = arrayOf(BaseDataType.STR, BaseDataType.ARRAY, BaseDataType.ARRAY_SPLITW)
 private val IntegerDatatypes = arrayOf(BaseDataType.UBYTE, BaseDataType.BYTE, BaseDataType.UWORD, BaseDataType.WORD, BaseDataType.LONG)
 private val NumericDatatypes = arrayOf(BaseDataType.UBYTE, BaseDataType.BYTE, BaseDataType.UWORD, BaseDataType.WORD, BaseDataType.LONG, BaseDataType.FLOAT)
-private val ByteDatatypes = arrayOf(BaseDataType.UBYTE, BaseDataType.BYTE)
-private val ArrayDatatypes = arrayOf(BaseDataType.ARRAY, BaseDataType.ARRAY_SPLITW)
 
 
 class FSignature(val pure: Boolean,      // does it have side effects?
@@ -69,7 +67,7 @@ class FSignature(val pure: Boolean,      // does it have side effects?
                 }
                 CallConvention(listOf(paramConv), returns)
             }
-            actualParamTypes.size==2 && (actualParamTypes[0] in ByteDatatypes && actualParamTypes[1].isWord) -> {
+            actualParamTypes.size==2 && (actualParamTypes[0].isByte && actualParamTypes[1].isWord) -> {
                 TODO("opportunity to pass word+byte arguments in A,Y and X registers but not implemented yet")
             }
             actualParamTypes.size==2 && (actualParamTypes[0].isWord && actualParamTypes[1].isByte) -> {
@@ -98,11 +96,9 @@ val BuiltinFunctions: Map<String, FSignature> = mapOf(
     "prog8_lib_stringcompare"     to FSignature(true, BaseDataType.BYTE, FParam("str1", BaseDataType.STR), FParam("str2", BaseDataType.STR)),
     "prog8_lib_square_byte"       to FSignature(true, BaseDataType.UBYTE, FParam("value", BaseDataType.BYTE, BaseDataType.UBYTE)),
     "prog8_lib_square_word"       to FSignature(true, BaseDataType.UWORD, FParam("value", BaseDataType.WORD, BaseDataType.UWORD)),
-    "prog8_ifelse_bittest_set"    to FSignature(true, BaseDataType.BOOL, FParam("variable", *ByteDatatypes), FParam("bitnumber", BaseDataType.UBYTE)),
-    "prog8_ifelse_bittest_notset" to FSignature(true, BaseDataType.BOOL, FParam("variable", *ByteDatatypes), FParam("bitnumber", BaseDataType.UBYTE)),
     "abs"           to FSignature(true, null, FParam("value", *NumericDatatypes)),
-    "abs__byte"     to FSignature(true, BaseDataType.BYTE, FParam("value", BaseDataType.BYTE)),
-    "abs__word"     to FSignature(true, BaseDataType.WORD, FParam("value", BaseDataType.WORD)),
+    "abs__byte"     to FSignature(true, BaseDataType.UBYTE, FParam("value", BaseDataType.BYTE)),
+    "abs__word"     to FSignature(true, BaseDataType.UWORD, FParam("value", BaseDataType.WORD)),
     "abs__float"    to FSignature(true, BaseDataType.FLOAT, FParam("value", BaseDataType.FLOAT)),
     "len"           to FSignature(true, BaseDataType.UWORD, FParam("values", *IterableDatatypes)),
     "sizeof"        to FSignature(true, BaseDataType.UBYTE, FParam("object", *BaseDataType.entries.toTypedArray())),

codeCore/src/prog8/code/core/CompilationOptions.kt

@@ -34,7 +34,7 @@ class CompilationOptions(val output: OutputType,
                          var symbolDefs: Map<String, String> = emptyMap()
 ) {
     init {
-        compTarget.machine.initializeMemoryAreas(this)
+        compTarget.initializeMemoryAreas(this)
     }
 
     companion object {

codeCore/src/prog8/code/core/Enumerations.kt

@@ -23,6 +23,7 @@ enum class BaseDataType {
             this.isWord -> other.isByteOrBool
             this == LONG -> other.isByteOrBool || other.isWord
             this == STR && other == UWORD || this == UWORD && other == STR -> false
+            this.isArray && other.isArray -> false
             this.isArray -> other != FLOAT
             this == STR -> other != FLOAT
             else -> true
@@ -31,6 +32,7 @@ enum class BaseDataType {
     fun equalsSize(other: BaseDataType) =
         when {
             this == other -> true
+            this.isArray && other.isArray -> true
             this.isByteOrBool -> other.isByteOrBool
             this.isWord -> other.isWord
             this == STR && other== UWORD || this== UWORD && other== STR -> true
@@ -100,7 +102,7 @@ class DataType private constructor(val base: BaseDataType, val sub: BaseDataType
                 if(actualElementDt.isNumericOrBool && actualElementDt != BaseDataType.LONG)
                     DataType(BaseDataType.ARRAY, actualElementDt)
                 else
-                    throw NoSuchElementException("invalid element dt "+elementDt)
+                    throw NoSuchElementException("invalid element dt $elementDt")
             }
         }
     }
@@ -183,14 +185,8 @@ class DataType private constructor(val base: BaseDataType, val sub: BaseDataType
             BaseDataType.UNDEFINED -> false
         }
 
-    fun largerSizeThan(other: DataType): Boolean {
-        if(isArray) throw IllegalArgumentException("cannot compare size of array types")
-        return base.largerSizeThan(other.base)
-    }
-    fun equalsSize(other: DataType): Boolean {
-        if(isArray) throw IllegalArgumentException("cannot compare size of array types")
-        return base.equalsSize(other.base)
-    }
+    fun largerSizeThan(other: DataType): Boolean = base.largerSizeThan(other.base)
+    fun equalsSize(other: DataType): Boolean = base.equalsSize(other.base)
 
     val isUndefined = base == BaseDataType.UNDEFINED
     val isByte = base.isByte
@@ -321,7 +317,8 @@ val CpuRegisters = arrayOf(
 enum class OutputType {
     RAW,
     PRG,
-    XEX
+    XEX,
+    LIBRARY
 }
 
 enum class CbmPrgLauncherType {

codeCore/src/prog8/code/core/ICompilationTarget.kt

@@ -1,8 +1,42 @@
 package prog8.code.core
 
+import java.nio.file.Path
+
+enum class CpuType {
+    CPU6502,
+    CPU65C02,
+    VIRTUAL
+}
+
 interface ICompilationTarget: IStringEncoding, IMemSizer {
     val name: String
-    val machine: IMachineDefinition
+
+    val FLOAT_MAX_NEGATIVE: Double
+    val FLOAT_MAX_POSITIVE: Double
+    val FLOAT_MEM_SIZE: Int
+    val STARTUP_CODE_RESERVED_SIZE: UInt        // this is here, so that certain compiler targets are able to tune this
+    val PROGRAM_LOAD_ADDRESS : UInt
+    val PROGRAM_MEMTOP_ADDRESS: UInt
+    val BSSHIGHRAM_START: UInt
+    val BSSHIGHRAM_END: UInt
+    val BSSGOLDENRAM_START: UInt
+    val BSSGOLDENRAM_END: UInt
+
+    val cpu: CpuType
+    var zeropage: Zeropage
+    var golden: GoldenRam
+    val libraryPath: Path?
+    val customLauncher: List<String>
+    val additionalAssemblerOptions: String?
+
+    fun initializeMemoryAreas(compilerOptions: CompilationOptions)
+    fun getFloatAsmBytes(num: Number): String
+
+    fun convertFloatToBytes(num: Double): List<UByte>
+    fun convertBytesToFloat(bytes: List<UByte>): Double
+
+    fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path)
+    fun isIOAddress(address: UInt): Boolean
 
     override fun encodeString(str: String, encoding: Encoding): List<UByte>
     override fun decodeString(bytes: Iterable<UByte>, encoding: Encoding): String

codeCore/src/prog8/code/core/IMachineDefinition.kt

@@ -1,36 +0,0 @@
-package prog8.code.core
-
-import java.nio.file.Path
-
-
-enum class CpuType {
-    CPU6502,
-    CPU65c02,
-    VIRTUAL
-}
-
-interface IMachineDefinition {
-    val FLOAT_MAX_NEGATIVE: Double
-    val FLOAT_MAX_POSITIVE: Double
-    val FLOAT_MEM_SIZE: Int
-    val STARTUP_CODE_RESERVED_SIZE: UInt        // this is here, so that certain compiler targets are able to tune this
-    val PROGRAM_LOAD_ADDRESS : UInt
-    val PROGRAM_MEMTOP_ADDRESS: UInt
-    val BSSHIGHRAM_START: UInt
-    val BSSHIGHRAM_END: UInt
-    val BSSGOLDENRAM_START: UInt
-    val BSSGOLDENRAM_END: UInt
-
-    val cpu: CpuType
-    var zeropage: Zeropage
-    var golden: GoldenRam
-
-    fun initializeMemoryAreas(compilerOptions: CompilationOptions)
-    fun getFloatAsmBytes(num: Number): String
-
-    fun convertFloatToBytes(num: Double): List<UByte>
-    fun convertBytesToFloat(bytes: List<UByte>): Double
-
-    fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path)
-    fun isIOAddress(address: UInt): Boolean
-}

codeCore/src/prog8/code/core/IStringEncoding.kt

@@ -9,7 +9,8 @@ enum class Encoding(val prefix: String) {
     ISO5("iso5"),               // cx16  (iso-8859-5, cyrillic)
     ISO16("iso16"),             // cx16  (iso-8859-16, eastern european)
     CP437("cp437"),             // cx16  (ibm pc, codepage 437)
-    KATAKANA("kata")                 // cx16  (katakana)
+    KATAKANA("kata"),           // cx16  (katakana)
+    C64OS("c64os")              // c64 (C64 OS)
 }
 
 interface IStringEncoding {

codeCore/src/prog8/code/core/MemoryRegions.kt

@@ -22,7 +22,7 @@ abstract class MemoryAllocator(protected val options: CompilationOptions) {
 abstract class Zeropage(options: CompilationOptions): MemoryAllocator(options) {
 
     abstract val SCRATCH_B1 : UInt      // temp storage for a single byte
-    abstract val SCRATCH_REG : UInt     // temp storage for a register, must be B1+1
+    abstract val SCRATCH_REG : UInt     // temp storage for a register byte, must be B1+1
     abstract val SCRATCH_W1 : UInt      // temp storage 1 for a word  $fb+$fc
     abstract val SCRATCH_W2 : UInt      // temp storage 2 for a word  $fb+$fc
 
@@ -133,8 +133,6 @@ abstract class Zeropage(options: CompilationOptions): MemoryAllocator(options) {
         require(size>0)
         return free.containsAll((address until address+size.toUInt()).toList())
     }
-
-    abstract fun allocateCx16VirtualRegisters()
 }
 
 

codeCore/src/prog8/code/optimize/Optimizer.kt

@@ -4,15 +4,14 @@ import prog8.code.StExtSub
 import prog8.code.SymbolTable
 import prog8.code.ast.*
 import prog8.code.core.*
+import prog8.code.target.VMTarget
 
 
-fun optimizeIntermediateAst(program: PtProgram, options: CompilationOptions, st: SymbolTable, errors: IErrorReporter) {
+fun optimizeSimplifiedAst(program: PtProgram, options: CompilationOptions, st: SymbolTable, errors: IErrorReporter) {
     if (!options.optimize)
         return
     while (errors.noErrors() &&
-            (optimizeBitTest(program, options)
-            + optimizeAssignTargets(program, st)) > 0
-    ) {
+        optimizeAssignTargets(program, st) + optimizeWordPlusTimesTwo(program, options) > 0) {
         // keep rolling
     }
 }
@@ -74,85 +73,6 @@ private fun optimizeAssignTargets(program: PtProgram, st: SymbolTable): Int {
 }
 
 
-private fun optimizeBitTest(program: PtProgram, options: CompilationOptions): Int {
-    if(options.compTarget.machine.cpu == CpuType.VIRTUAL)
-        return 0        // the special bittest optimization is not yet valid for the IR
-
-    fun makeBittestCall(condition: PtBinaryExpression, and: PtBinaryExpression, variable: PtIdentifier, bitmask: Int): PtBuiltinFunctionCall {
-        require(bitmask==128 || bitmask==64)
-        val setOrNot = if(condition.operator=="!=") "set" else "notset"
-        val bittestCall = PtBuiltinFunctionCall("prog8_ifelse_bittest_$setOrNot", false, true, DataType.forDt(BaseDataType.BOOL), condition.position)
-        bittestCall.add(variable)
-        if(bitmask==128)
-            bittestCall.add(PtNumber(BaseDataType.UBYTE, 7.0, and.right.position))
-        else
-            bittestCall.add(PtNumber(BaseDataType.UBYTE, 6.0, and.right.position))
-        return bittestCall
-    }
-
-    fun isAndByteConditionForBRK(condition: PtBinaryExpression?): Triple<PtBinaryExpression, PtIdentifier, Int>? {
-        if(condition!=null && (condition.operator=="==" || condition.operator=="!=")) {
-            if (condition.right.asConstInteger() == 0) {
-                val and = condition.left as? PtBinaryExpression
-                if (and != null && and.operator == "&" && and.type.isUnsignedByte) {
-                    val bitmask = and.right.asConstInteger()
-                    if(bitmask==128 || bitmask==64) {
-                        val variable = and.left as? PtIdentifier
-                        if (variable != null && variable.type.isByte) {
-                            return Triple(and, variable, bitmask)
-                        }
-                        val typecast = and.left as? PtTypeCast
-                        if (typecast != null && typecast.type.isUnsignedByte) {
-                            val castedVariable = typecast.value as? PtIdentifier
-                            if(castedVariable!=null && castedVariable.type.isByte)
-                                return Triple(and, castedVariable, bitmask)
-                        }
-                    }
-                }
-            }
-        }
-        return null
-    }
-
-    var changes = 0
-    var recurse = true
-    walkAst(program) { node: PtNode, depth: Int ->
-        if(node is PtIfElse) {
-            val condition = node.condition as? PtBinaryExpression
-            val check = isAndByteConditionForBRK(condition)
-            if(check!=null) {
-                val (and, variable, bitmask) = check
-                val bittestCall = makeBittestCall(condition!!, and, variable, bitmask)
-                val ifElse = PtIfElse(node.position)
-                ifElse.add(bittestCall)
-                ifElse.add(node.ifScope)
-                if (node.hasElse())
-                    ifElse.add(node.elseScope)
-                val index = node.parent.children.indexOf(node)
-                node.parent.children[index] = ifElse
-                ifElse.parent = node.parent
-                changes++
-                recurse = false
-            }
-        }
-        if (node is PtIfExpression) {
-            val condition = node.condition as? PtBinaryExpression
-            val check = isAndByteConditionForBRK(condition)
-            if(check!=null) {
-                val (and, variable, bitmask) = check
-                val bittestCall = makeBittestCall(condition!!, and, variable, bitmask)
-                node.children[0] = bittestCall
-                bittestCall.parent = node
-                changes++
-                recurse = false
-            }
-        }
-        recurse
-    }
-    return changes
-}
-
-
 internal fun isSame(identifier: PtIdentifier, type: DataType, returnedRegister: RegisterOrPair): Boolean {
     if(returnedRegister in Cx16VirtualRegisters) {
         val regname = returnedRegister.name.lowercase()
@@ -178,3 +98,42 @@ internal fun isSame(identifier: PtIdentifier, type: DataType, returnedRegister:
     }
     return false   // there are no identifiers directly corresponding to cpu registers
 }
+
+
+private fun optimizeWordPlusTimesTwo(program: PtProgram, options: CompilationOptions): Int {
+    if(options.compTarget.name== VMTarget.NAME)
+        return 0
+    var changes = 0
+    walkAst(program) { node: PtNode, depth: Int ->
+        if (node is PtBinaryExpression) {
+            if(node.operator=="*" && node.right.type.isWord && node.right.asConstValue()==2.0) {
+                TODO("optimize word + byte*2 (usually already replaced by w+b<<2)")
+            }
+            else if(node.operator=="<<" && node.right.asConstValue()==1.0) {
+                val typecast=node.left as? PtTypeCast
+                if(typecast!=null && typecast.type.isWord && typecast.value is PtIdentifier) {
+                    val addition = node.parent as? PtBinaryExpression
+                    if(addition!=null && (addition.operator=="+" || addition.operator=="-") && addition.type.isWord) {
+                        // word + (byte<<1 as uword) (== word + byte*2)  -->  (word + (byte as word)) + (byte as word)
+                        val parent = addition.parent
+                        val index = parent.children.indexOf(addition)
+                        val addFirst = PtBinaryExpression(addition.operator, addition.type, addition.position)
+                        val addSecond = PtBinaryExpression(addition.operator, addition.type, addition.position)
+                        if(addition.left===node)
+                            addFirst.add(addition.right)
+                        else
+                            addFirst.add(addition.left)
+                        addFirst.add(typecast)
+                        addSecond.add(addFirst)
+                        addSecond.add(typecast.copy())
+                        parent.children[index] = addSecond
+                        addSecond.parent = parent
+                        changes++
+                    }
+                }
+            }
+        }
+        true
+    }
+    return changes
+}

codeCore/src/prog8/code/source/ImportFileSystem.kt

@@ -21,12 +21,12 @@ object ImportFileSystem {
 
     fun expandTilde(path: Path): Path = Path(expandTilde(path.toString()))
 
-    fun getFile(path: Path): SourceCode {
+    fun getFile(path: Path, isLibrary: Boolean=false): SourceCode {
         val normalized = path.absolute().normalize()
         val cached = cache[normalized.toString()]
         if (cached != null)
             return cached
-        val file = SourceCode.File(normalized)
+        val file = SourceCode.File(normalized, isLibrary)
         cache[normalized.toString()] = file
         return file
     }

codeCore/src/prog8/code/source/SourceCode.kt

@@ -22,6 +22,11 @@ sealed class SourceCode {
      */
     abstract val isFromFilesystem: Boolean
 
+    /**
+     * Whether this [SourceCode] instance was created from a library module file
+     */
+    abstract val isFromLibrary: Boolean
+
     /**
      * The logical name of the source code unit. Usually the module's name.
      */
@@ -76,6 +81,7 @@ sealed class SourceCode {
         override val text = origText.replace("\\R".toRegex(), "\n")      // normalize line endings
         override val isFromResources = false
         override val isFromFilesystem = false
+        override val isFromLibrary = false
         override val origin = "$STRINGSOURCEPREFIX${System.identityHashCode(text).toString(16)}"
         override val name = "<unnamed-text>"
     }
@@ -89,7 +95,7 @@ sealed class SourceCode {
      * @throws NoSuchFileException if the file does not exist
      * @throws FileSystemException if the file cannot be read
      */
-    internal class File(path: Path): SourceCode() {
+    internal class File(path: Path, override val isFromLibrary: Boolean): SourceCode() {
         override val text: String
         override val origin: String
         override val name: String
@@ -120,6 +126,7 @@ sealed class SourceCode {
 
         override val isFromResources = true
         override val isFromFilesystem = false
+        override val isFromLibrary = true
         override val origin = "$LIBRARYFILEPREFIX$normalized"
         override val text: String
         override val name: String
@@ -146,6 +153,7 @@ sealed class SourceCode {
     class Generated(override val name: String) : SourceCode() {
         override val isFromResources: Boolean = false
         override val isFromFilesystem: Boolean = false
+        override val isFromLibrary: Boolean = false
         override val origin: String = name
         override val text: String = "<generated code node, no text representation>"
     }

codeCore/src/prog8/code/target/AtariTarget.kt

@@ -1,40 +0,0 @@
-package prog8.code.target
-
-import prog8.code.core.*
-import prog8.code.target.atari.AtariMachineDefinition
-
-
-class AtariTarget: ICompilationTarget, IStringEncoding by Encoder, IMemSizer {
-    override val name = NAME
-    override val machine = AtariMachineDefinition()
-    override val defaultEncoding = Encoding.ATASCII
-
-    companion object {
-        const val NAME = "atari"
-    }
-
-    override fun memorySize(dt: DataType, numElements: Int?): Int {
-        if(dt.isArray) {
-            if(numElements==null) return 2      // treat it as a pointer size
-            return when(dt.sub) {
-                BaseDataType.BOOL, BaseDataType.UBYTE, BaseDataType.BYTE -> numElements
-                BaseDataType.UWORD, BaseDataType.WORD, BaseDataType.STR -> numElements * 2
-                BaseDataType.FLOAT-> numElements * machine.FLOAT_MEM_SIZE
-                BaseDataType.UNDEFINED -> throw IllegalArgumentException("undefined has no memory size")
-                else -> throw IllegalArgumentException("invalid sub type")
-            }
-        }
-        else if (dt.isString) {
-            if(numElements!=null) return numElements        // treat it as the size of the given string with the length
-            else return 2    // treat it as the size to store a string pointer
-        }
-
-        return when {
-            dt.isByteOrBool -> 1 * (numElements ?: 1)
-            dt.isFloat -> machine.FLOAT_MEM_SIZE * (numElements ?: 1)
-            dt.isLong -> throw IllegalArgumentException("long can not yet be put into memory")
-            dt.isUndefined -> throw IllegalArgumentException("undefined has no memory size")
-            else -> 2 * (numElements ?: 1)
-        }
-    }
-}

codeCore/src/prog8/code/target/C128Target.kt

@@ -1,19 +1,73 @@
 package prog8.code.target
 
-import prog8.code.core.Encoding
-import prog8.code.core.ICompilationTarget
-import prog8.code.core.IMemSizer
-import prog8.code.core.IStringEncoding
-import prog8.code.target.c128.C128MachineDefinition
-import prog8.code.target.cbm.CbmMemorySizer
+import prog8.code.core.*
+import prog8.code.target.encodings.Encoder
+import prog8.code.target.zp.C128Zeropage
+import java.nio.file.Path
 
 
-class C128Target: ICompilationTarget, IStringEncoding by Encoder, IMemSizer by CbmMemorySizer {
+class C128Target: ICompilationTarget, IStringEncoding by Encoder, IMemSizer by NormalMemSizer(Mflpt5.FLOAT_MEM_SIZE) {
     override val name = NAME
-    override val machine = C128MachineDefinition()
     override val defaultEncoding = Encoding.PETSCII
+    override val libraryPath = null
+    override val customLauncher: List<String> = emptyList()
+    override val additionalAssemblerOptions = null
 
     companion object {
         const val NAME = "c128"
     }
+
+
+    override val cpu = CpuType.CPU6502
+
+    override val FLOAT_MAX_POSITIVE = Mflpt5.FLOAT_MAX_POSITIVE
+    override val FLOAT_MAX_NEGATIVE = Mflpt5.FLOAT_MAX_NEGATIVE
+    override val FLOAT_MEM_SIZE = Mflpt5.FLOAT_MEM_SIZE
+    override val STARTUP_CODE_RESERVED_SIZE = 20u
+    override val PROGRAM_LOAD_ADDRESS = 0x1c01u
+    override val PROGRAM_MEMTOP_ADDRESS = 0xc000u
+
+    override val BSSHIGHRAM_START = 0u    // TODO
+    override val BSSHIGHRAM_END = 0u      // TODO
+    override val BSSGOLDENRAM_START = 0u  // TODO
+    override val BSSGOLDENRAM_END = 0u    // TODO
+
+    override lateinit var zeropage: Zeropage
+    override lateinit var golden: GoldenRam
+
+    override fun getFloatAsmBytes(num: Number) = Mflpt5.fromNumber(num).makeFloatFillAsm()
+
+    override fun convertFloatToBytes(num: Double): List<UByte> {
+        val m5 = Mflpt5.fromNumber(num)
+        return listOf(m5.b0, m5.b1, m5.b2, m5.b3, m5.b4)
+    }
+
+    override fun convertBytesToFloat(bytes: List<UByte>): Double {
+        require(bytes.size==5) { "need 5 bytes" }
+        val m5 = Mflpt5(bytes[0], bytes[1], bytes[2], bytes[3], bytes[4])
+        return m5.toDouble()
+    }
+
+    override fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path) {
+        if(selectedEmulator!=1) {
+            System.err.println("The c128 target only supports the main emulator (Vice).")
+            return
+        }
+
+        println("\nStarting C-128 emulator x128...")
+        val viceMonlist = C64Target.viceMonListName(programNameWithPath.toString())
+        val cmdline = listOf("x128", "-silent", "-moncommands", viceMonlist,
+            "-autostartprgmode", "1", "-autostart-warp", "-autostart", "${programNameWithPath}.prg")
+        val processb = ProcessBuilder(cmdline).inheritIO()
+        val process: Process = processb.start()
+        process.waitFor()
+    }
+
+    override fun isIOAddress(address: UInt): Boolean = address==0u || address==1u || address in 0xd000u..0xdfffu
+
+    override fun initializeMemoryAreas(compilerOptions: CompilationOptions) {
+        zeropage = C128Zeropage(compilerOptions)
+        golden = GoldenRam(compilerOptions, UIntRange.EMPTY)    // TODO does the c128 have some of this somewhere?
+    }
+
 }

codeCore/src/prog8/code/target/C64Target.kt

@@ -1,23 +1,87 @@
 package prog8.code.target
 
-import prog8.code.core.Encoding
-import prog8.code.core.ICompilationTarget
-import prog8.code.core.IMemSizer
-import prog8.code.core.IStringEncoding
-import prog8.code.target.c64.C64MachineDefinition
-import prog8.code.target.cbm.CbmMemorySizer
+import prog8.code.core.*
+import prog8.code.target.encodings.Encoder
+import prog8.code.target.zp.C64Zeropage
+import java.io.IOException
+import java.nio.file.Path
 
 
-class C64Target: ICompilationTarget, IStringEncoding by Encoder, IMemSizer by CbmMemorySizer {
+class C64Target: ICompilationTarget, IStringEncoding by Encoder, IMemSizer by NormalMemSizer(Mflpt5.Companion.FLOAT_MEM_SIZE) {
     override val name = NAME
-    override val machine = C64MachineDefinition()
     override val defaultEncoding = Encoding.PETSCII
+    override val libraryPath = null
+    override val customLauncher: List<String> = emptyList()
+    override val additionalAssemblerOptions = null
 
     companion object {
         const val NAME = "c64"
 
         fun viceMonListName(baseFilename: String) = "$baseFilename.vice-mon-list"
     }
+
+
+    override val cpu = CpuType.CPU6502
+
+    override val FLOAT_MAX_POSITIVE = Mflpt5.FLOAT_MAX_POSITIVE
+    override val FLOAT_MAX_NEGATIVE = Mflpt5.FLOAT_MAX_NEGATIVE
+    override val FLOAT_MEM_SIZE = Mflpt5.FLOAT_MEM_SIZE
+    override val STARTUP_CODE_RESERVED_SIZE = 20u
+    override val PROGRAM_LOAD_ADDRESS = 0x0801u
+    override val PROGRAM_MEMTOP_ADDRESS = 0xcfe0u      // $a000  if floats are used
+    // note that at $cfe0-$cfff are the 16 'virtual registers' R0-R15
+
+    override val BSSHIGHRAM_START = 0xc000u
+    override val BSSHIGHRAM_END = 0xcfdfu
+    override val BSSGOLDENRAM_START = 0u        // no golden ram on C64
+    override val BSSGOLDENRAM_END = 0u
+
+    override lateinit var zeropage: Zeropage
+    override lateinit var golden: GoldenRam
+
+    override fun getFloatAsmBytes(num: Number) = Mflpt5.fromNumber(num).makeFloatFillAsm()
+
+    override fun convertFloatToBytes(num: Double): List<UByte> {
+        val m5 = Mflpt5.fromNumber(num)
+        return listOf(m5.b0, m5.b1, m5.b2, m5.b3, m5.b4)
+    }
+
+    override fun convertBytesToFloat(bytes: List<UByte>): Double {
+        require(bytes.size==5) { "need 5 bytes" }
+        val m5 = Mflpt5(bytes[0], bytes[1], bytes[2], bytes[3], bytes[4])
+        return m5.toDouble()
+    }
+
+    override fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path) {
+        if(selectedEmulator!=1) {
+            System.err.println("The c64 target only supports the main emulator (Vice).")
+            return
+        }
+
+        for(emulator in listOf("x64sc", "x64")) {
+            println("\nStarting C-64 emulator $emulator...")
+            val viceMonlist = viceMonListName(programNameWithPath.toString())
+            val cmdline = listOf(emulator, "-silent", "-moncommands", viceMonlist,
+                "-autostartprgmode", "1", "-autostart-warp", "-autostart", "${programNameWithPath}.prg")
+            val processb = ProcessBuilder(cmdline).inheritIO()
+            val process: Process
+            try {
+                process=processb.start()
+            } catch(_: IOException) {
+                continue  // try the next emulator executable
+            }
+            process.waitFor()
+            break
+        }
+    }
+
+    override fun isIOAddress(address: UInt): Boolean = address==0u || address==1u || address in 0xd000u..0xdfffu
+
+    override fun initializeMemoryAreas(compilerOptions: CompilationOptions) {
+        zeropage = C64Zeropage(compilerOptions)
+        golden = GoldenRam(compilerOptions, UIntRange.EMPTY)
+    }
+
 }
 
 
@@ -26,8 +90,6 @@ val CompilationTargets = listOf(
     C128Target.NAME,
     Cx16Target.NAME,
     PETTarget.NAME,
-    AtariTarget.NAME,
-    Neo6502Target.NAME,
     VMTarget.NAME
 )
 
@@ -36,8 +98,6 @@ fun getCompilationTargetByName(name: String) = when(name.lowercase()) {
     C128Target.NAME -> C128Target()
     Cx16Target.NAME -> Cx16Target()
     PETTarget.NAME -> PETTarget()
-    AtariTarget.NAME -> AtariTarget()
     VMTarget.NAME -> VMTarget()
-    Neo6502Target.NAME -> Neo6502Target()
     else -> throw IllegalArgumentException("invalid compilation target")
 }

codeCore/src/prog8/code/target/ConfigFileTarget.kt

@@ -0,0 +1,168 @@
+package prog8.code.target
+
+import prog8.code.core.*
+import prog8.code.source.ImportFileSystem.expandTilde
+import prog8.code.target.encodings.Encoder
+import prog8.code.target.zp.ConfigurableZeropage
+import java.io.IOException
+import java.nio.file.Path
+import java.util.*
+import kotlin.io.path.Path
+import kotlin.io.path.inputStream
+import kotlin.io.path.isDirectory
+import kotlin.io.path.nameWithoutExtension
+
+
+class ConfigFileTarget(
+    override val name: String,
+    override val defaultEncoding: Encoding,
+    override val cpu: CpuType,
+    override val PROGRAM_LOAD_ADDRESS: UInt,
+    override val PROGRAM_MEMTOP_ADDRESS: UInt,
+    override val STARTUP_CODE_RESERVED_SIZE: UInt,
+    override val BSSHIGHRAM_START: UInt,
+    override val BSSHIGHRAM_END: UInt,
+    override val BSSGOLDENRAM_START: UInt,
+    override val BSSGOLDENRAM_END: UInt,
+    override val libraryPath: Path,
+    override val customLauncher: List<String>,
+    override val additionalAssemblerOptions: String?,
+    val ioAddresses: List<UIntRange>,
+    val zpScratchB1: UInt,
+    val zpScratchReg: UInt,
+    val zpScratchW1: UInt,
+    val zpScratchW2: UInt,
+    val virtualregistersStart: UInt,
+    val zpFullsafe: List<UIntRange>,
+    val zpKernalsafe: List<UIntRange>,
+    val zpBasicsafe: List<UIntRange>
+): ICompilationTarget, IStringEncoding by Encoder, IMemSizer by NormalMemSizer(8) {
+
+    companion object {
+
+        private fun Properties.getString(property: String): String {
+            val value = this.getProperty(property, null)
+            if(value!=null)
+                return value
+            throw NoSuchElementException("string property '$property' not found in config file")
+        }
+
+        private fun Properties.getInteger(property: String): UInt {
+            val value = this.getProperty(property, null)
+            if(value!=null) return parseInt(value)
+            throw NoSuchElementException("integer property '$property' not found in config file")
+        }
+
+        private fun parseInt(value: String): UInt {
+            if(value.startsWith("0x"))
+                return value.drop(2).toUInt(16)
+            if(value.startsWith("$"))
+                return value.drop(1).toUInt(16)
+            if(value.startsWith("%"))
+                return value.drop(1).toUInt(2)
+            return value.toUInt()
+        }
+
+        private fun parseAddressRanges(key: String, props: Properties): List<UIntRange> {
+            val rangesStr = props.getString(key)
+            if(rangesStr.isBlank())
+                return emptyList()
+            val result = mutableListOf<UIntRange>()
+            val ranges = rangesStr.split(",").map { it.trim() }
+            for(r in ranges) {
+                if ('-' in r) {
+                    val (fromStr, toStr) = r.split("-")
+                    val from = parseInt(fromStr.trim())
+                    val to = parseInt(toStr.trim())
+                    result.add(from..to)
+                } else {
+                    val address = parseInt(r)
+                    result.add(address..address)
+                }
+            }
+            return result
+        }
+
+        fun fromConfigFile(configfile: Path): ConfigFileTarget {
+            val props = Properties()
+            props.load(configfile.inputStream())
+
+            val cpuString = props.getString("cpu").uppercase()
+            val cpuType = try {
+                CpuType.valueOf(cpuString)
+            } catch (_: IllegalArgumentException) {
+                CpuType.valueOf("CPU$cpuString")
+            }
+            val ioAddresses = parseAddressRanges("io_regions", props)
+            val zpFullsafe = parseAddressRanges("zp_fullsafe", props)
+            val zpKernalsafe = parseAddressRanges("zp_kernalsafe", props)
+            val zpBasicsafe = parseAddressRanges("zp_basicsafe", props)
+
+            val libraryPath = expandTilde(Path(props.getString("library")))
+            if(!libraryPath.isDirectory())
+                throw IOException("invalid library path: $libraryPath")
+
+            val customLauncherStr = props.getProperty("custom_launcher_code", null)
+            val customLauncher =
+                if(customLauncherStr?.isNotBlank()==true)
+                    (customLauncherStr+"\n").lines().map { it.trimEnd() }
+                else emptyList()
+            val assemblerOptionsStr = props.getProperty("assembler_options", "").trim()
+            val assemblerOptions = if(assemblerOptionsStr.isBlank()) null else assemblerOptionsStr
+
+            return ConfigFileTarget(
+                configfile.nameWithoutExtension,
+                Encoding.entries.first { it.prefix==props.getString("encoding") },
+                cpuType,
+                props.getInteger("load_address"),
+                props.getInteger("memtop"),
+                0u,         // used only in a very specific error condition check in a certain scenario...
+                props.getInteger("bss_highram_start"),
+                props.getInteger("bss_highram_end"),
+                props.getInteger("bss_goldenram_start"),
+                props.getInteger("bss_goldenram_end"),
+                libraryPath,
+                customLauncher,
+                assemblerOptions,
+                ioAddresses,
+                props.getInteger("zp_scratch_b1"),
+                props.getInteger("zp_scratch_reg"),
+                props.getInteger("zp_scratch_w1"),
+                props.getInteger("zp_scratch_w2"),
+                props.getInteger("virtual_registers"),
+                zpFullsafe,
+                zpKernalsafe,
+                zpBasicsafe,
+            )
+        }
+    }
+
+    // TODO floats are not yet supported here, just enter some values
+    override val FLOAT_MAX_POSITIVE = 9.999999999e97
+    override val FLOAT_MAX_NEGATIVE = -9.999999999e97
+    override val FLOAT_MEM_SIZE = 8
+
+    override lateinit var zeropage: Zeropage
+    override lateinit var golden: GoldenRam     // TODO this is not yet used
+
+    override fun getFloatAsmBytes(num: Number) = TODO("floats")
+    override fun convertFloatToBytes(num: Double): List<UByte> = TODO("floats")
+    override fun convertBytesToFloat(bytes: List<UByte>): Double = TODO("floats")
+    override fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path) {
+        throw IllegalArgumentException("Custom compiler target cannot automatically launch an emulator. Do this manually.")
+    }
+
+    override fun isIOAddress(address: UInt): Boolean = ioAddresses.any { address in it }
+
+    override fun initializeMemoryAreas(compilerOptions: CompilationOptions) {
+        zeropage = ConfigurableZeropage(
+            zpScratchB1, zpScratchReg, zpScratchW1, zpScratchW2,
+            virtualregistersStart,
+            zpBasicsafe,
+            zpKernalsafe,
+            zpFullsafe,
+            compilerOptions
+        )
+        // note: there's no golden ram yet
+    }
+}

codeCore/src/prog8/code/target/Cx16Target.kt

@@ -1,19 +1,86 @@
 package prog8.code.target
 
-import prog8.code.core.Encoding
-import prog8.code.core.ICompilationTarget
-import prog8.code.core.IMemSizer
-import prog8.code.core.IStringEncoding
-import prog8.code.target.cbm.CbmMemorySizer
-import prog8.code.target.cx16.CX16MachineDefinition
+import prog8.code.core.*
+import prog8.code.target.encodings.Encoder
+import prog8.code.target.zp.CX16Zeropage
+import java.nio.file.Path
 
 
-class Cx16Target: ICompilationTarget, IStringEncoding by Encoder, IMemSizer by CbmMemorySizer {
+class Cx16Target: ICompilationTarget, IStringEncoding by Encoder, IMemSizer by NormalMemSizer(Mflpt5.Companion.FLOAT_MEM_SIZE) {
     override val name = NAME
-    override val machine = CX16MachineDefinition()
     override val defaultEncoding = Encoding.PETSCII
+    override val libraryPath = null
+    override val customLauncher: List<String> = emptyList()
+    override val additionalAssemblerOptions = null
 
     companion object {
         const val NAME = "cx16"
     }
+
+
+    override val cpu = CpuType.CPU65C02
+
+    override val FLOAT_MAX_POSITIVE = Mflpt5.FLOAT_MAX_POSITIVE
+    override val FLOAT_MAX_NEGATIVE = Mflpt5.FLOAT_MAX_NEGATIVE
+    override val FLOAT_MEM_SIZE = Mflpt5.FLOAT_MEM_SIZE
+    override val STARTUP_CODE_RESERVED_SIZE = 20u
+    override val PROGRAM_LOAD_ADDRESS = 0x0801u
+    override val PROGRAM_MEMTOP_ADDRESS = 0x9f00u
+
+    override val BSSHIGHRAM_START = 0xa000u     // hiram bank 1, 8Kb, assumed to be active
+    override val BSSHIGHRAM_END = 0xbfffu       // Rom starts at $c000
+    override val BSSGOLDENRAM_START = 0x0400u
+    override val BSSGOLDENRAM_END = 0x07ffu
+
+    override lateinit var zeropage: Zeropage
+    override lateinit var golden: GoldenRam
+
+    override fun getFloatAsmBytes(num: Number) = Mflpt5.fromNumber(num).makeFloatFillAsm()
+
+    override fun convertFloatToBytes(num: Double): List<UByte> {
+        val m5 = Mflpt5.fromNumber(num)
+        return listOf(m5.b0, m5.b1, m5.b2, m5.b3, m5.b4)
+    }
+
+    override fun convertBytesToFloat(bytes: List<UByte>): Double {
+        require(bytes.size==5) { "need 5 bytes" }
+        val m5 = Mflpt5(bytes[0], bytes[1], bytes[2], bytes[3], bytes[4])
+        return m5.toDouble()
+    }
+
+    override fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path) {
+        val emulator: String
+        val extraArgs: List<String>
+
+        when(selectedEmulator) {
+            1 -> {
+                emulator = "x16emu"
+                extraArgs = listOf("-debug")
+            }
+            2 -> {
+                emulator = "box16"
+                extraArgs = listOf("-sym", C64Target.viceMonListName(programNameWithPath.toString()))
+            }
+            else -> {
+                System.err.println("Cx16 target only supports x16emu and box16 emulators.")
+                return
+            }
+        }
+
+        println("\nStarting Commander X16 emulator $emulator...")
+        val cmdline = listOf(emulator, "-scale", "2", "-rtc", "-run", "-prg", "${programNameWithPath}.prg") + extraArgs
+        val processb = ProcessBuilder(cmdline).inheritIO()
+        processb.environment()["PULSE_LATENCY_MSEC"] = "10"
+        val process: Process = processb.start()
+        process.waitFor()
+    }
+
+    override fun isIOAddress(address: UInt): Boolean = address==0u || address==1u || address in 0x9f00u..0x9fffu
+
+    override fun initializeMemoryAreas(compilerOptions: CompilationOptions) {
+        zeropage = CX16Zeropage(compilerOptions)
+        golden = GoldenRam(compilerOptions, BSSGOLDENRAM_START..BSSGOLDENRAM_END)
+    }
+
+
 }

codeCore/src/prog8/code/target/Mflpt5.kt

@@ -1,10 +1,9 @@
-package prog8.code.target.cbm
+package prog8.code.target
 
 import prog8.code.core.InternalCompilerException
 import kotlin.math.absoluteValue
 import kotlin.math.pow
 
-
 data class Mflpt5(val b0: UByte, val b1: UByte, val b2: UByte, val b3: UByte, val b4: UByte) {
 
     companion object {

codeCore/src/prog8/code/target/Neo6502Target.kt

@@ -1,40 +0,0 @@
-package prog8.code.target
-
-import prog8.code.core.*
-import prog8.code.target.neo6502.Neo6502MachineDefinition
-
-
-class Neo6502Target: ICompilationTarget, IStringEncoding by Encoder, IMemSizer {
-    override val name = NAME
-    override val machine = Neo6502MachineDefinition()
-    override val defaultEncoding = Encoding.ISO
-
-    companion object {
-        const val NAME = "neo"
-    }
-
-    override fun memorySize(dt: DataType, numElements: Int?): Int {
-        if(dt.isArray) {
-            if(numElements==null) return 2      // treat it as a pointer size
-            return when(dt.sub) {
-                BaseDataType.BOOL, BaseDataType.UBYTE, BaseDataType.BYTE -> numElements
-                BaseDataType.UWORD, BaseDataType.WORD, BaseDataType.STR -> numElements * 2
-                BaseDataType.FLOAT-> numElements * machine.FLOAT_MEM_SIZE
-                BaseDataType.UNDEFINED -> throw IllegalArgumentException("undefined has no memory size")
-                else -> throw IllegalArgumentException("invalid sub type")
-            }
-        }
-        else if (dt.isString) {
-            if(numElements!=null) return numElements        // treat it as the size of the given string with the length
-            else return 2    // treat it as the size to store a string pointer
-        }
-
-        return when {
-            dt.isByteOrBool -> 1 * (numElements ?: 1)
-            dt.isFloat -> machine.FLOAT_MEM_SIZE * (numElements ?: 1)
-            dt.isLong -> throw IllegalArgumentException("long can not yet be put into memory")
-            dt.isUndefined -> throw IllegalArgumentException("undefined has no memory size")
-            else -> 2 * (numElements ?: 1)
-        }
-    }
-}

codeCore/src/prog8/code/target/NormalMemSizer.kt

@@ -1,18 +1,18 @@
-package prog8.code.target.cbm
+package prog8.code.target
 
 import prog8.code.core.BaseDataType
 import prog8.code.core.DataType
 import prog8.code.core.IMemSizer
 
+internal class NormalMemSizer(val floatsize: Int): IMemSizer {
 
-internal object CbmMemorySizer: IMemSizer {
     override fun memorySize(dt: DataType, numElements: Int?): Int {
         if(dt.isArray) {
             if(numElements==null) return 2      // treat it as a pointer size
             return when(dt.sub) {
                 BaseDataType.BOOL, BaseDataType.UBYTE, BaseDataType.BYTE -> numElements
                 BaseDataType.UWORD, BaseDataType.WORD, BaseDataType.STR -> numElements * 2
-                BaseDataType.FLOAT-> numElements * Mflpt5.FLOAT_MEM_SIZE
+                BaseDataType.FLOAT-> numElements * floatsize
                 BaseDataType.UNDEFINED -> throw IllegalArgumentException("undefined has no memory size")
                 else -> throw IllegalArgumentException("invalid sub type")
             }
@@ -24,10 +24,11 @@ internal object CbmMemorySizer: IMemSizer {
 
         return when {
             dt.isByteOrBool -> 1 * (numElements ?: 1)
-            dt.isFloat -> Mflpt5.FLOAT_MEM_SIZE * (numElements ?: 1)
+            dt.isFloat -> floatsize * (numElements ?: 1)
             dt.isLong -> throw IllegalArgumentException("long can not yet be put into memory")
             dt.isUndefined -> throw IllegalArgumentException("undefined has no memory size")
             else -> 2 * (numElements ?: 1)
         }
     }
+
 }

codeCore/src/prog8/code/target/PETTarget.kt

@@ -1,19 +1,72 @@
 package prog8.code.target
 
-import prog8.code.core.Encoding
-import prog8.code.core.ICompilationTarget
-import prog8.code.core.IMemSizer
-import prog8.code.core.IStringEncoding
-import prog8.code.target.cbm.CbmMemorySizer
-import prog8.code.target.pet.PETMachineDefinition
+import prog8.code.core.*
+import prog8.code.target.encodings.Encoder
+import prog8.code.target.zp.PETZeropage
+import java.nio.file.Path
 
 
-class PETTarget: ICompilationTarget, IStringEncoding by Encoder, IMemSizer by CbmMemorySizer {
+class PETTarget: ICompilationTarget, IStringEncoding by Encoder, IMemSizer by NormalMemSizer(Mflpt5.Companion.FLOAT_MEM_SIZE) {
     override val name = NAME
-    override val machine = PETMachineDefinition()
     override val defaultEncoding = Encoding.PETSCII
+    override val libraryPath = null
+    override val customLauncher: List<String> = emptyList()
+    override val additionalAssemblerOptions = null
 
     companion object {
         const val NAME = "pet32"
     }
+
+    override val cpu = CpuType.CPU6502
+
+    override val FLOAT_MAX_POSITIVE = Mflpt5.FLOAT_MAX_POSITIVE
+    override val FLOAT_MAX_NEGATIVE = Mflpt5.FLOAT_MAX_NEGATIVE
+    override val FLOAT_MEM_SIZE = Mflpt5.FLOAT_MEM_SIZE
+    override val STARTUP_CODE_RESERVED_SIZE = 20u
+    override val PROGRAM_LOAD_ADDRESS = 0x0401u
+    override val PROGRAM_MEMTOP_ADDRESS = 0x8000u
+
+    override val BSSHIGHRAM_START = 0u
+    override val BSSHIGHRAM_END = 0u
+    override val BSSGOLDENRAM_START = 0u
+    override val BSSGOLDENRAM_END = 0u
+
+    override lateinit var zeropage: Zeropage
+    override lateinit var golden: GoldenRam
+
+    override fun getFloatAsmBytes(num: Number) = Mflpt5.fromNumber(num).makeFloatFillAsm()
+
+    override fun convertFloatToBytes(num: Double): List<UByte> {
+        val m5 = Mflpt5.fromNumber(num)
+        return listOf(m5.b0, m5.b1, m5.b2, m5.b3, m5.b4)
+    }
+
+    override fun convertBytesToFloat(bytes: List<UByte>): Double {
+        require(bytes.size==5) { "need 5 bytes" }
+        val m5 = Mflpt5(bytes[0], bytes[1], bytes[2], bytes[3], bytes[4])
+        return m5.toDouble()
+    }
+
+    override fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path) {
+        if(selectedEmulator!=1) {
+            System.err.println("The pet target only supports the main emulator (Vice).")
+            return
+        }
+
+        println("\nStarting PET emulator...")
+        val viceMonlist = C64Target.viceMonListName(programNameWithPath.toString())
+        val cmdline = listOf("xpet", "-model", "4032", "-ramsize", "32", "-videosize", "40", "-silent", "-moncommands", viceMonlist,
+            "-autostartprgmode", "1", "-autostart-warp", "-autostart", "${programNameWithPath}.prg")
+        val processb = ProcessBuilder(cmdline).inheritIO()
+        val process=processb.start()
+        process.waitFor()
+    }
+
+    override fun isIOAddress(address: UInt): Boolean = address in 0xe800u..0xe8ffu
+
+    override fun initializeMemoryAreas(compilerOptions: CompilationOptions) {
+        zeropage = PETZeropage(compilerOptions)
+        golden = GoldenRam(compilerOptions, UIntRange.EMPTY)
+    }
+
 }

codeCore/src/prog8/code/target/VMTarget.kt

@@ -1,15 +1,89 @@
 package prog8.code.target
 
 import prog8.code.core.*
-import prog8.code.target.virtual.VirtualMachineDefinition
+import prog8.code.target.encodings.Encoder
+import java.nio.file.Path
+import kotlin.io.path.isReadable
+import kotlin.io.path.name
+import kotlin.io.path.readText
 
-class VMTarget: ICompilationTarget, IStringEncoding by Encoder, IMemSizer {
+class VMTarget: ICompilationTarget, IStringEncoding by Encoder, IMemSizer by NormalMemSizer(FLOAT_MEM_SIZE) {
     override val name = NAME
-    override val machine = VirtualMachineDefinition()
     override val defaultEncoding = Encoding.ISO
+    override val libraryPath = null
+    override val customLauncher: List<String> = emptyList()
+    override val additionalAssemblerOptions = null
 
     companion object {
         const val NAME = "virtual"
+        const val FLOAT_MEM_SIZE = 8             // 64-bits double
+    }
+
+    override val cpu = CpuType.VIRTUAL
+
+    override val FLOAT_MAX_POSITIVE = Double.MAX_VALUE.toDouble()
+    override val FLOAT_MAX_NEGATIVE = -Double.MAX_VALUE.toDouble()
+    override val FLOAT_MEM_SIZE = VMTarget.FLOAT_MEM_SIZE
+    override val STARTUP_CODE_RESERVED_SIZE = 0u  // not actually used
+    override val PROGRAM_LOAD_ADDRESS = 0u      // not actually used
+    override val PROGRAM_MEMTOP_ADDRESS = 0xffffu  // not actually used
+
+    override val BSSHIGHRAM_START = 0u          // not actually used
+    override val BSSHIGHRAM_END = 0u            // not actually used
+    override val BSSGOLDENRAM_START = 0u        // not actually used
+    override val BSSGOLDENRAM_END = 0u          // not actually used
+    override lateinit var zeropage: Zeropage    // not actually used
+    override lateinit var golden: GoldenRam     // not actually used
+
+    override fun getFloatAsmBytes(num: Number): String {
+        // little endian binary representation
+        val bits = num.toDouble().toBits().toULong()
+        val hexStr = bits.toString(16).padStart(16, '0')
+        val parts = hexStr.chunked(2).map { "\$" + it }
+        return parts.joinToString(", ")
+    }
+
+    override fun convertFloatToBytes(num: Double): List<UByte> {
+        val bits = num.toBits().toULong()
+        val hexStr = bits.toString(16).padStart(16, '0')
+        val parts = hexStr.chunked(2).map { it.toInt(16).toUByte() }
+        return parts
+    }
+
+    override fun convertBytesToFloat(bytes: List<UByte>): Double {
+        require(bytes.size==8) { "need 8 bytes" }
+        val b0 = bytes[0].toLong() shl (8*7)
+        val b1 = bytes[1].toLong() shl (8*6)
+        val b2 = bytes[2].toLong() shl (8*5)
+        val b3 = bytes[3].toLong() shl (8*4)
+        val b4 = bytes[4].toLong() shl (8*3)
+        val b5 = bytes[5].toLong() shl (8*2)
+        val b6 = bytes[6].toLong() shl (8*1)
+        val b7 = bytes[7].toLong() shl (8*0)
+        return Double.fromBits(b0 or b1 or b2 or b3 or b4 or b5 or b6 or b7)
+    }
+
+    override fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path) {
+        println("\nStarting Virtual Machine...")
+        // to not have external module dependencies in our own module, we launch the virtual machine via reflection
+        val vm = Class.forName("prog8.vm.VmRunner").getDeclaredConstructor().newInstance() as IVirtualMachineRunner
+        val filename = programNameWithPath.name
+        if(programNameWithPath.isReadable()) {
+            vm.runProgram(programNameWithPath.readText())
+        } else {
+            val withExt = programNameWithPath.resolveSibling("$filename.p8ir")
+            if(withExt.isReadable())
+                vm.runProgram(withExt.readText())
+            else
+                throw NoSuchFileException(withExt.toFile(), reason="not a .p8ir file")
+        }
+    }
+
+    override fun isIOAddress(address: UInt): Boolean = false
+
+    override fun initializeMemoryAreas(compilerOptions: CompilationOptions) {
+        zeropage = VirtualZeropage(compilerOptions)
+        golden = GoldenRam(compilerOptions, UIntRange.EMPTY)
     }
 
     override fun memorySize(dt: DataType, numElements: Int?): Int {
@@ -18,7 +92,7 @@ class VMTarget: ICompilationTarget, IStringEncoding by Encoder, IMemSizer {
             return when(dt.sub) {
                 BaseDataType.BOOL, BaseDataType.UBYTE, BaseDataType.BYTE -> numElements
                 BaseDataType.UWORD, BaseDataType.WORD, BaseDataType.STR -> numElements * 2
-                BaseDataType.FLOAT-> numElements * machine.FLOAT_MEM_SIZE
+                BaseDataType.FLOAT-> numElements * FLOAT_MEM_SIZE
                 BaseDataType.UNDEFINED -> throw IllegalArgumentException("undefined has no memory size")
                 else -> throw IllegalArgumentException("invalid sub type")
             }
@@ -30,10 +104,27 @@ class VMTarget: ICompilationTarget, IStringEncoding by Encoder, IMemSizer {
 
         return when {
             dt.isByteOrBool -> 1 * (numElements ?: 1)
-            dt.isFloat -> machine.FLOAT_MEM_SIZE * (numElements ?: 1)
+            dt.isFloat -> FLOAT_MEM_SIZE * (numElements ?: 1)
             dt.isLong -> throw IllegalArgumentException("long can not yet be put into memory")
             dt.isUndefined -> throw IllegalArgumentException("undefined has no memory size")
             else -> 2 * (numElements ?: 1)
         }
     }
-}
+}
+
+
+
+interface IVirtualMachineRunner {
+    fun runProgram(irSource: String)
+}
+
+private class VirtualZeropage(options: CompilationOptions): Zeropage(options) {
+    override val SCRATCH_B1: UInt
+        get() = throw IllegalStateException("virtual shouldn't use this zeropage variable")
+    override val SCRATCH_REG: UInt
+        get() = throw IllegalStateException("virtual shouldn't use this zeropage variable")
+    override val SCRATCH_W1: UInt
+        get() = throw IllegalStateException("virtual shouldn't use this zeropage variable")
+    override val SCRATCH_W2: UInt
+        get() = throw IllegalStateException("virtual shouldn't use this zeropage variable")
+}

codeCore/src/prog8/code/target/atari/AtariMachineDefinition.kt

@@ -1,62 +0,0 @@
-package prog8.code.target.atari
-
-import prog8.code.core.*
-import java.nio.file.Path
-
-
-class AtariMachineDefinition: IMachineDefinition {
-
-    override val cpu = CpuType.CPU6502
-
-    override val FLOAT_MAX_POSITIVE = 9.999999999e97
-    override val FLOAT_MAX_NEGATIVE = -9.999999999e97
-    override val FLOAT_MEM_SIZE = 6
-    override val STARTUP_CODE_RESERVED_SIZE = 20u
-    override val PROGRAM_LOAD_ADDRESS = 0x2000u
-    override val PROGRAM_MEMTOP_ADDRESS = 0xffffu  // TODO what's memtop?
-
-    override val BSSHIGHRAM_START = 0u    // TODO
-    override val BSSHIGHRAM_END = 0u      // TODO
-    override val BSSGOLDENRAM_START = 0u  // TODO
-    override val BSSGOLDENRAM_END = 0u    // TODO
-
-    override lateinit var zeropage: Zeropage
-    override lateinit var golden: GoldenRam
-
-    override fun getFloatAsmBytes(num: Number) = TODO("atari float asm bytes from number")
-    override fun convertFloatToBytes(num: Double): List<UByte> = TODO("atari float to bytes")
-    override fun convertBytesToFloat(bytes: List<UByte>): Double = TODO("atari bytes to float")
-
-    override fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path) {
-        val emulatorName: String
-        val cmdline: List<String>
-        when(selectedEmulator) {
-            1 -> {
-                emulatorName = "atari800"
-                cmdline = listOf(emulatorName, "-xl", "-xl-rev", "2", "-nobasic", "-run", "${programNameWithPath}.xex")
-            }
-            2 -> {
-                emulatorName = "altirra"
-                cmdline = listOf("Altirra64.exe", "${programNameWithPath.normalize()}.xex")
-            }
-            else -> {
-                System.err.println("Atari target only supports atari800 and altirra emulators.")
-                return
-            }
-        }
-
-        // TODO monlist?
-
-        println("\nStarting Atari800XL emulator $emulatorName...")
-        val processb = ProcessBuilder(cmdline).inheritIO()
-        val process: Process = processb.start()
-        process.waitFor()
-    }
-
-    override fun isIOAddress(address: UInt): Boolean = address==0u || address==1u || address in 0xd000u..0xdfffu        // TODO
-
-    override fun initializeMemoryAreas(compilerOptions: CompilationOptions) {
-        zeropage = AtariZeropage(compilerOptions)
-        golden = GoldenRam(compilerOptions, UIntRange.EMPTY)
-    }
-}

codeCore/src/prog8/code/target/atari/AtariZeropage.kt

@@ -1,57 +0,0 @@
-package prog8.code.target.atari
-
-import prog8.code.core.CompilationOptions
-import prog8.code.core.InternalCompilerException
-import prog8.code.core.Zeropage
-import prog8.code.core.ZeropageType
-
-class AtariZeropage(options: CompilationOptions) : Zeropage(options) {
-
-    override val SCRATCH_B1 = 0xcbu      // temp storage for a single byte
-    override val SCRATCH_REG = 0xccu     // temp storage for a register, must be B1+1
-    override val SCRATCH_W1 = 0xcdu      // temp storage 1 for a word  $cd+$ce
-    override val SCRATCH_W2 = 0xcfu      // temp storage 2 for a word  $cf+$d0        TODO is $d0 okay to use?
-
-    init {
-        if (options.floats) {
-            throw InternalCompilerException("Atari target doesn't yet support floating point routines")
-        }
-
-        if (options.floats && options.zeropage !in arrayOf(
-                ZeropageType.FLOATSAFE,
-                ZeropageType.BASICSAFE,
-                ZeropageType.DONTUSE
-            ))
-            throw InternalCompilerException("when floats are enabled, zero page type should be 'floatsafe' or 'basicsafe' or 'dontuse'")
-
-        when (options.zeropage) {
-            ZeropageType.FULL -> {
-                // TODO all atari usable zero page locations, except the ones used by the system's IRQ routine
-                free.addAll(0x00u..0xffu)
-                // TODO atari  free.removeAll(arrayOf(0xa0u, 0xa1u, 0xa2u, 0x91u, 0xc0u, 0xc5u, 0xcbu, 0xf5u, 0xf6u))        // these are updated by IRQ
-            }
-            ZeropageType.KERNALSAFE -> {
-                free.addAll(0x80u..0xffu)       // TODO
-            }
-            ZeropageType.BASICSAFE,
-            ZeropageType.FLOATSAFE -> {
-                free.addAll(0x80u..0xffu)       // TODO
-                free.removeAll(0xd4u .. 0xefu)      // floating point storage
-            }
-            ZeropageType.DONTUSE -> {
-                free.clear()  // don't use zeropage at all
-            }
-        }
-
-        val distinctFree = free.distinct()
-        free.clear()
-        free.addAll(distinctFree)
-
-        removeReservedFromFreePool()
-        retainAllowed()
-    }
-
-    override fun allocateCx16VirtualRegisters() {
-        TODO("Not known if atari can put the virtual regs in ZP")
-    }
-}

codeCore/src/prog8/code/target/c128/C128MachineDefinition.kt

@@ -1,62 +0,0 @@
-package prog8.code.target.c128
-
-import prog8.code.core.*
-import prog8.code.target.C64Target
-import prog8.code.target.cbm.Mflpt5
-import java.nio.file.Path
-
-
-class C128MachineDefinition: IMachineDefinition {
-
-    override val cpu = CpuType.CPU6502
-
-    override val FLOAT_MAX_POSITIVE = Mflpt5.FLOAT_MAX_POSITIVE
-    override val FLOAT_MAX_NEGATIVE = Mflpt5.FLOAT_MAX_NEGATIVE
-    override val FLOAT_MEM_SIZE = Mflpt5.FLOAT_MEM_SIZE
-    override val STARTUP_CODE_RESERVED_SIZE = 20u
-    override val PROGRAM_LOAD_ADDRESS = 0x1c01u
-    override val PROGRAM_MEMTOP_ADDRESS = 0xc000u
-
-    override val BSSHIGHRAM_START = 0u    // TODO
-    override val BSSHIGHRAM_END = 0u      // TODO
-    override val BSSGOLDENRAM_START = 0u  // TODO
-    override val BSSGOLDENRAM_END = 0u    // TODO
-
-    override lateinit var zeropage: Zeropage
-    override lateinit var golden: GoldenRam
-
-    override fun getFloatAsmBytes(num: Number) = Mflpt5.fromNumber(num).makeFloatFillAsm()
-
-    override fun convertFloatToBytes(num: Double): List<UByte> {
-        val m5 = Mflpt5.fromNumber(num)
-        return listOf(m5.b0, m5.b1, m5.b2, m5.b3, m5.b4)
-    }
-
-    override fun convertBytesToFloat(bytes: List<UByte>): Double {
-        require(bytes.size==5) { "need 5 bytes" }
-        val m5 = Mflpt5(bytes[0], bytes[1], bytes[2], bytes[3], bytes[4])
-        return m5.toDouble()
-    }
-
-    override fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path) {
-        if(selectedEmulator!=1) {
-            System.err.println("The c128 target only supports the main emulator (Vice).")
-            return
-        }
-
-        println("\nStarting C-128 emulator x128...")
-        val viceMonlist = C64Target.viceMonListName(programNameWithPath.toString())
-        val cmdline = listOf("x128", "-silent", "-moncommands", viceMonlist,
-                "-autostartprgmode", "1", "-autostart-warp", "-autostart", "${programNameWithPath}.prg")
-        val processb = ProcessBuilder(cmdline).inheritIO()
-        val process: Process = processb.start()
-        process.waitFor()
-    }
-
-    override fun isIOAddress(address: UInt): Boolean = address==0u || address==1u || address in 0xd000u..0xdfffu
-
-    override fun initializeMemoryAreas(compilerOptions: CompilationOptions) {
-        zeropage = C128Zeropage(compilerOptions)
-        golden = GoldenRam(compilerOptions, UIntRange.EMPTY)    // TODO does the c128 have some of this somewhere?
-    }
-}

codeCore/src/prog8/code/target/c64/C64MachineDefinition.kt

@@ -1,73 +0,0 @@
-package prog8.code.target.c64
-
-import prog8.code.core.*
-import prog8.code.target.C64Target
-import prog8.code.target.cbm.Mflpt5
-import java.io.IOException
-import java.nio.file.Path
-
-
-class C64MachineDefinition: IMachineDefinition {
-
-    override val cpu = CpuType.CPU6502
-
-    override val FLOAT_MAX_POSITIVE = Mflpt5.FLOAT_MAX_POSITIVE
-    override val FLOAT_MAX_NEGATIVE = Mflpt5.FLOAT_MAX_NEGATIVE
-    override val FLOAT_MEM_SIZE = Mflpt5.FLOAT_MEM_SIZE
-    override val STARTUP_CODE_RESERVED_SIZE = 20u
-    override val PROGRAM_LOAD_ADDRESS = 0x0801u
-    override val PROGRAM_MEMTOP_ADDRESS = 0xcfe0u      // $a000  if floats are used
-            // note that at $cfe0-$cfff are the 16 'virtual registers' R0-R15
-
-    override val BSSHIGHRAM_START = 0xc000u
-    override val BSSHIGHRAM_END = 0xcfdfu
-    override val BSSGOLDENRAM_START = 0u
-    override val BSSGOLDENRAM_END = 0u
-
-    override lateinit var zeropage: Zeropage
-    override lateinit var golden: GoldenRam
-
-    override fun getFloatAsmBytes(num: Number) = Mflpt5.fromNumber(num).makeFloatFillAsm()
-
-    override fun convertFloatToBytes(num: Double): List<UByte> {
-        val m5 = Mflpt5.fromNumber(num)
-        return listOf(m5.b0, m5.b1, m5.b2, m5.b3, m5.b4)
-    }
-
-    override fun convertBytesToFloat(bytes: List<UByte>): Double {
-        require(bytes.size==5) { "need 5 bytes" }
-        val m5 = Mflpt5(bytes[0], bytes[1], bytes[2], bytes[3], bytes[4])
-        return m5.toDouble()
-    }
-
-    override fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path) {
-        if(selectedEmulator!=1) {
-            System.err.println("The c64 target only supports the main emulator (Vice).")
-            return
-        }
-
-        for(emulator in listOf("x64sc", "x64")) {
-            println("\nStarting C-64 emulator $emulator...")
-            val viceMonlist = C64Target.viceMonListName(programNameWithPath.toString())
-            val cmdline = listOf(emulator, "-silent", "-moncommands", viceMonlist,
-                    "-autostartprgmode", "1", "-autostart-warp", "-autostart", "${programNameWithPath}.prg")
-            val processb = ProcessBuilder(cmdline).inheritIO()
-            val process: Process
-            try {
-                process=processb.start()
-            } catch(_: IOException) {
-                continue  // try the next emulator executable
-            }
-            process.waitFor()
-            break
-        }
-    }
-
-    override fun isIOAddress(address: UInt): Boolean = address==0u || address==1u || address in 0xd000u..0xdfffu
-
-    override fun initializeMemoryAreas(compilerOptions: CompilationOptions) {
-        zeropage = C64Zeropage(compilerOptions)
-        golden = GoldenRam(compilerOptions, 0xc000u until 0xd000u)
-    }
-
-}

codeCore/src/prog8/code/target/cx16/CX16MachineDefinition.kt

@@ -1,75 +0,0 @@
-package prog8.code.target.cx16
-
-import prog8.code.core.*
-import prog8.code.target.C64Target
-import prog8.code.target.cbm.Mflpt5
-import java.nio.file.Path
-
-
-class CX16MachineDefinition: IMachineDefinition {
-
-    override val cpu = CpuType.CPU65c02
-
-    override val FLOAT_MAX_POSITIVE = Mflpt5.FLOAT_MAX_POSITIVE
-    override val FLOAT_MAX_NEGATIVE = Mflpt5.FLOAT_MAX_NEGATIVE
-    override val FLOAT_MEM_SIZE = Mflpt5.FLOAT_MEM_SIZE
-    override val STARTUP_CODE_RESERVED_SIZE = 20u
-    override val PROGRAM_LOAD_ADDRESS = 0x0801u
-    override val PROGRAM_MEMTOP_ADDRESS = 0x9f00u
-
-    override val BSSHIGHRAM_START = 0xa000u     // hiram bank 1, 8Kb, assumed to be active
-    override val BSSHIGHRAM_END = 0xbfffu       // Rom starts at $c000
-    override val BSSGOLDENRAM_START = 0x0400u
-    override val BSSGOLDENRAM_END = 0x07ffu
-
-    override lateinit var zeropage: Zeropage
-    override lateinit var golden: GoldenRam
-
-    override fun getFloatAsmBytes(num: Number) = Mflpt5.fromNumber(num).makeFloatFillAsm()
-
-    override fun convertFloatToBytes(num: Double): List<UByte> {
-        val m5 = Mflpt5.fromNumber(num)
-        return listOf(m5.b0, m5.b1, m5.b2, m5.b3, m5.b4)
-    }
-
-    override fun convertBytesToFloat(bytes: List<UByte>): Double {
-        require(bytes.size==5) { "need 5 bytes" }
-        val m5 = Mflpt5(bytes[0], bytes[1], bytes[2], bytes[3], bytes[4])
-        return m5.toDouble()
-    }
-
-    override fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path) {
-        val emulator: String
-        val extraArgs: List<String>
-
-        when(selectedEmulator) {
-            1 -> {
-                emulator = "x16emu"
-                extraArgs = listOf("-debug")
-            }
-            2 -> {
-                emulator = "box16"
-                extraArgs = listOf("-sym", C64Target.viceMonListName(programNameWithPath.toString()))
-            }
-            else -> {
-                System.err.println("Cx16 target only supports x16emu and box16 emulators.")
-                return
-            }
-        }
-
-        println("\nStarting Commander X16 emulator $emulator...")
-        val cmdline = listOf(emulator, "-scale", "2", "-rtc", "-run", "-prg", "${programNameWithPath}.prg") + extraArgs
-        val processb = ProcessBuilder(cmdline).inheritIO()
-        processb.environment()["PULSE_LATENCY_MSEC"] = "10"
-        val process: Process = processb.start()
-        process.waitFor()
-    }
-
-    override fun isIOAddress(address: UInt): Boolean = address==0u || address==1u || address in 0x9f00u..0x9fffu
-
-    override fun initializeMemoryAreas(compilerOptions: CompilationOptions) {
-        zeropage = CX16Zeropage(compilerOptions)
-        golden = GoldenRam(compilerOptions, 0x0400u until 0x0800u)
-    }
-
-}

codeCore/src/prog8/code/target/encodings/C64osEncoding.kt

@@ -0,0 +1,326 @@
+package prog8.code.target.encodings
+
+import com.github.michaelbull.result.Err
+import com.github.michaelbull.result.Ok
+import com.github.michaelbull.result.Result
+import java.io.CharConversionException
+
+object C64osEncoding {
+
+    // decoding:  from C64 OS Screencodes (0-255) to unicode
+    // character table from:
+    // https://www.c64os.com/c64os/usersguide/appendices#charactersets
+
+    private val decodingC64os = charArrayOf(
+        '@'     ,    //  @    0x00 -> COMMERCIAL AT
+        'a'     ,    //  a    0x01 -> LATIN SMALL LETTER A
+        'b'     ,    //  b    0x02 -> LATIN SMALL LETTER B
+        'c'     ,    //  c    0x03 -> LATIN SMALL LETTER C
+        'd'     ,    //  d    0x04 -> LATIN SMALL LETTER D
+        'e'     ,    //  e    0x05 -> LATIN SMALL LETTER E
+        'f'     ,    //  f    0x06 -> LATIN SMALL LETTER F
+        'g'     ,    //  g    0x07 -> LATIN SMALL LETTER G
+        'h'     ,    //  h    0x08 -> LATIN SMALL LETTER H
+        'i'     ,    //  i    0x09 -> LATIN SMALL LETTER I
+        'j'     ,    //  j    0x0A -> LATIN SMALL LETTER J
+        'k'     ,    //  k    0x0B -> LATIN SMALL LETTER K
+        'l'     ,    //  l    0x0C -> LATIN SMALL LETTER L
+        'm'     ,    //  m    0x0D -> LATIN SMALL LETTER M
+        'n'     ,    //  n    0x0E -> LATIN SMALL LETTER N
+        'o'     ,    //  o    0x0F -> LATIN SMALL LETTER O
+        'p'     ,    //  p    0x10 -> LATIN SMALL LETTER P
+        'q'     ,    //  q    0x11 -> LATIN SMALL LETTER Q
+        'r'     ,    //  r    0x12 -> LATIN SMALL LETTER R
+        's'     ,    //  s    0x13 -> LATIN SMALL LETTER S
+        't'     ,    //  t    0x14 -> LATIN SMALL LETTER T
+        'u'     ,    //  u    0x15 -> LATIN SMALL LETTER U
+        'v'     ,    //  v    0x16 -> LATIN SMALL LETTER V
+        'w'     ,    //  w    0x17 -> LATIN SMALL LETTER W
+        'x'     ,    //  x    0x18 -> LATIN SMALL LETTER X
+        'y'     ,    //  y    0x19 -> LATIN SMALL LETTER Y
+        'z'     ,    //  z    0x1A -> LATIN SMALL LETTER Z
+        '['     ,    //  [    0x1B -> LEFT SQUARE BRACKET
+        '\\'    ,    //  \    0x1C -> REVERSE SOLIDUS
+        ']'     ,    //  ]    0x1D -> RIGHT SQUARE BRACKET
+        '^'     ,    //  ^    0x1E -> CIRCUMFLEX
+        '_'     ,    //  _    0x1F -> UNDERSCORE
+        ' '     ,    //       0x20 -> SPACE
+        '!'     ,    //  !    0x21 -> EXCLAMATION MARK
+        '"'     ,    //  "    0x22 -> QUOTATION MARK
+        '#'     ,    //  #    0x23 -> NUMBER SIGN
+        '$'     ,    //  $    0x24 -> DOLLAR SIGN
+        '%'     ,    //  %    0x25 -> PERCENT SIGN
+        '&'     ,    //  &    0x26 -> AMPERSAND
+        '\''    ,    //  '    0x27 -> APOSTROPHE
+        '('     ,    //  (    0x28 -> LEFT PARENTHESIS
+        ')'     ,    //  )    0x29 -> RIGHT PARENTHESIS
+        '*'     ,    //  *    0x2A -> ASTERISK
+        '+'     ,    //  +    0x2B -> PLUS SIGN
+        ','     ,    //  ,    0x2C -> COMMA
+        '-'     ,    //  -    0x2D -> HYPHEN-MINUS
+        '.'     ,    //  .    0x2E -> FULL STOP
+        '/'     ,    //  /    0x2F -> SOLIDUS
+        '0'     ,    //  0    0x30 -> DIGIT ZERO
+        '1'     ,    //  1    0x31 -> DIGIT ONE
+        '2'     ,    //  2    0x32 -> DIGIT TWO
+        '3'     ,    //  3    0x33 -> DIGIT THREE
+        '4'     ,    //  4    0x34 -> DIGIT FOUR
+        '5'     ,    //  5    0x35 -> DIGIT FIVE
+        '6'     ,    //  6    0x36 -> DIGIT SIX
+        '7'     ,    //  7    0x37 -> DIGIT SEVEN
+        '8'     ,    //  8    0x38 -> DIGIT EIGHT
+        '9'     ,    //  9    0x39 -> DIGIT NINE
+        ':'     ,    //  :    0x3A -> COLON
+        ';'     ,    //  ;    0x3B -> SEMICOLON
+        '<'     ,    //  <    0x3C -> LESS-THAN SIGN
+        '='     ,    //  =    0x3D -> EQUALS SIGN
+        '>'     ,    //  >    0x3E -> GREATER-THAN SIGN
+        '?'     ,    //  ?    0x3F -> QUESTION MARK
+        '`'     ,    //  `    0x40 -> GRAVE ACCENT
+        'A'     ,    //  A    0x41 -> LATIN CAPITAL LETTER A
+        'B'     ,    //  B    0x42 -> LATIN CAPITAL LETTER B
+        'C'     ,    //  C    0x43 -> LATIN CAPITAL LETTER C
+        'D'     ,    //  D    0x44 -> LATIN CAPITAL LETTER D
+        'E'     ,    //  E    0x45 -> LATIN CAPITAL LETTER E
+        'F'     ,    //  F    0x46 -> LATIN CAPITAL LETTER F
+        'G'     ,    //  G    0x47 -> LATIN CAPITAL LETTER G
+        'H'     ,    //  H    0x48 -> LATIN CAPITAL LETTER H
+        'I'     ,    //  I    0x49 -> LATIN CAPITAL LETTER I
+        'J'     ,    //  J    0x4A -> LATIN CAPITAL LETTER J
+        'K'     ,    //  K    0x4B -> LATIN CAPITAL LETTER K
+        'L'     ,    //  L    0x4C -> LATIN CAPITAL LETTER L
+        'M'     ,    //  M    0x4D -> LATIN CAPITAL LETTER M
+        'N'     ,    //  N    0x4E -> LATIN CAPITAL LETTER N
+        'O'     ,    //  O    0x4F -> LATIN CAPITAL LETTER O
+        'P'     ,    //  P    0x50 -> LATIN CAPITAL LETTER P
+        'Q'     ,    //  Q    0x51 -> LATIN CAPITAL LETTER Q
+        'R'     ,    //  R    0x52 -> LATIN CAPITAL LETTER R
+        'S'     ,    //  S    0x53 -> LATIN CAPITAL LETTER S
+        'T'     ,    //  T    0x54 -> LATIN CAPITAL LETTER T
+        'U'     ,    //  U    0x55 -> LATIN CAPITAL LETTER U
+        'V'     ,    //  V    0x56 -> LATIN CAPITAL LETTER V
+        'W'     ,    //  W    0x57 -> LATIN CAPITAL LETTER W
+        'X'     ,    //  X    0x58 -> LATIN CAPITAL LETTER X
+        'Y'     ,    //  Y    0x59 -> LATIN CAPITAL LETTER Y
+        'Z'     ,    //  Z    0x5A -> LATIN CAPITAL LETTER Z
+        '{'     ,    //  {    0x5B -> LEFT BRACE
+        '|'     ,    //  |    0x5C -> VERTICAL BAR
+        '}'     ,    //  }    0x5D -> RIGHT BRACE
+        '~'     ,    //  ~    0x5E -> TILDE
+        '\ufffe',    //       0x5F -> RESERVED
+        '\u00a0',    //       0x60 -> NO-BREAK SPACE (TRANSPARENT)
+        '\ufffe',    //       0x61 -> COMMODORE SYMBOL
+        '\u2191',    //  ↑    0x62 -> UP ARROW
+        '\u2193',    //  ↓    0x63 -> DOWN ARROW
+        '\u2190',    //  ←    0x64 -> LEFT ARROW
+        '\u2192',    //  →    0x65 -> RIGHT ARROW
+        '\u231A',    //  ⌚   0x66 -> WATCH (ANALOG CLOCKFACE)
+        '\u21BB',    //  ↻    0x67 -> CYCLE ARROWS
+        '\u2026',    //  …    0x68 -> ELLIPSIS
+        '\u25a7',    //  ▧    0x69 -> DIAGNONAL STRIPES
+        '\u2610',    //  ☐    0x6A -> CHECKBOX UNCHECKED
+        '\u2611',    //  ☑    0x6B -> CHECKBOX CHECKED
+        '\ufffe',    //       0x6C -> RADIO BUTTON UNSELECTED
+        '\ufffe',    //       0x6D -> RADIO BUTTON SELECTED
+        '\ufffe',    //       0x6E -> UTILITY CLOSE BUTTON
+        '\ufffe',    //       0x6F -> UTILITY TITLE BAR
+        '\u00a9',    //  ©    0x70 -> COPYRIGHT
+        '\u2713',    //  ✓    0x71 -> CHECKMARK
+        '\u2261',    //  ≡    0x72 -> THREE HORIZONTAL STRIPES
+        '\ufffe',    //       0x73 -> TICK TRACK
+        '\ufffe',    //       0x74 -> TICK TRACK NUB
+        '\ufffe',    //       0x75 -> TAB CORNER
+        '\u2980',    //  ⦀    0x76 -> THREE VERTICAL STRIPES
+        '\ufffe',    //       0x77 -> CUSTOM 1
+        '\ufffe',    //       0x78 -> CUSTOM 2
+        '\ufffe',    //       0x79 -> CUSTOM 3
+        '\ufffe',    //       0x7A -> CUSTOM 4
+        '\ufffe',    //       0x7B -> CUSTOM 5
+        '\ufffe',    //       0x7C -> CUSTOM 6
+        '\ufffe',    //       0x7D -> CUSTOM 7
+        '\ufffe',    //       0x7E -> CUSTOM 8
+        '\ufffe',    //       0x7F -> CUSTOM 9
+        '\ufffe',    //       0x80 -> REVERSED COMMERCIAL AT
+        '\ufffe',    //       0x81 -> REVERSED LATIN SMALL LETTER A
+        '\ufffe',    //       0x82 -> REVERSED LATIN SMALL LETTER B
+        '\ufffe',    //       0x83 -> REVERSED LATIN SMALL LETTER C
+        '\ufffe',    //       0x84 -> REVERSED LATIN SMALL LETTER D
+        '\ufffe',    //       0x85 -> REVERSED LATIN SMALL LETTER E
+        '\ufffe',    //       0x86 -> REVERSED LATIN SMALL LETTER F
+        '\ufffe',    //       0x87 -> REVERSED LATIN SMALL LETTER G
+        '\ufffe',    //       0x88 -> REVERSED LATIN SMALL LETTER H
+        '\ufffe',    //       0x89 -> REVERSED LATIN SMALL LETTER I
+        '\ufffe',    //       0x8A -> REVERSED LATIN SMALL LETTER J
+        '\ufffe',    //       0x8B -> REVERSED LATIN SMALL LETTER K
+        '\ufffe',    //       0x8C -> REVERSED LATIN SMALL LETTER L
+        '\ufffe',    //       0x8D -> REVERSED LATIN SMALL LETTER M
+        '\ufffe',    //       0x8E -> REVERSED LATIN SMALL LETTER N
+        '\ufffe',    //       0x8F -> REVERSED LATIN SMALL LETTER O
+        '\ufffe',    //       0x90 -> REVERSED LATIN SMALL LETTER P
+        '\ufffe',    //       0x91 -> REVERSED LATIN SMALL LETTER Q
+        '\ufffe',    //       0x92 -> REVERSED LATIN SMALL LETTER R
+        '\ufffe',    //       0x93 -> REVERSED LATIN SMALL LETTER S
+        '\ufffe',    //       0x94 -> REVERSED LATIN SMALL LETTER T
+        '\ufffe',    //       0x95 -> REVERSED LATIN SMALL LETTER U
+        '\ufffe',    //       0x96 -> REVERSED LATIN SMALL LETTER V
+        '\ufffe',    //       0x97 -> REVERSED LATIN SMALL LETTER W
+        '\ufffe',    //       0x98 -> REVERSED LATIN SMALL LETTER X
+        '\ufffe',    //       0x99 -> REVERSED LATIN SMALL LETTER Y
+        '\ufffe',    //       0x9A -> REVERSED LATIN SMALL LETTER Z
+        '\ufffe',    //       0x9B -> REVERSED LEFT SQUARE BRACKET
+        '\ufffe',    //       0x9C -> REVERSED REVERSE SOLIDUS
+        '\ufffe',    //       0x9D -> REVERSED RIGHT SQUARE BRACKET
+        '\ufffe',    //       0x9E -> REVERSED CIRCUMFLEX
+        '\ufffe',    //       0x9F -> REVERSED UNDERSCORE
+        '\ufffe',    //       0xA0 -> REVERSED SPACE
+        '\ufffe',    //       0xA1 -> REVERSED EXCLAMATION MARK
+        '\ufffe',    //       0xA2 -> REVERSED QUOTATION MARK
+        '\ufffe',    //       0xA3 -> REVERSED NUMBER SIGN
+        '\ufffe',    //       0xA4 -> REVERSED DOLLAR SIGN
+        '\ufffe',    //       0xA5 -> REVERSED PERCENT SIGN
+        '\ufffe',    //       0xA6 -> REVERSED AMPERSAND
+        '\ufffe',    //       0xA7 -> REVERSED APOSTROPHE
+        '\ufffe',    //       0xA8 -> REVERSED LEFT PARENTHESIS
+        '\ufffe',    //       0xA9 -> REVERSED RIGHT PARENTHESIS
+        '\ufffe',    //       0xAA -> REVERSED ASTERISK
+        '\ufffe',    //       0xAB -> REVERSED PLUS SIGN
+        '\ufffe',    //       0xAC -> REVERSED COMMA
+        '\ufffe',    //       0xAD -> REVERSED HYPHEN-MINUS
+        '\ufffe',    //       0xAE -> REVERSED FULL STOP
+        '\ufffe',    //       0xAF -> REVERSED SOLIDUS
+        '\ufffe',    //       0xB0 -> REVERSED DIGIT ZERO
+        '\ufffe',    //       0xB1 -> REVERSED DIGIT ONE
+        '\ufffe',    //       0xB2 -> REVERSED DIGIT TWO
+        '\ufffe',    //       0xB3 -> REVERSED DIGIT THREE
+        '\ufffe',    //       0xB4 -> REVERSED DIGIT FOUR
+        '\ufffe',    //       0xB5 -> REVERSED DIGIT FIVE
+        '\ufffe',    //       0xB6 -> REVERSED DIGIT SIX
+        '\ufffe',    //       0xB7 -> REVERSED DIGIT SEVEN
+        '\ufffe',    //       0xB8 -> REVERSED DIGIT EIGHT
+        '\ufffe',    //       0xB9 -> REVERSED DIGIT NINE
+        '\ufffe',    //       0xBA -> REVERSED COLON
+        '\ufffe',    //       0xBB -> REVERSED SEMICOLON
+        '\ufffe',    //       0xBC -> REVERSED LESS-THAN SIGN
+        '\ufffe',    //       0xBD -> REVERSED EQUALS SIGN
+        '\ufffe',    //       0xBE -> REVERSED GREATER-THAN SIGN
+        '\ufffe',    //       0xBF -> REVERSED QUESTION MARK
+        '\ufffe',    //       0xC0 -> REVERSED GRAVE ACCENT
+        '\ufffe',    //       0xC1 -> REVERSED LATIN CAPITAL LETTER A
+        '\ufffe',    //       0xC2 -> REVERSED LATIN CAPITAL LETTER B
+        '\ufffe',    //       0xC3 -> REVERSED LATIN CAPITAL LETTER C
+        '\ufffe',    //       0xC4 -> REVERSED LATIN CAPITAL LETTER D
+        '\ufffe',    //       0xC5 -> REVERSED LATIN CAPITAL LETTER E
+        '\ufffe',    //       0xC6 -> REVERSED LATIN CAPITAL LETTER F
+        '\ufffe',    //       0xC7 -> REVERSED LATIN CAPITAL LETTER G
+        '\ufffe',    //       0xC8 -> REVERSED LATIN CAPITAL LETTER H
+        '\ufffe',    //       0xC9 -> REVERSED LATIN CAPITAL LETTER I
+        '\ufffe',    //       0xCA -> REVERSED LATIN CAPITAL LETTER J
+        '\ufffe',    //       0xCB -> REVERSED LATIN CAPITAL LETTER K
+        '\ufffe',    //       0xCC -> REVERSED LATIN CAPITAL LETTER L
+        '\ufffe',    //       0xCD -> REVERSED LATIN CAPITAL LETTER M
+        '\ufffe',    //       0xCE -> REVERSED LATIN CAPITAL LETTER N
+        '\ufffe',    //       0xCF -> REVERSED LATIN CAPITAL LETTER O
+        '\ufffe',    //       0xD0 -> REVERSED LATIN CAPITAL LETTER P
+        '\ufffe',    //       0xD1 -> REVERSED LATIN CAPITAL LETTER Q
+        '\ufffe',    //       0xD2 -> REVERSED LATIN CAPITAL LETTER R
+        '\ufffe',    //       0xD3 -> REVERSED LATIN CAPITAL LETTER S
+        '\ufffe',    //       0xD4 -> REVERSED LATIN CAPITAL LETTER T
+        '\ufffe',    //       0xD5 -> REVERSED LATIN CAPITAL LETTER U
+        '\ufffe',    //       0xD6 -> REVERSED LATIN CAPITAL LETTER V
+        '\ufffe',    //       0xD7 -> REVERSED LATIN CAPITAL LETTER W
+        '\ufffe',    //       0xD8 -> REVERSED LATIN CAPITAL LETTER X
+        '\ufffe',    //       0xD9 -> REVERSED LATIN CAPITAL LETTER Y
+        '\ufffe',    //       0xDA -> REVERSED LATIN CAPITAL LETTER Z
+        '\ufffe',    //       0xDB -> REVERSED LEFT BRACE
+        '\ufffe',    //       0xDC -> REVERSED VERTICAL BAR
+        '\ufffe',    //       0xDD -> REVERSED RIGHT BRACE
+        '\ufffe',    //       0xDE -> REVERSED TILDE
+        '\ufffe',    //       0xDF -> RESERVED
+        '\ufffe',    //       0xE0 -> RESERVED
+        '\ufffe',    //       0xE1 -> REVERSED COMMODORE SYMBOL
+        '\ufffe',    //       0xE2 -> REVERSED UP ARROW
+        '\ufffe',    //       0xE3 -> REVERSED DOWN ARROW
+        '\ufffe',    //       0xE4 -> REVERSED LEFT ARROW
+        '\ufffe',    //       0xE5 -> REVERSED RIGHT ARROW
+        '\ufffe',    //       0xE6 -> REVERSED ANALOG CLOCKFACE
+        '\ufffe',    //       0xE7 -> REVERSED CYCLE ARROWS
+        '\ufffe',    //       0xE8 -> REVERSED ELLIPSIS
+        '\ufffe',    //       0xE9 -> REVERSED DIAGONAL STRIPES
+        '\ufffe',    //       0xEA -> REVERSED CHECKBOX UNCHECKED
+        '\ufffe',    //       0xEB -> REVERSED CHECKBOX CHECKED
+        '\ufffe',    //       0xEC -> REVERSED RADIO BUTTON UNSELECTED
+        '\ufffe',    //       0xED -> REVERSED RADIO BUTTON SELECTED
+        '\ufffe',    //       0xEE -> MEMORY CHIP ICON
+        '\u21e7',    //  ⇧    0xEF -> SHIFT SYMBOL
+        '\ufffe',    //       0xF0 -> REVERSED COPYRIGHT SYMBOL
+        '\ufffe',    //       0xF1 -> REVERSED CHECKMARK
+        '\ufffe',    //       0xF2 -> REVERSED THREE HORIZONTAL STRIPES
+        '\ufffe',    //       0xF3 -> REVERSED TICK TRACK
+        '\ufffe',    //       0xF4 -> REVERSED TICK TRACK NUB
+        '\ufffe',    //       0xF5 -> REVERSED TAB CORNER
+        '\ufffe',    //       0xF6 -> REVERSED THREE VERTICAL STRIPES
+        '\ufffe',    //       0xF7 -> CUSTOM 10
+        '\ufffe',    //       0xF8 -> CUSTOM 11
+        '\ufffe',    //       0xF9 -> CUSTOM 12
+        '\ufffe',    //       0xFA -> CUSTOM 13
+        '\ufffe',    //       0xFB -> CUSTOM 14
+        '\ufffe',    //       0xFC -> CUSTOM 15
+        '\ufffe',    //       0xFD -> CUSTOM 16
+        '\ufffe',    //       0xFE -> CUSTOM 17
+        '\ufffe'     //       0xFF -> CUSTOM 18
+    )
+
+    // encoding:  from unicode to C64 OS Screencodes (0-255)
+    private val encodingC64os = decodingC64os.withIndex().associate{it.value to it.index}
+
+    private fun replaceSpecial(chr: Char): Char =
+        when(chr) {
+            '\r' -> '\n'        // to make \r (carriage returrn) equivalent to \n (line feed): RETURN ($0d)
+            else -> chr
+        }
+    
+    fun encode(text: String, lowercase: Boolean = false): Result<List<UByte>, CharConversionException> {
+        fun encodeChar(chr3: Char, lowercase: Boolean): UByte {
+            val chr = replaceSpecial(chr3)
+            val screencode = encodingC64os[chr]
+            return screencode?.toUByte() ?: when (chr) {
+                '\u0000' -> 0u
+                in '\u8000'..'\u80ff' -> {
+                    // special case: take the lower 8 bit hex value directly
+                    (chr.code - 0x8000).toUByte()
+                }
+                else -> {
+                    if(chr.isISOControl())
+                        throw CharConversionException("no c64os character for char #${chr.code}")
+                    else
+                        throw CharConversionException("no c64os character for char #${chr.code} '${chr}'")
+                }
+            }
+        }
+
+        return try {
+            Ok(text.map {
+                try {
+                    encodeChar(it, lowercase)
+                } catch (x: CharConversionException) {
+                    encodeChar(it, !lowercase)
+                }
+            })
+        } catch(cx: CharConversionException) {
+            Err(cx)
+        }
+    }
+
+    fun decode(screencode: Iterable<UByte>, lowercase: Boolean = false): Result<String, CharConversionException> {
+        return try {
+            Ok(screencode.map {
+                val code = it.toInt()
+                if(code<0 || code>= decodingC64os.size)
+                    throw CharConversionException("c64os $code out of range 0..${decodingC64os.size-1}")
+                decodingC64os[code]
+            }.joinToString(""))
+        } catch(ce: CharConversionException) {
+            Err(ce)
+        }
+    }
+}

codeCore/src/prog8/code/target/encodings/Encoder.kt

@@ -1,11 +1,9 @@
-package prog8.code.target
+package prog8.code.target.encodings
 
 import com.github.michaelbull.result.fold
 import prog8.code.core.Encoding
 import prog8.code.core.IStringEncoding
 import prog8.code.core.InternalCompilerException
-import prog8.code.target.encodings.*
-
 
 object Encoder: IStringEncoding {
     override val defaultEncoding: Encoding = Encoding.ISO
@@ -20,6 +18,7 @@ object Encoder: IStringEncoding {
             Encoding.ISO16 -> IsoEasternEncoding.encode(str)
             Encoding.CP437 -> Cp437Encoding.encode(str)
             Encoding.KATAKANA -> KatakanaEncoding.encode(str)
+            Encoding.C64OS -> C64osEncoding.encode(str)
             else -> throw InternalCompilerException("unsupported encoding $encoding")
         }
         return coded.fold(
@@ -37,6 +36,7 @@ object Encoder: IStringEncoding {
             Encoding.ISO16 -> IsoEasternEncoding.decode(bytes)
             Encoding.CP437 -> Cp437Encoding.decode(bytes)
             Encoding.KATAKANA -> KatakanaEncoding.decode(bytes)
+            Encoding.C64OS -> C64osEncoding.decode(bytes)
             else -> throw InternalCompilerException("unsupported encoding $encoding")
         }
         return decoded.fold(
@@ -44,4 +44,4 @@ object Encoder: IStringEncoding {
             success = { it }
         )
     }
-}
+}

codeCore/src/prog8/code/target/neo6502/Neo6502MachineDefinition.kt

@@ -1,50 +0,0 @@
-package prog8.code.target.neo6502
-
-import prog8.code.core.*
-import java.nio.file.Path
-
-
-class Neo6502MachineDefinition: IMachineDefinition {
-
-    override val cpu = CpuType.CPU65c02
-
-    override val FLOAT_MAX_POSITIVE = 9.999999999e97
-    override val FLOAT_MAX_NEGATIVE = -9.999999999e97
-    override val FLOAT_MEM_SIZE = 6
-    override val STARTUP_CODE_RESERVED_SIZE = 20u
-    override val PROGRAM_LOAD_ADDRESS = 0x0800u
-    override val PROGRAM_MEMTOP_ADDRESS = 0xfc00u       // kernal starts here
-
-    override val BSSHIGHRAM_START = 0u    // TODO
-    override val BSSHIGHRAM_END = 0u      // TODO
-    override val BSSGOLDENRAM_START = 0u  // TODO
-    override val BSSGOLDENRAM_END = 0u    // TODO
-
-    override lateinit var zeropage: Zeropage
-    override lateinit var golden: GoldenRam
-
-    override fun getFloatAsmBytes(num: Number) = TODO("atari float asm bytes from number")
-    override fun convertFloatToBytes(num: Double): List<UByte> = TODO("atari float to bytes")
-    override fun convertBytesToFloat(bytes: List<UByte>): Double = TODO("atari bytes to float")
-
-    override fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path) {
-        if(selectedEmulator!=1) {
-            System.err.println("The neo target only supports the main emulator (neo).")
-            return
-        }
-
-        val cmdline = listOf("neo", "${programNameWithPath}.bin@800", "cold")
-
-        println("\nStarting Neo6502 emulator...")
-        val processb = ProcessBuilder(cmdline).inheritIO()
-        val process: Process = processb.start()
-        process.waitFor()
-    }
-
-    override fun isIOAddress(address: UInt): Boolean = address in 0xff00u..0xff0fu
-
-    override fun initializeMemoryAreas(compilerOptions: CompilationOptions) {
-        zeropage = Neo6502Zeropage(compilerOptions)
-        golden = GoldenRam(compilerOptions, UIntRange.EMPTY)
-    }
-}

codeCore/src/prog8/code/target/neo6502/Neo6502Zeropage.kt

@@ -1,48 +0,0 @@
-package prog8.code.target.neo6502
-
-import prog8.code.core.*
-
-class Neo6502Zeropage(options: CompilationOptions) : Zeropage(options) {
-
-    override val SCRATCH_B1 = 0xfau      // temp storage for a single byte
-    override val SCRATCH_REG = 0xfbu     // temp storage for a register, must be B1+1
-    override val SCRATCH_W1 = 0xfcu      // temp storage 1 for a word  $fc+$fd
-    override val SCRATCH_W2 = 0xfeu      // temp storage 2 for a word  $fe+$ff
-
-    init {
-        if (options.floats) {
-            throw InternalCompilerException("Neo6502 target doesn't support floating point routines")
-        }
-
-        when (options.zeropage) {
-            ZeropageType.DONTUSE -> {
-                free.clear()  // don't use zeropage at all
-            }
-            else -> {
-                free.addAll(0x22u..0xffu)
-            }
-        }
-
-        val distinctFree = free.distinct()
-        free.clear()
-        free.addAll(distinctFree)
-
-        removeReservedFromFreePool()
-        allocateCx16VirtualRegisters()
-        retainAllowed()
-    }
-
-    override fun allocateCx16VirtualRegisters() {
-        // Note: the 16 virtual registers R0-R15 are not regular allocated variables, they're *memory mapped* elsewhere to fixed addresses.
-        // However, to be able for the compiler to "see" them as zeropage variables, we have to register them here as well.
-        // This is important because the compiler sometimes treats ZP variables more efficiently (for example if it's a pointer)
-        for(reg in 0..15) {
-            allocatedVariables["cx16.r${reg}"]   = VarAllocation((2+reg*2).toUInt(), DataType.forDt(BaseDataType.UWORD), 2)       // cx16.r0 .. cx16.r15
-            allocatedVariables["cx16.r${reg}s"]  = VarAllocation((2+reg*2).toUInt(), DataType.forDt(BaseDataType.WORD), 2)        // cx16.r0s .. cx16.r15s
-            allocatedVariables["cx16.r${reg}L"]  = VarAllocation((2+reg*2).toUInt(), DataType.forDt(BaseDataType.UBYTE), 1)       // cx16.r0L .. cx16.r15L
-            allocatedVariables["cx16.r${reg}H"]  = VarAllocation((3+reg*2).toUInt(), DataType.forDt(BaseDataType.UBYTE), 1)       // cx16.r0H .. cx16.r15H
-            allocatedVariables["cx16.r${reg}sL"] = VarAllocation((2+reg*2).toUInt(), DataType.forDt(BaseDataType.BYTE), 1)        // cx16.r0sL .. cx16.r15sL
-            allocatedVariables["cx16.r${reg}sH"] = VarAllocation((3+reg*2).toUInt(), DataType.forDt(BaseDataType.BYTE), 1)        // cx16.r0sH .. cx16.r15sH
-        }
-    }
-}

codeCore/src/prog8/code/target/pet/PETMachineDefinition.kt

@@ -1,63 +0,0 @@
-package prog8.code.target.pet
-
-import prog8.code.core.*
-import prog8.code.target.C64Target
-import prog8.code.target.cbm.Mflpt5
-import java.nio.file.Path
-
-
-class PETMachineDefinition: IMachineDefinition {
-
-    override val cpu = CpuType.CPU6502
-
-    override val FLOAT_MAX_POSITIVE = Mflpt5.FLOAT_MAX_POSITIVE
-    override val FLOAT_MAX_NEGATIVE = Mflpt5.FLOAT_MAX_NEGATIVE
-    override val FLOAT_MEM_SIZE = Mflpt5.FLOAT_MEM_SIZE
-    override val STARTUP_CODE_RESERVED_SIZE = 20u
-    override val PROGRAM_LOAD_ADDRESS = 0x0401u
-    override val PROGRAM_MEMTOP_ADDRESS = 0x8000u
-
-    override val BSSHIGHRAM_START = 0u
-    override val BSSHIGHRAM_END = 0u
-    override val BSSGOLDENRAM_START = 0u
-    override val BSSGOLDENRAM_END = 0u
-
-    override lateinit var zeropage: Zeropage
-    override lateinit var golden: GoldenRam
-
-    override fun getFloatAsmBytes(num: Number) = Mflpt5.fromNumber(num).makeFloatFillAsm()
-
-    override fun convertFloatToBytes(num: Double): List<UByte> {
-        val m5 = Mflpt5.fromNumber(num)
-        return listOf(m5.b0, m5.b1, m5.b2, m5.b3, m5.b4)
-    }
-
-    override fun convertBytesToFloat(bytes: List<UByte>): Double {
-        require(bytes.size==5) { "need 5 bytes" }
-        val m5 = Mflpt5(bytes[0], bytes[1], bytes[2], bytes[3], bytes[4])
-        return m5.toDouble()
-    }
-
-    override fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path) {
-        if(selectedEmulator!=1) {
-            System.err.println("The pet target only supports the main emulator (Vice).")
-            return
-        }
-
-        println("\nStarting PET emulator...")
-        val viceMonlist = C64Target.viceMonListName(programNameWithPath.toString())
-        val cmdline = listOf("xpet", "-model", "4032", "-ramsize", "32", "-videosize", "40", "-silent", "-moncommands", viceMonlist,
-                "-autostartprgmode", "1", "-autostart-warp", "-autostart", "${programNameWithPath}.prg")
-        val processb = ProcessBuilder(cmdline).inheritIO()
-        val process=processb.start()
-        process.waitFor()
-    }
-
-    override fun isIOAddress(address: UInt): Boolean = address in 0xe800u..0xe8ffu
-
-    override fun initializeMemoryAreas(compilerOptions: CompilationOptions) {
-        zeropage = PETZeropage(compilerOptions)
-        // there's no golden ram.
-    }
-
-}

codeCore/src/prog8/code/target/virtual/VirtualMachineDefinition.kt

@@ -1,93 +0,0 @@
-package prog8.code.target.virtual
-
-import prog8.code.core.*
-import java.nio.file.Path
-import kotlin.io.path.isReadable
-import kotlin.io.path.name
-import kotlin.io.path.readText
-
-class VirtualMachineDefinition: IMachineDefinition {
-
-    override val cpu = CpuType.VIRTUAL
-
-    override val FLOAT_MAX_POSITIVE = Double.MAX_VALUE.toDouble()
-    override val FLOAT_MAX_NEGATIVE = -Double.MAX_VALUE.toDouble()
-    override val FLOAT_MEM_SIZE = 8             // 64-bits double
-    override val STARTUP_CODE_RESERVED_SIZE = 0u  // not actually used
-    override val PROGRAM_LOAD_ADDRESS = 0u      // not actually used
-    override val PROGRAM_MEMTOP_ADDRESS = 0xffffu  // not actually used
-
-    override val BSSHIGHRAM_START = 0u          // not actually used
-    override val BSSHIGHRAM_END = 0u            // not actually used
-    override val BSSGOLDENRAM_START = 0u        // not actually used
-    override val BSSGOLDENRAM_END = 0u          // not actually used
-    override lateinit var zeropage: Zeropage    // not actually used
-    override lateinit var golden: GoldenRam     // not actually used
-
-    override fun getFloatAsmBytes(num: Number): String {
-        // little endian binary representation
-        val bits = num.toDouble().toBits().toULong()
-        val hexStr = bits.toString(16).padStart(16, '0')
-        val parts = hexStr.chunked(2).map { "\$" + it }
-        return parts.joinToString(", ")
-    }
-
-    override fun convertFloatToBytes(num: Double): List<UByte> {
-        val bits = num.toBits().toULong()
-        val hexStr = bits.toString(16).padStart(16, '0')
-        val parts = hexStr.chunked(2).map { it.toInt(16).toUByte() }
-        return parts
-    }
-
-    override fun convertBytesToFloat(bytes: List<UByte>): Double {
-        require(bytes.size==8) { "need 8 bytes" }
-        val b0 = bytes[0].toLong() shl (8*7)
-        val b1 = bytes[1].toLong() shl (8*6)
-        val b2 = bytes[2].toLong() shl (8*5)
-        val b3 = bytes[3].toLong() shl (8*4)
-        val b4 = bytes[4].toLong() shl (8*3)
-        val b5 = bytes[5].toLong() shl (8*2)
-        val b6 = bytes[6].toLong() shl (8*1)
-        val b7 = bytes[7].toLong() shl (8*0)
-        return Double.fromBits(b0 or b1 or b2 or b3 or b4 or b5 or b6 or b7)
-    }
-
-    override fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path) {
-        println("\nStarting Virtual Machine...")
-        // to not have external module dependencies in our own module, we launch the virtual machine via reflection
-        val vm = Class.forName("prog8.vm.VmRunner").getDeclaredConstructor().newInstance() as IVirtualMachineRunner
-        val filename = programNameWithPath.name
-        if(programNameWithPath.isReadable()) {
-            vm.runProgram(programNameWithPath.readText())
-        } else {
-            val withExt = programNameWithPath.resolveSibling("$filename.p8ir")
-            if(withExt.isReadable())
-                vm.runProgram(withExt.readText())
-            else
-                throw NoSuchFileException(withExt.toFile(), reason="not a .p8ir file")
-        }
-    }
-
-    override fun isIOAddress(address: UInt): Boolean = false
-
-    override fun initializeMemoryAreas(compilerOptions: CompilationOptions) {
-        zeropage = VirtualZeropage(compilerOptions)
-    }
-}
-
-interface IVirtualMachineRunner {
-    fun runProgram(irSource: String)
-}
-
-private class VirtualZeropage(options: CompilationOptions): Zeropage(options) {
-    override val SCRATCH_B1: UInt
-        get() = throw IllegalStateException("virtual shouldn't use this zeropage variable")
-    override val SCRATCH_REG: UInt
-        get() = throw IllegalStateException("virtual shouldn't use this zeropage variable")
-    override val SCRATCH_W1: UInt
-        get() = throw IllegalStateException("virtual shouldn't use this zeropage variable")
-    override val SCRATCH_W2: UInt
-        get() = throw IllegalStateException("virtual shouldn't use this zeropage variable")
-
-    override fun allocateCx16VirtualRegisters() { /* there is no actual zero page in this target to allocate thing in */ }
-}

codeCore/src/prog8/code/target/zp/C128Zeropage.kt

@@ -1,4 +1,4 @@
-package prog8.code.target.c128
+package prog8.code.target.zp
 
 import prog8.code.core.CompilationOptions
 import prog8.code.core.InternalCompilerException
@@ -11,7 +11,7 @@ import prog8.code.core.ZeropageType
 class C128Zeropage(options: CompilationOptions) : Zeropage(options) {
 
     override val SCRATCH_B1 = 0x74u      // temp storage for a single byte
-    override val SCRATCH_REG = 0x75u     // temp storage for a register, must be B1+1
+    override val SCRATCH_REG = 0x75u     // temp storage for a register byte, must be B1+1
     override val SCRATCH_W1 = 0xfbu      // temp storage 1 for a word  $fb+$fc
     override val SCRATCH_W2 = 0xfdu      // temp storage 2 for a word  $fd+$fe
 
@@ -71,8 +71,4 @@ class C128Zeropage(options: CompilationOptions) : Zeropage(options) {
         removeReservedFromFreePool()
         retainAllowed()
     }
-
-    override fun allocateCx16VirtualRegisters() {
-        TODO("Not known if C128 can put the virtual regs in ZP")
-    }
 }

codeCore/src/prog8/code/target/zp/C64Zeropage.kt

@@ -1,4 +1,4 @@
-package prog8.code.target.c64
+package prog8.code.target.zp
 
 import prog8.code.core.*
 
@@ -6,7 +6,7 @@ import prog8.code.core.*
 class C64Zeropage(options: CompilationOptions) : Zeropage(options) {
 
     override val SCRATCH_B1 = 0x02u      // temp storage for a single byte
-    override val SCRATCH_REG = 0x03u     // temp storage for a register, must be B1+1
+    override val SCRATCH_REG = 0x03u     // temp storage for a register byte, must be B1+1
     override val SCRATCH_W1 = 0xfbu      // temp storage 1 for a word  $fb+$fc
     override val SCRATCH_W2 = 0xfdu      // temp storage 2 for a word  $fd+$fe
 
@@ -79,7 +79,7 @@ class C64Zeropage(options: CompilationOptions) : Zeropage(options) {
         retainAllowed()
     }
 
-    override fun allocateCx16VirtualRegisters() {
+    private fun allocateCx16VirtualRegisters() {
         // Note: the 16 virtual registers R0-R15 are not regular allocated variables, they're *memory mapped* elsewhere to fixed addresses.
         // However, to be able for the compiler to "see" them as zeropage variables, we have to register them here as well.
         // This is important because the compiler sometimes treats ZP variables more efficiently (for example if it's a pointer)

codeCore/src/prog8/code/target/zp/CX16Zeropage.kt

@@ -1,4 +1,4 @@
-package prog8.code.target.cx16
+package prog8.code.target.zp
 
 import prog8.code.core.*
 
@@ -6,7 +6,7 @@ import prog8.code.core.*
 class CX16Zeropage(options: CompilationOptions) : Zeropage(options) {
 
     override val SCRATCH_B1 = 0x7au      // temp storage for a single byte
-    override val SCRATCH_REG = 0x7bu     // temp storage for a register, must be B1+1
+    override val SCRATCH_REG = 0x7bu     // temp storage for a register byte, must be B1+1
     override val SCRATCH_W1 = 0x7cu      // temp storage 1 for a word  $7c+$7d
     override val SCRATCH_W2 = 0x7eu      // temp storage 2 for a word  $7e+$7f
 
@@ -52,7 +52,7 @@ class CX16Zeropage(options: CompilationOptions) : Zeropage(options) {
         }
     }
 
-    override fun allocateCx16VirtualRegisters() {
+    private fun allocateCx16VirtualRegisters() {
         // Note: the 16 virtual registers R0-R15 are not regular allocated variables, they're *memory mapped* elsewhere to fixed addresses.
         // However, to be able for the compiler to "see" them as zeropage variables, we have to register them here as well.
         // This is important because the compiler sometimes treats ZP variables more efficiently (for example if it's a pointer)

codeCore/src/prog8/code/target/zp/ConfigurableZeropage.kt

@@ -0,0 +1,58 @@
+package prog8.code.target.zp
+
+import prog8.code.core.*
+
+class ConfigurableZeropage(
+    override val SCRATCH_B1: UInt,      // temp storage for a single byte
+    override val SCRATCH_REG: UInt,     // temp storage for a register byte, must be B1+1
+    override val SCRATCH_W1: UInt,      // temp storage 1 for a word
+    override val SCRATCH_W2: UInt,      // temp storage 2 for a word
+    val virtualRegistersStart: UInt,        // location of 32 bytes for the r0-r15 virtual registers
+    basicsafe: List<UIntRange>,
+    kernalsafe: List<UIntRange>,
+    fullsafe: List<UIntRange>,
+    options: CompilationOptions
+) : Zeropage(options) {
+
+    init {
+        if (options.floats) {
+            TODO("floats")
+        }
+
+        if(SCRATCH_REG!=SCRATCH_B1+1u)
+            throw IllegalArgumentException("Zero page scratch variable REG should be B1+1")
+
+        when (options.zeropage) {
+            ZeropageType.DONTUSE -> { /* don't use any zeropage at all */ }
+            ZeropageType.FULL -> fullsafe.forEach { free.addAll(it) }
+            ZeropageType.BASICSAFE -> basicsafe.forEach { free.addAll(it) }
+            ZeropageType.KERNALSAFE -> kernalsafe.forEach { free.addAll(it) }
+            ZeropageType.FLOATSAFE -> TODO("floatsafe")
+        }
+
+        val distinctFree = free.distinct()
+        free.clear()
+        free.addAll(distinctFree)
+
+        removeReservedFromFreePool()
+        allocateCx16VirtualRegisters()
+        retainAllowed()
+    }
+
+    private fun allocateCx16VirtualRegisters() {
+        // Note: the 16 virtual registers R0-R15 are not regular allocated variables, they're *memory mapped* elsewhere to fixed addresses.
+        // However, to be able for the compiler to "see" them as zeropage variables, we have to register them here as well.
+        // This is important because the compiler sometimes treats ZP variables more efficiently (for example if it's a pointer)
+        for(reg in 0..15) {
+            val address = virtualRegistersStart + (2*reg).toUInt()
+            if(address<=0xffu) {
+                allocatedVariables["cx16.r${reg}"]   = VarAllocation(address, DataType.forDt(BaseDataType.UWORD), 2)       // cx16.r0 .. cx16.r15
+                allocatedVariables["cx16.r${reg}s"]  = VarAllocation(address, DataType.forDt(BaseDataType.WORD), 2)        // cx16.r0s .. cx16.r15s
+                allocatedVariables["cx16.r${reg}L"]  = VarAllocation(address, DataType.forDt(BaseDataType.UBYTE), 1)       // cx16.r0L .. cx16.r15L
+                allocatedVariables["cx16.r${reg}H"]  = VarAllocation(address+1u, DataType.forDt(BaseDataType.UBYTE), 1)    // cx16.r0H .. cx16.r15H
+                allocatedVariables["cx16.r${reg}sL"] = VarAllocation(address, DataType.forDt(BaseDataType.BYTE), 1)        // cx16.r0sL .. cx16.r15sL
+                allocatedVariables["cx16.r${reg}sH"] = VarAllocation(address+1u, DataType.forDt(BaseDataType.BYTE), 1)     // cx16.r0sH .. cx16.r15sH
+            }
+        }
+    }
+}

codeCore/src/prog8/code/target/zp/PETZeropage.kt

@@ -1,4 +1,4 @@
-package prog8.code.target.pet
+package prog8.code.target.zp
 
 import prog8.code.core.CompilationOptions
 import prog8.code.core.InternalCompilerException
@@ -11,7 +11,7 @@ import prog8.code.core.ZeropageType
 class PETZeropage(options: CompilationOptions) : Zeropage(options) {
 
     override val SCRATCH_B1 = 0xb3u      // temp storage for a single byte
-    override val SCRATCH_REG = 0xb4u     // temp storage for a register, must be B1+1
+    override val SCRATCH_REG = 0xb4u     // temp storage for a register byte, must be B1+1
     override val SCRATCH_W1 = 0xb6u      // temp storage 1 for a word
     override val SCRATCH_W2 = 0xb8u      // temp storage 2 for a word
 
@@ -52,8 +52,4 @@ class PETZeropage(options: CompilationOptions) : Zeropage(options) {
         removeReservedFromFreePool()
         retainAllowed()
     }
-
-    override fun allocateCx16VirtualRegisters() {
-        TODO("Not known if PET can put the virtual regs in ZP")
-    }
 }

codeGenCpu6502/build.gradle.kts

@@ -8,7 +8,7 @@ dependencies {
     implementation(project(":codeCore"))
     // implementation("org.jetbrains.kotlin:kotlin-stdlib-jdk8")
     // implementation "org.jetbrains.kotlin:kotlin-reflect"
-    implementation("com.michael-bull.kotlin-result:kotlin-result-jvm:2.0.0")
+    implementation("com.michael-bull.kotlin-result:kotlin-result-jvm:2.0.1")
 
     testImplementation("io.kotest:kotest-runner-junit5-jvm:5.9.1")
     testImplementation("io.kotest:kotest-framework-datatest:5.9.1")
@@ -43,4 +43,4 @@ tasks.test {
     testLogging {
         events("skipped", "failed")
     }
-}
+}

codeGenCpu6502/src/prog8/codegen/cpu6502/AsmGen.kt

@@ -219,7 +219,7 @@ class AsmGen6502Internal (
     internal val optimizedByteMultiplications = arrayOf(3,5,6,7,9,10,11,12,13,14,15,20,25,40,50,80,100)
     internal val optimizedWordMultiplications = arrayOf(3,5,6,7,9,10,12,15,20,25,40,50,80,100,320,640)
     internal val loopEndLabels = ArrayDeque<String>()
-    private val zeropage = options.compTarget.machine.zeropage
+    private val zeropage = options.compTarget.zeropage
     private val allocator = VariableAllocator(symbolTable, options, errors)
     private val assembly = mutableListOf<String>()
     private val breakpointLabels = mutableListOf<String>()
@@ -251,7 +251,7 @@ class AsmGen6502Internal (
                 }
             }
             if(options.optimize) {
-                while(optimizeAssembly(asmLines, options.compTarget.machine, symbolTable)>0) {
+                while(optimizeAssembly(asmLines, options.compTarget, symbolTable)>0) {
                     // optimize the assembly source code
                 }
                 output.writeLines(asmLines)
@@ -272,33 +272,15 @@ class AsmGen6502Internal (
 
     private fun dumpVariables() {
         println("---- VARIABLES DUMP ----")
-        if(allocator.globalFloatConsts.isNotEmpty()) {
-            println("Floats:")
-            allocator.globalFloatConsts.forEach { (value, name) ->
-                println("  $name = $value")
-            }
-        }
-        if(symbolTable.allMemorySlabs.isNotEmpty()) {
-            println("Memory slabs:")
-            symbolTable.allMemorySlabs.sortedBy { it.name }.forEach { slab ->
-                println("  ${slab.name}  ${slab.size}  align ${slab.align}")
-            }
-        }
-        if(symbolTable.allMemMappedVariables.isNotEmpty()) {
-            println("Memory mapped:")
-            symbolTable.allMemMappedVariables
-                .sortedWith( compareBy( {it.address}, {it.scopedName} ))
-                .forEach { mvar ->
-                    println("  ${'$'}${mvar.address.toString(16).padStart(4, '0')}\t${mvar.dt}\t${mvar.scopedName}")
-                }
-        }
         if(allocator.zeropageVars.isNotEmpty()) {
             println("ZeroPage:")
-            allocator.zeropageVars
-                .asSequence()
-                .sortedWith( compareBy( {it.value.address}, {it.key} ))
-                .forEach { (name, alloc) ->
-                    println("  ${'$'}${alloc.address.toString(16).padStart(2, '0')}\t${alloc.dt}\t$name")
+            val allvars = allocator.zeropageVars.map { (name, alloc) -> Triple(name, alloc.address, alloc.dt) } + symbolTable.allMemMappedVariables.map { Triple(it.name, it.address, it.dt) }
+            allvars
+                .filter { it.second in 0u..255u }
+                .distinct()
+                .sortedWith( compareBy( {it.second}, {it.first} ))
+                .forEach {
+                    println("  $${it.second.toString(16).padStart(2, '0')}\t${it.third}\t${it.first}")
                 }
         }
         if(symbolTable.allVariables.isNotEmpty()) {
@@ -309,6 +291,26 @@ class AsmGen6502Internal (
                     println("  ${it.dt}\t${it.scopedName}\t")
                 }
         }
+        if(allocator.globalFloatConsts.isNotEmpty()) {
+            println("Floats:")
+            allocator.globalFloatConsts.forEach { (value, name) ->
+                println("  $name = $value")
+            }
+        }
+        if(symbolTable.allMemMappedVariables.isNotEmpty()) {
+            println("Memory mapped:")
+            symbolTable.allMemMappedVariables
+                .sortedWith( compareBy( {it.address}, {it.scopedName} ))
+                .forEach { mvar ->
+                    println("  $${mvar.address.toString(16).padStart(4, '0')}\t${mvar.dt}\t${mvar.scopedName}")
+                }
+        }
+        if(symbolTable.allMemorySlabs.isNotEmpty()) {
+            println("Memory slabs:")
+            symbolTable.allMemorySlabs.sortedBy { it.name }.forEach { slab ->
+                println("  ${slab.name}  ${slab.size}  align ${slab.align}")
+            }
+        }
         println("---- VARIABLES DUMP END ----")
     }
 
@@ -328,7 +330,7 @@ class AsmGen6502Internal (
         }
     }
 
-    internal fun isTargetCpu(cpu: CpuType) = options.compTarget.machine.cpu == cpu
+    internal fun isTargetCpu(cpu: CpuType) = options.compTarget.cpu == cpu
 
     private var lastSourceLineNumber: Int = -1
 
@@ -428,7 +430,7 @@ class AsmGen6502Internal (
             }
             is PtVariable, is PtMemMapped -> {
                 val sourceName = asmVariableName(pointervar)
-                if (isTargetCpu(CpuType.CPU65c02)) {
+                if (isTargetCpu(CpuType.CPU65C02)) {
                     return if (allocator.isZpVar((target as PtNamedNode).scopedName)) {
                         // pointervar is already in the zero page, no need to copy
                         out("  lda  ($sourceName)")
@@ -465,7 +467,7 @@ class AsmGen6502Internal (
 
     internal fun storeAIntoPointerVar(pointervar: PtIdentifier) {
         val sourceName = asmVariableName(pointervar)
-        if (isTargetCpu(CpuType.CPU65c02)) {
+        if (isTargetCpu(CpuType.CPU65C02)) {
             if (allocator.isZpVar(pointervar.name)) {
                 // pointervar is already in the zero page, no need to copy
                 out("  sta  ($sourceName)")
@@ -494,7 +496,7 @@ class AsmGen6502Internal (
     }
 
     internal fun storeAIntoZpPointerVar(zpPointerVar: String, keepY: Boolean) {
-        if (isTargetCpu(CpuType.CPU65c02))
+        if (isTargetCpu(CpuType.CPU65C02))
             out("  sta  ($zpPointerVar)")
         else {
             if(keepY)
@@ -505,7 +507,7 @@ class AsmGen6502Internal (
     }
 
     internal fun loadAFromZpPointerVar(zpPointerVar: String, keepY: Boolean) {
-        if (isTargetCpu(CpuType.CPU65c02))
+        if (isTargetCpu(CpuType.CPU65C02))
             out("  lda  ($zpPointerVar)")
         else {
             if(keepY)
@@ -524,7 +526,7 @@ class AsmGen6502Internal (
         when (register) {
             CpuRegister.A -> out("  pha")
             CpuRegister.X -> {
-                if (isTargetCpu(CpuType.CPU65c02)) out("  phx")
+                if (isTargetCpu(CpuType.CPU65C02)) out("  phx")
                 else {
                     if(keepA)
                         out("  sta  P8ZP_SCRATCH_REG |  txa |  pha  |  lda  P8ZP_SCRATCH_REG")
@@ -533,7 +535,7 @@ class AsmGen6502Internal (
                 }
             }
             CpuRegister.Y -> {
-                if (isTargetCpu(CpuType.CPU65c02)) out("  phy")
+                if (isTargetCpu(CpuType.CPU65C02)) out("  phy")
                 else {
                     if(keepA)
                         out("  sta  P8ZP_SCRATCH_REG |  tya |  pha  |  lda  P8ZP_SCRATCH_REG")
@@ -552,7 +554,7 @@ class AsmGen6502Internal (
                 out("  pla")
             }
             CpuRegister.X -> {
-                if (isTargetCpu(CpuType.CPU65c02)) out("  plx")
+                if (isTargetCpu(CpuType.CPU65C02)) out("  plx")
                 else {
                     if(keepA)
                         out("  sta  P8ZP_SCRATCH_REG |  pla |  tax |  lda  P8ZP_SCRATCH_REG")
@@ -561,7 +563,7 @@ class AsmGen6502Internal (
                 }
             }
             CpuRegister.Y -> {
-                if (isTargetCpu(CpuType.CPU65c02)) out("  ply")
+                if (isTargetCpu(CpuType.CPU65C02)) out("  ply")
                 else {
                     if(keepA)
                         out("  sta  P8ZP_SCRATCH_REG |  pla |  tay |  lda  P8ZP_SCRATCH_REG")
@@ -604,6 +606,7 @@ class AsmGen6502Internal (
             is PtBlock -> throw AssemblyError("block should have been handled elsewhere")
             is PtDefer -> throw AssemblyError("defer should have been transformed")
             is PtNodeGroup -> stmt.children.forEach { translate(it) }
+            is PtJmpTable -> translate(stmt)
             is PtNop -> {}
             else -> throw AssemblyError("missing asm translation for $stmt")
         }
@@ -640,7 +643,7 @@ class AsmGen6502Internal (
                 }
             }
             expr.type.isFloat -> {
-                require(options.compTarget.machine.FLOAT_MEM_SIZE == 5) {"invalid float size ${expr.position}"}
+                require(options.compTarget.FLOAT_MEM_SIZE == 5) {"invalid float size ${expr.position}"}
                 assignExpressionToRegister(expr.index, RegisterOrPair.A, false)
                 out("""
                     sta  P8ZP_SCRATCH_REG
@@ -731,7 +734,7 @@ class AsmGen6502Internal (
                 translateNormalAssignment(
                     AsmAssignment(
                         AsmAssignSource(SourceStorageKind.REGISTER, program, this, target.datatype, register=RegisterOrPair.AY),
-                        target, program.memsizer, value.position
+                            listOf(target), program.memsizer, value.position
                     ), value.definingISub()
                 )
             }
@@ -820,7 +823,7 @@ class AsmGen6502Internal (
     private fun repeatWordCount(iterations: Int, stmt: PtRepeatLoop) {
         require(iterations in 257..65536) { "invalid repeat count ${stmt.position}" }
         val repeatLabel = makeLabel("repeat")
-        val counterVar = createRepeatCounterVar(BaseDataType.UWORD, isTargetCpu(CpuType.CPU65c02), stmt)
+        val counterVar = createRepeatCounterVar(BaseDataType.UWORD, isTargetCpu(CpuType.CPU65C02), stmt)
         val loopcount = if(iterations==65536) 0 else if(iterations and 0x00ff == 0) iterations else iterations + 0x0100   // so that the loop can simply use a double-dec
         out("""
             ldy  #>$loopcount
@@ -862,7 +865,7 @@ $repeatLabel""")
     private fun repeatByteCount(count: Int, stmt: PtRepeatLoop) {
         require(count in 2..256) { "invalid repeat count ${stmt.position}" }
         val repeatLabel = makeLabel("repeat")
-        if(isTargetCpu(CpuType.CPU65c02)) {
+        if(isTargetCpu(CpuType.CPU65C02)) {
             val counterVar = createRepeatCounterVar(BaseDataType.UBYTE, true, stmt)
             out("  lda  #${count and 255} |  sta  $counterVar")
             out(repeatLabel)
@@ -880,7 +883,7 @@ $repeatLabel""")
     private fun repeatCountInY(stmt: PtRepeatLoop, endLabel: String) {
         val repeatLabel = makeLabel("repeat")
         out("  cpy  #0")
-        if(isTargetCpu(CpuType.CPU65c02)) {
+        if(isTargetCpu(CpuType.CPU65C02)) {
             val counterVar = createRepeatCounterVar(BaseDataType.UBYTE, true, stmt)
             out("  beq  $endLabel |  sty  $counterVar")
             out(repeatLabel)
@@ -961,8 +964,7 @@ $repeatLabel""")
                         bne  +
                         cpy  #>${value.toHex()}
                         beq  $choiceLabel
-+
-                        """)
++""")
                     }
                 }
             }
@@ -981,6 +983,14 @@ $repeatLabel""")
         out(stmt.name)
     }
 
+    private fun translate(stmt: PtJmpTable) {
+        out("  ; jumptable")
+        for(name in stmt.children) {
+            out("  jmp  ${asmSymbolName((name as PtIdentifier).name)}")
+        }
+        out("  ; end jumptable")
+    }
+
     private fun translate(stmt: PtConditionalBranch) {
         if(stmt.trueScope.children.isEmpty() && stmt.falseScope.children.isNotEmpty())
             throw AssemblyError("only else part contains code, shoud have been switched already")
@@ -1052,18 +1062,26 @@ $repeatLabel""")
     }
 
     private fun translate(ret: PtReturn) {
-        ret.value?.let { returnvalue ->
+        val returnvalue = ret.children.singleOrNull()
+        if(returnvalue!=null) {
             val sub = ret.definingSub()!!
-            val returnReg = sub.returnRegister()!!
-            if (sub.returntype?.isNumericOrBool==true) {
-                assignExpressionToRegister(returnvalue, returnReg.registerOrPair!!)
+            val returnReg = sub.returnsWhatWhere().single()
+            if (sub.returns.single().isNumericOrBool==true) {
+                assignExpressionToRegister(returnvalue as PtExpression, returnReg.first.registerOrPair!!)
             }
             else {
                 // all else take its address and assign that also to AY register pair
                 val addrofValue = PtAddressOf(returnvalue.position)
                 addrofValue.add(returnvalue as PtIdentifier)
                 addrofValue.parent = ret.parent
-                assignmentAsmGen.assignExpressionToRegister(addrofValue, returnReg.registerOrPair!!, false)
+                assignmentAsmGen.assignExpressionToRegister(addrofValue, returnReg.first.registerOrPair!!, false)
+            }
+        }
+        else if(ret.children.size>1) {
+            // multi-value returns are passed throug cx16.R15 down to R0 (allows unencumbered use of many Rx registers if you don't return that many values)
+            val registersReverseOrder = Cx16VirtualRegisters.reversed()
+            ret.children.zip(registersReverseOrder).forEach { (value, register) ->
+                assignExpressionToRegister(value as PtExpression, register)
             }
         }
         out("  rts")
@@ -1109,8 +1127,21 @@ $repeatLabel""")
                 cmp  #$80
                 bcc  +
                 dey
-+
-            """)
++""")
+            else -> throw AssemblyError("need byte type")
+        }
+    }
+
+    internal fun signExtendAXlsb(valueDt: BaseDataType) {
+        // sign extend signed byte in A to full word in AX
+        when(valueDt) {
+            BaseDataType.UBYTE -> out("  ldx  #0")
+            BaseDataType.BYTE -> out("""
+                ldx  #0
+                cmp  #$80
+                bcc  +
+                dex
++""")
             else -> throw AssemblyError("need byte type")
         }
     }
@@ -1119,7 +1150,7 @@ $repeatLabel""")
         // sign extend signed byte in a var to a full word in that variable
         when(valueDt) {
             BaseDataType.UBYTE -> {
-                if(isTargetCpu(CpuType.CPU65c02))
+                if(isTargetCpu(CpuType.CPU65C02))
                     out("  stz  $asmvar+1")
                 else
                     out("  lda  #0 |  sta  $asmvar+1")
@@ -1142,19 +1173,20 @@ $repeatLabel""")
         if(indirect) {
             out("  jmp  ($asmLabel)")
         } else {
-            if (isTargetCpu(CpuType.CPU65c02))
+            if (isTargetCpu(CpuType.CPU65C02))
                 out("  bra  $asmLabel")     // note: 64tass will convert this automatically to a jmp if the relative distance is too large
             else
                 out("  jmp  $asmLabel")
         }
     }
 
-    internal fun pointerViaIndexRegisterPossible(pointerOffsetExpr: PtExpression): Pair<PtExpression, PtExpression>? {
+    internal fun pointerViaIndexRegisterPossible(pointerOffsetExpr: PtExpression, allowNegativeIndex: Boolean=false): Pair<PtExpression, PtExpression>? {
         if (pointerOffsetExpr !is PtBinaryExpression) return null
         val operator = pointerOffsetExpr.operator
         val left = pointerOffsetExpr.left
         val right = pointerOffsetExpr.right
-        if (operator != "+") return null
+        if (operator != "+" && (operator != "-" || !allowNegativeIndex))
+            return null
         val leftDt = left.type
         val rightDt = right.type
         if(leftDt.isUnsignedWord && rightDt.isUnsignedByte)
@@ -1197,70 +1229,162 @@ $repeatLabel""")
         }
 
         if(addressExpr.operator=="+") {
-            val ptrAndIndex = pointerViaIndexRegisterPossible(addressExpr)
-            if(ptrAndIndex!=null) {
+            val ptrAndIndex = pointerViaIndexRegisterPossible(addressExpr, false)
+            if (ptrAndIndex == null) return false
+
+            if(write) {
+
+                // WRITING TO pointer + offset
+
+                val addrOf = ptrAndIndex.first as? PtAddressOf
+                val constOffset = (ptrAndIndex.second as? PtNumber)?.number?.toInt()
+                if(addrOf!=null && constOffset!=null) {
+                    if(addrOf.isFromArrayElement) {
+                        TODO("address-of array element $addrOf")
+                    } else {
+                        out("  sta  ${asmSymbolName(addrOf.identifier)}+${constOffset}")
+                        return true
+                    }
+                }
+
                 val pointervar = ptrAndIndex.first as? PtIdentifier
-                val target = if(pointervar==null) null else symbolTable.lookup(pointervar.name)!!.astNode
-                when(target) {
-                    is PtLabel -> {
+                if(pointervar!=null && isZpVar(pointervar)) {
+                    val saveA = evalBytevalueWillClobberA(ptrAndIndex.second)
+                    if(saveA) out("  pha")
+                    assignExpressionToRegister(ptrAndIndex.second, RegisterOrPair.Y)
+                    if(saveA) out("  pla")
+                    out("  sta  (${asmSymbolName(pointervar)}),y")
+                } else {
+                    // copy the pointer var to zp first
+                    val saveA = evalBytevalueWillClobberA(ptrAndIndex.first) || evalBytevalueWillClobberA(ptrAndIndex.second)
+                    if(saveA) out("  pha")
+                    if(ptrAndIndex.second.isSimple()) {
+                        assignExpressionToVariable(ptrAndIndex.first, "P8ZP_SCRATCH_W2", DataType.forDt(BaseDataType.UWORD))
                         assignExpressionToRegister(ptrAndIndex.second, RegisterOrPair.Y)
-                        out("  lda  ${asmSymbolName(pointervar!!)},y")
-                        return true
+                        if(saveA) out("  pla")
+                        out("  sta  (P8ZP_SCRATCH_W2),y")
+                    } else {
+                        pushCpuStack(BaseDataType.UBYTE,  ptrAndIndex.second)
+                        assignExpressionToVariable(ptrAndIndex.first, "P8ZP_SCRATCH_W2", DataType.forDt(BaseDataType.UWORD))
+                        restoreRegisterStack(CpuRegister.Y, true)
+                        if(saveA) out("  pla")
+                        out("  sta  (P8ZP_SCRATCH_W2),y")
                     }
-                    is IPtVariable, null -> {
-                        if(write) {
-                            if(pointervar!=null && isZpVar(pointervar)) {
-                                val saveA = evalBytevalueWillClobberA(ptrAndIndex.second)
-                                if(saveA)
-                                    out("  pha")
-                                assignExpressionToRegister(ptrAndIndex.second, RegisterOrPair.Y)
-                                if(saveA)
-                                    out("  pla")
-                                out("  sta  (${asmSymbolName(pointervar)}),y")
-                            } else {
-                                // copy the pointer var to zp first
-                                val saveA = evalBytevalueWillClobberA(ptrAndIndex.first) || evalBytevalueWillClobberA(ptrAndIndex.second)
-                                if(saveA)
-                                    out("  pha")
-                                if(ptrAndIndex.second.isSimple()) {
-                                    assignExpressionToVariable(ptrAndIndex.first, "P8ZP_SCRATCH_W2", DataType.forDt(BaseDataType.UWORD))
-                                    assignExpressionToRegister(ptrAndIndex.second, RegisterOrPair.Y)
-                                    if(saveA)
-                                        out("  pla")
-                                    out("  sta  (P8ZP_SCRATCH_W2),y")
-                                } else {
-                                    pushCpuStack(BaseDataType.UBYTE,  ptrAndIndex.second)
-                                    assignExpressionToVariable(ptrAndIndex.first, "P8ZP_SCRATCH_W2", DataType.forDt(BaseDataType.UWORD))
-                                    restoreRegisterStack(CpuRegister.Y, true)
-                                    if(saveA)
-                                        out("  pla")
-                                    out("  sta  (P8ZP_SCRATCH_W2),y")
-                                }
-                            }
+                }
+                return true
+            }
+
+            // READING FROM pointer + offset
+
+            val addrOf = ptrAndIndex.first as? PtAddressOf
+            val constOffset = (ptrAndIndex.second as? PtNumber)?.number?.toInt()
+            if(addrOf!=null && constOffset!=null) {
+                if(addrOf.isFromArrayElement) {
+                    TODO("address-of array element $addrOf")
+                } else {
+                    out("  lda  ${asmSymbolName(addrOf.identifier)}+${constOffset}")
+                    return true
+                }
+            }
+
+            val pointervar = ptrAndIndex.first as? PtIdentifier
+            val targetVariable = if(pointervar==null) null else symbolTable.lookup(pointervar.name)!!.astNode
+            when(targetVariable) {
+                is PtLabel -> {
+                    assignExpressionToRegister(ptrAndIndex.second, RegisterOrPair.Y)
+                    out("  lda  ${asmSymbolName(pointervar!!)},y")
+                    return true
+                }
+                is IPtVariable, null -> {
+                    if(pointervar!=null && isZpVar(pointervar)) {
+                        assignExpressionToRegister(ptrAndIndex.second, RegisterOrPair.Y)
+                        out("  lda  (${asmSymbolName(pointervar)}),y")
+                    } else {
+                        // copy the pointer var to zp first
+                        if(ptrAndIndex.second.isSimple()) {
+                            assignExpressionToVariable(ptrAndIndex.first, "P8ZP_SCRATCH_W2", DataType.forDt(BaseDataType.UWORD))
+                            assignExpressionToRegister(ptrAndIndex.second, RegisterOrPair.Y)
+                            out("  lda  (P8ZP_SCRATCH_W2),y")
                         } else {
-                            if(pointervar!=null && isZpVar(pointervar)) {
-                                assignExpressionToRegister(ptrAndIndex.second, RegisterOrPair.Y)
-                                out("  lda  (${asmSymbolName(pointervar)}),y")
-                            } else {
-                                // copy the pointer var to zp first
-                                if(ptrAndIndex.second.isSimple()) {
-                                    assignExpressionToVariable(ptrAndIndex.first, "P8ZP_SCRATCH_W2", DataType.forDt(BaseDataType.UWORD))
-                                    assignExpressionToRegister(ptrAndIndex.second, RegisterOrPair.Y)
-                                    out("  lda  (P8ZP_SCRATCH_W2),y")
-                                } else {
-                                    pushCpuStack(BaseDataType.UBYTE, ptrAndIndex.second)
-                                    assignExpressionToVariable(ptrAndIndex.first, "P8ZP_SCRATCH_W2", DataType.forDt(BaseDataType.UWORD))
-                                    restoreRegisterStack(CpuRegister.Y, false)
-                                    out("  lda  (P8ZP_SCRATCH_W2),y")
-                                }
-                            }
+                            pushCpuStack(BaseDataType.UBYTE, ptrAndIndex.second)
+                            assignExpressionToVariable(ptrAndIndex.first, "P8ZP_SCRATCH_W2", DataType.forDt(BaseDataType.UWORD))
+                            restoreRegisterStack(CpuRegister.Y, false)
+                            out("  lda  (P8ZP_SCRATCH_W2),y")
                         }
+                    }
+                    return true
+                }
+                else -> throw AssemblyError("invalid pointervar $pointervar")
+            }
+        }
+
+        else if(addressExpr.operator=="-") {
+            val ptrAndIndex = pointerViaIndexRegisterPossible(addressExpr, true)
+            if (ptrAndIndex == null) return false
+
+            if(write) {
+
+                // WRITING TO pointer - offset
+
+                val addrOf = ptrAndIndex.first as? PtAddressOf
+                val constOffset = (ptrAndIndex.second as? PtNumber)?.number?.toInt()
+                if(addrOf!=null && constOffset!=null) {
+                    if(addrOf.isFromArrayElement) {
+                        TODO("address-of array element $addrOf")
+                    } else {
+                        out("  sta  ${asmSymbolName(addrOf.identifier)}-${constOffset}")
+                        return true
+                    }
+                }
+
+                if(constOffset!=null) {
+                    val pointervar = ptrAndIndex.first as? PtIdentifier
+                    if(pointervar!=null && isZpVar(pointervar)) {
+                        val varname = asmSymbolName(pointervar)
+                        out("  ldy  #${256-constOffset}     ; negative offset $constOffset")
+                        out("  dec  $varname+1 |  sta  ($varname),y |  inc  $varname+1")        // temporarily make MSB 1 less
+                        return true
+                    } else {
+                        // copy the pointer var to zp first
+                        assignExpressionToVariable(ptrAndIndex.first, "P8ZP_SCRATCH_W2", DataType.forDt(BaseDataType.UWORD))
+                        out("  ldy  #${256-constOffset}     ; negative offset $constOffset")
+                        out("  dec  P8ZP_SCRATCH_W2+1 |  sta  (P8ZP_SCRATCH_W2),y |  inc  P8ZP_SCRATCH_W2+1")        // temporarily make MSB 1 less
+                        return true
+                    }
+                }
+            } else {
+
+                // READING FROM pointer - offset
+
+                val addrOf = ptrAndIndex.first as? PtAddressOf
+                val constOffset = (ptrAndIndex.second as? PtNumber)?.number?.toInt()
+                if(addrOf!=null && constOffset!=null) {
+                    if(addrOf.isFromArrayElement) {
+                        TODO("address-of array element $addrOf")
+                    } else {
+                        out("  lda  ${asmSymbolName(addrOf.identifier)}-${constOffset}")
+                        return true
+                    }
+                }
+
+                if(constOffset!=null) {
+                    val pointervar = ptrAndIndex.first as? PtIdentifier
+                    if(pointervar!=null && isZpVar(pointervar)) {
+                        val varname = asmSymbolName(pointervar)
+                        out("  ldy  #${256-constOffset}     ; negative offset $constOffset")
+                        out("  dec  $varname+1 |  lda  ($varname),y |  inc  $varname+1")        // temporarily make MSB 1 less
+                        return true
+                    } else {
+                        // copy the pointer var to zp first
+                        assignExpressionToVariable(ptrAndIndex.first, "P8ZP_SCRATCH_W2", DataType.forDt(BaseDataType.UWORD))
+                        out("  ldy  #${256-constOffset}     ; negative offset $constOffset")
+                        out("  dec  P8ZP_SCRATCH_W2+1 |  lda  (P8ZP_SCRATCH_W2),y |  inc  P8ZP_SCRATCH_W2+1")        // temporarily make MSB 1 less
                         return true
                     }
-                    else -> throw AssemblyError("invalid pointervar $pointervar")
                 }
             }
         }
+
         return false
     }
 
@@ -1299,7 +1423,7 @@ $repeatLabel""")
 
         fun assignViaExprEval() {
             assignExpressionToVariable(expr.address, "P8ZP_SCRATCH_W2", DataType.forDt(BaseDataType.UWORD))
-            if (isTargetCpu(CpuType.CPU65c02)) {
+            if (isTargetCpu(CpuType.CPU65C02)) {
                 out("  lda  (P8ZP_SCRATCH_W2)")
             } else {
                 out("  ldy  #0 |  lda  (P8ZP_SCRATCH_W2),y")
@@ -1332,7 +1456,7 @@ $repeatLabel""")
             out("  pha")
         } else if(dt.isWord) {
             assignExpressionToRegister(value, RegisterOrPair.AY, signed)
-            if (isTargetCpu(CpuType.CPU65c02))
+            if (isTargetCpu(CpuType.CPU65C02))
                 out("  pha |  phy")
             else
                 out("  pha |  tya |  pha")
@@ -1437,7 +1561,7 @@ $repeatLabel""")
     }
 
     internal fun immediateAndInplace(name: String, value: Int) {
-        if(isTargetCpu(CpuType.CPU65c02)) {
+        if(isTargetCpu(CpuType.CPU65C02)) {
             out(" lda  #${value xor 255} |  trb  $name")     // reset bit
         } else  {
             out(" lda  $name |  and  #$value |  sta  $name")
@@ -1445,7 +1569,7 @@ $repeatLabel""")
     }
 
     internal fun immediateOrInplace(name: String, value: Int) {
-        if(isTargetCpu(CpuType.CPU65c02)) {
+        if(isTargetCpu(CpuType.CPU65C02)) {
             out(" lda  #$value |  tsb  $name")       // set bit
         } else  {
             out(" lda  $name |  ora  #$value |  sta  $name")
@@ -1556,6 +1680,30 @@ $repeatLabel""")
             }
         }
     }
+
+    internal fun checkIfConditionCanUseBIT(condition: PtBinaryExpression): Triple<Boolean, PtIdentifier, Int>? {
+        if(condition.operator == "==" || condition.operator == "!=") {
+            if (condition.right.asConstInteger() == 0) {
+                val and = condition.left as? PtBinaryExpression
+                if (and != null && and.operator == "&" && and.type.isUnsignedByte) {
+                    val bitmask = and.right.asConstInteger()
+                    if(bitmask==128 || bitmask==64) {
+                        val variable = and.left as? PtIdentifier
+                        if (variable != null && variable.type.isByte) {
+                            return Triple(condition.operator=="!=", variable, bitmask)
+                        }
+                        val typecast = and.left as? PtTypeCast
+                        if (typecast != null && typecast.type.isUnsignedByte) {
+                            val castedVariable = typecast.value as? PtIdentifier
+                            if(castedVariable!=null && castedVariable.type.isByte)
+                                return Triple(condition.operator=="!=", castedVariable, bitmask)
+                        }
+                    }
+                }
+            }
+        }
+        return null
+    }
 }
 
 /**

codeGenCpu6502/src/prog8/codegen/cpu6502/AsmOptimizer.kt

@@ -4,13 +4,13 @@ import prog8.code.StConstant
 import prog8.code.StMemVar
 import prog8.code.SymbolTable
 import prog8.code.ast.PtLabel
-import prog8.code.core.IMachineDefinition
+import prog8.code.core.ICompilationTarget
 
 
 // note: see https://wiki.nesdev.org/w/index.php/6502_assembly_optimisations
 
 
-internal fun optimizeAssembly(lines: MutableList<String>, machine: IMachineDefinition, symbolTable: SymbolTable): Int {
+internal fun optimizeAssembly(lines: MutableList<String>, machine: ICompilationTarget, symbolTable: SymbolTable): Int {
 
     var numberOfOptimizations = 0
 
@@ -123,7 +123,7 @@ private fun getLinesBy(lines: MutableList<String>, windowSize: Int) =
 
 private fun optimizeSameAssignments(
     linesByFourteen: Sequence<List<IndexedValue<String>>>,
-    machine: IMachineDefinition,
+    machine: ICompilationTarget,
     symbolTable: SymbolTable
 ): List<Modification> {
 
@@ -386,7 +386,7 @@ This gets generated after certain if conditions, and only the branch instruction
 
 private fun optimizeStoreLoadSame(
     linesByFour: Sequence<List<IndexedValue<String>>>,
-    machine: IMachineDefinition,
+    machine: ICompilationTarget,
     symbolTable: SymbolTable
 ): List<Modification> {
     val mods = mutableListOf<Modification>()

codeGenCpu6502/src/prog8/codegen/cpu6502/AssemblyProgram.kt

@@ -2,9 +2,9 @@ package prog8.codegen.cpu6502
 
 import prog8.code.ast.PtLabel
 import prog8.code.core.*
-import prog8.code.target.AtariTarget
+import prog8.code.target.C128Target
 import prog8.code.target.C64Target
-import prog8.code.target.Neo6502Target
+import prog8.code.target.PETTarget
 import java.nio.file.Path
 
 
@@ -19,21 +19,17 @@ internal class AssemblyProgram(
     private val binFile = outputDir.resolve("$name.bin")
     private val viceMonListFile = outputDir.resolve(C64Target.viceMonListName(name))
     private val listFile = outputDir.resolve("$name.list")
-    private val targetWithoutBreakpointsForEmulator = arrayOf(AtariTarget.NAME, Neo6502Target.NAME)
 
     override fun assemble(options: CompilationOptions, errors: IErrorReporter): Boolean {
 
         val assemblerCommand: List<String>
 
-        when (compTarget.name) {
-            in arrayOf("c64", "c128", "cx16", "pet32") -> {
+        when(options.output) {
+            OutputType.PRG -> {
                 // CBM machines .prg generation.
 
-                // add "-Wlong-branch"  to see warnings about conversion of branch instructions to jumps (default = do this silently)
-                val command = mutableListOf("64tass", "--ascii", "--case-sensitive", "--long-branch",
-                    "-Wall", // "-Wno-strict-bool", "-Werror",
-                    "--dump-labels", "--vice-labels", "--labels=$viceMonListFile"
-                )
+                val command = mutableListOf("64tass", "--cbm-prg", "--ascii", "--case-sensitive", "--long-branch",
+                    "-Wall", "-Wno-implied-reg", "--no-monitor", "--dump-labels", "--vice-labels", "--labels=$viceMonListFile")
 
                 if(options.warnSymbolShadowing)
                     command.add("-Wshadow")
@@ -44,34 +40,59 @@ internal class AssemblyProgram(
                     command.add("--quiet")
 
                 if(options.asmListfile) {
-                    command.addAll(listOf("--list=$listFile", "--no-monitor"))
+                    command.add("--list=$listFile")
                 }
 
-                val outFile = when (options.output) {
-                    OutputType.PRG -> {
-                        command.add("--cbm-prg")
-                        println("\nCreating prg for target ${compTarget.name}.")
-                        prgFile
-                    }
-                    OutputType.RAW -> {
-                        command.add("--nostart")
-                        println("\nCreating raw binary for target ${compTarget.name}.")
-                        binFile
-                    }
-                    else -> throw AssemblyError("invalid output type")
-                }
-                command.addAll(listOf("--output", outFile.toString(), assemblyFile.toString()))
+                command.addAll(listOf("--output", prgFile.toString(), assemblyFile.toString()))
                 assemblerCommand = command
-
+                println("\nCreating prg for target ${compTarget.name}.")
             }
-            "atari" -> {
+            OutputType.XEX -> {
                 // Atari800XL .xex generation.
 
-                // TODO are these options okay for atari?
+                val command = mutableListOf("64tass", "--atari-xex", "--case-sensitive", "--long-branch",
+                    "-Wall", "-Wno-implied-reg", "--no-monitor", "--dump-labels", "--vice-labels", "--labels=$viceMonListFile")
+
+                if(options.warnSymbolShadowing)
+                    command.add("-Wshadow")
+                else
+                    command.add("-Wno-shadow")
+
+                if(options.asmQuiet)
+                    command.add("--quiet")
+
+                if(options.asmListfile)
+                    command.add("--list=$listFile")
+
+                command.addAll(listOf("--output", xexFile.toString(), assemblyFile.toString()))
+                assemblerCommand = command
+                println("\nCreating xex for target ${compTarget.name}.")
+            }
+            OutputType.RAW -> {
+                // Neo6502/headerless raw program generation.
+                val command = mutableListOf("64tass", "--nostart", "--case-sensitive", "--long-branch",
+                    "-Wall", "-Wno-implied-reg", "--no-monitor", "--dump-labels", "--vice-labels", "--labels=$viceMonListFile")
+
+                if(options.warnSymbolShadowing)
+                    command.add("-Wshadow")
+                else
+                    command.add("-Wno-shadow")
+
+                if(options.asmQuiet)
+                    command.add("--quiet")
+
+                if(options.asmListfile)
+                    command.add("--list=$listFile")
+
+                command.addAll(listOf("--output", binFile.toString(), assemblyFile.toString()))
+                assemblerCommand = command
+                println("\nCreating raw binary for target ${compTarget.name}.")
+            }
+            OutputType.LIBRARY -> {
+                // CBM machines library (.bin) generation (with or without 2 byte load address header depending on the compilation target machine)
+
                 val command = mutableListOf("64tass", "--ascii", "--case-sensitive", "--long-branch",
-                    "-Wall", // "-Werror", "-Wno-strict-bool"
-                    "--no-monitor"
-                )
+                    "-Wall", "-Wno-implied-reg", "--no-monitor", "--dump-labels", "--vice-labels", "--labels=$viceMonListFile")
 
                 if(options.warnSymbolShadowing)
                     command.add("-Wshadow")
@@ -84,63 +105,25 @@ internal class AssemblyProgram(
                 if(options.asmListfile)
                     command.add("--list=$listFile")
 
-                val outFile = when (options.output) {
-                    OutputType.XEX -> {
-                        command.add("--atari-xex")
-                        println("\nCreating xex for target ${compTarget.name}.")
-                        xexFile
-                    }
-                    OutputType.RAW -> {
-                        command.add("--nostart")
-                        println("\nCreating raw binary for target ${compTarget.name}.")
-                        binFile
-                    }
-                    else -> throw AssemblyError("invalid output type")
+                if(compTarget.name in listOf(C64Target.NAME, C128Target.NAME, PETTarget.NAME)) {
+                    println("\nCreating binary library file with header for target ${compTarget.name}.")
+                    command.add("--cbm-prg")
+                } else {
+                    println("\nCreating binary library file without header for target ${compTarget.name}.")
+                    command.add("--nostart")       // should be headerless bin, because basic has problems doing a normal LOAD"lib",8,1 - need to use BLOAD
                 }
-                command.addAll(listOf("--output", outFile.toString(), assemblyFile.toString()))
+
+                command.addAll(listOf("--output", binFile.toString(), assemblyFile.toString()))
                 assemblerCommand = command
             }
-            "neo" -> {
-                // Neo6502 raw program generation.
-
-                if(options.output!=OutputType.RAW || options.loadAddress!=0x0800u || options.launcher!=CbmPrgLauncherType.NONE) {
-                    throw AssemblyError("invalid program compilation options. Neo6502 requires %output raw, %launcher none, %address $0800")
-                }
-
-                // TODO are these options okay for neo?
-                val command = mutableListOf("64tass", "--case-sensitive", "--long-branch",
-                    "-Wall", // "-Werror", "-Wno-strict-bool"
-                    "--no-monitor"
-                )
-
-                if(options.warnSymbolShadowing)
-                    command.add("-Wshadow")
-                else
-                    command.add("-Wno-shadow")
-
-                if(options.asmQuiet)
-                    command.add("--quiet")
-
-                if(options.asmListfile)
-                    command.add("--list=$listFile")
-
-                val outFile = when (options.output) {
-                    OutputType.RAW -> {
-                        command.add("--nostart")
-                        println("\nCreating raw binary for target ${compTarget.name}.")
-                        binFile
-                    }
-                    else -> throw AssemblyError("invalid output type, need 'raw'")
-                }
-                command.addAll(listOf("--output", outFile.toString(), assemblyFile.toString()))
-                assemblerCommand = command
-            }
-            else -> throw AssemblyError("invalid compilation target")
         }
 
+        if(options.compTarget.additionalAssemblerOptions!=null)
+            assemblerCommand.add(options.compTarget.additionalAssemblerOptions!!)
+
         val proc = ProcessBuilder(assemblerCommand).inheritIO().start()
         val result = proc.waitFor()
-        if (result == 0 && compTarget.name !in targetWithoutBreakpointsForEmulator) {
+        if (result == 0) {
             removeGeneratedLabelsFromMonlist()
             generateBreakpointList()
         }

codeGenCpu6502/src/prog8/codegen/cpu6502/BuiltinFunctionsAsmGen.kt

@@ -66,8 +66,6 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
             "callfar" -> funcCallFar(fcall, resultRegister)
             "callfar2" -> funcCallFar2(fcall, resultRegister)
             "call" -> funcCall(fcall)
-            "prog8_ifelse_bittest_set" -> throw AssemblyError("prog8_ifelse_bittest_set() should have been translated as part of an ifElse statement")
-            "prog8_ifelse_bittest_notset" -> throw AssemblyError("prog8_ifelse_bittest_notset() should have been translated as part of an ifElse statement")
             "prog8_lib_stringcompare" -> funcStringCompare(fcall, resultRegister)
             "prog8_lib_square_byte" -> funcSquare(fcall, BaseDataType.UBYTE, resultRegister)
             "prog8_lib_square_word" -> funcSquare(fcall, BaseDataType.UWORD, resultRegister)
@@ -141,7 +139,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
     }
 
     private fun funcRsave() {
-        if (asmgen.isTargetCpu(CpuType.CPU65c02))
+        if (asmgen.isTargetCpu(CpuType.CPU65C02))
             asmgen.out("""
                 php
                 pha
@@ -161,7 +159,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
     }
 
     private fun funcRrestore() {
-        if (asmgen.isTargetCpu(CpuType.CPU65c02))
+        if (asmgen.isTargetCpu(CpuType.CPU65C02))
             asmgen.out("""
                 plx
                 ply
@@ -382,7 +380,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
         addressOf.parent = fcall
         val src = AsmAssignSource(SourceStorageKind.EXPRESSION, program, asmgen, DataType.forDt(BaseDataType.UWORD), expression = addressOf)
         val target = AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, false, fcall.position, null, asmgen)
-        val assign = AsmAssignment(src, target, program.memsizer, fcall.position)
+        val assign = AsmAssignment(src, listOf(target), program.memsizer, fcall.position)
         asmgen.translateNormalAssignment(assign, fcall.definingISub())
     }
 
@@ -783,7 +781,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
                 if(asmgen.isZpVar(addrExpr)) {
                     // pointervar is already in the zero page, no need to copy
                     asmgen.assignExpressionToRegister(fcall.args[1], RegisterOrPair.AX)
-                    if (asmgen.isTargetCpu(CpuType.CPU65c02)) {
+                    if (asmgen.isTargetCpu(CpuType.CPU65C02)) {
                         asmgen.out("""
                             sta  ($varname)
                             txa
@@ -849,7 +847,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
                 val varname = asmgen.asmVariableName(addrExpr)
                 if(asmgen.isZpVar(addrExpr)) {
                     // pointervar is already in the zero page, no need to copy
-                    if (asmgen.isTargetCpu(CpuType.CPU65c02)) {
+                    if (asmgen.isTargetCpu(CpuType.CPU65C02)) {
                         asmgen.out("""
                             ldy  #1
                             lda  ($varname),y
@@ -1035,38 +1033,58 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
 
     private fun funcMkword(fcall: PtBuiltinFunctionCall, resultRegister: RegisterOrPair?) {
         val reg = resultRegister ?: RegisterOrPair.AY
-        var needAsave = asmgen.needAsaveForExpr(fcall.args[0])
-        if(!needAsave) {
+        var needAsaveForArg0 = asmgen.needAsaveForExpr(fcall.args[0])
+        if(!needAsaveForArg0) {
             val mr0 = fcall.args[0] as? PtMemoryByte
             val mr1 = fcall.args[1] as? PtMemoryByte
             if (mr0 != null)
-                needAsave =  mr0.address !is PtNumber
+                needAsaveForArg0 =  mr0.address !is PtNumber
             if (mr1 != null)
-                needAsave = needAsave or (mr1.address !is PtNumber)
+                needAsaveForArg0 = needAsaveForArg0 or (mr1.address !is PtNumber)
         }
         when(reg) {
             RegisterOrPair.AX -> {
-                asmgen.assignExpressionToRegister(fcall.args[1], RegisterOrPair.A)      // lsb
-                if(needAsave)
-                    asmgen.out("  pha")
-                asmgen.assignExpressionToRegister(fcall.args[0], RegisterOrPair.X)      // msb
-                if(needAsave)
-                    asmgen.out("  pla")
+                if(needAsaveForArg0 && !asmgen.needAsaveForExpr(fcall.args[1])) {
+                    // first 0 then 1
+                    asmgen.assignExpressionToRegister(fcall.args[0], RegisterOrPair.X)      // msb
+                    asmgen.assignExpressionToRegister(fcall.args[1], RegisterOrPair.A)      // lsb
+                } else if(!needAsaveForArg0 && asmgen.needAsaveForExpr(fcall.args[1])) {
+                    // first 1 then 0
+                    asmgen.assignExpressionToRegister(fcall.args[1], RegisterOrPair.A)      // lsb
+                    asmgen.assignExpressionToRegister(fcall.args[0], RegisterOrPair.X)      // msb
+                } else {
+                    asmgen.assignExpressionToRegister(fcall.args[1], RegisterOrPair.A)      // lsb
+                    if (needAsaveForArg0)
+                        asmgen.out("  pha")
+                    asmgen.assignExpressionToRegister(fcall.args[0], RegisterOrPair.X)      // msb
+                    if (needAsaveForArg0)
+                        asmgen.out("  pla")
+                }
             }
             RegisterOrPair.AY -> {
-                asmgen.assignExpressionToRegister(fcall.args[1], RegisterOrPair.A)      // lsb
-                if(needAsave)
-                    asmgen.out("  pha")
-                asmgen.assignExpressionToRegister(fcall.args[0], RegisterOrPair.Y)      // msb
-                if(needAsave)
-                    asmgen.out("  pla")
+                if(needAsaveForArg0 && !asmgen.needAsaveForExpr(fcall.args[1])) {
+                    // first 0 then 1
+                    asmgen.assignExpressionToRegister(fcall.args[0], RegisterOrPair.Y)      // msb
+                    asmgen.assignExpressionToRegister(fcall.args[1], RegisterOrPair.A)      // lsb
+                } else if(!needAsaveForArg0 && asmgen.needAsaveForExpr(fcall.args[1])) {
+                    // first 1 then 0
+                    asmgen.assignExpressionToRegister(fcall.args[1], RegisterOrPair.A)      // lsb
+                    asmgen.assignExpressionToRegister(fcall.args[0], RegisterOrPair.Y)      // msb
+                } else {
+                    asmgen.assignExpressionToRegister(fcall.args[1], RegisterOrPair.A)      // lsb
+                    if (needAsaveForArg0)
+                        asmgen.out("  pha")
+                    asmgen.assignExpressionToRegister(fcall.args[0], RegisterOrPair.Y)      // msb
+                    if (needAsaveForArg0)
+                        asmgen.out("  pla")
+                }
             }
             RegisterOrPair.XY -> {
                 asmgen.assignExpressionToRegister(fcall.args[1], RegisterOrPair.A)      // lsb
-                if(needAsave)
+                if (needAsaveForArg0)
                     asmgen.out("  pha")
                 asmgen.assignExpressionToRegister(fcall.args[0], RegisterOrPair.Y)      // msb
-                if(needAsave)
+                if (needAsaveForArg0)
                     asmgen.out("  pla")
                 asmgen.out("  tax")
             }
@@ -1097,7 +1115,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
                 RegisterOrPair.XY -> asmgen.out("  ldx  $sourceName+1 |  ldy  #0")
                 in Cx16VirtualRegisters -> {
                     val regname = resultRegister.name.lowercase()
-                    if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                    if(asmgen.isTargetCpu(CpuType.CPU65C02))
                         asmgen.out("  lda  $sourceName+1 |  sta  cx16.$regname |  stz  cx16.$regname+1")
                     else
                         asmgen.out("  lda  $sourceName+1 |  sta  cx16.$regname |  lda  #0 |  sta  cx16.$regname+1")
@@ -1197,7 +1215,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
                 RegisterOrPair.XY -> asmgen.out("  ldx  $sourceName |  ldy  #0")
                 in Cx16VirtualRegisters -> {
                     val regname = resultRegister.name.lowercase()
-                    if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                    if(asmgen.isTargetCpu(CpuType.CPU65C02))
                         asmgen.out("  lda  $sourceName |  sta  cx16.$regname |  stz  cx16.$regname+1")
                     else
                         asmgen.out("  lda  $sourceName |  sta  cx16.$regname |  lda  #0 |  sta  cx16.$regname+1")
@@ -1316,7 +1334,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
                         }
                     }
                     val tgt = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.forDt(conv.dt), null, value.position, variableAsmName = varname)
-                    val assign = AsmAssignment(src, tgt, program.memsizer, value.position)
+                    val assign = AsmAssignment(src, listOf(tgt), program.memsizer, value.position)
                     asmgen.translateNormalAssignment(assign, scope)
                 }
                 conv.reg != null -> {
@@ -1334,7 +1352,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
                         }
                     }
                     val tgt = AsmAssignTarget.fromRegisters(conv.reg!!, false, value.position, null, asmgen)
-                    val assign = AsmAssignment(src, tgt, program.memsizer, value.position)
+                    val assign = AsmAssignment(src, listOf(tgt), program.memsizer, value.position)
                     asmgen.translateNormalAssignment(assign, scope)
                 }
                 else -> throw AssemblyError("callconv")

codeGenCpu6502/src/prog8/codegen/cpu6502/Extensions.kt

@@ -3,6 +3,7 @@ package prog8.codegen.cpu6502
 import prog8.code.ast.IPtSubroutine
 import prog8.code.ast.PtAsmSub
 import prog8.code.ast.PtSub
+import prog8.code.core.AssemblyError
 import prog8.code.core.DataType
 import prog8.code.core.RegisterOrPair
 import prog8.code.core.RegisterOrStatusflag
@@ -14,29 +15,25 @@ internal fun IPtSubroutine.returnsWhatWhere(): List<Pair<RegisterOrStatusflag, D
             return returns
         }
         is PtSub -> {
-            // for non-asm subroutines, determine the return registers based on the type of the return value
-            return if(returntype==null)
-                emptyList()
-            else {
-                val register = when {
-                    returntype!!.isByteOrBool -> RegisterOrStatusflag(RegisterOrPair.A, null)
-                    returntype!!.isWord -> RegisterOrStatusflag(RegisterOrPair.AY, null)
-                    returntype!!.isFloat -> RegisterOrStatusflag(RegisterOrPair.FAC1, null)
-                    else -> RegisterOrStatusflag(RegisterOrPair.AY, null)
+            // for non-asm subroutines, determine the return registers based on the type of the return values
+
+            when(returns.size) {
+                0 -> return emptyList()
+                1 -> {
+                    val returntype = returns.single()
+                    val register = when {
+                        returntype.isByteOrBool -> RegisterOrStatusflag(RegisterOrPair.A, null)
+                        returntype.isWord -> RegisterOrStatusflag(RegisterOrPair.AY, null)
+                        returntype.isFloat -> RegisterOrStatusflag(RegisterOrPair.FAC1, null)
+                        else -> RegisterOrStatusflag(RegisterOrPair.AY, null)
+                    }
+                    return listOf(Pair(register, returntype))
+                }
+                else -> {
+                    // TODO for multi-value results, put the first one in register(s) and only the rest in the virtual registers?
+                    throw AssemblyError("multi-value returns from a normal subroutine are not put into registers, this routine shouldn't have been called in this scenario")
                 }
-                listOf(Pair(register, returntype!!))
             }
         }
     }
 }
-
-
-internal fun PtSub.returnRegister(): RegisterOrStatusflag? {
-    return when {
-        returntype?.isByteOrBool==true -> RegisterOrStatusflag(RegisterOrPair.A, null)
-        returntype?.isWord==true -> RegisterOrStatusflag(RegisterOrPair.AY, null)
-        returntype?.isFloat==true -> RegisterOrStatusflag(RegisterOrPair.FAC1, null)
-        returntype==null -> null
-        else -> RegisterOrStatusflag(RegisterOrPair.AY, null)
-    }
-}

codeGenCpu6502/src/prog8/codegen/cpu6502/FunctionCallAsmGen.kt

@@ -15,12 +15,16 @@ internal class FunctionCallAsmGen(private val program: PtProgram, private val as
         // just ignore any result values from the function call.
     }
 
-    internal fun optimizeIntArgsViaCpuRegisters(params: List<PtSubroutineParameter>) =
-        when(params.size) {
-            1 -> params[0].type.isIntegerOrBool
-            2 -> params[0].type.isByteOrBool && params[1].type.isByteOrBool
+    internal fun optimizeIntArgsViaCpuRegisters(params: List<PtSubroutineParameter>): Boolean {
+        // When the parameter(s) are passed via an explicit register or register pair,
+        // we consider them NOT to be optimized into (possibly different) CPU registers.
+        // Just load them in whatever the register spec says.
+        return when (params.size) {
+            1 -> params[0].type.isIntegerOrBool && params[0].register == null
+            2 -> params[0].type.isByteOrBool && params[1].type.isByteOrBool && params[0].register == null && params[1].register == null
             else -> false
         }
+    }
 
     internal fun translateFunctionCall(call: PtFunctionCall) {
         // Output only the code to set up the parameters and perform the actual call
@@ -131,15 +135,16 @@ internal class FunctionCallAsmGen(private val program: PtProgram, private val as
                 useCpuRegistersForArgs(call.args, sub)
             } else {
                 // arguments via variables
-                val (normalParams, registerParams) = sub.parameters.withIndex().partition { it.value.register == null }
+                val paramValues = sub.parameters.zip(call.args)
+                val (normalParams, registerParams) = paramValues.partition { it.first.register == null }
                 if (normalParams.isNotEmpty()) {
-                    for (arg in normalParams.zip(call.args))
-                        argumentViaVariable(sub, arg.first.value, arg.second)
+                    for (p in normalParams)
+                        argumentViaVariable(sub, p.first, p.second)
                 }
                 if (registerParams.isNotEmpty()) {
                     // the R0-R15 'registers' are not really registers. They're just special variables.
-                    for (arg in registerParams.zip(call.args))
-                        argumentViaVariable(sub, arg.first.value, arg.second)
+                    for (p in registerParams)
+                        argumentViaVariable(sub, p.first, p.second)
                 }
             }
             asmgen.out("  jsr  $subAsmName")
@@ -159,12 +164,22 @@ internal class FunctionCallAsmGen(private val program: PtProgram, private val as
             2 -> {
                 if(params[0].type.isByteOrBool && params[1].type.isByteOrBool) {
                     // 2 byte params, second in Y, first in A
-                    argumentViaRegister(sub, IndexedValue(0, params[0]), args[0], RegisterOrPair.A)
-                    if(asmgen.needAsaveForExpr(args[1]))
-                        asmgen.out("  pha")
-                    argumentViaRegister(sub, IndexedValue(1, params[1]), args[1], RegisterOrPair.Y)
-                    if(asmgen.needAsaveForExpr(args[1]))
-                        asmgen.out("  pla")
+                    if(asmgen.needAsaveForExpr(args[0]) && !asmgen.needAsaveForExpr(args[1])) {
+                        // first 0 then 1
+                        argumentViaRegister(sub, IndexedValue(0, params[0]), args[0], RegisterOrPair.A)
+                        argumentViaRegister(sub, IndexedValue(1, params[1]), args[1], RegisterOrPair.Y)
+                    } else if(!asmgen.needAsaveForExpr(args[0]) && asmgen.needAsaveForExpr(args[1])) {
+                        // first 1 then 0
+                        argumentViaRegister(sub, IndexedValue(1, params[1]), args[1], RegisterOrPair.Y)
+                        argumentViaRegister(sub, IndexedValue(0, params[0]), args[0], RegisterOrPair.A)
+                    } else {
+                        argumentViaRegister(sub, IndexedValue(0, params[0]), args[0], RegisterOrPair.A)
+                        if (asmgen.needAsaveForExpr(args[1]))
+                            asmgen.out("  pha")
+                        argumentViaRegister(sub, IndexedValue(1, params[1]), args[1], RegisterOrPair.Y)
+                        if (asmgen.needAsaveForExpr(args[1]))
+                            asmgen.out("  pla")
+                    }
                 } else {
                     throw AssemblyError("cannot use registers for word+byte")
                 }
@@ -323,7 +338,7 @@ internal class FunctionCallAsmGen(private val program: PtProgram, private val as
                 } else {
                     AsmAssignSource.fromAstSource(value, program, asmgen).adjustSignedUnsigned(target)
                 }
-                asmgen.translateNormalAssignment(AsmAssignment(src, target, program.memsizer, target.position), scope)
+                asmgen.translateNormalAssignment(AsmAssignment(src, listOf(target), program.memsizer, target.position), scope)
             }
             return RegisterOrStatusflag(register, null)
         }

codeGenCpu6502/src/prog8/codegen/cpu6502/IfElseAsmGen.kt

@@ -32,6 +32,15 @@ internal class IfElseAsmGen(private val program: PtProgram,
 
         val compareCond = stmt.condition as? PtBinaryExpression
         if(compareCond!=null) {
+
+            val useBIT = asmgen.checkIfConditionCanUseBIT(compareCond)
+            if(useBIT!=null) {
+                // use a BIT instruction to test for bit 7 or 6 set/clear
+                val (testBitSet, variable, bitmask) = useBIT
+                return translateIfBIT(stmt, jumpAfterIf, testBitSet, variable, bitmask)
+                return
+            }
+
             val rightDt = compareCond.right.type
             return when {
                 rightDt.isByteOrBool -> translateIfByte(stmt, jumpAfterIf)
@@ -58,6 +67,63 @@ internal class IfElseAsmGen(private val program: PtProgram,
         throw AssemblyError("weird non-boolean condition node type ${stmt.condition} at ${stmt.condition.position}")
     }
 
+    private fun translateIfBIT(ifElse: PtIfElse, jumpAfterIf: PtJump?, testForBitSet: Boolean, variable: PtIdentifier, bitmask: Int) {
+        // use a BIT instruction to test for bit 7 or 6 set/clear
+
+        fun branch(branchInstr: String, target: AsmGen6502Internal.JumpTarget) {
+            require(!target.needsExpressionEvaluation)
+            if(target.indirect)
+                throw AssemblyError("cannot BIT to indirect label ${ifElse.position}")
+            if(ifElse.hasElse())
+                throw AssemblyError("didn't expect else part here ${ifElse.position}")
+            else
+                asmgen.out("  $branchInstr  ${target.asmLabel}")
+        }
+
+        when (bitmask) {
+            128 -> {
+                // test via bit + N flag
+                asmgen.out("  bit  ${variable.name}")
+                if(testForBitSet) {
+                    if(jumpAfterIf!=null) {
+                        val target = asmgen.getJumpTarget(jumpAfterIf)
+                        branch("bmi", target)
+                    }
+                    else
+                        translateIfElseBodies("bpl", ifElse)
+                } else {
+                    if(jumpAfterIf!=null) {
+                        val target = asmgen.getJumpTarget(jumpAfterIf)
+                        branch("bpl", target)
+                    }
+                    else
+                        translateIfElseBodies("bmi", ifElse)
+                }
+                return
+            }
+            64 -> {
+                // test via bit + V flag
+                asmgen.out("  bit  ${variable.name}")
+                if(testForBitSet) {
+                    if(jumpAfterIf!=null) {
+                        val target = asmgen.getJumpTarget(jumpAfterIf)
+                        branch("bvs", target)
+                    }
+                    else
+                        translateIfElseBodies("bvc", ifElse)
+                } else {
+                    if(jumpAfterIf!=null) {
+                        val target = asmgen.getJumpTarget(jumpAfterIf)
+                        branch("bvc", target)
+                    }
+                    else
+                        translateIfElseBodies("bvs", ifElse)
+                }
+                return
+            }
+            else -> throw AssemblyError("BIT only works for bits 6 and 7")
+        }
+    }
 
     private fun checkNotExtsubReturnsStatusReg(condition: PtExpression) {
         val fcall = condition as? PtFunctionCall
@@ -70,82 +136,8 @@ internal class IfElseAsmGen(private val program: PtProgram,
     }
 
     private fun fallbackTranslateForSimpleCondition(ifElse: PtIfElse) {
-        val bittest = ifElse.condition as? PtBuiltinFunctionCall
         val jumpAfterIf = ifElse.ifScope.children.singleOrNull() as? PtJump
 
-        if(bittest!=null && bittest.name.startsWith("prog8_ifelse_bittest_")) {
-            val variable = bittest.args[0] as PtIdentifier
-            val bitnumber = (bittest.args[1] as PtNumber).number.toInt()
-            val testForBitSet = bittest.name.endsWith("_set")
-            when (bitnumber) {
-                7 -> {
-                    // test via bit + N flag
-                    asmgen.out("  bit  ${variable.name}")
-                    if(testForBitSet) {
-                        if(jumpAfterIf!=null) {
-                            val target = asmgen.getJumpTarget(jumpAfterIf)
-                            require(!target.needsExpressionEvaluation)
-                            if(target.indirect)
-                                throw AssemblyError("cannot BIT to indirect label ${ifElse.position}")
-                            if(ifElse.hasElse())
-                                throw AssemblyError("didn't expect else part here ${ifElse.position}")
-                            else
-                                asmgen.out("  bmi  ${target.asmLabel}")
-                        }
-                        else
-                            translateIfElseBodies("bpl", ifElse)
-                    } else {
-                        if(jumpAfterIf!=null) {
-                            val target = asmgen.getJumpTarget(jumpAfterIf)
-                            require(!target.needsExpressionEvaluation)
-                            if(target.indirect)
-                                throw AssemblyError("cannot BIT to indirect label ${ifElse.position}")
-                            if(ifElse.hasElse())
-                                throw AssemblyError("didn't expect else part here ${ifElse.position}")
-                            else
-                                asmgen.out("  bpl  ${target.asmLabel}")
-                        }
-                        else
-                            translateIfElseBodies("bmi", ifElse)
-                    }
-                    return
-                }
-                6 -> {
-                    // test via bit + V flag
-                    asmgen.out("  bit  ${variable.name}")
-                    if(testForBitSet) {
-                        if(jumpAfterIf!=null) {
-                            val target = asmgen.getJumpTarget(jumpAfterIf)
-                            require(!target.needsExpressionEvaluation)
-                            if(target.indirect)
-                                throw AssemblyError("cannot BIT to indirect label ${ifElse.position}")
-                            if(ifElse.hasElse())
-                                throw AssemblyError("didn't expect else part here ${ifElse.position}")
-                            else
-                                asmgen.out("  bvs  ${target.asmLabel}")
-                        }
-                        else
-                            translateIfElseBodies("bvc", ifElse)
-                    } else {
-                        if(jumpAfterIf!=null) {
-                            val target = asmgen.getJumpTarget(jumpAfterIf)
-                            require(!target.needsExpressionEvaluation)
-                            if(target.indirect)
-                                throw AssemblyError("cannot BIT to indirect label ${ifElse.position}")
-                            if(ifElse.hasElse())
-                                throw AssemblyError("didn't expect else part here ${ifElse.position}")
-                            else
-                                asmgen.out("  bvc  ${target.asmLabel}")
-                        }
-                        else
-                            translateIfElseBodies("bvs", ifElse)
-                    }
-                    return
-                }
-                else -> throw AssemblyError("prog8_ifelse_bittest can only work on bits 7 and 6")
-            }
-        }
-
         // the condition is "simple" enough to just assign its 0/1 value to a register and branch on that
         asmgen.assignConditionValueToRegisterAndTest(ifElse.condition)
         if(jumpAfterIf!=null)

codeGenCpu6502/src/prog8/codegen/cpu6502/IfExpressionAsmGen.kt

@@ -1,19 +1,7 @@
 package prog8.codegen.cpu6502
 
-import prog8.code.ast.PtBinaryExpression
-import prog8.code.ast.PtBuiltinFunctionCall
-import prog8.code.ast.PtExpression
-import prog8.code.ast.PtIdentifier
-import prog8.code.ast.PtIfExpression
-import prog8.code.ast.PtNumber
-import prog8.code.ast.PtPrefix
-import prog8.code.core.AssemblyError
-import prog8.code.core.BaseDataType
-import prog8.code.core.CpuRegister
-import prog8.code.core.DataType
-import prog8.code.core.IErrorReporter
-import prog8.code.core.LogicalOperators
-import prog8.code.core.RegisterOrPair
+import prog8.code.ast.*
+import prog8.code.core.*
 import prog8.codegen.cpu6502.assignment.AsmAssignTarget
 import prog8.codegen.cpu6502.assignment.AssignmentAsmGen
 import prog8.codegen.cpu6502.assignment.TargetStorageKind
@@ -21,7 +9,7 @@ import prog8.codegen.cpu6502.assignment.TargetStorageKind
 internal class IfExpressionAsmGen(private val asmgen: AsmGen6502Internal, private val assignmentAsmGen: AssignmentAsmGen, private val errors: IErrorReporter) {
 
     internal fun assignIfExpression(target: AsmAssignTarget, expr: PtIfExpression) {
-        require(target.datatype==expr.type)
+        require(target.datatype==expr.type || target.datatype.isUnsignedWord && expr.type.isString)
         val falseLabel = asmgen.makeLabel("ifexpr_false")
         val endLabel = asmgen.makeLabel("ifexpr_end")
         evalIfExpressionConditonAndBranchWhenFalse(expr.condition, falseLabel)
@@ -34,7 +22,7 @@ internal class IfExpressionAsmGen(private val asmgen: AsmGen6502Internal, privat
                 asmgen.out(endLabel)
                 assignmentAsmGen.assignRegisterByte(target, CpuRegister.A, false, false)
             }
-            expr.type.isWord -> {
+            expr.type.isWord || expr.type.isString -> {
                 asmgen.assignExpressionToRegister(expr.truevalue, RegisterOrPair.AY, false)
                 asmgen.jmp(endLabel)
                 asmgen.out(falseLabel)
@@ -67,31 +55,6 @@ internal class IfExpressionAsmGen(private val asmgen: AsmGen6502Internal, privat
         else if(condition is PtPrefix && condition.operator=="not") {
             throw AssemblyError("not prefix in ifexpression should have been replaced by swapped values")
         } else {
-            // 'simple' condition, check if it is a byte bittest
-            val bittest = condition as? PtBuiltinFunctionCall
-            if(bittest!=null && bittest.name.startsWith("prog8_ifelse_bittest_")) {
-                val variable = bittest.args[0] as PtIdentifier
-                val bitnumber = (bittest.args[1] as PtNumber).number.toInt()
-                val testForBitSet = bittest.name.endsWith("_set")
-                when (bitnumber) {
-                    7 -> {
-                        // test via bit + N flag
-                        asmgen.out("  bit  ${variable.name}")
-                        if(testForBitSet) asmgen.out("  bpl  $falseLabel")
-                        else asmgen.out("  bmi  $falseLabel")
-                        return
-                    }
-                    6 -> {
-                        // test via bit + V flag
-                        asmgen.out("  bit  ${variable.name}")
-                        if(testForBitSet) asmgen.out("  bvc  $falseLabel")
-                        else asmgen.out("  bvs  $falseLabel")
-                        return
-                    }
-                    else -> throw AssemblyError("prog8_ifelse_bittest can only work on bits 7 and 6")
-                }
-            }
-
             // the condition is "simple" enough to just assign its 0/1 value to a register and branch on that
             asmgen.assignConditionValueToRegisterAndTest(condition)
             asmgen.out("  beq  $falseLabel")
@@ -338,6 +301,30 @@ internal class IfExpressionAsmGen(private val asmgen: AsmGen6502Internal, privat
 
     private fun translateIfCompareWithZeroByteBranch(condition: PtBinaryExpression, signed: Boolean, falseLabel: String) {
         // optimized code for byte comparisons with 0
+
+        val useBIT = asmgen.checkIfConditionCanUseBIT(condition)
+        if(useBIT!=null) {
+            // use a BIT instruction to test for bit 7 or 6 set/clear
+            val (testForBitSet, variable, bitmask) = useBIT
+            when (bitmask) {
+                128 -> {
+                    // test via bit + N flag
+                    asmgen.out("  bit  ${variable.name}")
+                    if(testForBitSet) asmgen.out("  bpl  $falseLabel")
+                    else asmgen.out("  bmi  $falseLabel")
+                    return
+                }
+                64 -> {
+                    // test via bit + V flag
+                    asmgen.out("  bit  ${variable.name}")
+                    if(testForBitSet) asmgen.out("  bvc  $falseLabel")
+                    else asmgen.out("  bvs  $falseLabel")
+                    return
+                }
+                else -> throw AssemblyError("BIT can only work on bits 7 and 6")
+            }
+        }
+
         asmgen.assignConditionValueToRegisterAndTest(condition.left)
         when (condition.operator) {
             "==" -> asmgen.out("  bne  $falseLabel")

codeGenCpu6502/src/prog8/codegen/cpu6502/ProgramAndVarsGen.kt

@@ -39,7 +39,7 @@ internal class ProgramAndVarsGen(
             // the global list of all floating point constants for the whole program
             asmgen.out("; global float constants")
             for (flt in allocator.globalFloatConsts) {
-                val floatFill = compTarget.machine.getFloatAsmBytes(flt.key)
+                val floatFill = compTarget.getFloatAsmBytes(flt.key)
                 val floatvalue = flt.key
                 asmgen.out("${flt.value}\t.byte  $floatFill  ; float $floatvalue")
             }
@@ -52,9 +52,9 @@ internal class ProgramAndVarsGen(
 
     private fun header() {
         val ourName = this.javaClass.name
-        val cpu = when(compTarget.machine.cpu) {
+        val cpu = when(compTarget.cpu) {
             CpuType.CPU6502 -> "6502"
-            CpuType.CPU65c02 -> "w65c02"
+            CpuType.CPU65C02 -> "w65c02"
             else -> "unsupported"
         }
 
@@ -87,93 +87,121 @@ internal class ProgramAndVarsGen(
             }
         }
 
-        when(options.output) {
-            OutputType.RAW -> {
-                asmgen.out("; ---- raw assembler program ----")
-                asmgen.out("* = ${options.loadAddress.toHex()}")
-                asmgen.out("prog8_program_start\t; start of program label")
-                asmgen.out("  cld")
-                asmgen.out("  tsx  ; save stackpointer for sys.exit()")
-                asmgen.out("  stx  prog8_lib.orig_stackpointer")
-                if(!options.noSysInit)
-                    asmgen.out("  jsr  p8_sys_startup.init_system")
-                asmgen.out("  jsr  p8_sys_startup.init_system_phase2")
+        if(options.compTarget.customLauncher.isNotEmpty()) {
+            asmgen.out("; ---- custom launcher assembler program ----")
+            asmgen.out("* = ${options.loadAddress.toHex()}")
+            asmgen.out("prog8_program_start\t; start of program label")
+            for(line in options.compTarget.customLauncher) {
+                asmgen.out(line)
             }
-            OutputType.PRG -> {
-                when(options.launcher) {
-                    CbmPrgLauncherType.BASIC -> {
-                        if (options.loadAddress != options.compTarget.machine.PROGRAM_LOAD_ADDRESS) {
-                            errors.err("BASIC output must have load address ${options.compTarget.machine.PROGRAM_LOAD_ADDRESS.toHex()}", program.position)
+            return
+        }
+
+        if(options.output == OutputType.LIBRARY) {
+
+            asmgen.out("; ---- library assembler program ----")
+            asmgen.out("* = ${options.loadAddress.toHex()}")
+            asmgen.out("prog8_program_start\t; start of program label")
+            asmgen.out("    jmp  p8b_main.p8s_start")
+            // note: the jmp above has 2 effects:
+            // 1. it prevents 64tass from stripping away all procs as unused code
+            // 2. it functions as the first entrypoint of the library, required anyway, to run the variable initialization/bss clear bootstrap code.
+
+        } else {
+
+            when (options.output) {
+                OutputType.LIBRARY -> { }
+                OutputType.RAW -> {
+                    asmgen.out("; ---- raw assembler program ----")
+                    asmgen.out("* = ${options.loadAddress.toHex()}")
+                    asmgen.out("prog8_program_start\t; start of program label")
+                    asmgen.out("  cld")
+                    asmgen.out("  tsx  ; save stackpointer for sys.exit()")
+                    asmgen.out("  stx  prog8_lib.orig_stackpointer")
+                    if (!options.noSysInit)
+                        asmgen.out("  jsr  p8_sys_startup.init_system")
+                    asmgen.out("  jsr  p8_sys_startup.init_system_phase2")
+                }
+                OutputType.PRG -> {
+                    when (options.launcher) {
+                        CbmPrgLauncherType.BASIC -> {
+                            if (options.loadAddress != options.compTarget.PROGRAM_LOAD_ADDRESS) {
+                                errors.err(
+                                    "BASIC output must have load address ${options.compTarget.PROGRAM_LOAD_ADDRESS.toHex()}",
+                                    program.position
+                                )
+                            }
+                            asmgen.out("; ---- basic program with sys call ----")
+                            asmgen.out("* = ${options.loadAddress.toHex()}")
+                            asmgen.out("prog8_program_start\t; start of program label")
+                            val year = LocalDate.now().year
+                            asmgen.out("  .word  (+), $year")
+                            asmgen.out("  .null  $9e, format(' %d ', prog8_entrypoint), $3a, $8f, ' prog8'")
+                            asmgen.out("+\t.word  0")
+                            asmgen.out("prog8_entrypoint")
+                            asmgen.out("  cld")
+                            asmgen.out("  tsx  ; save stackpointer for sys.exit()")
+                            asmgen.out("  stx  prog8_lib.orig_stackpointer")
+                            if (!options.noSysInit)
+                                asmgen.out("  jsr  p8_sys_startup.init_system")
+                            asmgen.out("  jsr  p8_sys_startup.init_system_phase2")
+                        }
+
+                        CbmPrgLauncherType.NONE -> {
+                            // this is the same as RAW
+                            asmgen.out("; ---- program without basic sys call ----")
+                            asmgen.out("* = ${options.loadAddress.toHex()}")
+                            asmgen.out("prog8_program_start\t; start of program label")
+                            asmgen.out("  cld")
+                            asmgen.out("  tsx  ; save stackpointer for sys.exit()")
+                            asmgen.out("  stx  prog8_lib.orig_stackpointer")
+                            if (!options.noSysInit)
+                                asmgen.out("  jsr  p8_sys_startup.init_system")
+                            asmgen.out("  jsr  p8_sys_startup.init_system_phase2")
                         }
-                        asmgen.out("; ---- basic program with sys call ----")
-                        asmgen.out("* = ${options.loadAddress.toHex()}")
-                        asmgen.out("prog8_program_start\t; start of program label")
-                        val year = LocalDate.now().year
-                        asmgen.out("  .word  (+), $year")
-                        asmgen.out("  .null  $9e, format(' %d ', prog8_entrypoint), $3a, $8f, ' prog8'")
-                        asmgen.out("+\t.word  0")
-                        asmgen.out("prog8_entrypoint")
-                        asmgen.out("  cld")
-                        asmgen.out("  tsx  ; save stackpointer for sys.exit()")
-                        asmgen.out("  stx  prog8_lib.orig_stackpointer")
-                        if(!options.noSysInit)
-                            asmgen.out("  jsr  p8_sys_startup.init_system")
-                        asmgen.out("  jsr  p8_sys_startup.init_system_phase2")
-                    }
-                    CbmPrgLauncherType.NONE -> {
-                        // this is the same as RAW
-                        asmgen.out("; ---- program without basic sys call ----")
-                        asmgen.out("* = ${options.loadAddress.toHex()}")
-                        asmgen.out("prog8_program_start\t; start of program label")
-                        asmgen.out("  cld")
-                        asmgen.out("  tsx  ; save stackpointer for sys.exit()")
-                        asmgen.out("  stx  prog8_lib.orig_stackpointer")
-                        if(!options.noSysInit)
-                            asmgen.out("  jsr  p8_sys_startup.init_system")
-                        asmgen.out("  jsr  p8_sys_startup.init_system_phase2")
                     }
                 }
+                OutputType.XEX -> {
+                    asmgen.out("; ---- atari xex program ----")
+                    asmgen.out("* = ${options.loadAddress.toHex()}")
+                    asmgen.out("prog8_program_start\t; start of program label")
+                    asmgen.out("  cld")
+                    asmgen.out("  tsx  ; save stackpointer for sys.exit()")
+                    asmgen.out("  stx  prog8_lib.orig_stackpointer")
+                    if (!options.noSysInit)
+                        asmgen.out("  jsr  p8_sys_startup.init_system")
+                    asmgen.out("  jsr  p8_sys_startup.init_system_phase2")
+                }
             }
-            OutputType.XEX -> {
-                asmgen.out("; ---- atari xex program ----")
-                asmgen.out("* = ${options.loadAddress.toHex()}")
-                asmgen.out("prog8_program_start\t; start of program label")
-                asmgen.out("  cld")
-                asmgen.out("  tsx  ; save stackpointer for sys.exit()")
-                asmgen.out("  stx  prog8_lib.orig_stackpointer")
-                if(!options.noSysInit)
-                    asmgen.out("  jsr  p8_sys_startup.init_system")
-                asmgen.out("  jsr  p8_sys_startup.init_system_phase2")
-            }
-        }
 
-        if(options.zeropage !in arrayOf(ZeropageType.BASICSAFE, ZeropageType.DONTUSE)) {
-            asmgen.out("""
-                ; zeropage is clobbered so we need to reset the machine at exit
-                lda  #>sys.reset_system
-                pha
-                lda  #<sys.reset_system
-                pha""")
-        }
+            if (options.zeropage !in arrayOf(ZeropageType.BASICSAFE, ZeropageType.DONTUSE)) {
+                asmgen.out("""
+                    ; zeropage is clobbered so we need to reset the machine at exit
+                    lda  #>sys.reset_system
+                    pha
+                    lda  #<sys.reset_system
+                    pha""")
+            }
 
-        when(compTarget.name) {
-            "cx16" -> {
-                if(options.floats)
-                    asmgen.out("  lda  #4 |  sta  $01")    // to use floats, make sure Basic rom is banked in
-                asmgen.out("  jsr  p8b_main.p8s_start")
-                asmgen.out("  jmp  p8_sys_startup.cleanup_at_exit")
-            }
-            "c64" -> {
-                asmgen.out("  jsr  p8b_main.p8s_start")
-                asmgen.out("  jmp  p8_sys_startup.cleanup_at_exit")
-            }
-            "c128" -> {
-                asmgen.out("  jsr  p8b_main.p8s_start")
-                asmgen.out("  jmp  p8_sys_startup.cleanup_at_exit")
-            }
-            else -> {
-                asmgen.out("  jsr  p8b_main.p8s_start")
-                asmgen.out("  jmp  p8_sys_startup.cleanup_at_exit")
+            when (compTarget.name) {
+                "cx16" -> {
+                    if (options.floats)
+                        asmgen.out("  lda  #4 |  sta  $01")    // to use floats, make sure Basic rom is banked in
+                    asmgen.out("  jsr  p8b_main.p8s_start")
+                    asmgen.out("  jmp  p8_sys_startup.cleanup_at_exit")
+                }
+                "c64" -> {
+                    asmgen.out("  jsr  p8b_main.p8s_start")
+                    asmgen.out("  jmp  p8_sys_startup.cleanup_at_exit")
+                }
+                "c128" -> {
+                    asmgen.out("  jsr  p8b_main.p8s_start")
+                    asmgen.out("  jmp  p8_sys_startup.cleanup_at_exit")
+                }
+                else -> {
+                    asmgen.out("  jsr  p8b_main.p8s_start")
+                    asmgen.out("  jmp  p8_sys_startup.cleanup_at_exit")
+                }
             }
         }
     }
@@ -203,7 +231,7 @@ internal class ProgramAndVarsGen(
                         BaseDataType.UBYTE -> asmgen.out("$name    .byte  ?")
                         BaseDataType.WORD  -> asmgen.out("$name    .sint  ?")
                         BaseDataType.UWORD -> asmgen.out("$name    .word  ?")
-                        BaseDataType.FLOAT -> asmgen.out("$name    .fill  ${options.compTarget.machine.FLOAT_MEM_SIZE}")
+                        BaseDataType.FLOAT -> asmgen.out("$name    .fill  ${options.compTarget.FLOAT_MEM_SIZE}")
                         else -> throw AssemblyError("weird dt for extravar $dt")
                     }
                 }
@@ -219,49 +247,49 @@ internal class ProgramAndVarsGen(
         var relocatedBssEnd = 0u
 
         if(options.varsGolden) {
-            if(options.compTarget.machine.BSSGOLDENRAM_START == 0u ||
-                options.compTarget.machine.BSSGOLDENRAM_END == 0u ||
-                options.compTarget.machine.BSSGOLDENRAM_END <= options.compTarget.machine.BSSGOLDENRAM_START) {
+            if(options.compTarget.BSSGOLDENRAM_START == 0u ||
+                options.compTarget.BSSGOLDENRAM_END == 0u ||
+                options.compTarget.BSSGOLDENRAM_END <= options.compTarget.BSSGOLDENRAM_START) {
                 throw AssemblyError("current compilation target hasn't got the golden ram area properly defined or it is simply not available")
             }
             relocateBssVars = true
-            relocatedBssStart = options.compTarget.machine.BSSGOLDENRAM_START
-            relocatedBssEnd = options.compTarget.machine.BSSGOLDENRAM_END
+            relocatedBssStart = options.compTarget.BSSGOLDENRAM_START
+            relocatedBssEnd = options.compTarget.BSSGOLDENRAM_END
         }
         else if(options.varsHighBank!=null) {
-            if(options.compTarget.machine.BSSHIGHRAM_START == 0u ||
-                options.compTarget.machine.BSSHIGHRAM_END == 0u ||
-                options.compTarget.machine.BSSHIGHRAM_END <= options.compTarget.machine.BSSHIGHRAM_START) {
+            if(options.compTarget.BSSHIGHRAM_START == 0u ||
+                options.compTarget.BSSHIGHRAM_END == 0u ||
+                options.compTarget.BSSHIGHRAM_END <= options.compTarget.BSSHIGHRAM_START) {
                 throw AssemblyError("current compilation target hasn't got the high ram area properly defined or it is simply not available")
             }
             if(options.slabsHighBank!=null && options.varsHighBank!=options.slabsHighBank)
                 throw AssemblyError("slabs and vars high bank must be the same")
             relocateBssVars = true
-            relocatedBssStart = options.compTarget.machine.BSSHIGHRAM_START
-            relocatedBssEnd = options.compTarget.machine.BSSHIGHRAM_END
+            relocatedBssStart = options.compTarget.BSSHIGHRAM_START
+            relocatedBssEnd = options.compTarget.BSSHIGHRAM_END
         }
 
         if(options.slabsGolden) {
-            if(options.compTarget.machine.BSSGOLDENRAM_START == 0u ||
-                options.compTarget.machine.BSSGOLDENRAM_END == 0u ||
-                options.compTarget.machine.BSSGOLDENRAM_END <= options.compTarget.machine.BSSGOLDENRAM_START) {
+            if(options.compTarget.BSSGOLDENRAM_START == 0u ||
+                options.compTarget.BSSGOLDENRAM_END == 0u ||
+                options.compTarget.BSSGOLDENRAM_END <= options.compTarget.BSSGOLDENRAM_START) {
                 throw AssemblyError("current compilation target hasn't got the golden ram area properly defined or it is simply not available")
             }
             relocateBssSlabs = true
-            relocatedBssStart = options.compTarget.machine.BSSGOLDENRAM_START
-            relocatedBssEnd = options.compTarget.machine.BSSGOLDENRAM_END
+            relocatedBssStart = options.compTarget.BSSGOLDENRAM_START
+            relocatedBssEnd = options.compTarget.BSSGOLDENRAM_END
         }
         else if(options.slabsHighBank!=null) {
-            if(options.compTarget.machine.BSSHIGHRAM_START == 0u ||
-                options.compTarget.machine.BSSHIGHRAM_END == 0u ||
-                options.compTarget.machine.BSSHIGHRAM_END <= options.compTarget.machine.BSSHIGHRAM_START) {
+            if(options.compTarget.BSSHIGHRAM_START == 0u ||
+                options.compTarget.BSSHIGHRAM_END == 0u ||
+                options.compTarget.BSSHIGHRAM_END <= options.compTarget.BSSHIGHRAM_START) {
                 throw AssemblyError("current compilation target hasn't got the high ram area properly defined or it is simply not available")
             }
             if(options.varsHighBank!=null && options.varsHighBank!=options.slabsHighBank)
                 throw AssemblyError("slabs and vars high bank must be the same")
             relocateBssSlabs = true
-            relocatedBssStart = options.compTarget.machine.BSSHIGHRAM_START
-            relocatedBssEnd = options.compTarget.machine.BSSHIGHRAM_END
+            relocatedBssStart = options.compTarget.BSSHIGHRAM_START
+            relocatedBssEnd = options.compTarget.BSSHIGHRAM_END
         }
 
         asmgen.out("; bss sections")
@@ -465,14 +493,14 @@ internal class ProgramAndVarsGen(
             else when(dt) {
                 BaseDataType.UBYTE -> asmgen.out("$name    .byte  ?")
                 BaseDataType.UWORD -> asmgen.out("$name    .word  ?")
-                BaseDataType.FLOAT -> asmgen.out("$name    .fill  ${options.compTarget.machine.FLOAT_MEM_SIZE}")
+                BaseDataType.FLOAT -> asmgen.out("$name    .fill  ${options.compTarget.FLOAT_MEM_SIZE}")
                 else -> throw AssemblyError("weird dt for extravar $dt")
             }
         }
         if(asmGenInfo.usedFloatEvalResultVar1)
-            asmgen.out("$subroutineFloatEvalResultVar1    .fill  ${options.compTarget.machine.FLOAT_MEM_SIZE}")
+            asmgen.out("$subroutineFloatEvalResultVar1    .fill  ${options.compTarget.FLOAT_MEM_SIZE}")
         if(asmGenInfo.usedFloatEvalResultVar2)
-            asmgen.out("$subroutineFloatEvalResultVar2    .fill  ${options.compTarget.machine.FLOAT_MEM_SIZE}")
+            asmgen.out("$subroutineFloatEvalResultVar2    .fill  ${options.compTarget.FLOAT_MEM_SIZE}")
         asmgen.out("  .send BSS")
 
         // normal statically allocated variables
@@ -650,7 +678,7 @@ internal class ProgramAndVarsGen(
             dt.isSignedByte -> asmgen.out("${variable.name}\t.char  ?")
             dt.isUnsignedWord -> asmgen.out("${variable.name}\t.word  ?")
             dt.isSignedWord -> asmgen.out("${variable.name}\t.sint  ?")
-            dt.isFloat -> asmgen.out("${variable.name}\t.fill  ${compTarget.machine.FLOAT_MEM_SIZE}")
+            dt.isFloat -> asmgen.out("${variable.name}\t.fill  ${compTarget.FLOAT_MEM_SIZE}")
             dt.isSplitWordArray -> {
                 alignVar(variable.align)
                 val numbytesPerHalf = compTarget.memorySize(variable.dt, variable.length!!) / 2
@@ -674,28 +702,34 @@ internal class ProgramAndVarsGen(
     }
 
     private fun staticVariable2asm(variable: StStaticVariable) {
-        val initialValue: Number =
-            if(variable.initializationNumericValue!=null) {
-                if(variable.dt.isFloat)
-                    variable.initializationNumericValue!!
-                else
-                    variable.initializationNumericValue!!.toInt()
-            } else 0
+        if(!variable.dt.isArray && !variable.dt.isString) {
+            throw AssemblyError("static variables with an initialization value can only be an array or a string, not ${variable.dt} (${variable.name} ${variable.astNode?.position}")
+            // because numeric variables are in the BSS section and get initialized via assignment statements
+        }
+
+//        val initialValue: Number =
+//            if(variable.initializationNumericValue!=null) {
+//                if(variable.dt.isFloat)
+//                    variable.initializationNumericValue!!
+//                else
+//                    variable.initializationNumericValue!!.toInt()
+//            } else 0
+//
 
         val dt=variable.dt
         when {
-            dt.isBool || dt.isUnsignedByte -> asmgen.out("${variable.name}\t.byte  ${initialValue.toHex()}")
-            dt.isSignedByte -> asmgen.out("${variable.name}\t.char  $initialValue")
-            dt.isUnsignedWord -> asmgen.out("${variable.name}\t.word  ${initialValue.toHex()}")
-            dt.isSignedWord -> asmgen.out("${variable.name}\t.sint  $initialValue")
-            dt.isFloat -> {
-                if(initialValue==0) {
-                    asmgen.out("${variable.name}\t.byte  0,0,0,0,0  ; float")
-                } else {
-                    val floatFill = compTarget.machine.getFloatAsmBytes(initialValue)
-                    asmgen.out("${variable.name}\t.byte  $floatFill  ; float $initialValue")
-                }
-            }
+//            dt.isBool || dt.isUnsignedByte -> asmgen.out("${variable.name}\t.byte  ${initialValue.toHex()}")
+//            dt.isSignedByte -> asmgen.out("${variable.name}\t.char  $initialValue")
+//            dt.isUnsignedWord -> asmgen.out("${variable.name}\t.word  ${initialValue.toHex()}")
+//            dt.isSignedWord -> asmgen.out("${variable.name}\t.sint  $initialValue")
+//            dt.isFloat -> {
+//                if(initialValue==0) {
+//                    asmgen.out("${variable.name}\t.byte  0,0,0,0,0  ; float")
+//                } else {
+//                    val floatFill = compTarget.getFloatAsmBytes(initialValue)
+//                    asmgen.out("${variable.name}\t.byte  $floatFill  ; float $initialValue")
+//                }
+//            }
             dt.isString -> {
                 throw AssemblyError("all string vars should have been interned into prog")
             }
@@ -767,7 +801,7 @@ internal class ProgramAndVarsGen(
             dt.isFloatArray -> {
                 val array = value ?: zeroFilledArray(orNumberOfZeros!!)
                 val floatFills = array.map {
-                    compTarget.machine.getFloatAsmBytes(it.number!!)
+                    compTarget.getFloatAsmBytes(it.number!!)
                 }
                 asmgen.out(varname)
                 for (f in array.zip(floatFills))

codeGenCpu6502/src/prog8/codegen/cpu6502/VariableAllocator.kt

@@ -14,7 +14,7 @@ internal class VariableAllocator(private val symboltable: SymbolTable,
                                  private val errors: IErrorReporter
 ) {
 
-    private val zeropage = options.compTarget.machine.zeropage
+    private val zeropage = options.compTarget.zeropage
     internal val globalFloatConsts = mutableMapOf<Double, String>()     // all float values in the entire program (value -> varname)
     internal val zeropageVars: Map<String, MemoryAllocator.VarAllocation>
 

codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AsmAssignment.kt

@@ -10,7 +10,8 @@ internal enum class TargetStorageKind {
     VARIABLE,
     ARRAY,
     MEMORY,
-    REGISTER
+    REGISTER,
+    VOID       // assign nothing - used in multi-value assigns for void placeholders
 }
 
 internal enum class SourceStorageKind {
@@ -49,6 +50,15 @@ internal class AsmAssignTarget(val kind: TargetStorageKind,
     }
 
     companion object {
+        fun fromAstAssignmentMulti(targets: List<PtAssignTarget>, definingSub: IPtSubroutine?, asmgen: AsmGen6502Internal): List<AsmAssignTarget> {
+            return targets.map {
+                if(it.void)
+                    AsmAssignTarget(TargetStorageKind.VOID, asmgen, DataType.forDt(BaseDataType.UNDEFINED), null, it.position)
+                else
+                    fromAstAssignment(it, definingSub, asmgen)
+            }
+        }
+
         fun fromAstAssignment(target: PtAssignTarget, definingSub: IPtSubroutine?, asmgen: AsmGen6502Internal): AsmAssignTarget {
             with(target) {
                 when {
@@ -130,9 +140,8 @@ internal class AsmAssignTarget(val kind: TargetStorageKind,
             TargetStorageKind.MEMORY -> {
                 left isSameAs memory!!
             }
-            TargetStorageKind.REGISTER -> {
-                false
-            }
+            TargetStorageKind.REGISTER -> false
+            TargetStorageKind.VOID -> false
         }
 }
 
@@ -194,9 +203,12 @@ internal class AsmAssignSource(val kind: SourceStorageKind,
                 is PtFunctionCall -> {
                     val symbol = asmgen.symbolTable.lookup(value.name) ?: throw AssemblyError("lookup error ${value.name}")
                     val sub = symbol.astNode as IPtSubroutine
-                    val returnType = sub.returnsWhatWhere().firstOrNull { rr -> rr.first.registerOrPair != null || rr.first.statusflag!=null }?.second
+                    val returnType =
+                        if(sub is PtSub && sub.returns.size>1)
+                            DataType.forDt(BaseDataType.UNDEFINED)      // TODO list of types instead?
+                        else
+                            sub.returnsWhatWhere().firstOrNull { rr -> rr.first.registerOrPair != null || rr.first.statusflag!=null }?.second
                             ?: throw AssemblyError("can't translate zero return values in assignment")
-
                     AsmAssignSource(SourceStorageKind.EXPRESSION, program, asmgen, returnType, expression = value)
                 }
                 else -> {
@@ -226,27 +238,30 @@ internal class AsmAssignSource(val kind: SourceStorageKind,
 
 
 internal sealed class AsmAssignmentBase(val source: AsmAssignSource,
-                                        val target: AsmAssignTarget,
+                                        val targets: List<AsmAssignTarget>,
                                         val memsizer: IMemSizer,
                                         val position: Position) {
     init {
-        if(target.register !in arrayOf(RegisterOrPair.XY, RegisterOrPair.AX, RegisterOrPair.AY))
-            require(!source.datatype.isUndefined) { "must not be placeholder/undefined datatype at $position" }
-        if(!source.datatype.isArray && !target.datatype.isArray)
-            require(memsizer.memorySize(source.datatype, null) <= memsizer.memorySize(target.datatype, null)) {
-                "source dt size must be less or equal to target dt size at $position srcdt=${source.datatype} targetdt=${target.datatype}"
-            }
+        targets.forEach { target ->
+            if (!source.datatype.isArray && !source.datatype.isUndefined && !target.datatype.isArray && !target.datatype.isUndefined)
+                require(memsizer.memorySize(source.datatype, null) <= memsizer.memorySize(target.datatype, null)) {
+                    "source dt size must be less or equal to target dt size at $position srcdt=${source.datatype} targetdt=${target.datatype}"
+                }
+        }
     }
+
+    val target: AsmAssignTarget
+        get() = targets.single()
 }
 
 internal class AsmAssignment(source: AsmAssignSource,
-                             target: AsmAssignTarget,
+                             targets: List<AsmAssignTarget>,
                              memsizer: IMemSizer,
-                             position: Position): AsmAssignmentBase(source, target, memsizer, position)
+                             position: Position): AsmAssignmentBase(source, targets, memsizer, position)
 
 internal class AsmAugmentedAssignment(source: AsmAssignSource,
                                       val operator: String,
                                       target: AsmAssignTarget,
                                       memsizer: IMemSizer,
-                                      position: Position): AsmAssignmentBase(source, target, memsizer, position)
+                                      position: Position): AsmAssignmentBase(source, listOf(target), memsizer, position)
 

codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AugmentableAssignmentAsmGen.kt

@@ -15,11 +15,11 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
 
         when(assign.operator) {
             "-" -> {
-                val a2 = AsmAssignment(assign.source, assign.target, assign.memsizer, assign.position)
+                val a2 = AsmAssignment(assign.source, assign.targets, assign.memsizer, assign.position)
                 assignmentAsmGen.inplaceNegate(a2, false, scope)
             }
             "~", "not" -> {
-                val a2 = AsmAssignment(assign.source, assign.target, assign.memsizer, assign.position)
+                val a2 = AsmAssignment(assign.source, assign.targets, assign.memsizer, assign.position)
                 assignmentAsmGen.inplaceInvert(a2, scope)
             }
             "+" -> { /* is a nop */ }
@@ -68,18 +68,18 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                 when {
                     target.datatype.isByteOrBool -> {
                         when(value.kind) {
-                            SourceStorageKind.LITERALBOOLEAN -> inplacemodificationByteVariableWithLiteralval(target.asmVarname, target.datatype, operator, value.boolean!!.asInt())
-                            SourceStorageKind.LITERALNUMBER -> inplacemodificationByteVariableWithLiteralval(target.asmVarname, target.datatype, operator, value.number!!.number.toInt())
-                            SourceStorageKind.VARIABLE -> inplacemodificationByteVariableWithVariable(target.asmVarname, target.datatype.isSigned, operator, value.asmVarname)
-                            SourceStorageKind.REGISTER -> inplacemodificationByteVariableWithVariable(target.asmVarname, target.datatype.isSigned, operator, regName(value))
-                            SourceStorageKind.MEMORY -> inplacemodificationByteVariableWithValue(target.asmVarname, target.datatype, operator, value.memory!!)
-                            SourceStorageKind.ARRAY -> inplacemodificationByteVariableWithValue(target.asmVarname, target.datatype, operator, value.array!!)
+                            SourceStorageKind.LITERALBOOLEAN -> inplacemodificationByteWithLiteralval(target.asmVarname, target.datatype, operator, value.boolean!!.asInt())
+                            SourceStorageKind.LITERALNUMBER -> inplacemodificationByteWithLiteralval(target.asmVarname, target.datatype, operator, value.number!!.number.toInt())
+                            SourceStorageKind.VARIABLE -> inplacemodificationByteWithVariable(target.asmVarname, target.datatype.isSigned, operator, value.asmVarname)
+                            SourceStorageKind.REGISTER -> inplacemodificationByteWithVariable(target.asmVarname, target.datatype.isSigned, operator, regName(value))
+                            SourceStorageKind.MEMORY -> inplacemodificationByteWithValue(target.asmVarname, target.datatype, operator, value.memory!!)
+                            SourceStorageKind.ARRAY -> inplacemodificationByteWithValue(target.asmVarname, target.datatype, operator, value.array!!)
                             SourceStorageKind.EXPRESSION -> {
                                 if(value.expression is PtTypeCast) {
                                     if (tryInplaceModifyWithRemovedRedundantCast(value.expression, target, operator)) return
-                                    inplacemodificationByteVariableWithValue(target.asmVarname, target.datatype, operator, value.expression)
+                                    inplacemodificationByteWithValue(target.asmVarname, target.datatype, operator, value.expression)
                                 } else  {
-                                    inplacemodificationByteVariableWithValue(target.asmVarname, target.datatype, operator, value.expression!!)
+                                    inplacemodificationByteWithValue(target.asmVarname, target.datatype, operator, value.expression!!)
                                 }
                             }
                         }
@@ -131,18 +131,18 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                     is PtNumber -> {
                         val addr = (memory.address as PtNumber).number.toInt()
                         when(value.kind) {
-                            SourceStorageKind.LITERALBOOLEAN -> inplacemodificationByteVariableWithLiteralval(addr.toHex(), DataType.forDt(BaseDataType.UBYTE), operator, value.boolean!!.asInt())
-                            SourceStorageKind.LITERALNUMBER -> inplacemodificationByteVariableWithLiteralval(addr.toHex(), DataType.forDt(BaseDataType.UBYTE), operator, value.number!!.number.toInt())
-                            SourceStorageKind.VARIABLE -> inplacemodificationByteVariableWithVariable(addr.toHex(), false, operator, value.asmVarname)
-                            SourceStorageKind.REGISTER -> inplacemodificationByteVariableWithVariable(addr.toHex(), false, operator, regName(value))
-                            SourceStorageKind.MEMORY -> inplacemodificationByteVariableWithValue(addr.toHex(), DataType.forDt(BaseDataType.UBYTE), operator, value.memory!!)
-                            SourceStorageKind.ARRAY -> inplacemodificationByteVariableWithValue(addr.toHex(), DataType.forDt(BaseDataType.UBYTE), operator, value.array!!)
+                            SourceStorageKind.LITERALBOOLEAN -> inplacemodificationByteWithLiteralval(addr.toHex(), DataType.forDt(BaseDataType.UBYTE), operator, value.boolean!!.asInt())
+                            SourceStorageKind.LITERALNUMBER -> inplacemodificationByteWithLiteralval(addr.toHex(), DataType.forDt(BaseDataType.UBYTE), operator, value.number!!.number.toInt())
+                            SourceStorageKind.VARIABLE -> inplacemodificationByteWithVariable(addr.toHex(), false, operator, value.asmVarname)
+                            SourceStorageKind.REGISTER -> inplacemodificationByteWithVariable(addr.toHex(), false, operator, regName(value))
+                            SourceStorageKind.MEMORY -> inplacemodificationByteWithValue(addr.toHex(), DataType.forDt(BaseDataType.UBYTE), operator, value.memory!!)
+                            SourceStorageKind.ARRAY -> inplacemodificationByteWithValue(addr.toHex(), DataType.forDt(BaseDataType.UBYTE), operator, value.array!!)
                             SourceStorageKind.EXPRESSION -> {
                                 if(value.expression is PtTypeCast) {
                                     if (tryInplaceModifyWithRemovedRedundantCast(value.expression, target, operator)) return
-                                    inplacemodificationByteVariableWithValue(addr.toHex(), DataType.forDt(BaseDataType.UBYTE), operator, value.expression)
+                                    inplacemodificationByteWithValue(addr.toHex(), DataType.forDt(BaseDataType.UBYTE), operator, value.expression)
                                 } else {
-                                    inplacemodificationByteVariableWithValue(addr.toHex(), DataType.forDt(BaseDataType.UBYTE), operator, value.expression!!)
+                                    inplacemodificationByteWithValue(addr.toHex(), DataType.forDt(BaseDataType.UBYTE), operator, value.expression!!)
                                 }
                             }
                         }
@@ -169,10 +169,14 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                     else -> {
                         if(memory.address is PtBinaryExpression && tryOptimizedMemoryInplace(memory.address as PtBinaryExpression, operator, value))
                             return
+                        // slower method to calculate and use the pointer to access the memory with:
                         asmgen.assignExpressionToRegister(memory.address, RegisterOrPair.AY, false)
                         asmgen.saveRegisterStack(CpuRegister.A, true)
                         asmgen.saveRegisterStack(CpuRegister.Y, true)
-                        asmgen.out("  jsr  prog8_lib.read_byte_from_address_in_AY_into_A")
+                        if(asmgen.isTargetCpu(CpuType.CPU65C02))
+                            asmgen.out("  jsr  prog8_lib.read_byte_from_address_in_AY_into_A_65c02")
+                        else
+                            asmgen.out("  jsr  prog8_lib.read_byte_from_address_in_AY_into_A")
                         when(value.kind) {
                             SourceStorageKind.LITERALBOOLEAN -> {
                                 inplacemodificationRegisterAwithVariable(operator, "#${value.boolean!!.asInt()}", false)
@@ -192,27 +196,30 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                             }
                             SourceStorageKind.MEMORY -> {
                                 asmgen.out("  sta  P8ZP_SCRATCH_B1")
-                                inplacemodificationByteVariableWithValue("P8ZP_SCRATCH_B1", DataType.forDt(BaseDataType.UBYTE), operator, value.memory!!)
+                                inplacemodificationByteWithValue("P8ZP_SCRATCH_B1", DataType.forDt(BaseDataType.UBYTE), operator, value.memory!!)
                                 asmgen.out("  ldx  P8ZP_SCRATCH_B1")
                             }
                             SourceStorageKind.ARRAY -> {
                                 asmgen.out("  sta  P8ZP_SCRATCH_B1")
-                                inplacemodificationByteVariableWithValue("P8ZP_SCRATCH_B1", DataType.forDt(BaseDataType.UBYTE), operator, value.array!!)
+                                inplacemodificationByteWithValue("P8ZP_SCRATCH_B1", DataType.forDt(BaseDataType.UBYTE), operator, value.array!!)
                                 asmgen.out("  ldx  P8ZP_SCRATCH_B1")
                             }
                             SourceStorageKind.EXPRESSION -> {
                                 val tempVar = asmgen.getTempVarName(BaseDataType.UBYTE)
                                 asmgen.out("  sta  $tempVar")
                                 if(value.expression is PtTypeCast)
-                                    inplacemodificationByteVariableWithValue(tempVar, DataType.forDt(BaseDataType.UBYTE), operator, value.expression)
+                                    inplacemodificationByteWithValue(tempVar, DataType.forDt(BaseDataType.UBYTE), operator, value.expression)
                                 else
-                                    inplacemodificationByteVariableWithValue(tempVar, DataType.forDt(BaseDataType.UBYTE), operator, value.expression!!)
+                                    inplacemodificationByteWithValue(tempVar, DataType.forDt(BaseDataType.UBYTE), operator, value.expression!!)
                                 asmgen.out("  ldx  $tempVar")
                             }
                         }
                         asmgen.restoreRegisterStack(CpuRegister.Y, false)
                         asmgen.restoreRegisterStack(CpuRegister.A, false)
-                        asmgen.out("  jsr  prog8_lib.write_byte_X_to_address_in_AY")
+                        if(asmgen.isTargetCpu(CpuType.CPU65C02))
+                            asmgen.out("  jsr  prog8_lib.write_byte_X_to_address_in_AY_65c02")
+                        else
+                            asmgen.out("  jsr  prog8_lib.write_byte_X_to_address_in_AY")
                     }
                 }
             }
@@ -227,7 +234,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                                 // TODO: more optimized code for VARIABLE, REGISTER, MEMORY, ARRAY, EXPRESSION in the case of split-word arrays
                                 val scope = target.origAstTarget?.definingISub()
                                 val regTarget = AsmAssignTarget.fromRegisters(RegisterOrPair.R0, false, target.position, scope, asmgen)
-                                val assignToReg = AsmAssignment(value, regTarget, program.memsizer, target.position)
+                                val assignToReg = AsmAssignment(value, listOf(regTarget), program.memsizer, target.position)
                                 assignmentAsmGen.translateNormalAssignment(assignToReg, scope)
                                 inplacemodificationSplitWordWithR0(target.asmVarname, index, operator)
                             }
@@ -239,18 +246,18 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                     when {
                         target.datatype.isByteOrBool -> {
                             when(value.kind) {
-                                SourceStorageKind.LITERALBOOLEAN -> inplacemodificationByteVariableWithLiteralval(targetVarName, target.datatype, operator, value.boolean!!.asInt())
-                                SourceStorageKind.LITERALNUMBER -> inplacemodificationByteVariableWithLiteralval(targetVarName, target.datatype, operator, value.number!!.number.toInt())
-                                SourceStorageKind.VARIABLE -> inplacemodificationByteVariableWithVariable(targetVarName, target.datatype.isSigned, operator, value.asmVarname)
-                                SourceStorageKind.REGISTER -> inplacemodificationByteVariableWithVariable(targetVarName, target.datatype.isSigned, operator, regName(value))
-                                SourceStorageKind.MEMORY -> inplacemodificationByteVariableWithValue(targetVarName, target.datatype, operator, value.memory!!)
-                                SourceStorageKind.ARRAY -> inplacemodificationByteVariableWithValue(targetVarName, target.datatype, operator, value.array!!)
+                                SourceStorageKind.LITERALBOOLEAN -> inplacemodificationByteWithLiteralval(targetVarName, target.datatype, operator, value.boolean!!.asInt())
+                                SourceStorageKind.LITERALNUMBER -> inplacemodificationByteWithLiteralval(targetVarName, target.datatype, operator, value.number!!.number.toInt())
+                                SourceStorageKind.VARIABLE -> inplacemodificationByteWithVariable(targetVarName, target.datatype.isSigned, operator, value.asmVarname)
+                                SourceStorageKind.REGISTER -> inplacemodificationByteWithVariable(targetVarName, target.datatype.isSigned, operator, regName(value))
+                                SourceStorageKind.MEMORY -> inplacemodificationByteWithValue(targetVarName, target.datatype, operator, value.memory!!)
+                                SourceStorageKind.ARRAY -> inplacemodificationByteWithValue(targetVarName, target.datatype, operator, value.array!!)
                                 SourceStorageKind.EXPRESSION -> {
                                     if(value.expression is PtTypeCast) {
                                         if (tryInplaceModifyWithRemovedRedundantCast(value.expression, target, operator)) return
-                                        inplacemodificationByteVariableWithValue(targetVarName, target.datatype, operator, value.expression)
+                                        inplacemodificationByteWithValue(targetVarName, target.datatype, operator, value.expression)
                                     } else {
-                                        inplacemodificationByteVariableWithValue(targetVarName, target.datatype, operator, value.expression!!)
+                                        inplacemodificationByteWithValue(targetVarName, target.datatype, operator, value.expression!!)
                                     }
                                 }
                             }
@@ -336,14 +343,14 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
 
                                 SourceStorageKind.MEMORY -> {
                                     asmgen.out("  sta  P8ZP_SCRATCH_B1")
-                                    inplacemodificationByteVariableWithValue("P8ZP_SCRATCH_B1", target.datatype, operator, value.memory!!)
+                                    inplacemodificationByteWithValue("P8ZP_SCRATCH_B1", target.datatype, operator, value.memory!!)
                                     asmgen.restoreRegisterStack(CpuRegister.Y, false)
                                     asmgen.out("  lda  P8ZP_SCRATCH_B1")
                                 }
 
                                 SourceStorageKind.ARRAY -> {
                                     asmgen.out("  sta  P8ZP_SCRATCH_B1")
-                                    inplacemodificationByteVariableWithValue("P8ZP_SCRATCH_B1", target.datatype, operator, value.array!!)
+                                    inplacemodificationByteWithValue("P8ZP_SCRATCH_B1", target.datatype, operator, value.array!!)
                                     asmgen.restoreRegisterStack(CpuRegister.Y, false)
                                     asmgen.out("  lda  P8ZP_SCRATCH_B1")
                                 }
@@ -352,9 +359,9 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                                     val tempVar = asmgen.getTempVarName(BaseDataType.UBYTE)
                                     asmgen.out("  sta  $tempVar")
                                     if(value.expression is PtTypeCast)
-                                        inplacemodificationByteVariableWithValue(tempVar, target.datatype, operator, value.expression)
+                                        inplacemodificationByteWithValue(tempVar, target.datatype, operator, value.expression)
                                     else
-                                        inplacemodificationByteVariableWithValue(tempVar, target.datatype, operator, value.expression!!)
+                                        inplacemodificationByteWithValue(tempVar, target.datatype, operator, value.expression!!)
                                     asmgen.restoreRegisterStack(CpuRegister.Y, false)
                                     asmgen.out("  lda  $tempVar")
                                 }
@@ -503,6 +510,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                 }
             }
             TargetStorageKind.REGISTER -> throw AssemblyError("no asm gen for reg in-place modification")
+            TargetStorageKind.VOID -> { /* do nothing */ }
         }
     }
 
@@ -583,8 +591,10 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
 
         fun assignValueToA() {
             val assignValue = AsmAssignment(value,
-                AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, DataType.forDt(BaseDataType.UBYTE),
-                    address.definingISub(), Position.DUMMY, register = RegisterOrPair.A),
+                listOf(
+                    AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, DataType.forDt(BaseDataType.UBYTE),
+                    address.definingISub(), Position.DUMMY, register = RegisterOrPair.A)
+                ),
                 program.memsizer, Position.DUMMY)
             assignmentAsmGen.translateNormalAssignment(assignValue, address.definingISub())   // calculate value into A
         }
@@ -668,7 +678,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                     sbc  cx16.r0H
                     sta  ${arrayVar}_msb+$index""")
             }
-            else -> TODO("in-place modify split-words array value for operator $operator")
+            else -> TODO("inplace split word array value $operator")
         }
     }
 
@@ -734,8 +744,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                     txa
                     ora  $variable+1
                     tax
-                    tya
-                """)
+                    tya""")
                 return true
             }
             "&" -> {
@@ -745,8 +754,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                     txa
                     and  $variable+1
                     tax
-                    tya
-                """)
+                    tya""")
                 return true
             }
             "^" -> {
@@ -756,8 +764,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                     txa
                     eor  $variable+1
                     tax
-                    tya
-                """)
+                    tya""")
                 return true
             }
             else -> return false
@@ -768,7 +775,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
         when(operator) {
             "+" -> {
                 if(number==1) {
-                    if(asmgen.isTargetCpu(CpuType.CPU65c02)) {
+                    if(asmgen.isTargetCpu(CpuType.CPU65C02)) {
                         asmgen.out("""
                             inc  a
                             bne  +
@@ -806,7 +813,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
             }
             "-" -> {
                 if(number==1) {
-                    if(asmgen.isTargetCpu(CpuType.CPU65c02)) {
+                    if(asmgen.isTargetCpu(CpuType.CPU65C02)) {
                         asmgen.out("""
                             cmp  #0
                             bne  +
@@ -849,8 +856,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                     txa
                     ora  #>$number
                     tax
-                    tya
-                """)
+                    tya""")
                 return true
             }
             "&" -> {
@@ -860,8 +866,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                     txa
                     and  #>$number
                     tax
-                    tya
-                """)
+                    tya""")
                 return true
             }
             "^" -> {
@@ -871,8 +876,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
                     txa
                     eor  #>$number
                     tax
-                    tya
-                """)
+                    tya""")
                 return true
             }
             else -> return false
@@ -1057,7 +1061,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
         }
     }
 
-    private fun inplacemodificationByteVariableWithValue(name: String, dt: DataType, operator: String, value: PtExpression) {
+    private fun inplacemodificationByteWithValue(name: String, dt: DataType, operator: String, value: PtExpression) {
         require(dt.isByteOrBool)
         if(!value.isSimple()) {
             // attempt short-circuit (McCarthy) evaluation
@@ -1087,7 +1091,7 @@ $shortcutLabel:""")
             }
         }
 
-        if(asmgen.isTargetCpu(CpuType.CPU65c02)) {
+        if(asmgen.isTargetCpu(CpuType.CPU65C02)) {
             if(operator=="&" && value is PtPrefix && value.operator=="~") {
                 // M &= ~A  -->  use TRB 65c02 instruction for that
                 asmgen.assignExpressionToRegister(value.value, RegisterOrPair.A, dt.isSigned)
@@ -1102,16 +1106,30 @@ $shortcutLabel:""")
             }
         }
 
+        if(value is PtArrayIndexer && value.isSimple()) {
+            // use the already existing optimized codegen for regular assignments  x += array[index]
+            val binexpr = PtBinaryExpression(operator, dt, value.position)
+            binexpr.add(PtIdentifier(name, dt, value.position))
+            val arrayValue = PtArrayIndexer(value.type, value.position)
+            arrayValue.add(value.variable)
+            arrayValue.add(value.index)
+            binexpr.add(arrayValue)
+            binexpr.parent = value
+            assignmentAsmGen.assignExpressionToRegister(binexpr, RegisterOrPair.A, dt.isSigned)
+            asmgen.out("  sta  $name")
+            return
+        }
+
         // normal evaluation
         asmgen.assignExpressionToRegister(value, RegisterOrPair.A, dt.isSigned)
         inplacemodificationRegisterAwithVariableWithSwappedOperands(operator, name, dt.isSigned)
         asmgen.out("  sta  $name")
     }
 
-    private fun inplacemodificationByteVariableWithVariable(name: String, signed: Boolean, operator: String, otherName: String) {
+    private fun inplacemodificationByteWithVariable(name: String, signed: Boolean, operator: String, otherName: String) {
         // note: no logical and/or shortcut here, not worth it due to simple right operand
 
-        if(asmgen.isTargetCpu(CpuType.CPU65c02)) {
+        if(asmgen.isTargetCpu(CpuType.CPU65C02)) {
             if(operator=="|") {
                 // M |= A  -->  use TSB 65c02 instruction for that
                 asmgen.out("  lda  $otherName |  tsb  $name")
@@ -1126,7 +1144,7 @@ $shortcutLabel:""")
 
     private fun inplacemodificationRegisterAwithVariable(operator: String, variable: String, signed: Boolean) {
         if(operator in "+-" && variable in arrayOf("#1", "#$1", "#$01", "#%1", "#%00000001")) {
-            if(asmgen.isTargetCpu(CpuType.CPU65c02)) {
+            if(asmgen.isTargetCpu(CpuType.CPU65C02)) {
                 if(operator=="+")
                     asmgen.out("  inc  a")
                 else
@@ -1314,6 +1332,7 @@ $shortcutLabel:""")
         when (operator) {
             "-" -> {
                 // A = variable - A
+                // TODO optimize codegen to avoid temporary
                 val tmpVar = if(variable!="P8ZP_SCRATCH_B1") "P8ZP_SCRATCH_B1" else "P8ZP_SCRATCH_REG"
                 asmgen.out("  sta  $tmpVar |  lda  $variable |  sec |  sbc  $tmpVar")
             }
@@ -1465,7 +1484,7 @@ $shortcutLabel:""")
         }
     }
 
-    private fun inplacemodificationByteVariableWithLiteralval(name: String, dt: DataType, operator: String, value: Int) {
+    private fun inplacemodificationByteWithLiteralval(name: String, dt: DataType, operator: String, value: Int) {
         // note: this contains special optimized cases because we know the exact value. Don't replace this with another routine.
         // note: no logical and/or shortcut here, not worth it due to simple right operand
         require(dt.isByteOrBool)
@@ -1502,7 +1521,7 @@ $shortcutLabel:""")
             }
             "<<" -> {
                 if(value>=8) {
-                    if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                    if(asmgen.isTargetCpu(CpuType.CPU65C02))
                         asmgen.out("  stz  $name")
                     else
                         asmgen.out("  lda  #0 |  sta  $name")
@@ -1513,7 +1532,7 @@ $shortcutLabel:""")
                 if(value>0) {
                     if (dt.isUnsignedByte) {
                         if(value>=8) {
-                            if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                            if(asmgen.isTargetCpu(CpuType.CPU65C02))
                                 asmgen.out("  stz  $name")
                             else
                                 asmgen.out("  lda  #0 |  sta  $name")
@@ -1695,7 +1714,7 @@ $shortcutLabel:""")
                 asmgen.translateDirectMemReadExpressionToRegA(memread)
                 asmgen.out("  and  $name  |  sta  $name")
                 if(dt.isWord) {
-                    if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                    if(asmgen.isTargetCpu(CpuType.CPU65C02))
                         asmgen.out("  stz  $name+1")
                     else
                         asmgen.out("  lda  #0 |  sta  $name+1")
@@ -1834,8 +1853,7 @@ $shortcutLabel:""")
                             ldy  #>$value
                             jsr  prog8_math.divmod_w_asm
                             sta  $lsb
-                            sty  $msb
-                        """)
+                            sty  $msb""")
                     }
                     else {
                         asmgen.out("""
@@ -1847,8 +1865,7 @@ $shortcutLabel:""")
                             ldy  #>$value
                             jsr  prog8_math.divmod_uw_asm
                             sta  $lsb
-                            sty  $msb
-                        """)
+                            sty  $msb""")
                     }
                 }
             }
@@ -1868,31 +1885,43 @@ $shortcutLabel:""")
                     lda  P8ZP_SCRATCH_W2
                     ldy  P8ZP_SCRATCH_W2+1
                     sta  $lsb
-                    sty  $msb
-                """)
+                    sty  $msb""")
             }
             "<<" -> {
                 when {
                     value>=16 -> {
-                        if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                        if(asmgen.isTargetCpu(CpuType.CPU65C02))
                             asmgen.out("  stz  $lsb |  stz  $msb")
                         else
                             asmgen.out("  lda  #0 |  sta  $lsb |  sta  $msb")
                     }
                     value==8 -> {
                         asmgen.out("  lda  $lsb |  sta  $msb")
-                        if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                        if(asmgen.isTargetCpu(CpuType.CPU65C02))
                             asmgen.out("  stz  $lsb")
                         else
                             asmgen.out("  lda  #0 |  sta  $lsb")
                     }
+                    value==7 -> {
+                        // optimized shift left 7 (*128) by first swapping the lsb/msb and then doing just one final shift
+                        asmgen.out("""
+                            ; shift left 7
+                            lsr  $msb
+                            php     ; save carry
+                            lda  $lsb
+                            sta  $msb
+                            lda  #0
+                            sta  $lsb
+                            plp     ; restore carry
+                            ror  $msb
+                            ror  $lsb""")
+                    }
                     value>3 -> asmgen.out("""
                         ldy  #$value
 -                       asl  $lsb
                         rol  $msb
                         dey
-                        bne  -
-                    """)
+                        bne  -""")
                     else -> repeat(value) { asmgen.out(" asl  $lsb |  rol  $msb") }
                 }
             }
@@ -1901,14 +1930,14 @@ $shortcutLabel:""")
                     if(dt.isUnsignedWord) {
                         when {
                             value>=16 -> {
-                                if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                                if(asmgen.isTargetCpu(CpuType.CPU65C02))
                                     asmgen.out("  stz  $lsb |  stz  $msb")
                                 else
                                     asmgen.out("  lda  #0 |  sta  $lsb |  sta  $msb")
                             }
                             value==8 -> {
                                 asmgen.out("  lda  $msb |  sta  $lsb")
-                                if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                                if(asmgen.isTargetCpu(CpuType.CPU65C02))
                                     asmgen.out("  stz  $msb")
                                 else
                                     asmgen.out("  lda  #0 |  sta  $msb")
@@ -1957,25 +1986,25 @@ $shortcutLabel:""")
             "&" -> {
                 when {
                     value == 0 -> {
-                        if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                        if(asmgen.isTargetCpu(CpuType.CPU65C02))
                             asmgen.out("  stz  $lsb |  stz  $msb")
                         else
                             asmgen.out("  lda  #0 |  sta  $lsb |  sta  $msb")
                     }
                     value == 0x00ff -> {
-                        if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                        if(asmgen.isTargetCpu(CpuType.CPU65C02))
                             asmgen.out("  stz  $msb")
                         else
                             asmgen.out("  lda  #0 |  sta  $msb")
                     }
                     value == 0xff00 -> {
-                        if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                        if(asmgen.isTargetCpu(CpuType.CPU65C02))
                             asmgen.out("  stz  $lsb")
                         else
                             asmgen.out("  lda  #0 |  sta  $lsb")
                     }
                     value and 255 == 0 -> {
-                        if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                        if(asmgen.isTargetCpu(CpuType.CPU65C02))
                             asmgen.out("  stz  $lsb")
                         else
                             asmgen.out("  lda  #0 |  sta  $lsb")
@@ -1983,7 +2012,7 @@ $shortcutLabel:""")
                     }
                     value < 0x0100 -> {
                         asmgen.immediateAndInplace(lsb, value)
-                        if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                        if(asmgen.isTargetCpu(CpuType.CPU65C02))
                             asmgen.out("  stz  $msb")
                         else
                             asmgen.out("  lda  #0 |  sta  $msb")
@@ -2268,7 +2297,7 @@ $shortcutLabel:""")
                             // cx16 verafx hardware muls
                             if(valueDt.isUnsignedByte) {
                                 asmgen.out("  lda  $otherName |  sta  cx16.r1")
-                                if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                                if(asmgen.isTargetCpu(CpuType.CPU65C02))
                                     asmgen.out("  stz  cx16.r1+1")
                                 else
                                     asmgen.out("  lda  #0 |  sta  cx16.r1+1")
@@ -2288,7 +2317,7 @@ $shortcutLabel:""")
                         } else {
                             if(valueDt.isUnsignedByte) {
                                 asmgen.out("  lda  $otherName |  sta  prog8_math.multiply_words.multiplier")
-                                if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                                if(asmgen.isTargetCpu(CpuType.CPU65C02))
                                     asmgen.out("  stz  prog8_math.multiply_words.multiplier+1")
                                 else
                                     asmgen.out("  lda  #0 |  sta  prog8_math.multiply_words.multiplier+1")
@@ -2316,8 +2345,7 @@ $shortcutLabel:""")
                                 ldy  #0
                                 jsr  prog8_math.divmod_uw_asm
                                 sta  $name
-                                sty  $name+1
-                            """)
+                                sty  $name+1""")
                         } else {
                             asmgen.out("""
                                 lda  $name
@@ -2328,8 +2356,7 @@ $shortcutLabel:""")
                                 ldy  #0
                                 jsr  prog8_math.divmod_w_asm
                                 sta  $name
-                                sty  $name+1
-                            """)
+                                sty  $name+1""")
                         }
                     }
                     "%" -> {
@@ -2346,8 +2373,7 @@ $shortcutLabel:""")
                             lda  P8ZP_SCRATCH_W2
                             sta  $name
                             lda  P8ZP_SCRATCH_W2+1
-                            sta  $name+1
-                        """)
+                            sta  $name+1""")
                     }
                     "<<" -> {
                         asmgen.out("""
@@ -2384,7 +2410,7 @@ $shortcutLabel:""")
                     }
                     "&" -> {
                         asmgen.out("  lda  $otherName |  and  $name |  sta  $name")
-                        if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                        if(asmgen.isTargetCpu(CpuType.CPU65C02))
                             asmgen.out("  stz  $name+1")
                         else
                             asmgen.out("  lda  #0 |  sta  $name+1")
@@ -2496,8 +2522,7 @@ $shortcutLabel:""")
                             lda  P8ZP_SCRATCH_W2
                             sta  $name
                             lda  P8ZP_SCRATCH_W2+1
-                            sta  $name+1
-                        """)
+                            sta  $name+1""")
                     }
                     "<<", ">>" -> {
                         throw AssemblyError("shift by a word variable not supported, max is a byte")
@@ -2634,30 +2659,28 @@ $shortcutLabel:""")
 
     private fun inplacemodificationWordWithValue(name: String, dt: DataType, operator: String, value: PtExpression, block: PtBlock?) {
         require(dt.isWord)
-        fun multiplyVarByWordInAY() {
+        fun multiplyVarByWordInAX() {
             if(block?.options?.veraFxMuls==true)
                 // cx16 verafx hardware muls
                 asmgen.out("""
                     sta  cx16.r1
-                    sty  cx16.r1+1
+                    stx  cx16.r1+1
                     lda  $name
-                    ldy  $name+1
+                    ldx  $name+1
                     sta  cx16.r0
-                    sty  cx16.r0+1
+                    stx  cx16.r0+1
                     jsr  verafx.muls
                     sta  $name
-                    sty  $name+1
-                """)
+                    sty  $name+1""")
             else
                 asmgen.out("""
                     sta  prog8_math.multiply_words.multiplier
-                    sty  prog8_math.multiply_words.multiplier+1
+                    stx  prog8_math.multiply_words.multiplier+1
                     lda  $name
                     ldy  $name+1
                     jsr  prog8_math.multiply_words
                     sta  $name
-                    sty  $name+1
-                """)
+                    sty  $name+1""")
         }
 
         fun divideVarByWordInAY() {
@@ -2689,8 +2712,7 @@ $shortcutLabel:""")
                 lda  P8ZP_SCRATCH_W2
                 ldy  P8ZP_SCRATCH_W2+1
                 sta  $name
-                sty  $name+1
-            """)
+                sty  $name+1""")
         }
         val valueDt = value.type
         when {
@@ -2753,8 +2775,8 @@ $shortcutLabel:""")
                         // value is (u) byte value, sign extend that and proceed with regular 16 bit operation
                         // TODO use an optimized word * byte multiplication routine?
                         asmgen.assignExpressionToRegister(value, RegisterOrPair.A)
-                        asmgen.signExtendAYlsb(valueDt.base)
-                        multiplyVarByWordInAY()
+                        asmgen.signExtendAXlsb(valueDt.base)
+                        multiplyVarByWordInAX()
                     }
                     "/" -> {
                         // value is (u) byte value, sign extend that and proceed with regular 16 bit operation
@@ -2804,7 +2826,7 @@ $shortcutLabel:""")
                     "&" -> {
                         asmgen.assignExpressionToRegister(value, RegisterOrPair.A)
                         asmgen.out("  and  $name |  sta  $name")
-                        if(asmgen.isTargetCpu(CpuType.CPU65c02))
+                        if(asmgen.isTargetCpu(CpuType.CPU65C02))
                             asmgen.out("  stz  $name+1")
                         else
                             asmgen.out("  lda  #0 |  sta  $name+1")
@@ -2852,6 +2874,66 @@ $shortcutLabel:""")
             }
             valueDt.isWord -> {
                 // the value is a proper 16-bit word, so use both bytes of it.
+
+                if(value is PtArrayIndexer && value.isSimple()) {
+                    // note: use AX as much as possible, to free Y for array indexing
+                    when (operator) {
+                        // note: use AX as much as possible, to free Y for array indexing
+                        "+" -> {
+                            asmgen.assignExpressionToRegister(value, RegisterOrPair.AX)
+                            asmgen.out("  clc |  adc  $name |  sta  $name |  txa |  adc  $name+1 |  sta  $name+1")
+                            return
+                        }
+                        "-" -> {
+                            if(value.index.type.isByte) {
+                                // it's an array indexed by a byte so we can use sbc array,y
+                                val arrayname = value.variable.name
+                                asmgen.loadScaledArrayIndexIntoRegister(value, CpuRegister.Y)
+                                if(value.splitWords) {
+                                    asmgen.out("""
+                                        lda  $name
+                                        sec
+                                        sbc  ${arrayname}_lsb,y
+                                        sta  $name
+                                        lda  $name+1
+                                        sbc  ${arrayname}_msb,y
+                                        sta  $name+1""")
+                                } else {
+                                    asmgen.out("""
+                                        lda  $name
+                                        sec
+                                        sbc  $arrayname,y
+                                        sta  $name
+                                        lda  $name+1
+                                        sbc  $arrayname+1,y
+                                        sta  $name+1""")
+                                }
+                                return
+                            }
+                        }
+                        "*" -> {
+                            asmgen.assignExpressionToRegister(value, RegisterOrPair.AX)
+                            multiplyVarByWordInAX()
+                            return
+                        }
+                        "&" -> {
+                            asmgen.assignExpressionToRegister(value, RegisterOrPair.AX)
+                            asmgen.out("  and  $name |  sta  $name |  txa |  and  $name+1 |  sta  $name+1")
+                            return
+                        }
+                        "|" -> {
+                            asmgen.assignExpressionToRegister(value, RegisterOrPair.AX)
+                            asmgen.out("  ora  $name |  sta  $name |  txa |  ora  $name+1 |  sta  $name+1")
+                            return
+                        }
+                        "^" -> {
+                            asmgen.assignExpressionToRegister(value, RegisterOrPair.AX)
+                            asmgen.out("  eor  $name |  sta  $name |  txa |  eor  $name+1 |  sta  $name+1")
+                            return
+                        }
+                    }
+                }
+
                 when (operator) {
                     "+" -> {
                         asmgen.assignExpressionToRegister(value, RegisterOrPair.AY)
@@ -2860,11 +2942,11 @@ $shortcutLabel:""")
                     "-" -> {
                         val tmpWord = if(name!="P8ZP_SCRATCH_W1") "P8ZP_SCRATCH_W1" else "P8ZP_SCRATCH_W2"
                         asmgen.assignExpressionToVariable(value, tmpWord, valueDt)
-                        asmgen.out(" lda  $name |  sec |  sbc  $tmpWord |  sta  $name |  lda  $name+1 |  sbc  $tmpWord+1 |  sta  $name+1")
+                        asmgen.out("  lda  $name |  sec |  sbc  $tmpWord |  sta  $name |  lda  $name+1 |  sbc  $tmpWord+1 |  sta  $name+1")
                     }
                     "*" -> {
-                        asmgen.assignExpressionToRegister(value, RegisterOrPair.AY)
-                        multiplyVarByWordInAY()
+                        asmgen.assignExpressionToRegister(value, RegisterOrPair.AX)
+                        multiplyVarByWordInAX()
                     }
                     "/" -> {
                         asmgen.assignExpressionToRegister(value, RegisterOrPair.AY)
@@ -2893,37 +2975,7 @@ $shortcutLabel:""")
                         asmgen.assignExpressionToRegister(value, RegisterOrPair.AY)
                         asmgen.out("  eor  $name |  sta  $name |  tya |  eor  $name+1 |  sta  $name+1")
                     }
-                    "==" -> {
-                        asmgen.assignExpressionToRegister(value, RegisterOrPair.AY)
-                        asmgen.out("""
-                            cmp  $name
-                            bne  +
-                            cpy  $name+1
-                            bne  +
-                            lda  #1
-                            bne  ++
-+                           lda  #0
-+                           sta  $name
-                            lda  #0
-                            sta  $name+1""")
-                    }
-                    "!=" -> {
-                        asmgen.assignExpressionToRegister(value, RegisterOrPair.AY)
-                        asmgen.out("""
-                            cmp  $name
-                            bne  +
-                            cpy  $name+1
-                            bne  +
-                            lda  #0
-                            beq  ++
-+                           lda  #1
-+                           sta  $name
-                            lda  #0
-                            sta  $name+1""")
-                    }
-                    // pretty uncommon, who's going to assign a comparison boolean expression to a word var?:
-                    "<", "<=", ">", ">=" -> TODO("word-value-to-var comparisons")
-                    else -> throw AssemblyError("invalid operator for in-place modification $operator")
+                    else -> throw AssemblyError("invalid operator for in-place word modification $operator")
                 }
             }
             else -> throw AssemblyError("can only use integer datatypes here")
@@ -2937,29 +2989,25 @@ $shortcutLabel:""")
                 asmgen.out("""
                     lda  #<$name
                     ldy  #>$name
-                    jsr  floats.FADD
-                """)
+                    jsr  floats.FADD""")
             }
             "-" -> {
                 asmgen.out("""
                     lda  #<$name
                     ldy  #>$name
-                    jsr  floats.FSUB
-                """)
+                    jsr  floats.FSUB""")
             }
             "*" -> {
                 asmgen.out("""
                     lda  #<$name
                     ldy  #>$name
-                    jsr  floats.FMULT
-                """)
+                    jsr  floats.FMULT""")
             }
             "/" -> {
                 asmgen.out("""
                     lda  #<$name
                     ldy  #>$name
-                    jsr  floats.FDIV
-                """)
+                    jsr  floats.FDIV""")
             }
             // pretty uncommon, who's going to assign a comparison boolean expression to a float var:
             "==" -> TODO("float-value-to-var comparison ==")
@@ -2971,8 +3019,7 @@ $shortcutLabel:""")
         asmgen.out("""
             ldx  #<$name
             ldy  #>$name
-            jsr  floats.MOVMF
-        """)
+            jsr  floats.MOVMF""")
     }
 
     private fun inplacemodificationFloatWithVariable(name: String, operator: String, otherName: String) {
@@ -2984,8 +3031,7 @@ $shortcutLabel:""")
                     jsr  floats.MOVFM
                     lda  #<$otherName
                     ldy  #>$otherName
-                    jsr  floats.FADD
-                """)
+                    jsr  floats.FADD""")
             }
             "-" -> {
                 asmgen.out("""
@@ -2994,8 +3040,7 @@ $shortcutLabel:""")
                     jsr  floats.MOVFM
                     lda  #<$name
                     ldy  #>$name
-                    jsr  floats.FSUB
-                """)
+                    jsr  floats.FSUB""")
             }
             "*" -> {
                 asmgen.out("""
@@ -3004,8 +3049,7 @@ $shortcutLabel:""")
                     jsr  floats.MOVFM
                     lda  #<$otherName
                     ldy  #>$otherName
-                    jsr  floats.FMULT
-                """)
+                    jsr  floats.FMULT""")
             }
             "/" -> {
                 asmgen.out("""
@@ -3014,8 +3058,7 @@ $shortcutLabel:""")
                     jsr  floats.MOVFM
                     lda  #<$name
                     ldy  #>$name
-                    jsr  floats.FDIV
-                """)
+                    jsr  floats.FDIV""")
             }
             // pretty uncommon, who's going to assign a comparison boolean expression to a float var:
             "==" -> {
@@ -3085,8 +3128,7 @@ $shortcutLabel:""")
         asmgen.out("""
             ldx  #<$name
             ldy  #>$name
-            jsr  floats.MOVMF
-        """)
+            jsr  floats.MOVMF""")
     }
 
     private fun inplacemodificationFloatWithLiteralval(name: String, operator: String, value: Double) {
@@ -3104,16 +3146,14 @@ $shortcutLabel:""")
                         lda  #<$name
                         ldy  #>$name
                         jsr  floats.MOVFM
-                        jsr  floats.FADDH
-                    """)
+                        jsr  floats.FADDH""")
                     else -> asmgen.out("""
                         lda  #<$name
                         ldy  #>$name
                         jsr  floats.MOVFM
                         lda  #<$constValueName
                         ldy  #>$constValueName
-                        jsr  floats.FADD
-                    """)
+                        jsr  floats.FADD""")
                 }
             }
             "-" -> {
@@ -3129,8 +3169,7 @@ $shortcutLabel:""")
                     jsr  floats.MOVFM
                     lda  #<$name
                     ldy  #>$name
-                    jsr  floats.FSUB
-                """)
+                    jsr  floats.FSUB""")
             }
             "*" -> {
                 // assume that code optimization is already done on the AST level for special cases such as 0, 1, 2...
@@ -3139,8 +3178,7 @@ $shortcutLabel:""")
                         lda  #<$name
                         ldy  #>$name
                         jsr  floats.MOVFM
-                        jsr  floats.MUL10
-                    """)
+                        jsr  floats.MUL10""")
                 } else {
                     asmgen.out("""
                         lda  #<$name
@@ -3148,8 +3186,7 @@ $shortcutLabel:""")
                         jsr  floats.MOVFM
                         lda  #<$constValueName
                         ldy  #>$constValueName
-                        jsr  floats.FMULT
-                    """)
+                        jsr  floats.FMULT""")
                 }
             }
             "/" -> {
@@ -3161,8 +3198,7 @@ $shortcutLabel:""")
                     jsr  floats.MOVFM
                     lda  #<$name
                     ldy  #>$name
-                    jsr  floats.FDIV
-                """)
+                    jsr  floats.FDIV""")
             }
             "==" -> {
                 asmgen.out("""
@@ -3231,7 +3267,6 @@ $shortcutLabel:""")
         asmgen.out("""
             ldx  #<$name
             ldy  #>$name
-            jsr  floats.MOVMF
-        """)
+            jsr  floats.MOVMF""")
     }
 }

codeGenCpu6502/test/TestCodegen.kt

@@ -27,7 +27,7 @@ class TestCodegen: FunSpec({
             floats = true,
             noSysInit = false,
             compTarget = target,
-            loadAddress = target.machine.PROGRAM_LOAD_ADDRESS,
+            loadAddress = target.PROGRAM_LOAD_ADDRESS,
             memtopAddress = 0xffffu
         )
     }
@@ -48,13 +48,13 @@ class TestCodegen: FunSpec({
         val codegen = AsmGen6502(prefixSymbols = false, 0)
         val program = PtProgram("test", DummyMemsizer, DummyStringEncoder)
         val block = PtBlock("main",false, SourceCode.Generated("test"), PtBlock.Options(), Position.DUMMY)
-        val sub = PtSub("start", emptyList(), null, Position.DUMMY)
+        val sub = PtSub("start", emptyList(), emptyList(), Position.DUMMY)
         sub.add(PtVariable(
             "pi",
             DataType.forDt(BaseDataType.UBYTE),
             ZeropageWish.DONTCARE,
             0u,
-            PtNumber(BaseDataType.UBYTE, 0.0, Position.DUMMY),
+            null,
             null,
             Position.DUMMY
         ))
@@ -81,7 +81,7 @@ class TestCodegen: FunSpec({
             DataType.forDt(BaseDataType.WORD),
             ZeropageWish.DONTCARE,
             0u,
-            PtNumber(BaseDataType.WORD, 1.0, Position.DUMMY),
+            null,
             null,
             Position.DUMMY
         ))

codeGenExperimental/build.gradle.kts

@@ -10,7 +10,7 @@ dependencies {
     implementation(project(":codeGenIntermediate"))
     // implementation("org.jetbrains.kotlin:kotlin-stdlib-jdk8")
     // implementation "org.jetbrains.kotlin:kotlin-reflect"
-    implementation("com.michael-bull.kotlin-result:kotlin-result-jvm:2.0.0")
+    implementation("com.michael-bull.kotlin-result:kotlin-result-jvm:2.0.1")
 }
 
 sourceSets {
@@ -24,4 +24,4 @@ sourceSets {
     }
 }
 
-// note: there are no unit tests in this module!
+// note: there are no unit tests in this module!

codeGenExperimental/src/prog8/codegen/experimental/ExperiCodeGen.kt

@@ -21,6 +21,7 @@ class ExperiCodeGen: ICodeGeneratorBackend {
         // but you can also use the Intermediate Representation to build a codegen on:
         val irCodeGen = IRCodeGen(program, symbolTable, options, errors)
         val irProgram = irCodeGen.generate()
+        irProgram.verifyRegisterTypes(irCodeGen.registerTypes())
 
         // this stub only writes the IR program to disk but doesn't generate anything else.
         IRFileWriter(irProgram, null).write()

codeGenIntermediate/build.gradle.kts

@@ -10,7 +10,7 @@ dependencies {
     implementation(project(":intermediate"))
     // implementation("org.jetbrains.kotlin:kotlin-stdlib-jdk8")
     // implementation "org.jetbrains.kotlin:kotlin-reflect"
-    implementation("com.michael-bull.kotlin-result:kotlin-result-jvm:2.0.0")
+    implementation("com.michael-bull.kotlin-result:kotlin-result-jvm:2.0.1")
 
     testImplementation("io.kotest:kotest-runner-junit5-jvm:5.9.1")
     testImplementation("org.junit.jupiter:junit-jupiter:5.9.1")
@@ -45,4 +45,4 @@ tasks.test {
     testLogging {
         events("skipped", "failed")
     }
-}
+}

codeGenIntermediate/src/prog8/codegen/intermediate/AssignmentGen.kt

@@ -2,6 +2,7 @@ package prog8.codegen.intermediate
 
 import prog8.code.StExtSub
 import prog8.code.StExtSubParameter
+import prog8.code.StSub
 import prog8.code.ast.*
 import prog8.code.core.*
 import prog8.intermediate.*
@@ -14,29 +15,47 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
             val values = assignment.value as? PtFunctionCall
                 ?: throw AssemblyError("only function calls can return multiple values in a multi-assign")
 
-            val sub = codeGen.symbolTable.lookup(values.name) as? StExtSub
-                ?: throw AssemblyError("only asmsubs can return multiple values")
-
             val result = mutableListOf<IRCodeChunkBase>()
-            val funcCall = this.expressionEval.translate(values)
-            require(funcCall.multipleResultRegs.size + funcCall.multipleResultFpRegs.size >= 2)
-            if(funcCall.multipleResultFpRegs.isNotEmpty())
-                TODO("deal with (multiple?) FP return registers")
+            val funcCall = expressionEval.translate(values)
             val assignmentTargets = assignment.children.dropLast(1)
             addToResult(result, funcCall, funcCall.resultReg, funcCall.resultFpReg)
-            if(sub.returns.size==assignmentTargets.size) {
-                // Targets and values match. Assign all the things. Skip 'void' targets.
-                sub.returns.zip(assignmentTargets).zip(funcCall.multipleResultRegs).forEach {
-                    val target = it.first.second as PtAssignTarget
-                    if(!target.void) {
-                        val regNumber = it.second
-                        val returns = it.first.first
-                        result += assignCpuRegister(returns, regNumber, target)
+
+            val extsub = codeGen.symbolTable.lookup(values.name) as? StExtSub
+            if(extsub!=null) {
+                require(funcCall.multipleResultRegs.size + funcCall.multipleResultFpRegs.size >= 2)
+                if (funcCall.multipleResultFpRegs.isNotEmpty())
+                    TODO("deal with (multiple?) FP return registers")
+                if (extsub.returns.size == assignmentTargets.size) {
+                    // Targets and values match. Assign all the things. Skip 'void' targets.
+                    extsub.returns.zip(assignmentTargets).zip(funcCall.multipleResultRegs).forEach {
+                        val target = it.first.second as PtAssignTarget
+                        if (!target.void) {
+                            val regNumber = it.second
+                            val returns = it.first.first
+                            result += assignCpuRegister(returns, regNumber, target)
+                        }
                     }
+                } else {
+                    throw AssemblyError("number of values and targets don't match")
                 }
             } else {
-                throw AssemblyError("number of values and targets don't match")
+                val normalsub = codeGen.symbolTable.lookup(values.name) as? StSub
+                if (normalsub != null) {
+                    // multi-value returns are passed throug cx16.R15 down to R0 (allows unencumbered use of many Rx registers if you don't return that many values)
+                    val registersReverseOrder = Cx16VirtualRegisters.reversed()
+                    normalsub.returns.zip(assignmentTargets).zip(registersReverseOrder).forEach {
+                        val target = it.first.second as PtAssignTarget
+                        if(!target.void) {
+                            val assignSingle = PtAssignment(assignment.position, assignment.isVarInitializer)
+                            assignSingle.add(target)
+                            assignSingle.add(PtIdentifier("cx16.${it.second.toString().lowercase()}", it.first.first, assignment.position))
+                            result += translateRegularAssign(assignSingle)
+                        }
+                    }
+                }
+                else throw AssemblyError("expected extsub or normal sub")
             }
+
             return result
         } else {
             if (assignment.target.children.single() is PtIrRegister)
@@ -98,12 +117,6 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
             "<<=" -> operatorShiftLeftInplace(symbol, array, constAddress, memTarget, targetDt, value)
             ">>=" -> operatorShiftRightInplace(symbol, array, constAddress, memTarget, targetDt, value, signed)
             "%=" -> operatorModuloInplace(symbol, array, constAddress, memTarget, targetDt, value)
-            "==" -> operatorEqualsInplace(symbol, array, constAddress, memTarget, targetDt, value)
-            "!=" -> operatorNotEqualsInplace(symbol, array, constAddress, memTarget, targetDt, value)
-            "<" -> operatorLessInplace(symbol, array, constAddress, memTarget, targetDt, value, signed)
-            ">" -> operatorGreaterInplace(symbol, array, constAddress, memTarget, targetDt, value, signed)
-            "<=" -> operatorLessEqualInplace(symbol, array, constAddress, memTarget, targetDt, value, signed)
-            ">=" -> operatorGreaterEqualInplace(symbol, array, constAddress, memTarget, targetDt, value, signed)
             in PrefixOperators -> inplacePrefix(augAssign.operator, symbol, array, constAddress, memTarget, targetDt)
 
             else -> throw AssemblyError("invalid augmented assign operator ${augAssign.operator}")
@@ -125,7 +138,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                     origAssign.operator.dropLast(1)
                 }
             }
-            value = PtBinaryExpression(operator, origAssign.value.type, origAssign.value.position)
+            value = PtBinaryExpression(operator, origAssign.target.type, origAssign.value.position)
             val left: PtExpression = origAssign.target.children.single() as PtExpression
             value.add(left)
             value.add(origAssign.value)
@@ -145,7 +158,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
 
         val result = mutableListOf<IRCodeChunkBase>()
         if(constAddress==null && memory!=null) {
-            val register = codeGen.registers.nextFree()
+            val register = codeGen.registers.next(vmDt)
             val tr = expressionEval.translateExpression(memory.address)
             addToResult(result, tr, tr.resultReg, -1)
             when(operator) {
@@ -169,7 +182,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 "-" -> addInstr(result, IRInstruction(Opcode.NEGM, vmDt, address = constAddress, labelSymbol = symbol), null)
                 "~" -> addInstr(result, IRInstruction(Opcode.INVM, vmDt, address = constAddress, labelSymbol = symbol), null)
                 "not" -> {
-                    val regMask = codeGen.registers.nextFree()
+                    val regMask = codeGen.registers.next(vmDt)
                     result += IRCodeChunk(null, null).also {
                         it += IRInstruction(Opcode.LOAD, vmDt, reg1=regMask, immediate = 1)
                         it += IRInstruction(Opcode.XORM, vmDt, reg1=regMask, address = constAddress, labelSymbol = symbol)
@@ -208,8 +221,8 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                         addInstr(result, IRInstruction(Opcode.NEGM, IRDataType.BYTE, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex), skipCarryLabel)
                     } else {
                         val indexReg = loadIndex()
-                        val registerLsb = codeGen.registers.nextFree()
-                        val registerMsb = codeGen.registers.nextFree()
+                        val registerLsb = codeGen.registers.next(IRDataType.BYTE)
+                        val registerMsb = codeGen.registers.next(IRDataType.BYTE)
                         result += IRCodeChunk(null, null).also {
                             it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1 = registerLsb, reg2 = indexReg, labelSymbol = array.variable.name+"_lsb")
                             it += IRInstruction(Opcode.NEG, IRDataType.BYTE, reg1 = registerLsb)
@@ -231,7 +244,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                         addInstr(result, IRInstruction(Opcode.INVM, IRDataType.BYTE, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex), null)
                     } else {
                         val indexReg = loadIndex()
-                        val register = codeGen.registers.nextFree()
+                        val register = codeGen.registers.next(IRDataType.BYTE)
                         result += IRCodeChunk(null, null).also {
                             it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1 = register, reg2 = indexReg, labelSymbol = array.variable.name+"_lsb")
                             it += IRInstruction(Opcode.INV, IRDataType.BYTE, reg1 = register)
@@ -256,7 +269,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                     addInstr(result, IRInstruction(Opcode.NEGM, vmDt, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize), null)
                 } else {
                     val indexReg = loadIndex()
-                    val register = codeGen.registers.nextFree()
+                    val register = codeGen.registers.next(vmDt)
                     result += IRCodeChunk(null, null).also {
                         it += IRInstruction(Opcode.LOADX, vmDt, reg1 = register, reg2 = indexReg, labelSymbol = array.variable.name)
                         it += IRInstruction(Opcode.NEG, vmDt, reg1 = register)
@@ -269,7 +282,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                     addInstr(result, IRInstruction(Opcode.INVM, vmDt, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize), null)
                 } else {
                     val indexReg = loadIndex()
-                    val register = codeGen.registers.nextFree()
+                    val register = codeGen.registers.next(vmDt)
                     result += IRCodeChunk(null, null).also {
                         it += IRInstruction(Opcode.LOADX, vmDt, reg1 = register, reg2 = indexReg, labelSymbol = array.variable.name)
                         it += IRInstruction(Opcode.INV, vmDt, reg1 = register)
@@ -278,7 +291,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 }
             }
             "not" -> {
-                val register = codeGen.registers.nextFree()
+                val register = codeGen.registers.next(vmDt)
                 if(constIndex!=null) {
                     result += IRCodeChunk(null, null).also {
                         it += IRInstruction(Opcode.LOAD, vmDt, reg1=register, immediate = 1)
@@ -327,7 +340,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 if (assignment.value is PtIrRegister) {
                     valueRegister = (assignment.value as PtIrRegister).register
                     if(extendByteToWord) {
-                        valueRegister = codeGen.registers.nextFree()
+                        valueRegister = codeGen.registers.next(IRDataType.WORD)
                         addInstr(result, IRInstruction(Opcode.EXT, IRDataType.BYTE, reg1=valueRegister, reg2=(assignment.value as PtIrRegister).register), null)
                     }
                 } else {
@@ -335,7 +348,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                     valueRegister = tr.resultReg
                     addToResult(result, tr, valueRegister, -1)
                     if(extendByteToWord) {
-                        valueRegister = codeGen.registers.nextFree()
+                        valueRegister = codeGen.registers.next(IRDataType.WORD)
                         val opcode = if(assignment.value.type.isSigned) Opcode.EXTS else Opcode.EXT
                         addInstr(result, IRInstruction(opcode, IRDataType.BYTE, reg1=valueRegister, reg2=tr.resultReg), null)
                     }
@@ -403,10 +416,11 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                     if(fixedIndex!=null) {
                         val chunk = IRCodeChunk(null, null).also {
                             if(targetArray.splitWords) {
-                                val msbReg = codeGen.registers.nextFree()
-                                it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = valueRegister, immediate = arrayLength, labelSymbol = "${variable}_lsb", symbolOffset = fixedIndex)
-                                it += IRInstruction(Opcode.MSIG, IRDataType.BYTE, reg1 = msbReg, reg2 = valueRegister)
-                                it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = msbReg, immediate = arrayLength, labelSymbol = "${variable}_msb", symbolOffset = fixedIndex)
+                                val lsbmsbReg = codeGen.registers.next(IRDataType.BYTE)
+                                it += IRInstruction(Opcode.LSIG, IRDataType.BYTE, reg1 = lsbmsbReg, reg2 = valueRegister)
+                                it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = lsbmsbReg, immediate = arrayLength, labelSymbol = "${variable}_lsb", symbolOffset = fixedIndex)
+                                it += IRInstruction(Opcode.MSIG, IRDataType.BYTE, reg1 = lsbmsbReg, reg2 = valueRegister)
+                                it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = lsbmsbReg, immediate = arrayLength, labelSymbol = "${variable}_msb", symbolOffset = fixedIndex)
                             }
                             else
                                 it += IRInstruction(Opcode.STOREM, targetDt, reg1 = valueRegister, labelSymbol = variable, symbolOffset = fixedIndex*itemsize)
@@ -417,10 +431,11 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                         result += code
                         result += IRCodeChunk(null, null).also {
                             if(targetArray.splitWords) {
-                                val msbReg = codeGen.registers.nextFree()
-                                it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1 = valueRegister, reg2=indexReg, immediate = arrayLength, labelSymbol = "${variable}_lsb")
-                                it += IRInstruction(Opcode.MSIG, IRDataType.BYTE, reg1 = msbReg, reg2 = valueRegister)
-                                it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1 = msbReg, reg2=indexReg, immediate = arrayLength, labelSymbol = "${variable}_msb")
+                                val lsbmsbReg = codeGen.registers.next(IRDataType.BYTE)
+                                it += IRInstruction(Opcode.LSIG, IRDataType.BYTE, reg1 = lsbmsbReg, reg2 = valueRegister)
+                                it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1 = lsbmsbReg, reg2=indexReg, immediate = arrayLength, labelSymbol = "${variable}_lsb")
+                                it += IRInstruction(Opcode.MSIG, IRDataType.BYTE, reg1 = lsbmsbReg, reg2 = valueRegister)
+                                it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1 = lsbmsbReg, reg2=indexReg, immediate = arrayLength, labelSymbol = "${variable}_msb")
                             }
                             else
                                 it += IRInstruction(Opcode.STOREX, targetDt, reg1 = valueRegister, reg2=indexReg, labelSymbol = variable)
@@ -455,7 +470,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                     if((ptrWithOffset.right as? PtNumber)?.number?.toInt() in 0..255) {
                         // STOREIX only works with byte index.
                         val ptrName = (ptrWithOffset.left as PtIdentifier).name
-                        val offsetReg = codeGen.registers.nextFree()
+                        val offsetReg = codeGen.registers.next(IRDataType.BYTE)
                         result += IRCodeChunk(null, null).also {
                             it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=offsetReg, immediate = ptrWithOffset.right.asConstInteger())
                             it += IRInstruction(Opcode.STOREIX, IRDataType.BYTE, reg1=valueRegister, reg2=offsetReg, labelSymbol = ptrName)
@@ -514,16 +529,16 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
             val eltSize = codeGen.program.memsizer.memorySize(array.type, null)
             if(constIndex!=null && constValue!=null) {
                 if(array.splitWords) {
-                    val valueRegLsb = codeGen.registers.nextFree()
-                    val valueRegMsb = codeGen.registers.nextFree()
+                    val valueRegLsb = codeGen.registers.next(IRDataType.BYTE)
+                    val valueRegMsb = codeGen.registers.next(IRDataType.BYTE)
                     result += IRCodeChunk(null, null).also {
-                        it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueRegLsb, immediate=constValue and 255)
-                        it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueRegMsb, immediate=constValue shr 8)
-                        it += IRInstruction(Opcode.ANDM, vmDt, reg1=valueRegLsb, labelSymbol = array.variable.name+"_lsb", symbolOffset = constIndex)
-                        it += IRInstruction(Opcode.ANDM, vmDt, reg1=valueRegMsb, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex)
+                        it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=valueRegLsb, immediate=constValue and 255)
+                        it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=valueRegMsb, immediate=constValue shr 8)
+                        it += IRInstruction(Opcode.ANDM, IRDataType.BYTE, reg1=valueRegLsb, labelSymbol = array.variable.name+"_lsb", symbolOffset = constIndex)
+                        it += IRInstruction(Opcode.ANDM, IRDataType.BYTE, reg1=valueRegMsb, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex)
                     }
                 } else {
-                    val valueReg = codeGen.registers.nextFree()
+                    val valueReg = codeGen.registers.next(vmDt)
                     result += IRCodeChunk(null, null).also {
                         it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueReg, immediate=constValue)
                         it += IRInstruction(Opcode.ANDM, vmDt, reg1=valueReg, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
@@ -531,7 +546,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 }
                 return result
             }
-            return null // TODO("inplace word array &")
+            return null // TODO("optimized inplace word array &")
         }
         if(constAddress==null && memory!=null)
             return null // TODO("optimized memory in-place &")
@@ -554,16 +569,9 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
             val eltSize = codeGen.program.memsizer.memorySize(array.type, null)
             if(constIndex!=null && constValue!=null) {
                 if(array.splitWords) {
-                    val valueRegLsb = codeGen.registers.nextFree()
-                    val valueRegMsb = codeGen.registers.nextFree()
-                    result += IRCodeChunk(null, null).also {
-                        it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueRegLsb, immediate=constValue and 255)
-                        it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueRegMsb, immediate=constValue shr 8)
-                        it += IRInstruction(Opcode.ANDM, vmDt, reg1=valueRegLsb, labelSymbol = array.variable.name+"_lsb", symbolOffset = constIndex)
-                        it += IRInstruction(Opcode.ANDM, vmDt, reg1=valueRegMsb, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex)
-                    }
+                    throw AssemblyError("logical and on (split) word array should not happen")
                 } else {
-                    val valueReg = codeGen.registers.nextFree()
+                    val valueReg = codeGen.registers.next(vmDt)
                     result += IRCodeChunk(null, null).also {
                         it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueReg, immediate=constValue)
                         it += IRInstruction(Opcode.ANDM, vmDt, reg1=valueReg, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
@@ -571,7 +579,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 }
                 return result
             }
-            return null // TODO("inplace word array and")
+            return null // TODO("optimized inplace word array and")
         }
         if(constAddress==null && memory!=null)
             return null // TODO("optimized memory in-place and")
@@ -580,7 +588,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
         val tr = expressionEval.translateExpression(operand)
         if(!operand.isSimple()) {
             // short-circuit  LEFT and RIGHT  -->  if LEFT then RIGHT else LEFT   (== if !LEFT then LEFT else RIGHT)
-            val inplaceReg = codeGen.registers.nextFree()
+            val inplaceReg = codeGen.registers.next(vmDt)
             val shortcutLabel = codeGen.createLabelName()
             result += IRCodeChunk(null, null).also {
                 it += if(constAddress!=null)
@@ -614,16 +622,16 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
             val eltSize = codeGen.program.memsizer.memorySize(array.type, null)
             if(constIndex!=null && constValue!=null) {
                 if(array.splitWords) {
-                    val valueRegLsb = codeGen.registers.nextFree()
-                    val valueRegMsb = codeGen.registers.nextFree()
+                    val valueRegLsb = codeGen.registers.next(IRDataType.BYTE)
+                    val valueRegMsb = codeGen.registers.next(IRDataType.BYTE)
                     result += IRCodeChunk(null, null).also {
-                        it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueRegLsb, immediate=constValue and 255)
-                        it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueRegMsb, immediate=constValue shr 8)
-                        it += IRInstruction(Opcode.ORM, vmDt, reg1=valueRegLsb, labelSymbol = array.variable.name+"_lsb", symbolOffset = constIndex)
-                        it += IRInstruction(Opcode.ORM, vmDt, reg1=valueRegMsb, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex)
+                        it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=valueRegLsb, immediate=constValue and 255)
+                        it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=valueRegMsb, immediate=constValue shr 8)
+                        it += IRInstruction(Opcode.ORM, IRDataType.BYTE, reg1=valueRegLsb, labelSymbol = array.variable.name+"_lsb", symbolOffset = constIndex)
+                        it += IRInstruction(Opcode.ORM, IRDataType.BYTE, reg1=valueRegMsb, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex)
                     }
                 } else {
-                    val valueReg = codeGen.registers.nextFree()
+                    val valueReg = codeGen.registers.next(vmDt)
                     result += IRCodeChunk(null, null).also {
                         it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueReg, immediate=constValue)
                         it += IRInstruction(Opcode.ORM, vmDt, reg1=valueReg, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
@@ -631,7 +639,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 }
                 return result
             }
-            return null // TODO("inplace word array |")
+            return null // TODO("optimized inplace word array |")
         }
         if(constAddress==null && memory!=null)
             return null // TODO("optimized memory in-place |")
@@ -654,16 +662,9 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
             val eltSize = codeGen.program.memsizer.memorySize(array.type, null)
             if(constIndex!=null && constValue!=null) {
                 if(array.splitWords) {
-                    val valueRegLsb = codeGen.registers.nextFree()
-                    val valueRegMsb = codeGen.registers.nextFree()
-                    result += IRCodeChunk(null, null).also {
-                        it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueRegLsb, immediate=constValue and 255)
-                        it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueRegMsb, immediate=constValue shr 8)
-                        it += IRInstruction(Opcode.ORM, vmDt, reg1=valueRegLsb, labelSymbol = array.variable.name+"_lsb", symbolOffset = constIndex)
-                        it += IRInstruction(Opcode.ORM, vmDt, reg1=valueRegMsb, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex)
-                    }
+                    throw AssemblyError("logical or on (split) word array should not happen")
                 } else {
-                    val valueReg = codeGen.registers.nextFree()
+                    val valueReg = codeGen.registers.next(vmDt)
                     result += IRCodeChunk(null, null).also {
                         it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueReg, immediate=constValue)
                         it += IRInstruction(Opcode.ORM, vmDt, reg1=valueReg, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
@@ -671,7 +672,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 }
                 return result
             }
-            return null  // TODO("inplace word array or")
+            return null  // TODO("optimized inplace word array or")
         }
         if(constAddress==null && memory!=null)
             return null  // TODO("optimized memory in-place or"")
@@ -680,7 +681,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
         val tr = expressionEval.translateExpression(operand)
         if(!operand.isSimple()) {
             // short-circuit  LEFT or RIGHT  -->  if LEFT then LEFT else RIGHT
-            val inplaceReg = codeGen.registers.nextFree()
+            val inplaceReg = codeGen.registers.next(vmDt)
             val shortcutLabel = codeGen.createLabelName()
             result += IRCodeChunk(null, null).also {
                 it += if(constAddress!=null)
@@ -772,7 +773,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
             val constValue = operand.asConstInteger()
             if(constIndex!=null && constValue!=null) {
                 if(constValue!=1) {
-                    val valueReg=codeGen.registers.nextFree()
+                    val valueReg=codeGen.registers.next(eltDt)
                     result += IRCodeChunk(null, null).also {
                         it += IRInstruction(Opcode.LOAD, eltDt, reg1=valueReg, immediate = constValue)
                         it += IRInstruction(Opcode.MULM, eltDt, reg1=valueReg, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
@@ -780,7 +781,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 }
                 return result
             }
-            return null  // TODO("inplace array * non-const")
+            return null  // TODO("optimized inplace array * non-const")
         }
         if(constAddress==null && memory!=null)
             return null  // TODO("optimized memory in-place *"")
@@ -830,7 +831,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 if(constValue==1) {
                     addInstr(result, IRInstruction(Opcode.DECM, eltDt, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize), null)
                 } else {
-                    val valueReg=codeGen.registers.nextFree()
+                    val valueReg=codeGen.registers.next(eltDt)
                     result += IRCodeChunk(null, null).also {
                         it += IRInstruction(Opcode.LOAD, eltDt, reg1=valueReg, immediate = constValue)
                         it += IRInstruction(Opcode.SUBM, eltDt, reg1=valueReg, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
@@ -838,7 +839,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 }
                 return result
             }
-            return null  // TODO("inplace array -")
+            return null  // TODO("optimized inplace array -")
         }
         if(constAddress==null && memory!=null)
             return null  // TODO("optimized memory in-place -"")
@@ -883,7 +884,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
     }
 
     private fun operatorMultiplyInplaceSplitArray(array: PtArrayIndexer, operand: PtExpression): IRCodeChunks? {
-        return null  // TODO("inplace split word array *")
+        return null  // fallback to slow method   // TODO("inplace split word array *")
     }
 
     private fun operatorMinusInplaceSplitArray(array: PtArrayIndexer, operand: PtExpression): IRCodeChunks? {
@@ -893,7 +894,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
         if(constIndex!=null) {
             val skip = codeGen.createLabelName()
             if(constValue==1) {
-                val lsbReg = codeGen.registers.nextFree()
+                val lsbReg = codeGen.registers.next(IRDataType.BYTE)
                 result += IRCodeChunk(null, null).also {
                     it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = lsbReg, labelSymbol = array.variable.name+"_lsb", symbolOffset = constIndex)
                     it += IRInstruction(Opcode.BSTNE, labelSymbol = skip)
@@ -904,10 +905,10 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 }
                 return result
             } else {
-                return null  // TODO("inplace split word array -")
+                return null  // fallback to slow method   // TODO("inplace split word array -")
             }
         }
-        return null  // TODO("inplace split word array -")
+        return null  // fallback to slow method   // TODO("inplace split word array -")
     }
 
     private fun operatorPlusInplace(symbol: String?, array: PtArrayIndexer?, constAddress: Int?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks? {
@@ -923,7 +924,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 if(constValue==1) {
                     addInstr(result, IRInstruction(Opcode.INCM, elementDt, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize), null)
                 } else {
-                    val valueReg=codeGen.registers.nextFree()
+                    val valueReg=codeGen.registers.next(elementDt)
                     result += IRCodeChunk(null, null).also {
                         it += IRInstruction(Opcode.LOAD, elementDt, reg1=valueReg, immediate = constValue)
                         it += IRInstruction(Opcode.ADDM, elementDt, reg1=valueReg, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
@@ -931,7 +932,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 }
                 return result
             }
-            return null  // TODO("inplace array +")
+            return null  // TODO("optimized inplace array +")
         }
         if(constAddress==null && memory!=null)
             return null  // TODO("optimized memory in-place +"")
@@ -990,18 +991,46 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 result += IRCodeChunk(skip, null)
                 return result
             } else {
-                return null  // TODO("inplace split word array +")
+                return null  // fallback to slow method   // TODO("inplace split word array +")
             }
         }
-        return null  // TODO("inplace split word array +")
+        return null  // fallback to slow method   // TODO("inplace split word array +")
     }
 
     private fun operatorShiftRightInplace(symbol: String?, array: PtArrayIndexer?, constAddress: Int?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression, signed: Boolean): IRCodeChunks? {
         if(array!=null) {
-            TODO(">> in array")
+            val result = mutableListOf<IRCodeChunkBase>()
+            val constIndex = array.index.asConstInteger()
+            val constValue = operand.asConstInteger()
+
+            if(constIndex!=null && constValue!=null) {
+                if(array.splitWords) {
+                    repeat(constValue) {
+                        result += IRCodeChunk(null, null).also {
+                            it += IRInstruction(Opcode.LSRM, IRDataType.BYTE, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex)
+                            it += IRInstruction(Opcode.ROXRM, IRDataType.BYTE, labelSymbol = array.variable.name+"_lsb", symbolOffset = constIndex)
+                        }
+                    }
+                } else {
+                    val eltSize = codeGen.program.memsizer.memorySize(array.type, null)
+                    if(constValue==1) {
+                        result += IRCodeChunk(null, null).also {
+                            it += IRInstruction(Opcode.LSRM, vmDt, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
+                        }
+                    } else {
+                        val valueReg = codeGen.registers.next(IRDataType.BYTE)
+                        result += IRCodeChunk(null, null).also {
+                            it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=valueReg, immediate=constValue and 255)
+                            it += IRInstruction(Opcode.LSRNM, vmDt, reg1=valueReg, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
+                        }
+                    }
+                }
+                return result
+            }
+            return null   // TODO("optimized >> in array")
         }
         if(constAddress==null && memory!=null)
-            return null  // TODO("optimized memory in-place >>"")
+            return null  //  TODO("optimized memory in-place >>"")
 
         val result = mutableListOf<IRCodeChunkBase>()
         if(codeGen.isOne(operand)) {
@@ -1026,7 +1055,35 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
 
     private fun operatorShiftLeftInplace(symbol: String?, array: PtArrayIndexer?, constAddress: Int?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks? {
         if(array!=null) {
-            TODO("<< in array")
+            val result = mutableListOf<IRCodeChunkBase>()
+            val constIndex = array.index.asConstInteger()
+            val constValue = operand.asConstInteger()
+
+            if(constIndex!=null && constValue!=null) {
+                if(array.splitWords) {
+                    repeat(constValue) {
+                        result += IRCodeChunk(null, null).also {
+                            it += IRInstruction(Opcode.LSLM, IRDataType.BYTE, labelSymbol = array.variable.name+"_lsb", symbolOffset = constIndex)
+                            it += IRInstruction(Opcode.ROXLM, IRDataType.BYTE, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex)
+                        }
+                    }
+                } else {
+                    val eltSize = codeGen.program.memsizer.memorySize(array.type, null)
+                    if(constValue==1) {
+                        result += IRCodeChunk(null, null).also {
+                            it += IRInstruction(Opcode.LSLM, vmDt, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
+                        }
+                    } else {
+                        val valueReg = codeGen.registers.next(IRDataType.BYTE)
+                        result += IRCodeChunk(null, null).also {
+                            it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=valueReg, immediate=constValue and 255)
+                            it += IRInstruction(Opcode.LSLNM, vmDt, reg1=valueReg, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
+                        }
+                    }
+                }
+                return result
+            }
+            return null   // TODO("optimized << in array")
         }
         if(constAddress==null && memory!=null)
             return null  // TODO("optimized memory in-place <<"")
@@ -1058,16 +1115,16 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
             val eltSize = codeGen.program.memsizer.memorySize(array.type, null)
             if(constIndex!=null && constValue!=null) {
                 if(array.splitWords) {
-                    val valueRegLsb = codeGen.registers.nextFree()
-                    val valueRegMsb = codeGen.registers.nextFree()
+                    val valueRegLsb = codeGen.registers.next(IRDataType.BYTE)
+                    val valueRegMsb = codeGen.registers.next(IRDataType.BYTE)
                     result += IRCodeChunk(null, null).also {
-                        it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueRegLsb, immediate=constValue and 255)
-                        it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueRegMsb, immediate=constValue shr 8)
-                        it += IRInstruction(Opcode.XORM, vmDt, reg1=valueRegLsb, labelSymbol = array.variable.name+"_lsb", symbolOffset = constIndex)
-                        it += IRInstruction(Opcode.XORM, vmDt, reg1=valueRegMsb, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex)
+                        it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=valueRegLsb, immediate=constValue and 255)
+                        it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=valueRegMsb, immediate=constValue shr 8)
+                        it += IRInstruction(Opcode.XORM, IRDataType.BYTE, reg1=valueRegLsb, labelSymbol = array.variable.name+"_lsb", symbolOffset = constIndex)
+                        it += IRInstruction(Opcode.XORM, IRDataType.BYTE, reg1=valueRegMsb, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex)
                     }
                 } else {
-                    val valueReg = codeGen.registers.nextFree()
+                    val valueReg = codeGen.registers.next(vmDt)
                     result += IRCodeChunk(null, null).also {
                         it += IRInstruction(Opcode.LOAD, vmDt, reg1=valueReg, immediate=constValue)
                         it += IRInstruction(Opcode.XORM, vmDt, reg1=valueReg, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
@@ -1075,7 +1132,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
                 }
                 return result
             }
-            return null  // TODO("inplace word array xor")
+            return null  // TODO("optimized inplace word array xor")
         }
         if(constAddress==null && memory!=null)
             return null  // TODO("optimized memory in-place xor"")
@@ -1099,7 +1156,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
             return null  // TODO("optimized memory in-place %"")
 
         val result = mutableListOf<IRCodeChunkBase>()
-        val resultReg = codeGen.registers.nextFree()
+        val resultReg = codeGen.registers.next(vmDt)
         if(operand is PtNumber) {
             val number = operand.number.toInt()
             if (constAddress != null) {
@@ -1138,293 +1195,4 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
         }
         return result
     }
-
-    private fun operatorEqualsInplace(symbol: String?, array: PtArrayIndexer?, constAddress: Int?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks? {
-        if(array!=null)
-            return createInplaceArrayComparison(array, operand, "==")
-        if(constAddress==null && memory!=null)
-            return null  // TODO("optimized memory in-place compare"")
-
-        val chunks = if(vmDt==IRDataType.FLOAT) {
-            createInplaceFloatComparison(constAddress, symbol, operand, Opcode.SEQ)
-        } else {
-            createInplaceComparison(constAddress, symbol, vmDt, operand, Opcode.SEQ)
-        }
-        return chunks
-    }
-
-    private fun operatorNotEqualsInplace(symbol: String?, array: PtArrayIndexer?, constAddress: Int?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks? {
-        if(array!=null)
-            return createInplaceArrayComparison(array, operand, "!=")
-        if(constAddress==null && memory!=null)
-            return null  // TODO("optimized memory in-place compare"")
-
-        val chunks = if(vmDt==IRDataType.FLOAT) {
-            createInplaceFloatComparison(constAddress, symbol, operand, Opcode.SNE)
-        } else {
-            createInplaceComparison(constAddress, symbol, vmDt, operand, Opcode.SNE)
-        }
-        return chunks
-    }
-
-    private fun operatorGreaterInplace(symbol: String?, array: PtArrayIndexer?, constAddress: Int?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression, signed: Boolean): IRCodeChunks? {
-        if(array!=null)
-            return createInplaceArrayComparison(array, operand, ">")
-        if(constAddress==null && memory!=null)
-            return null  // TODO("optimized memory in-place compare"")
-
-        val opcode = if(signed) Opcode.SGTS else Opcode.SGT
-        val chunks = if(vmDt==IRDataType.FLOAT) {
-            createInplaceFloatComparison(constAddress, symbol, operand, opcode)
-        } else {
-            createInplaceComparison(constAddress, symbol, vmDt, operand, opcode)
-        }
-        return chunks
-    }
-
-    private fun operatorLessInplace(symbol: String?, array: PtArrayIndexer?, constAddress: Int?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression, signed: Boolean): IRCodeChunks? {
-        if(array!=null)
-            return createInplaceArrayComparison(array, operand, "<")
-        if(constAddress==null && memory!=null)
-            return null  // TODO("optimized memory in-place compare"")
-
-        val opcode = if(signed) Opcode.SLTS else Opcode.SLT
-        val chunks = if(vmDt==IRDataType.FLOAT) {
-            createInplaceFloatComparison(constAddress, symbol, operand, opcode)
-        } else {
-            createInplaceComparison(constAddress, symbol, vmDt, operand, opcode)
-        }
-        return chunks
-    }
-
-    private fun operatorGreaterEqualInplace(symbol: String?, array: PtArrayIndexer?, constAddress: Int?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression, signed: Boolean): IRCodeChunks? {
-        if(array!=null)
-            return createInplaceArrayComparison(array, operand, ">=")
-        if(constAddress==null && memory!=null)
-            return null  // TODO("optimized memory in-place compare"")
-
-        val opcode = if(signed) Opcode.SGES else Opcode.SGE
-        val chunks = if(vmDt==IRDataType.FLOAT) {
-            createInplaceFloatComparison(constAddress, symbol, operand, opcode)
-        } else {
-            createInplaceComparison(constAddress, symbol, vmDt, operand, opcode)
-        }
-        return chunks
-    }
-
-    private fun operatorLessEqualInplace(symbol: String?, array: PtArrayIndexer?, constAddress: Int?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression, signed: Boolean): IRCodeChunks? {
-        if(array!=null)
-            return createInplaceArrayComparison(array, operand, "<=")
-        if(constAddress==null && memory!=null)
-            return null  // TODO("optimized memory in-place compare"")
-
-        val opcode = if(signed) Opcode.SLES else Opcode.SLE
-        val chunks = if(vmDt==IRDataType.FLOAT) {
-            createInplaceFloatComparison(constAddress, symbol, operand, opcode)
-        } else {
-            createInplaceComparison(constAddress, symbol, vmDt, operand, opcode)
-        }
-        return chunks
-    }
-
-    private fun createInplaceComparison(
-        constAddress: Int?,
-        symbol: String?,
-        vmDt: IRDataType,
-        operand: PtExpression,
-        compareAndSetOpcode: Opcode
-    ): MutableList<IRCodeChunkBase> {
-        val result = mutableListOf<IRCodeChunkBase>()
-        val valueReg = codeGen.registers.nextFree()
-        val cmpResultReg = codeGen.registers.nextFree()
-        if(operand is PtNumber || operand is PtBool) {
-
-            if(operand is PtNumber && operand.number==0.0 && compareAndSetOpcode in arrayOf(Opcode.SEQ, Opcode.SNE)) {
-                // ==0 or !=0 optimized case
-                val compareAndSetOpcodeZero = if(compareAndSetOpcode==Opcode.SEQ) Opcode.SZ else Opcode.SNZ
-                if (constAddress != null) {
-                    // in-place modify a memory location
-                    result += IRCodeChunk(null, null).also {
-                        it += IRInstruction(Opcode.LOADM, vmDt, reg1 = valueReg, address = constAddress)
-                        it += IRInstruction(compareAndSetOpcodeZero, vmDt, reg1 = cmpResultReg, reg2 = valueReg)
-                        it += IRInstruction(Opcode.STOREM, vmDt, reg1 = cmpResultReg, address = constAddress)
-                    }
-                } else {
-                    // in-place modify a symbol (variable)
-                    result += IRCodeChunk(null, null).also {
-                        it += IRInstruction(Opcode.LOADM, vmDt, reg1 = valueReg, labelSymbol = symbol)
-                        it += IRInstruction(compareAndSetOpcodeZero, vmDt, reg1=cmpResultReg, reg2 = valueReg)
-                        it += IRInstruction(Opcode.STOREM, vmDt, reg1 = cmpResultReg, labelSymbol = symbol)
-                    }
-                }
-                return result
-            }
-
-            // compare against number that is not 0
-            val numberReg = codeGen.registers.nextFree()
-            val value = if(operand is PtNumber) operand.number.toInt() else if(operand is PtBool) operand.asInt() else throw AssemblyError("wrong operand type")
-            if (constAddress != null) {
-                // in-place modify a memory location
-                val innervalue = if(operand is PtNumber) operand.number.toInt() else if(operand is PtBool) operand.asInt() else throw AssemblyError("wrong operand type")
-                result += IRCodeChunk(null, null).also {
-                    it += IRInstruction(Opcode.LOADM, vmDt, reg1 = valueReg, address = constAddress)
-                    it += IRInstruction(Opcode.LOAD, vmDt, reg1=numberReg, immediate = innervalue)
-                    it += IRInstruction(compareAndSetOpcode, vmDt, reg1 = cmpResultReg, reg2 = valueReg, reg3 = numberReg)
-                    it += IRInstruction(Opcode.STOREM, vmDt, reg1 = cmpResultReg, address = constAddress)
-                }
-            } else {
-                // in-place modify a symbol (variable)
-                result += IRCodeChunk(null, null).also {
-                    it += IRInstruction(Opcode.LOADM, vmDt, reg1 = valueReg, labelSymbol = symbol)
-                    it += IRInstruction(Opcode.LOAD, vmDt, reg1=numberReg, immediate = value)
-                    it += IRInstruction(compareAndSetOpcode, vmDt, reg1=cmpResultReg, reg2 = valueReg, reg3 = numberReg)
-                    it += IRInstruction(Opcode.STOREM, vmDt, reg1 = cmpResultReg, labelSymbol = symbol)
-                }
-            }
-        } else {
-            val tr = expressionEval.translateExpression(operand)
-            addToResult(result, tr, tr.resultReg, -1)
-            if (constAddress != null) {
-                // in-place modify a memory location
-                result += IRCodeChunk(null, null).also {
-                    it += IRInstruction(Opcode.LOADM, vmDt, reg1 = valueReg, address = constAddress)
-                    it += IRInstruction(compareAndSetOpcode, vmDt, reg1=cmpResultReg, reg2 = valueReg, reg3 = tr.resultReg)
-                    it += IRInstruction(Opcode.STOREM, vmDt, reg1 = cmpResultReg, address = constAddress)
-                }
-            } else {
-                // in-place modify a symbol (variable)
-                result += IRCodeChunk(null, null).also {
-                    it += IRInstruction(Opcode.LOADM, vmDt, reg1 = valueReg, labelSymbol = symbol)
-                    it += IRInstruction(compareAndSetOpcode, vmDt, reg1=cmpResultReg, reg2 = valueReg, reg3 = tr.resultReg)
-                    it += IRInstruction(Opcode.STOREM, vmDt, reg1 = cmpResultReg, labelSymbol = symbol)
-                }
-            }
-        }
-        return result
-    }
-
-    private fun createInplaceFloatComparison(
-        constAddress: Int?,
-        symbol: String?,
-        operand: PtExpression,
-        compareAndSetOpcode: Opcode
-    ): MutableList<IRCodeChunkBase> {
-        val result = mutableListOf<IRCodeChunkBase>()
-        val valueReg = codeGen.registers.nextFreeFloat()
-        val cmpReg = codeGen.registers.nextFree()
-        val zeroReg = codeGen.registers.nextFree()
-        if(operand is PtNumber) {
-            val numberReg = codeGen.registers.nextFreeFloat()
-            val cmpResultReg = codeGen.registers.nextFree()
-            if (constAddress != null) {
-                // in-place modify a memory location
-                result += IRCodeChunk(null, null).also {
-                    it += IRInstruction(Opcode.LOADM, IRDataType.FLOAT, fpReg1 = valueReg, address = constAddress)
-                    it += IRInstruction(Opcode.LOAD, IRDataType.FLOAT, fpReg1 = numberReg, immediateFp = operand.number)
-                    it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=cmpReg, fpReg1 = valueReg, fpReg2 = numberReg)
-                    it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=zeroReg, immediate = 0)
-                    it += IRInstruction(compareAndSetOpcode, IRDataType.BYTE, reg1=cmpResultReg, reg2=cmpReg, reg3=zeroReg)
-                    it += IRInstruction(Opcode.FFROMUB, IRDataType.FLOAT, reg1=cmpResultReg, fpReg1 = valueReg)
-                    it += IRInstruction(Opcode.STOREM, IRDataType.FLOAT, fpReg1 = valueReg, address = constAddress)
-                }
-            } else {
-                // in-place modify a symbol (variable)
-                result += IRCodeChunk(null, null).also {
-                    it += IRInstruction(Opcode.LOADM, IRDataType.FLOAT, fpReg1 = valueReg, labelSymbol = symbol)
-                    it += IRInstruction(Opcode.LOAD, IRDataType.FLOAT, fpReg1 = numberReg, immediateFp = operand.number)
-                    it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=cmpReg, fpReg1 = valueReg, fpReg2 = numberReg)
-                    it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=zeroReg, immediate = 0)
-                    it += IRInstruction(compareAndSetOpcode, IRDataType.BYTE, reg1=cmpResultReg, reg2=cmpReg, reg3=zeroReg)
-                    it += IRInstruction(Opcode.FFROMUB, IRDataType.FLOAT, reg1=cmpResultReg, fpReg1 = valueReg)
-                    it += IRInstruction(Opcode.STOREM, IRDataType.FLOAT, fpReg1 = valueReg, labelSymbol = symbol)
-                }
-            }
-        } else {
-            val tr = expressionEval.translateExpression(operand)
-            val cmpResultReg = codeGen.registers.nextFree()
-            addToResult(result, tr, -1, tr.resultFpReg)
-            if (constAddress != null) {
-                // in-place modify a memory location
-                result += IRCodeChunk(null, null).also {
-                    it += IRInstruction(Opcode.LOADM, IRDataType.FLOAT, fpReg1 = valueReg, address = constAddress)
-                    it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=cmpReg, fpReg1 = valueReg, fpReg2 = tr.resultFpReg)
-                    it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=zeroReg, immediate = 0)
-                    it += IRInstruction(compareAndSetOpcode, IRDataType.BYTE, reg1=cmpResultReg, reg2=cmpReg, reg3=zeroReg)
-                    it += IRInstruction(Opcode.FFROMUB, IRDataType.FLOAT, reg1=cmpResultReg, fpReg1 = valueReg)
-                    it += IRInstruction(Opcode.STOREM, IRDataType.FLOAT, fpReg1 = valueReg, address = constAddress)
-                }
-            } else {
-                // in-place modify a symbol (variable)
-                result += IRCodeChunk(null, null).also {
-                    it += IRInstruction(Opcode.LOADM, IRDataType.FLOAT, fpReg1 = valueReg, labelSymbol = symbol)
-                    it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=cmpReg, fpReg1 = valueReg, fpReg2 = tr.resultFpReg)
-                    it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=zeroReg, immediate = 0)
-                    it += IRInstruction(compareAndSetOpcode, IRDataType.BYTE, reg1=cmpResultReg, reg2=cmpReg, reg3=zeroReg)
-                    it += IRInstruction(Opcode.FFROMUB, IRDataType.FLOAT, reg1=cmpResultReg, fpReg1 = valueReg)
-                    it += IRInstruction(Opcode.STOREM, IRDataType.FLOAT, fpReg1 = valueReg, labelSymbol = symbol)
-                }
-            }
-        }
-        return result
-    }
-
-    private fun createInplaceArrayComparison(array: PtArrayIndexer, value: PtExpression, comparisonOperator: String): IRCodeChunks? {
-        if(array.type.isFloat)
-            return null  // TODO("optimized in-place compare on float arrays"))
-
-        val eltSize = codeGen.program.memsizer.memorySize(array.type, null)
-        val result = mutableListOf<IRCodeChunkBase>()
-        if(array.splitWords)
-            TODO("inplace compare for split word array")
-        val vmDt = irType(array.type)
-        val constIndex = array.index.asConstInteger()
-        val constValue = value.asConstInteger()
-        val cmpResultReg = codeGen.registers.nextFree()
-        if(constIndex!=null) {
-            if(constValue==0) {
-                // comparison against zero.
-                val valueReg = codeGen.registers.nextFree()
-                result += IRCodeChunk(null, null).also {
-                    it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
-                    it += when(comparisonOperator) {
-                        "==" -> IRInstruction(Opcode.SZ, vmDt, reg1=cmpResultReg, reg2=valueReg)
-                        "!=" -> IRInstruction(Opcode.SNZ, vmDt, reg1=cmpResultReg, reg2=valueReg)
-                        "<" -> return null  // TODO("array <0 inplace"))
-                        "<=" -> return null  // TODO("array <=0 inplace"))
-                        ">" -> return null  // TODO("array >0 inplace"))
-                        ">=" -> return null  // TODO("array >=0 inplace"))
-                        else -> throw AssemblyError("invalid operator")
-                    }
-                    it += IRInstruction(Opcode.STOREM, vmDt, reg1 = cmpResultReg, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
-                }
-                return result
-            } else {
-                return null  // TODO("compare against non-zero value"))
-            }
-        } else {
-            if(constValue==0) {
-                // comparison against zero.
-                val valueReg = codeGen.registers.nextFree()
-                val indexTr = expressionEval.translateExpression(array.index)
-                addToResult(result, indexTr, indexTr.resultReg, -1)
-                result += IRCodeChunk(null, null).also {
-                    it += IRInstruction(Opcode.LOADX, vmDt, reg1=valueReg, reg2=indexTr.resultReg, labelSymbol = array.variable.name)
-                    it += when(comparisonOperator) {
-                        "==" -> IRInstruction(Opcode.SZ, vmDt, reg1=cmpResultReg, reg2=valueReg)
-                        "!=" -> IRInstruction(Opcode.SNZ, vmDt, reg1=cmpResultReg, reg2=valueReg)
-                        "<" -> return null  // TODO("array <0 inplace"))
-                        "<=" -> return null  // TODO("array <=0 inplace"))
-                        ">" -> return null  // TODO("array >0 inplace"))
-                        ">=" -> return null  // TODO("array >=0 inplace"))
-                        else -> throw AssemblyError("invalid operator")
-                    }
-                    it += IRInstruction(Opcode.STOREX, vmDt, reg1=valueReg, reg2=indexTr.resultReg, labelSymbol = array.variable.name)
-                }
-                return result
-            }
-            else
-                return null  // TODO("compare against non-zero value"))
-        }
-    }
-
 }

codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt

@@ -42,8 +42,6 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
             "ror" -> funcRolRor(call)
             "rol2" -> funcRolRor(call)
             "ror2" -> funcRolRor(call)
-            "prog8_ifelse_bittest_set" -> throw AssemblyError("prog8_ifelse_bittest_set() should have been translated as part of an ifElse/ifExpression statement")
-            "prog8_ifelse_bittest_notset" -> throw AssemblyError("prog8_ifelse_bittest_notset() should have been translated as part of an ifElse/ifExpression statement")
             "prog8_lib_stringcompare" -> funcStringCompare(call)
             "prog8_lib_square_byte" -> funcSquare(call, IRDataType.BYTE)
             "prog8_lib_square_word" -> funcSquare(call, IRDataType.WORD)
@@ -56,12 +54,12 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
         val valueTr = exprGen.translateExpression(call.args[0])
         addToResult(result, valueTr, valueTr.resultReg, valueTr.resultFpReg)
         return if(resultType==IRDataType.FLOAT) {
-            val resultFpReg = codeGen.registers.nextFreeFloat()
+            val resultFpReg = codeGen.registers.next(IRDataType.FLOAT)
             addInstr(result, IRInstruction(Opcode.SQUARE, resultType, fpReg1 = resultFpReg, fpReg2 = valueTr.resultFpReg), null)
             ExpressionCodeResult(result, resultType, -1, resultFpReg)
         }
         else {
-            val resultReg = codeGen.registers.nextFree()
+            val resultReg = codeGen.registers.next(resultType)
             addInstr(result, IRInstruction(Opcode.SQUARE, resultType, reg1 = resultReg, reg2 = valueTr.resultReg), null)
             ExpressionCodeResult(result, resultType, resultReg, -1)
         }
@@ -75,7 +73,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
         return if(call.void)
             ExpressionCodeResult(result, IRDataType.BYTE, -1, -1)
         else
-            ExpressionCodeResult(result, IRDataType.WORD, codeGen.registers.nextFree(), -1)      // TODO actually the result is returned in CPU registers AY...
+            ExpressionCodeResult(result, IRDataType.WORD, codeGen.registers.next(IRDataType.WORD), -1)      // TODO actually the result is returned in CPU registers AY...
     }
 
     private fun funcCallfar(call: PtBuiltinFunctionCall): ExpressionCodeResult {
@@ -125,7 +123,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
             addToResult(result, tr, tr.resultReg, -1)
             addInstr(result, IRInstruction(Opcode.DIVMOD, type, reg1 = tr.resultReg, immediate = divident.number.toInt()), null)
             divisionReg = tr.resultReg
-            remainderReg = codeGen.registers.nextFree()
+            remainderReg = codeGen.registers.next(type)
         } else {
             val numTr = exprGen.translateExpression(number)
             addToResult(result, numTr, numTr.resultReg, -1)
@@ -150,8 +148,9 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
         val right = exprGen.translateExpression(call.args[1])
         addToResult(result, left, left.resultReg, -1)
         addToResult(result, right, right.resultReg, -1)
-        result += codeGen.makeSyscall(IMSyscall.COMPARE_STRINGS, listOf(IRDataType.WORD to left.resultReg, IRDataType.WORD to right.resultReg), IRDataType.BYTE to left.resultReg)
-        return ExpressionCodeResult(result, IRDataType.BYTE, left.resultReg, -1)
+        val resultReg = codeGen.registers.next(IRDataType.BYTE)
+        result += codeGen.makeSyscall(IMSyscall.COMPARE_STRINGS, listOf(IRDataType.WORD to left.resultReg, IRDataType.WORD to right.resultReg), IRDataType.BYTE to resultReg)
+        return ExpressionCodeResult(result, IRDataType.BYTE, resultReg, -1)
     }
 
     private fun funcCmp(call: PtBuiltinFunctionCall): ExpressionCodeResult {
@@ -178,7 +177,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
         when (sourceDt.base) {
             BaseDataType.BYTE -> {
                 val notNegativeLabel = codeGen.createLabelName()
-                val compareReg = codeGen.registers.nextFree()
+                val compareReg = codeGen.registers.next(IRDataType.BYTE)
                 result += IRCodeChunk(null, null).also {
                     it += IRInstruction(Opcode.LOADR, IRDataType.BYTE, reg1=compareReg, reg2=tr.resultReg)
                     it += IRInstruction(Opcode.BSTPOS, labelSymbol = notNegativeLabel)
@@ -189,7 +188,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
             }
             BaseDataType.WORD -> {
                 val notNegativeLabel = codeGen.createLabelName()
-                val compareReg = codeGen.registers.nextFree()
+                val compareReg = codeGen.registers.next(IRDataType.WORD)
                 result += IRCodeChunk(null, null).also {
                     it += IRInstruction(Opcode.LOADR, IRDataType.WORD, reg1=compareReg, reg2=tr.resultReg)
                     it += IRInstruction(Opcode.BSTPOS, labelSymbol = notNegativeLabel)
@@ -199,7 +198,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
                 return ExpressionCodeResult(result, IRDataType.WORD, tr.resultReg, -1)
             }
             BaseDataType.FLOAT -> {
-                val resultFpReg = codeGen.registers.nextFreeFloat()
+                val resultFpReg = codeGen.registers.next(IRDataType.FLOAT)
                 addInstr(result, IRInstruction(Opcode.FABS, IRDataType.FLOAT, fpReg1 = resultFpReg, fpReg2 = tr.resultFpReg), null)
                 return ExpressionCodeResult(result, IRDataType.FLOAT, -1, resultFpReg)
             }
@@ -210,7 +209,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
     private fun funcSgn(call: PtBuiltinFunctionCall): ExpressionCodeResult {
         val result = mutableListOf<IRCodeChunkBase>()
         val tr = exprGen.translateExpression(call.args.single())
-        val resultReg = codeGen.registers.nextFree()
+        val resultReg = codeGen.registers.next(tr.dt)
 
         if(tr.dt==IRDataType.FLOAT) {
             addToResult(result, tr, -1, tr.resultFpReg)
@@ -233,7 +232,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
         when(dt.base) {
             BaseDataType.UBYTE -> {
                 addToResult(result, tr, tr.resultReg, -1)
-                val resultReg = codeGen.registers.nextFree()
+                val resultReg = codeGen.registers.next(IRDataType.BYTE)
                 result += IRCodeChunk(null, null).also {
                     it += IRInstruction(Opcode.SQRT, IRDataType.BYTE, reg1=resultReg, reg2=tr.resultReg)
                 }
@@ -241,7 +240,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
             }
             BaseDataType.UWORD -> {
                 addToResult(result, tr, tr.resultReg, -1)
-                val resultReg = codeGen.registers.nextFree()
+                val resultReg = codeGen.registers.next(IRDataType.WORD)
                 result += IRCodeChunk(null, null).also {
                     it += IRInstruction(Opcode.SQRT, IRDataType.WORD, reg1=resultReg, reg2=tr.resultReg)
                 }
@@ -249,7 +248,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
             }
             BaseDataType.FLOAT -> {
                 addToResult(result, tr, -1, tr.resultFpReg)
-                val resultFpReg = codeGen.registers.nextFreeFloat()
+                val resultFpReg = codeGen.registers.next(IRDataType.FLOAT)
                 result += IRCodeChunk(null, null).also {
                     it += IRInstruction(Opcode.SQRT, IRDataType.FLOAT, fpReg1 = resultFpReg, fpReg2 = tr.resultFpReg)
                 }
@@ -261,7 +260,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
 
     private fun funcMkword(call: PtBuiltinFunctionCall): ExpressionCodeResult {
         val result = mutableListOf<IRCodeChunkBase>()
-        val resultReg = codeGen.registers.nextFree()
+        val resultReg = codeGen.registers.next(IRDataType.WORD)
         if((call.args[0] as? PtNumber)?.number == 0.0) {
             // msb is 0, use EXT
             val lsbTr = exprGen.translateExpression(call.args[1])
@@ -406,7 +405,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
         val result = mutableListOf<IRCodeChunkBase>()
         return if(dt==IRDataType.FLOAT) {
             if(call.args[0] is PtNumber) {
-                val resultFpRegister = codeGen.registers.nextFreeFloat()
+                val resultFpRegister = codeGen.registers.next(IRDataType.FLOAT)
                 val address = (call.args[0] as PtNumber).number.toInt()
                 result += IRCodeChunk(null, null).also {
                     it += IRInstruction(Opcode.LOADM, IRDataType.FLOAT, fpReg1 = resultFpRegister, address = address)
@@ -415,7 +414,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
             } else {
                 val tr = exprGen.translateExpression(call.args.single())
                 addToResult(result, tr, tr.resultReg, -1)
-                val resultFpReg = codeGen.registers.nextFreeFloat()
+                val resultFpReg = codeGen.registers.next(IRDataType.FLOAT)
                 result += IRCodeChunk(null, null).also {
                     it += IRInstruction(Opcode.LOADI, IRDataType.FLOAT, reg1 = tr.resultReg, fpReg1 = resultFpReg)
                 }
@@ -423,7 +422,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
             }
         } else {
             if (call.args[0] is PtNumber) {
-                val resultRegister = codeGen.registers.nextFree()
+                val resultRegister = codeGen.registers.next(dt)
                 val address = (call.args[0] as PtNumber).number.toInt()
                 result += IRCodeChunk(null, null).also {
                     it += IRInstruction(Opcode.LOADM, dt, reg1 = resultRegister, address = address)
@@ -432,7 +431,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
             } else {
                 val tr = exprGen.translateExpression(call.args.single())
                 addToResult(result, tr, tr.resultReg, -1)
-                val resultReg = codeGen.registers.nextFree()
+                val resultReg = codeGen.registers.next(dt)
                 result += IRCodeChunk(null, null).also {
                     it += IRInstruction(Opcode.LOADI, dt, reg1 = resultReg, reg2 = tr.resultReg)
                 }
@@ -474,7 +473,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
         }
 
         return if(address is PtNumber) {
-            val resultRegister = codeGen.registers.nextFree()
+            val resultRegister = codeGen.registers.next(IRDataType.BYTE)
             val addressNum = address.number.toInt()
             result += IRCodeChunk(null, null).also {
                 it += IRInstruction(Opcode.LOADM, IRDataType.BYTE, reg1 = resultRegister, address = addressNum)
@@ -484,7 +483,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
         } else {
             val addressTr = exprGen.translateExpression(address)
             addToResult(result, addressTr, addressTr.resultReg, -1)
-            val resultReg = codeGen.registers.nextFree()
+            val resultReg = codeGen.registers.next(IRDataType.BYTE)
             result += IRCodeChunk(null, null).also {
                 it += IRInstruction(Opcode.LOADI, IRDataType.BYTE, reg1 = resultReg, reg2 = addressTr.resultReg)
             }
@@ -497,22 +496,26 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
     private fun funcMemory(call: PtBuiltinFunctionCall): ExpressionCodeResult {
         val name = (call.args[0] as PtString).value
         val code = IRCodeChunk(null, null)
-        val resultReg = codeGen.registers.nextFree()
+        val resultReg = codeGen.registers.next(IRDataType.WORD)
         code += IRInstruction(Opcode.LOAD, IRDataType.WORD, reg1=resultReg, labelSymbol = "prog8_slabs.prog8_memoryslab_$name")
         return ExpressionCodeResult(code, IRDataType.BYTE, resultReg, -1)
     }
 
     private fun funcLsb(call: PtBuiltinFunctionCall): ExpressionCodeResult {
-        return exprGen.translateExpression(call.args.single())
+        val result = mutableListOf<IRCodeChunkBase>()
+        val tr = exprGen.translateExpression(call.args.single())
+        addToResult(result, tr, tr.resultReg, -1)
+        val resultReg = codeGen.registers.next(IRDataType.BYTE)
+        addInstr(result, IRInstruction(Opcode.LSIG, IRDataType.BYTE, reg1 = resultReg, reg2 = tr.resultReg), null)
         // note: if a word result is needed, the upper byte is cleared by the typecast that follows. No need to do it here.
-        // ....To be more strict, maybe we should introduce a new result register that is of type .b?
+        return ExpressionCodeResult(result, IRDataType.BYTE, resultReg, -1)
     }
 
     private fun funcMsb(call: PtBuiltinFunctionCall): ExpressionCodeResult {
         val result = mutableListOf<IRCodeChunkBase>()
         val tr = exprGen.translateExpression(call.args.single())
         addToResult(result, tr, tr.resultReg, -1)
-        val resultReg = codeGen.registers.nextFree()
+        val resultReg = codeGen.registers.next(IRDataType.BYTE)
         addInstr(result, IRInstruction(Opcode.MSIG, IRDataType.BYTE, reg1 = resultReg, reg2 = tr.resultReg), null)
         // note: if a word result is needed, the upper byte is cleared by the typecast that follows. No need to do it here.
         return ExpressionCodeResult(result, IRDataType.BYTE, resultReg, -1)
@@ -545,10 +548,25 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
         val arr = (arg as? PtArrayIndexer)
         val index = arr?.index?.asConstInteger()
         if(arr!=null && index!=null) {
-            if(arr.splitWords)  TODO("IR rol/ror on split words array")
             val variable = arr.variable.name
-            val offset = codeGen.program.memsizer.memorySize(arr.type, index)
-            addInstr(result, IRInstruction(opcodeMemAndReg.first, vmDt, labelSymbol = variable, symbolOffset = offset), null)
+            if(arr.splitWords) {
+                result += IRCodeChunk(null, null).also {
+                    when(opcodeMemAndReg.first) {
+                        Opcode.ROXRM, Opcode.RORM -> {
+                            it += IRInstruction(opcodeMemAndReg.first, IRDataType.BYTE, labelSymbol = "${variable}_msb", symbolOffset = index)
+                            it += IRInstruction(opcodeMemAndReg.first, IRDataType.BYTE, labelSymbol = "${variable}_lsb", symbolOffset = index)
+                        }
+                        Opcode.ROXLM, Opcode.ROLM -> {
+                            it += IRInstruction(opcodeMemAndReg.first, IRDataType.BYTE, labelSymbol = "${variable}_lsb", symbolOffset = index)
+                            it += IRInstruction(opcodeMemAndReg.first, IRDataType.BYTE, labelSymbol = "${variable}_msb", symbolOffset = index)
+                        }
+                        else -> throw AssemblyError("wrong rol/ror opcode")
+                    }
+                }
+            } else {
+                val offset = codeGen.program.memsizer.memorySize(arr.type, index)
+                addInstr(result, IRInstruction(opcodeMemAndReg.first, vmDt, labelSymbol = variable, symbolOffset = offset), null)
+            }
             return ExpressionCodeResult(result, vmDt, -1, -1)
         }
 
@@ -577,7 +595,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
             is PtIdentifier -> {
                 if(isConstZeroValue) {
                     result += IRCodeChunk(null, null).also {
-                        val pointerReg = codeGen.registers.nextFree()
+                        val pointerReg = codeGen.registers.next(IRDataType.WORD)
                         it += IRInstruction(Opcode.LOAD, IRDataType.WORD, reg1 = pointerReg, labelSymbol = target.name)
                         if (msb)
                             it += IRInstruction(Opcode.INC, IRDataType.WORD, reg1 = pointerReg)
@@ -587,7 +605,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
                     val valueTr = exprGen.translateExpression(call.args[1])
                     addToResult(result, valueTr, valueTr.resultReg, -1)
                     result += IRCodeChunk(null, null).also {
-                        val pointerReg = codeGen.registers.nextFree()
+                        val pointerReg = codeGen.registers.next(IRDataType.WORD)
                         it += IRInstruction(Opcode.LOAD, IRDataType.WORD, reg1 = pointerReg, labelSymbol = target.name)
                         if (msb)
                             it += IRInstruction(Opcode.INC, IRDataType.WORD, reg1 = pointerReg)
@@ -602,7 +620,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
                     val varName = target.variable.name + if(msb) "_msb" else "_lsb"
                     if(isConstZeroValue) {
                         if(constIndex!=null) {
-                            val offsetReg = codeGen.registers.nextFree()
+                            val offsetReg = codeGen.registers.next(IRDataType.BYTE)
                             result += IRCodeChunk(null, null).also {
                                 it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=offsetReg, immediate = constIndex)
                                 it += IRInstruction(Opcode.STOREZX, IRDataType.BYTE, reg1=offsetReg, labelSymbol = varName)
@@ -618,7 +636,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
                         val valueTr = exprGen.translateExpression(call.args[1])
                         addToResult(result, valueTr, valueTr.resultReg, -1)
                         if(constIndex!=null) {
-                            val offsetReg = codeGen.registers.nextFree()
+                            val offsetReg = codeGen.registers.next(IRDataType.BYTE)
                             result += IRCodeChunk(null, null).also {
                                 it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=offsetReg, immediate = constIndex)
                                 it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1=valueTr.resultReg, reg2=offsetReg, labelSymbol = varName)
@@ -637,7 +655,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
                     val constIndex = target.index.asConstInteger()
                     if(isConstZeroValue) {
                         if(constIndex!=null) {
-                            val offsetReg = codeGen.registers.nextFree()
+                            val offsetReg = codeGen.registers.next(IRDataType.BYTE)
                             val offset = eltSize*constIndex + if(msb) 1 else 0
                             result += IRCodeChunk(null, null).also {
                                 it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=offsetReg, immediate = offset)
@@ -658,7 +676,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
                         val valueTr = exprGen.translateExpression(call.args[1])
                         addToResult(result, valueTr, valueTr.resultReg, -1)
                         if(constIndex!=null) {
-                            val offsetReg = codeGen.registers.nextFree()
+                            val offsetReg = codeGen.registers.next(IRDataType.BYTE)
                             val offset = eltSize*constIndex + if(msb) 1 else 0
                             result += IRCodeChunk(null, null).also {
                                 it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=offsetReg, immediate = offset)

codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt

@@ -33,7 +33,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             }
             is PtBool -> {
                 val code = IRCodeChunk(null, null)
-                val resultRegister = codeGen.registers.nextFree()
+                val resultRegister = codeGen.registers.next(IRDataType.BYTE)
                 code += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = resultRegister, immediate = expr.asInt())
                 ExpressionCodeResult(code, IRDataType.BYTE, resultRegister, -1)
             }
@@ -41,12 +41,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                 val vmDt = irType(expr.type)
                 val code = IRCodeChunk(null, null)
                 if(vmDt==IRDataType.FLOAT) {
-                    val resultFpRegister = codeGen.registers.nextFreeFloat()
+                    val resultFpRegister = codeGen.registers.next(IRDataType.FLOAT)
                     code += IRInstruction(Opcode.LOAD, vmDt, fpReg1 = resultFpRegister, immediateFp = expr.number)
                     ExpressionCodeResult(code, vmDt,-1, resultFpRegister)
                 }
                 else {
-                    val resultRegister = codeGen.registers.nextFree()
+                    val resultRegister = codeGen.registers.next(vmDt)
                     code += IRInstruction(Opcode.LOAD, vmDt, reg1 = resultRegister, immediate = expr.number.toInt())
                     ExpressionCodeResult(code, vmDt, resultRegister, -1)
                 }
@@ -56,12 +56,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                 if (expr.type.isPassByValue) {
                     val vmDt = irType(expr.type)
                     if(vmDt==IRDataType.FLOAT) {
-                        val resultFpRegister = codeGen.registers.nextFreeFloat()
+                        val resultFpRegister = codeGen.registers.next(IRDataType.FLOAT)
                         code += IRInstruction(Opcode.LOADM, vmDt, fpReg1 = resultFpRegister, labelSymbol = expr.name)
                         ExpressionCodeResult(code, vmDt, -1, resultFpRegister)
                     }
                     else {
-                        val resultRegister = codeGen.registers.nextFree()
+                        val resultRegister = codeGen.registers.next(vmDt)
                         code += IRInstruction(Opcode.LOADM, vmDt, reg1 = resultRegister, labelSymbol = expr.name)
                         ExpressionCodeResult(code, vmDt, resultRegister, -1)
                     }
@@ -69,7 +69,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                     // for strings and arrays etc., load the *address* of the value instead
                     // for arrays this could mean a split word array, in which case we take the address of the _lsb array which comes first
                     val vmDt = if(expr.type.isUndefined) IRDataType.WORD else irType(expr.type)
-                    val resultRegister = codeGen.registers.nextFree()
+                    val resultRegister = codeGen.registers.next(vmDt)
                     val labelsymbol = if(expr.type.isSplitWordArray) expr.name+"_lsb" else expr.name
                     code += IRInstruction(Opcode.LOAD, vmDt, reg1 = resultRegister, labelSymbol = labelsymbol)
                     ExpressionCodeResult(code, vmDt, resultRegister, -1)
@@ -96,15 +96,46 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
         if((ifExpr.condition as? PtPrefix)?.operator=="not")
             throw AssemblyError("not prefix in ifexpression should have been replaced by swapped values")
 
-        // TODO don't store condition as expression result but just use the flags, like a normal PtIfElse translation does
-        val condTr = translateExpression(ifExpr.condition)
+        val result = mutableListOf<IRCodeChunkBase>()
         val trueTr = translateExpression(ifExpr.truevalue)
         val falseTr = translateExpression(ifExpr.falsevalue)
-        val irDt = irType(ifExpr.type)
-        val result = mutableListOf<IRCodeChunkBase>()
         val falseLabel = codeGen.createLabelName()
         val endLabel = codeGen.createLabelName()
+        val irDt = irType(ifExpr.type)
 
+        if(ifExpr.condition is PtBinaryExpression) {
+            val useBIT = checkIfConditionCanUseBIT(ifExpr.condition as PtBinaryExpression)
+            if(useBIT!=null) {
+                // use a BIT instruction to test for bit 7 or 6 set/clear
+                val (testBitSet, variable, bitmask) = useBIT
+                val bitBranchOpcode = when(testBitSet) {
+                    true -> when(bitmask) {
+                        64 -> Opcode.BSTVC
+                        128 -> Opcode.BSTPOS
+                        else -> throw AssemblyError("need bit 6 or 7")
+                    }
+                    false -> when(bitmask) {
+                        64 -> Opcode.BSTVS
+                        128 -> Opcode.BSTNEG
+                        else -> throw AssemblyError("need bit 6 or 7")
+                    }
+                }
+                result += IRCodeChunk(null, null).also {
+                    it += IRInstruction(Opcode.BIT, IRDataType.BYTE, labelSymbol = variable.name)
+                    it += IRInstruction(bitBranchOpcode, labelSymbol = falseLabel)
+                }
+                addToResult(result, trueTr, trueTr.resultReg, -1)
+                addInstr(result, IRInstruction(Opcode.JUMP, labelSymbol = endLabel), null)
+                result += IRCodeChunk(falseLabel, null)
+                addToResult(result, falseTr, trueTr.resultReg, -1)
+                result += IRCodeChunk(endLabel, null)
+                return ExpressionCodeResult(result, irDt, trueTr.resultReg, -1)
+            }
+        }
+
+
+        // TODO don't store condition as expression result but just use the flags, like a normal PtIfElse translation does
+        val condTr = translateExpression(ifExpr.condition)
         addToResult(result, condTr, condTr.resultReg, -1)
         addInstr(result, IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=condTr.resultReg, immediate = 0), null)
         addInstr(result, IRInstruction(Opcode.BSTEQ, labelSymbol = falseLabel), null)
@@ -131,16 +162,25 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
         val symbol = expr.identifier.name
         // note: LOAD <symbol>  gets you the address of the symbol, whereas LOADM <symbol> would get you the value stored at that location
         val result = mutableListOf<IRCodeChunkBase>()
-        val resultRegister = codeGen.registers.nextFree()
+        val resultRegister = codeGen.registers.next(vmDt)
+
+        fun loadAddressOfArrayLabel(reg: Int) {
+            if (expr.isMsbForSplitArray) {
+                addInstr(result, IRInstruction(Opcode.LOAD, vmDt, reg1 = reg, labelSymbol = symbol + "_msb"), null)
+            } else if (expr.identifier.type.isSplitWordArray) {
+                // the _lsb split array comes first in memory
+                addInstr(result, IRInstruction(Opcode.LOAD, vmDt, reg1 = reg, labelSymbol = symbol + "_lsb"), null)
+            } else
+                addInstr(result, IRInstruction(Opcode.LOAD, vmDt, reg1 = reg, labelSymbol = symbol), null)
+        }
+
         if(expr.isFromArrayElement) {
-            if(expr.identifier.type.isSplitWordArray)
-                TODO("address of element of a split word array")
-            addInstr(result, IRInstruction(Opcode.LOAD, vmDt, reg1 = resultRegister, labelSymbol = symbol), null)
-            val indexTr2 = translateExpression(expr.arrayIndexExpr!!)
-            addToResult(result, indexTr2, indexTr2.resultReg, -1)
-            val indexWordReg = codeGen.registers.nextFree()
-            addInstr(result, IRInstruction(Opcode.EXT, IRDataType.BYTE, reg1=indexWordReg, reg2=indexTr2.resultReg), null)
+            val indexTr = translateExpression(expr.arrayIndexExpr!!)
+            addToResult(result, indexTr, indexTr.resultReg, -1)
+            val indexWordReg = codeGen.registers.next(IRDataType.WORD)
+            addInstr(result, IRInstruction(Opcode.EXT, IRDataType.BYTE, reg1=indexWordReg, reg2=indexTr.resultReg), null)
             if(expr.identifier.type.isUnsignedWord) {
+                require(!expr.isMsbForSplitArray)
                 result += IRCodeChunk(null, null).also {
                     it += IRInstruction(Opcode.LOADM, vmDt, reg1 = resultRegister, labelSymbol = symbol)
                     it += IRInstruction(Opcode.ADDR, IRDataType.WORD, reg1=resultRegister, reg2=indexWordReg)
@@ -148,29 +188,22 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             } else {
                 val eltSize = codeGen.program.memsizer.memorySize(expr.identifier.type, 1)
                 result += IRCodeChunk(null, null).also {
-                    // multiply indexTr resultreg by the eltSize and add this to the resultRegister.
-                    it += IRInstruction(Opcode.LOAD, vmDt, reg1 = resultRegister, labelSymbol = symbol)
-                    if(eltSize>1) {
+                    loadAddressOfArrayLabel(resultRegister)
+                    if(eltSize>1 && !expr.identifier.type.isSplitWordArray) {
                         it += IRInstruction(Opcode.MUL, IRDataType.WORD, reg1=indexWordReg, immediate = eltSize)
                     }
                     it += IRInstruction(Opcode.ADDR, IRDataType.WORD, reg1=resultRegister, reg2=indexWordReg)
                 }
             }
         } else {
-            if(expr.isMsbForSplitArray) {
-                addInstr(result, IRInstruction(Opcode.LOAD, vmDt, reg1 = resultRegister, labelSymbol = symbol+"_msb"), null)
-            } else if(expr.identifier.type.isSplitWordArray) {
-                // the _lsb split array comes first in memory
-                addInstr(result, IRInstruction(Opcode.LOAD, vmDt, reg1 = resultRegister, labelSymbol = symbol+"_lsb"), null)
-            } else
-                addInstr(result, IRInstruction(Opcode.LOAD, vmDt, reg1 = resultRegister, labelSymbol = symbol), null)
+            loadAddressOfArrayLabel(resultRegister)
         }
         return ExpressionCodeResult(result, vmDt, resultRegister, -1)
     }
 
     private fun translate(mem: PtMemoryByte): ExpressionCodeResult {
         val result = mutableListOf<IRCodeChunkBase>()
-        val resultRegister = codeGen.registers.nextFree()
+        val resultRegister = codeGen.registers.next(IRDataType.BYTE)
 
         val constAddress = mem.address as? PtNumber
         if(constAddress!=null) {
@@ -183,7 +216,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             if((ptrWithOffset.right as? PtNumber)?.number?.toInt() in 0..255) {
                 // LOADIX only works with byte index.
                 val ptrName = (ptrWithOffset.left as PtIdentifier).name
-                val offsetReg = codeGen.registers.nextFree()
+                val offsetReg = codeGen.registers.next(IRDataType.BYTE)
                 result += IRCodeChunk(null, null).also {
                     it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=offsetReg, immediate = ptrWithOffset.right.asConstInteger())
                     it += IRInstruction(Opcode.LOADIX, IRDataType.BYTE, reg1=resultRegister, reg2=offsetReg, labelSymbol = ptrName)
@@ -228,17 +261,18 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                     val endLabel = codeGen.createLabelName()
                     val elementTr = translateExpression(check.needle)
                     addToResult(result, elementTr, elementTr.resultReg, -1)
+                    val boolResultRegister = if(elementDt.isByteOrBool) elementTr.resultReg else codeGen.registers.next(IRDataType.BYTE)
                     result += IRCodeChunk(null, null).also {
                         for(value in haystack){
                             it += IRInstruction(Opcode.CMPI, irType(elementDt), elementTr.resultReg, immediate = value)
                             it += IRInstruction(Opcode.BSTEQ, labelSymbol = gottemLabel)
                         }
-                        it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, elementTr.resultReg, immediate = 0)
+                        it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, boolResultRegister, immediate = 0)
                         it += IRInstruction(Opcode.JUMP, labelSymbol = endLabel)
                     }
-                    addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, elementTr.resultReg, immediate = 1), gottemLabel)
+                    addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, boolResultRegister, immediate = 1), gottemLabel)
                     result += IRCodeChunk(endLabel, null)
-                    return ExpressionCodeResult(result, IRDataType.BYTE, elementTr.resultReg, -1)
+                    return ExpressionCodeResult(result, IRDataType.BYTE, boolResultRegister, -1)
                 }
                 elementDt.isFloat -> throw AssemblyError("containmentchecks for floats should always be done on an array variable with subroutine")
                 else -> throw AssemblyError("weird dt $elementDt")
@@ -253,9 +287,10 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                 addToResult(result, elementTr, elementTr.resultReg, -1)
                 val iterableTr = translateExpression(haystackVar)
                 addToResult(result, iterableTr, iterableTr.resultReg, -1)
-                result += codeGen.makeSyscall(IMSyscall.STRING_CONTAINS, listOf(IRDataType.BYTE to elementTr.resultReg, IRDataType.WORD to iterableTr.resultReg), IRDataType.BYTE to elementTr.resultReg)
-                addInstr(result, IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=elementTr.resultReg, immediate = 0), null)
-                return ExpressionCodeResult(result, IRDataType.BYTE, elementTr.resultReg, -1)
+                val resultReg = codeGen.registers.next(IRDataType.BYTE)
+                result += codeGen.makeSyscall(IMSyscall.STRING_CONTAINS, listOf(IRDataType.BYTE to elementTr.resultReg, IRDataType.WORD to iterableTr.resultReg), IRDataType.BYTE to resultReg)
+                addInstr(result, IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=resultReg, immediate = 0), null)
+                return ExpressionCodeResult(result, IRDataType.BYTE, resultReg, -1)
             }
             haystackVar.type.isByteArray -> {
                 addInstr(result, IRInstruction(Opcode.PREPARECALL, immediate = 3), null)
@@ -263,12 +298,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                 addToResult(result, elementTr, elementTr.resultReg, -1)
                 val iterableTr = translateExpression(haystackVar)
                 addToResult(result, iterableTr, iterableTr.resultReg, -1)
-                val lengthReg = codeGen.registers.nextFree()
+                val lengthReg = codeGen.registers.next(IRDataType.BYTE)
                 val iterableLength = codeGen.symbolTable.getLength(haystackVar.name)
                 addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=lengthReg, immediate = iterableLength!!), null)
-                result += codeGen.makeSyscall(IMSyscall.BYTEARRAY_CONTAINS, listOf(IRDataType.BYTE to elementTr.resultReg, IRDataType.WORD to iterableTr.resultReg, IRDataType.BYTE to lengthReg), IRDataType.BYTE to elementTr.resultReg)
-                addInstr(result, IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=elementTr.resultReg, immediate = 0), null)
-                return ExpressionCodeResult(result, IRDataType.BYTE, elementTr.resultReg, -1)
+                val resultReg = codeGen.registers.next(IRDataType.BYTE)
+                result += codeGen.makeSyscall(IMSyscall.BYTEARRAY_CONTAINS, listOf(IRDataType.BYTE to elementTr.resultReg, IRDataType.WORD to iterableTr.resultReg, IRDataType.BYTE to lengthReg), IRDataType.BYTE to resultReg)
+                addInstr(result, IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=resultReg, immediate = 0), null)
+                return ExpressionCodeResult(result, IRDataType.BYTE, resultReg, -1)
             }
             haystackVar.type.isWordArray -> {
                 addInstr(result, IRInstruction(Opcode.PREPARECALL, immediate = 3), null)
@@ -276,12 +312,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                 addToResult(result, elementTr, elementTr.resultReg, -1)
                 val iterableTr = translateExpression(haystackVar)
                 addToResult(result, iterableTr, iterableTr.resultReg, -1)
-                val lengthReg = codeGen.registers.nextFree()
+                val lengthReg = codeGen.registers.next(IRDataType.BYTE)
                 val iterableLength = codeGen.symbolTable.getLength(haystackVar.name)
                 addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=lengthReg, immediate = iterableLength!!), null)
-                result += codeGen.makeSyscall(IMSyscall.WORDARRAY_CONTAINS, listOf(IRDataType.WORD to elementTr.resultReg, IRDataType.WORD to iterableTr.resultReg, IRDataType.BYTE to lengthReg), IRDataType.BYTE to elementTr.resultReg)
-                addInstr(result, IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=elementTr.resultReg, immediate = 0), null)
-                return ExpressionCodeResult(result, IRDataType.BYTE, elementTr.resultReg, -1)
+                val resultReg = codeGen.registers.next(IRDataType.BYTE)
+                result += codeGen.makeSyscall(IMSyscall.WORDARRAY_CONTAINS, listOf(IRDataType.WORD to elementTr.resultReg, IRDataType.WORD to iterableTr.resultReg, IRDataType.BYTE to lengthReg), IRDataType.BYTE to resultReg)
+                addInstr(result, IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=resultReg, immediate = 0), null)
+                return ExpressionCodeResult(result, IRDataType.BYTE, resultReg, -1)
             }
             haystackVar.type.isFloatArray -> {
                 addInstr(result, IRInstruction(Opcode.PREPARECALL, immediate = 3), null)
@@ -289,8 +326,8 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                 addToResult(result, elementTr, -1, elementTr.resultFpReg)
                 val iterableTr = translateExpression(haystackVar)
                 addToResult(result, iterableTr, iterableTr.resultReg, -1)
-                val lengthReg = codeGen.registers.nextFree()
-                val resultReg = codeGen.registers.nextFree()
+                val lengthReg = codeGen.registers.next(IRDataType.BYTE)
+                val resultReg = codeGen.registers.next(IRDataType.BYTE)
                 val iterableLength = codeGen.symbolTable.getLength(haystackVar.name)
                 addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=lengthReg, immediate = iterableLength!!), null)
                 result += codeGen.makeSyscall(IMSyscall.FLOATARRAY_CONTAINS, listOf(IRDataType.FLOAT to elementTr.resultFpReg, IRDataType.WORD to iterableTr.resultReg, IRDataType.BYTE to lengthReg), IRDataType.BYTE to resultReg)
@@ -310,12 +347,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
 
         if(arrayIx.splitWords) {
             require(vmDt==IRDataType.WORD)
-            resultRegister = codeGen.registers.nextFree()
-            val finalResultReg = codeGen.registers.nextFree()
+            resultRegister = codeGen.registers.next(IRDataType.BYTE)
+            val finalResultReg = codeGen.registers.next(IRDataType.WORD)
             if(arrayIx.index is PtNumber) {
                 val memOffset = (arrayIx.index as PtNumber).number.toInt()
                 result += IRCodeChunk(null, null).also {
-                    val tmpRegMsb = codeGen.registers.nextFree()
+                    val tmpRegMsb = codeGen.registers.next(IRDataType.BYTE)
                     it += IRInstruction(Opcode.LOADM, IRDataType.BYTE, reg1=tmpRegMsb, labelSymbol= "${arrayVarSymbol}_msb", symbolOffset = memOffset)
                     it += IRInstruction(Opcode.LOADM, IRDataType.BYTE, reg1=resultRegister, labelSymbol= "${arrayVarSymbol}_lsb", symbolOffset = memOffset)
                     it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1=finalResultReg, reg2=tmpRegMsb, reg3=resultRegister)
@@ -324,7 +361,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                 val tr = translateExpression(arrayIx.index)
                 addToResult(result, tr, tr.resultReg, -1)
                 result += IRCodeChunk(null, null).also {
-                    val tmpRegMsb = codeGen.registers.nextFree()
+                    val tmpRegMsb = codeGen.registers.next(IRDataType.BYTE)
                     it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1=tmpRegMsb, reg2 = tr.resultReg, labelSymbol= "${arrayVarSymbol}_msb")
                     it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1=resultRegister, reg2 = tr.resultReg, labelSymbol= "${arrayVarSymbol}_lsb")
                     it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1=finalResultReg, reg2=tmpRegMsb, reg3=resultRegister)
@@ -337,11 +374,11 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
         if(arrayIx.index is PtNumber) {
             val memOffset = ((arrayIx.index as PtNumber).number.toInt() * eltSize)
             if(vmDt==IRDataType.FLOAT) {
-                resultFpRegister = codeGen.registers.nextFreeFloat()
+                resultFpRegister = codeGen.registers.next(IRDataType.FLOAT)
                 addInstr(result, IRInstruction(Opcode.LOADM, IRDataType.FLOAT, fpReg1=resultFpRegister, labelSymbol = arrayVarSymbol, symbolOffset = memOffset), null)
             }
             else {
-                resultRegister = codeGen.registers.nextFree()
+                resultRegister = codeGen.registers.next(vmDt)
                 addInstr(result, IRInstruction(Opcode.LOADM, vmDt, reg1=resultRegister, labelSymbol = arrayVarSymbol, symbolOffset = memOffset), null)
             }
         } else {
@@ -350,11 +387,11 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             if(eltSize>1)
                 result += codeGen.multiplyByConst(IRDataType.BYTE, tr.resultReg, eltSize)
             if(vmDt==IRDataType.FLOAT) {
-                resultFpRegister = codeGen.registers.nextFreeFloat()
+                resultFpRegister = codeGen.registers.next(IRDataType.FLOAT)
                 addInstr(result, IRInstruction(Opcode.LOADX, IRDataType.FLOAT, fpReg1 = resultFpRegister, reg1=tr.resultReg, labelSymbol = arrayVarSymbol), null)
             }
             else {
-                resultRegister = codeGen.registers.nextFree()
+                resultRegister = codeGen.registers.next(vmDt)
                 addInstr(result, IRInstruction(Opcode.LOADX, vmDt, reg1=resultRegister, reg2=tr.resultReg, labelSymbol = arrayVarSymbol), null)
             }
         }
@@ -398,15 +435,15 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             BaseDataType.BOOL -> {
                 when {
                     valueDt.isByte -> {
-                        actualResultReg2 = codeGen.registers.nextFree()
-                        addInstr(result, IRInstruction(Opcode.SNZ, IRDataType.BYTE, reg1=actualResultReg2, reg2=tr.resultReg), null)
+                        addInstr(result, IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=tr.resultReg, immediate = 0), null)
+                        actualResultReg2 = loadStatusAsBooleanResult(Opcode.BSTNE, result)
                     }
                     valueDt.isWord -> {
-                        actualResultReg2 = codeGen.registers.nextFree()
-                        addInstr(result, IRInstruction(Opcode.SNZ, IRDataType.WORD, reg1=actualResultReg2, reg2=tr.resultReg), null)
+                        addInstr(result, IRInstruction(Opcode.CMPI, IRDataType.WORD, reg1=tr.resultReg, immediate = 0), null)
+                        actualResultReg2 =loadStatusAsBooleanResult(Opcode.BSTNE, result)
                     }
                     valueDt.isFloat -> {
-                        actualResultReg2 = codeGen.registers.nextFree()
+                        actualResultReg2 = codeGen.registers.next(IRDataType.BYTE)
                         result += IRCodeChunk(null, null).also {
                             it += IRInstruction(Opcode.SGN, IRDataType.FLOAT, reg1=actualResultReg2, fpReg1 = tr.resultFpReg)
                             it += IRInstruction(Opcode.AND, IRDataType.BYTE, reg1=actualResultReg2, immediate = 1)
@@ -417,11 +454,15 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             }
             BaseDataType.UBYTE -> {
                 when(valueDt.base) {
-                    BaseDataType.BOOL, BaseDataType.BYTE, BaseDataType.UWORD, BaseDataType.WORD -> {
-                        actualResultReg2 = tr.resultReg  // just keep the LSB as it is
+                    BaseDataType.BOOL, BaseDataType.BYTE -> {
+                        actualResultReg2 = tr.resultReg
+                    }
+                    BaseDataType.UWORD, BaseDataType.WORD -> {
+                        actualResultReg2 = codeGen.registers.next(IRDataType.BYTE)
+                        addInstr(result, IRInstruction(Opcode.LSIG, IRDataType.BYTE, reg1=actualResultReg2, reg2=tr.resultReg, immediate = 0), null)
                     }
                     BaseDataType.FLOAT -> {
-                        actualResultReg2 = codeGen.registers.nextFree()
+                        actualResultReg2 = codeGen.registers.next(IRDataType.BYTE)
                         addInstr(result, IRInstruction(Opcode.FTOUB, IRDataType.FLOAT, reg1=actualResultReg2, fpReg1 = tr.resultFpReg), null)
                     }
                     else -> throw AssemblyError("weird cast value type")
@@ -429,11 +470,15 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             }
             BaseDataType.BYTE -> {
                 when(valueDt.base) {
-                    BaseDataType.BOOL, BaseDataType.UBYTE, BaseDataType.UWORD, BaseDataType.WORD -> {
-                        actualResultReg2 = tr.resultReg  // just keep the LSB as it is
+                    BaseDataType.BOOL, BaseDataType.UBYTE -> {
+                        actualResultReg2 = tr.resultReg
+                    }
+                    BaseDataType.UWORD, BaseDataType.WORD -> {
+                        actualResultReg2 = codeGen.registers.next(IRDataType.BYTE)
+                        addInstr(result, IRInstruction(Opcode.LSIG, IRDataType.BYTE, reg1=actualResultReg2, reg2=tr.resultReg, immediate = 0), null)
                     }
                     BaseDataType.FLOAT -> {
-                        actualResultReg2 = codeGen.registers.nextFree()
+                        actualResultReg2 = codeGen.registers.next(IRDataType.BYTE)
                         addInstr(result, IRInstruction(Opcode.FTOSB, IRDataType.FLOAT, reg1=actualResultReg2, fpReg1 = tr.resultFpReg), null)
                     }
                     else -> throw AssemblyError("weird cast value type")
@@ -443,19 +488,19 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                 when(valueDt.base) {
                     BaseDataType.BYTE -> {
                         // byte -> uword:   sign extend
-                        actualResultReg2 = codeGen.registers.nextFree()
+                        actualResultReg2 = codeGen.registers.next(IRDataType.WORD)
                         addInstr(result, IRInstruction(Opcode.EXTS, type = IRDataType.BYTE, reg1 = actualResultReg2, reg2 = tr.resultReg), null)
                     }
                     BaseDataType.BOOL, BaseDataType.UBYTE -> {
                         // ubyte -> uword:   sign extend
-                        actualResultReg2 = codeGen.registers.nextFree()
+                        actualResultReg2 = codeGen.registers.next(IRDataType.WORD)
                         addInstr(result, IRInstruction(Opcode.EXT, type = IRDataType.BYTE, reg1 = actualResultReg2, reg2 = tr.resultReg), null)
                     }
                     BaseDataType.WORD -> {
                         actualResultReg2 = tr.resultReg
                     }
                     BaseDataType.FLOAT -> {
-                        actualResultReg2 = codeGen.registers.nextFree()
+                        actualResultReg2 = codeGen.registers.next(IRDataType.WORD)
                         addInstr(result, IRInstruction(Opcode.FTOUW, IRDataType.FLOAT, reg1=actualResultReg2, fpReg1 = tr.resultFpReg), null)
                     }
                     else -> throw AssemblyError("weird cast value type")
@@ -465,26 +510,26 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                 when(valueDt.base) {
                     BaseDataType.BYTE -> {
                         // byte -> word:   sign extend
-                        actualResultReg2 = codeGen.registers.nextFree()
+                        actualResultReg2 = codeGen.registers.next(IRDataType.WORD)
                         addInstr(result, IRInstruction(Opcode.EXTS, type = IRDataType.BYTE, reg1 = actualResultReg2, reg2=tr.resultReg), null)
                     }
                     BaseDataType.BOOL, BaseDataType.UBYTE -> {
                         // byte -> word:   sign extend
-                        actualResultReg2 = codeGen.registers.nextFree()
+                        actualResultReg2 = codeGen.registers.next(IRDataType.WORD)
                         addInstr(result, IRInstruction(Opcode.EXT, type = IRDataType.BYTE, reg1 = actualResultReg2, reg2=tr.resultReg), null)
                     }
                     BaseDataType.UWORD -> {
                         actualResultReg2 = tr.resultReg
                     }
                     BaseDataType.FLOAT -> {
-                        actualResultReg2 = codeGen.registers.nextFree()
+                        actualResultReg2 = codeGen.registers.next(IRDataType.WORD)
                         addInstr(result, IRInstruction(Opcode.FTOSW, IRDataType.FLOAT, reg1=actualResultReg2, fpReg1 = tr.resultFpReg), null)
                     }
                     else -> throw AssemblyError("weird cast value type")
                 }
             }
             BaseDataType.FLOAT -> {
-                actualResultFpReg2 = codeGen.registers.nextFreeFloat()
+                actualResultFpReg2 = codeGen.registers.next(IRDataType.FLOAT)
                 when(valueDt.base) {
                     BaseDataType.BOOL, BaseDataType.UBYTE -> {
                         addInstr(result, IRInstruction(Opcode.FFROMUB, IRDataType.FLOAT, reg1=tr.resultReg, fpReg1 = actualResultFpReg2), null)
@@ -533,7 +578,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
         }
     }
 
-    fun translate(fcall: PtFunctionCall): ExpressionCodeResult {
+    internal fun translate(fcall: PtFunctionCall): ExpressionCodeResult {
         val callTarget = codeGen.symbolTable.flat.getValue(fcall.name)
 
         if(callTarget.scopedName in listOf("sys.push", "sys.pushw", "sys.pop", "sys.popw", "floats.push", "floats.pop")) {
@@ -589,23 +634,29 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                         result += codeGen.translateNode(assign)
                     }
                 }
-                // return value (always singular for normal Subs)
-                val returnRegSpec = if(fcall.void) null else {
-                    val returnIrType = irType(callTarget.returnType!!)
-                    if(returnIrType==IRDataType.FLOAT)
-                        FunctionCallArgs.RegSpec(returnIrType, codeGen.registers.nextFreeFloat(), null)
-                    else
-                        FunctionCallArgs.RegSpec(returnIrType, codeGen.registers.nextFree(), null)
+                // return value(s)
+                val returnRegSpecs = if(fcall.void) emptyList() else {
+                    callTarget.returns.map {
+                        val returnIrType = irType(it)
+                        FunctionCallArgs.RegSpec(returnIrType, codeGen.registers.next(returnIrType), null)
+                    }
                 }
                 // create the call
                 addInstr(result, IRInstruction(Opcode.CALL, labelSymbol = fcall.name,
-                    fcallArgs = FunctionCallArgs(argRegisters, if(returnRegSpec==null) emptyList() else listOf(returnRegSpec))), null)
+                    fcallArgs = FunctionCallArgs(argRegisters, returnRegSpecs)), null)
                 return if(fcall.void)
+                    ExpressionCodeResult(result, IRDataType.BYTE, -1, -1)       // TODO datatype void?
+                else if(returnRegSpecs.size==1) {
+                    val returnRegSpec = returnRegSpecs.single()
+                    if (fcall.type.isFloat)
+                        ExpressionCodeResult(result, returnRegSpec.dt, -1, returnRegSpec.registerNum)
+                    else
+                        ExpressionCodeResult(result, returnRegSpec.dt, returnRegSpec.registerNum, -1)
+                } else {
+                    // multi-value returns are passed throug cx16.R15 down to R0 (allows unencumbered use of many Rx registers if you don't return that many values)
+                    // so the actual result of the expression here is 'void' (doesn't use IR virtual registers at all)
                     ExpressionCodeResult(result, IRDataType.BYTE, -1, -1)
-                else if(fcall.type.isFloat)
-                    ExpressionCodeResult(result, returnRegSpec!!.dt, -1, returnRegSpec.registerNum)
-                else
-                    ExpressionCodeResult(result, returnRegSpec!!.dt, returnRegSpec.registerNum, -1)
+                }
             }
             is StExtSub -> {
                 val result = mutableListOf<IRCodeChunkBase>()
@@ -627,7 +678,8 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                         RegisterOrPair.AX -> addInstr(result, IRInstruction(Opcode.STOREHAX, IRDataType.WORD, reg1=tr.resultReg), null)
                         RegisterOrPair.AY -> addInstr(result, IRInstruction(Opcode.STOREHAY, IRDataType.WORD, reg1=tr.resultReg), null)
                         RegisterOrPair.XY -> addInstr(result, IRInstruction(Opcode.STOREHXY, IRDataType.WORD, reg1=tr.resultReg), null)
-                        RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> TODO("floating point register parameters not supported")
+                        RegisterOrPair.FAC1 -> addInstr(result, IRInstruction(Opcode.STOREHFACZERO, IRDataType.FLOAT, fpReg1 = tr.resultFpReg), null)
+                        RegisterOrPair.FAC2 -> addInstr(result, IRInstruction(Opcode.STOREHFACONE, IRDataType.FLOAT, fpReg1 = tr.resultFpReg), null)
                         in Cx16VirtualRegisters -> {
                             addInstr(result, IRInstruction(Opcode.STOREM, paramDt, reg1=tr.resultReg, labelSymbol = "cx16.${parameter.register.registerOrPair.toString().lowercase()}"), null)
                         }
@@ -650,12 +702,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                     else {
                         val returns = callTarget.returns[0]
                         val returnIrType = irType(returns.type)
-                        if (returnIrType == IRDataType.FLOAT)
-                            FunctionCallArgs.RegSpec(returnIrType, codeGen.registers.nextFreeFloat(), returns.register)
-                        else {
-                            val returnRegister = codeGen.registers.nextFree()
-                            FunctionCallArgs.RegSpec(returnIrType, returnRegister, returns.register)
-                        }
+                        FunctionCallArgs.RegSpec(returnIrType, codeGen.registers.next(returnIrType), returns.register)
                     }
                 }
                 // create the call
@@ -685,10 +732,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                         // assign status flag bit to the return value register
                         finalReturnRegister = returnRegSpec.registerNum
                         if(finalReturnRegister<0)
-                            finalReturnRegister = codeGen.registers.nextFree()
+                            finalReturnRegister = codeGen.registers.next(returnRegSpec.dt)
                         when(statusFlagResult) {
                             Statusflag.Pc -> {
-                                addInstr(result, IRInstruction(Opcode.SCS, returnRegSpec.dt, reg1=finalReturnRegister), null)
+                                result += IRCodeChunk(null, null).also {
+                                    it += IRInstruction(Opcode.LOAD, returnRegSpec.dt, reg1 = finalReturnRegister, immediate = 0)
+                                    it += IRInstruction(Opcode.ROXL, returnRegSpec.dt, reg1 = finalReturnRegister)
+                                }
                             }
                             else -> {
                                 val branchOpcode = when(statusFlagResult) {
@@ -724,6 +774,31 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
         }
     }
 
+    internal fun checkIfConditionCanUseBIT(condition: PtBinaryExpression): Triple<Boolean, PtIdentifier, Int>? {
+        // test for occurrence of:  x & 64 != 0    (or 128) , this can be performed with a BIT instruction
+        if(condition.operator == "==" || condition.operator == "!=") {
+            if (condition.right.asConstInteger() == 0) {
+                val and = condition.left as? PtBinaryExpression
+                if (and != null && and.operator == "&" && and.type.isUnsignedByte) {
+                    val bitmask = and.right.asConstInteger()
+                    if(bitmask==128 || bitmask==64) {
+                        val variable = and.left as? PtIdentifier
+                        if (variable != null && variable.type.isByte) {
+                            return Triple(condition.operator=="!=", variable, bitmask)
+                        }
+                        val typecast = and.left as? PtTypeCast
+                        if (typecast != null && typecast.type.isUnsignedByte) {
+                            val castedVariable = typecast.value as? PtIdentifier
+                            if(castedVariable!=null && castedVariable.type.isByte)
+                                return Triple(condition.operator=="!=", castedVariable, bitmask)
+                        }
+                    }
+                }
+            }
+        }
+        return null
+    }
+
     private fun translateStackFunctions(fcall: PtFunctionCall, callTarget: StNode): ExpressionCodeResult {
         val chunk = mutableListOf<IRCodeChunkBase>()
         when(callTarget.scopedName) {
@@ -743,13 +818,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             }
             "sys.pop" -> {
                 // pop byte
-                val popReg = codeGen.registers.nextFree()
+                val popReg = codeGen.registers.next(IRDataType.BYTE)
                 addInstr(chunk, IRInstruction(Opcode.POP, IRDataType.BYTE, reg1=popReg), null)
                 return ExpressionCodeResult(chunk, IRDataType.BYTE, popReg, -1)
             }
             "sys.popw" -> {
                 // pop word
-                val popReg = codeGen.registers.nextFree()
+                val popReg = codeGen.registers.next(IRDataType.WORD)
                 addInstr(chunk, IRInstruction(Opcode.POP, IRDataType.WORD, reg1=popReg), null)
                 return ExpressionCodeResult(chunk, IRDataType.WORD, popReg, -1)
             }
@@ -762,7 +837,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             }
             "floats.pop" -> {
                 // pop float
-                val popReg = codeGen.registers.nextFreeFloat()
+                val popReg = codeGen.registers.next(IRDataType.FLOAT)
                 addInstr(chunk, IRInstruction(Opcode.POP, IRDataType.FLOAT, fpReg1 = popReg), null)
                 return ExpressionCodeResult(chunk, IRDataType.FLOAT, -1, resultFpReg = popReg)
             }
@@ -778,7 +853,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
     ): ExpressionCodeResult {
         // return multiple values
         val returnRegisters = callTarget.returns.map {
-            val regnum = if(it.type.isFloat) codeGen.registers.nextFreeFloat() else codeGen.registers.nextFree()
+            val regnum = codeGen.registers.next(irType(it.type))
             FunctionCallArgs.RegSpec(irType(it.type), regnum, it.register)
         }
         // create the call
@@ -809,23 +884,36 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
         greaterEquals: Boolean
     ): ExpressionCodeResult {
         val result = mutableListOf<IRCodeChunkBase>()
-        val cmpResultReg = codeGen.registers.nextFree()
         if(vmDt==IRDataType.FLOAT) {
             val leftTr = translateExpression(binExpr.left)
             addToResult(result, leftTr, -1, leftTr.resultFpReg)
             val rightTr = translateExpression(binExpr.right)
             addToResult(result, rightTr, -1, rightTr.resultFpReg)
-            val resultRegister = codeGen.registers.nextFree()
+            val resultRegister = codeGen.registers.next(IRDataType.BYTE)
             addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=resultRegister, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null)
-            val zeroRegister = codeGen.registers.nextFree()
-            addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=zeroRegister, immediate = 0), null)
-            val ins = if (signed) {
-                if (greaterEquals) Opcode.SGES else Opcode.SGTS
+            addInstr(result, IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=resultRegister, immediate = 0), null)
+            val other = codeGen.createLabelName()
+            val after = codeGen.createLabelName()
+            val resultReg = codeGen.registers.next(IRDataType.BYTE)
+            // TODO can this be done more efficiently? also see operatorLessThan
+            if(greaterEquals) {
+                result += IRCodeChunk(null, null).also {
+                    it += IRInstruction(Opcode.BSTPOS, labelSymbol = other)
+                    it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = resultReg, immediate = 0)
+                    it += IRInstruction(Opcode.JUMP, labelSymbol = after)
+                }
+                addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultReg, immediate = 1), other)
             } else {
-                if (greaterEquals) Opcode.SGE else Opcode.SGT
+                result += IRCodeChunk(null, null).also {
+                    it += IRInstruction(Opcode.BSTNEG, labelSymbol = other)
+                    it += IRInstruction(Opcode.BSTEQ, labelSymbol = other)
+                    it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = resultReg, immediate = 1)
+                    it += IRInstruction(Opcode.JUMP, labelSymbol = after)
+                }
+                addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultReg, immediate = 0), other)
             }
-            addInstr(result, IRInstruction(ins, IRDataType.BYTE, reg1=cmpResultReg, reg2 = resultRegister, reg3 = zeroRegister), null)
-            return ExpressionCodeResult(result, IRDataType.BYTE, cmpResultReg, -1)
+            result += IRCodeChunk(after, null)
+            return ExpressionCodeResult(result, IRDataType.BYTE, resultReg, -1)
         } else {
             if(binExpr.left.type.isString || binExpr.right.type.isString) {
                 throw AssemblyError("str compares should have been replaced with builtin function call to do the compare")
@@ -834,13 +922,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                 addToResult(result, leftTr, leftTr.resultReg, -1)
                 val rightTr = translateExpression(binExpr.right)
                 addToResult(result, rightTr, rightTr.resultReg, -1)
-                val ins = if (signed) {
-                    if (greaterEquals) Opcode.SGES else Opcode.SGTS
+                val branch = if (signed) {
+                    if (greaterEquals) Opcode.BGESR else Opcode.BGTSR
                 } else {
-                    if (greaterEquals) Opcode.SGE else Opcode.SGT
+                    if (greaterEquals) Opcode.BGER else Opcode.BGTR
                 }
-                addInstr(result, IRInstruction(ins, vmDt, reg1=cmpResultReg, reg2 = leftTr.resultReg, reg3 = rightTr.resultReg), null)
-                return ExpressionCodeResult(result, IRDataType.BYTE, cmpResultReg, -1)
+                val resultReg = compareRegisterAsBooleanResult(branch, leftTr.dt, leftTr.resultReg, rightTr.resultReg, result)
+                return ExpressionCodeResult(result, IRDataType.BYTE, resultReg, -1)
             }
         }
     }
@@ -852,23 +940,36 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
         lessEquals: Boolean
     ): ExpressionCodeResult {
         val result = mutableListOf<IRCodeChunkBase>()
-        val cmpResultRegister = codeGen.registers.nextFree()
         if(vmDt==IRDataType.FLOAT) {
             val leftTr = translateExpression(binExpr.left)
             addToResult(result, leftTr, -1, leftTr.resultFpReg)
             val rightTr = translateExpression(binExpr.right)
             addToResult(result, rightTr, -1, rightTr.resultFpReg)
-            val resultRegister = codeGen.registers.nextFree()
+            val resultRegister = codeGen.registers.next(IRDataType.BYTE)
             addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=resultRegister, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null)
-            val zeroRegister = codeGen.registers.nextFree()
-            addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=zeroRegister, immediate = 0), null)
-            val ins = if (signed) {
-                if (lessEquals) Opcode.SLES else Opcode.SLTS
+            addInstr(result, IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=resultRegister, immediate = 0), null)
+            val other = codeGen.createLabelName()
+            val after = codeGen.createLabelName()
+            val resultReg = codeGen.registers.next(IRDataType.BYTE)
+            // TODO can this be done more efficiently? also see operatorGreaterThan
+            if(lessEquals) {
+                result += IRCodeChunk(null, null).also {
+                    it += IRInstruction(Opcode.BSTNEG, labelSymbol = other)
+                    it += IRInstruction(Opcode.BSTEQ, labelSymbol = other)
+                    it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = resultReg, immediate = 0)
+                    it += IRInstruction(Opcode.JUMP, labelSymbol = after)
+                }
+                addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultReg, immediate = 1), other)
             } else {
-                if (lessEquals) Opcode.SLE else Opcode.SLT
+                result += IRCodeChunk(null, null).also {
+                    it += IRInstruction(Opcode.BSTNEG, labelSymbol = other)
+                    it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = resultReg, immediate = 0)
+                    it += IRInstruction(Opcode.JUMP, labelSymbol = after)
+                }
+                addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultReg, immediate = 1), other)
             }
-            addInstr(result, IRInstruction(ins, IRDataType.BYTE, reg1=cmpResultRegister, reg2 = resultRegister, reg3 = zeroRegister), null)
-            return ExpressionCodeResult(result, IRDataType.BYTE, cmpResultRegister, -1)
+            result += IRCodeChunk(after, null)
+            return ExpressionCodeResult(result, IRDataType.BYTE, resultReg, -1)
         } else {
             if(binExpr.left.type.isString || binExpr.right.type.isString) {
                 throw AssemblyError("str compares should have been replaced with builtin function call to do the compare")
@@ -877,13 +978,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
                 addToResult(result, leftTr, leftTr.resultReg, -1)
                 val rightTr = translateExpression(binExpr.right)
                 addToResult(result, rightTr, rightTr.resultReg, -1)
-                val ins = if (signed) {
-                    if (lessEquals) Opcode.SLES else Opcode.SLTS
+                val branch = if (signed) {
+                    if (lessEquals) Opcode.BGESR else Opcode.BGTSR
                 } else {
-                    if (lessEquals) Opcode.SLE else Opcode.SLT
+                    if (lessEquals) Opcode.BGER else Opcode.BGTR
                 }
-                addInstr(result, IRInstruction(ins, vmDt, reg1=cmpResultRegister, reg2 = leftTr.resultReg, reg3 = rightTr.resultReg), null)
-                return ExpressionCodeResult(result, IRDataType.BYTE, cmpResultRegister, -1)
+                val resultReg = compareRegisterAsBooleanResult(branch, leftTr.dt, rightTr.resultReg, leftTr.resultReg, result)
+                return ExpressionCodeResult(result, IRDataType.BYTE, resultReg, -1)
             }
         }
     }
@@ -895,18 +996,18 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             addToResult(result, leftTr, -1, leftTr.resultFpReg)
             val rightTr = translateExpression(binExpr.right)
             addToResult(result, rightTr, -1, rightTr.resultFpReg)
-            val resultRegister = codeGen.registers.nextFree()
-            val valueReg = codeGen.registers.nextFree()
+            val resultRegister = codeGen.registers.next(IRDataType.BYTE)
+            val valueReg = codeGen.registers.next(IRDataType.BYTE)
             val label = codeGen.createLabelName()
             result += IRCodeChunk(null, null).also {
-                it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, immediate = 1)
+                it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, immediate = 0)
                 it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=valueReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg)
                 it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=valueReg, immediate = 0)
                 it += if (notEquals)
-                    IRInstruction(Opcode.BSTNE, labelSymbol = label)
-                else
                     IRInstruction(Opcode.BSTEQ, labelSymbol = label)
-                it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, immediate = 0)
+                else
+                    IRInstruction(Opcode.BSTNE, labelSymbol = label)
+                it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, immediate = 1)
             }
             result += IRCodeChunk(label, null)
             return ExpressionCodeResult(result, IRDataType.BYTE, resultRegister, -1)
@@ -914,27 +1015,56 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             if(binExpr.left.type.isString || binExpr.right.type.isString) {
                 throw AssemblyError("str compares should have been replaced with builtin function call to do the compare")
             } else {
-                return if(binExpr.right.asConstValue()==0.0) {
-                    val tr = translateExpression(binExpr.left)
-                    addToResult(result, tr, tr.resultReg, -1)
-                    val opcode = if (notEquals) Opcode.SNZ else Opcode.SZ
-                    val resultReg = codeGen.registers.nextFree()
-                    addInstr(result, IRInstruction(opcode, vmDt, reg1 = resultReg, reg2 = tr.resultReg), null)
+                val rightConst = binExpr.right.asConstValue()
+                return if(rightConst!=null) {
+                    val leftTr = translateExpression(binExpr.left)
+                    addToResult(result, leftTr, leftTr.resultReg, -1)
+                    addInstr(result, IRInstruction(Opcode.CMPI, leftTr.dt, reg1 = leftTr.resultReg, immediate = rightConst.toInt()), null)
+                    val resultReg = loadStatusAsBooleanResult(if(notEquals) Opcode.BSTNE else Opcode.BSTEQ, result)
                     ExpressionCodeResult(result, IRDataType.BYTE, resultReg, -1)
                 } else {
                     val leftTr = translateExpression(binExpr.left)
                     addToResult(result, leftTr, leftTr.resultReg, -1)
                     val rightTr = translateExpression(binExpr.right)
                     addToResult(result, rightTr, rightTr.resultReg, -1)
-                    val opcode = if (notEquals) Opcode.SNE else Opcode.SEQ
-                    val resultReg = codeGen.registers.nextFree()
-                    addInstr(result, IRInstruction(opcode, vmDt, reg1 = resultReg, reg2 = leftTr.resultReg, reg3 = rightTr.resultReg), null)
+                    addInstr(result, IRInstruction(Opcode.CMP, leftTr.dt, reg1=leftTr.resultReg, reg2=rightTr.resultReg), null)
+                    val resultReg = loadStatusAsBooleanResult(if(notEquals) Opcode.BSTNE else Opcode.BSTEQ, result)
                     ExpressionCodeResult(result, IRDataType.BYTE, resultReg, -1)
                 }
             }
         }
     }
 
+    private fun loadStatusAsBooleanResult(branchForTrue: Opcode, result: MutableList<IRCodeChunkBase>): Int {
+        // TODO this used to be a single instruction like SCC, SCS, SZ etc but those were problematic
+        val other = codeGen.createLabelName()
+        val after = codeGen.createLabelName()
+        val resultReg = codeGen.registers.next(IRDataType.BYTE)
+        result += IRCodeChunk(null, null).also {
+            it += IRInstruction(branchForTrue, labelSymbol = other)
+            it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = resultReg, immediate = 0)
+            it += IRInstruction(Opcode.JUMP, labelSymbol = after)
+        }
+        addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultReg, immediate = 1), other)
+        result += IRCodeChunk(after, null)
+        return resultReg
+    }
+
+    private fun compareRegisterAsBooleanResult(branchForTrue: Opcode, dt: IRDataType, reg1: Int, reg2: Int, result: MutableList<IRCodeChunkBase>): Int {
+        // TODO this used to be a single instruction like SCC, SCS, SZ etc but those were problematic
+        val other = codeGen.createLabelName()
+        val after = codeGen.createLabelName()
+        val resultReg = codeGen.registers.next(IRDataType.BYTE)
+        result += IRCodeChunk(null, null).also {
+            it += IRInstruction(branchForTrue, dt, reg1=reg1, reg2=reg2, labelSymbol = other)
+            it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = resultReg, immediate = 0)
+            it += IRInstruction(Opcode.JUMP, labelSymbol = after)
+        }
+        addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultReg, immediate = 1), other)
+        result += IRCodeChunk(after, null)
+        return resultReg
+    }
+
     private fun operatorShiftRight(binExpr: PtBinaryExpression, vmDt: IRDataType, signed: Boolean): ExpressionCodeResult {
         val result = mutableListOf<IRCodeChunkBase>()
         return if(codeGen.isOne(binExpr.right)) {
@@ -947,6 +1077,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             val leftTr = translateExpression(binExpr.left)
             addToResult(result, leftTr, leftTr.resultReg, -1)
             val rightTr = translateExpression(binExpr.right)
+            require(rightTr.dt== IRDataType.BYTE) { "can only shift by 0-255" }
             addToResult(result, rightTr, rightTr.resultReg, -1)
             val opc = if (signed) Opcode.ASRN else Opcode.LSRN
             addInstr(result, IRInstruction(opc, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg), null)
@@ -965,6 +1096,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             val leftTr = translateExpression(binExpr.left)
             addToResult(result, leftTr, leftTr.resultReg, -1)
             val rightTr = translateExpression(binExpr.right)
+            require(rightTr.dt== IRDataType.BYTE) { "can only shift by 0-255" }
             addToResult(result, rightTr, rightTr.resultReg, -1)
             addInstr(result, IRInstruction(Opcode.LSLN, vmDt, reg1=leftTr.resultReg, rightTr.resultReg), null)
             ExpressionCodeResult(result, vmDt, leftTr.resultReg, -1)

codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt

@@ -231,7 +231,11 @@ class IRCodeGen(
                 chunk += IRInstruction(Opcode.BREAKPOINT)
                 listOf(chunk)
             }
-            is PtAlign -> TODO("ir support for inline %align")
+            is PtAlign -> {
+                val chunk = IRCodeChunk(null, null)
+                chunk += IRInstruction(Opcode.ALIGN, immediate = node.align.toInt())
+                listOf(chunk)
+            }
             is PtConditionalBranch -> translate(node)
             is PtInlineAssembly -> listOf(IRInlineAsmChunk(null, node.assembly, node.isIR, null))
             is PtIncludeBinary -> listOf(IRInlineBinaryChunk(null, readBinaryData(node), null))
@@ -280,31 +284,23 @@ class IRCodeGen(
             val address = goto.target.asConstInteger()
             val label = (goto.target as? PtIdentifier)?.name
             if(address!=null) {
-                val branchIns = when(branch.condition) {
-                    BranchCondition.CS -> IRInstruction(Opcode.BSTCS, address = address)
-                    BranchCondition.CC -> IRInstruction(Opcode.BSTCC, address = address)
-                    BranchCondition.EQ, BranchCondition.Z -> IRInstruction(Opcode.BSTEQ, address = address)
-                    BranchCondition.NE, BranchCondition.NZ -> IRInstruction(Opcode.BSTNE, address = address)
-                    BranchCondition.MI, BranchCondition.NEG -> IRInstruction(Opcode.BSTNEG, address = address)
-                    BranchCondition.PL, BranchCondition.POS -> IRInstruction(Opcode.BSTPOS, address = address)
-                    BranchCondition.VC -> IRInstruction(Opcode.BSTVC, address = address)
-                    BranchCondition.VS -> IRInstruction(Opcode.BSTVS, address = address)
-                }
+                val branchIns = IRBranchInstr(branch.condition, address=address)
                 addInstr(result, branchIns, null)
             } else if(label!=null && !isIndirectJump(goto)) {
-                val branchIns = when(branch.condition) {
-                    BranchCondition.CS -> IRInstruction(Opcode.BSTCS, labelSymbol = label)
-                    BranchCondition.CC -> IRInstruction(Opcode.BSTCC, labelSymbol = label)
-                    BranchCondition.EQ, BranchCondition.Z -> IRInstruction(Opcode.BSTEQ, labelSymbol = label)
-                    BranchCondition.NE, BranchCondition.NZ -> IRInstruction(Opcode.BSTNE, labelSymbol = label)
-                    BranchCondition.MI, BranchCondition.NEG -> IRInstruction(Opcode.BSTNEG, labelSymbol = label)
-                    BranchCondition.PL, BranchCondition.POS -> IRInstruction(Opcode.BSTPOS, labelSymbol = label)
-                    BranchCondition.VC -> IRInstruction(Opcode.BSTVC, labelSymbol = label)
-                    BranchCondition.VS -> IRInstruction(Opcode.BSTVS, labelSymbol = label)
-                }
+                val branchIns = IRBranchInstr(branch.condition, label = label)
                 addInstr(result, branchIns, null)
             } else {
-                TODO("JUMP to expression address ${goto.target}")  // keep in mind the branch insruction that may need to precede this!
+                val skipJumpLabel = createLabelName()
+                // note that the branch opcode used is the opposite as the branch condition, because it needs to skip the indirect jump
+                val branchIns = IRInvertedBranchInstr(branch.condition, label = skipJumpLabel)
+                // evaluate jump address expression into a register and jump indirectly to it
+                addInstr(result, branchIns, null)
+                val tr = expressionEval.translateExpression(goto.target)
+                result += tr.chunks
+                result += IRCodeChunk(null, null).also {
+                    it += IRInstruction(Opcode.JUMPI, reg1=tr.resultReg)
+                }
+                result += IRCodeChunk(skipJumpLabel, null)
             }
             if(branch.falseScope.children.isNotEmpty())
                 result += translateNode(branch.falseScope)
@@ -313,16 +309,7 @@ class IRCodeGen(
 
         val elseLabel = createLabelName()
         // note that the branch opcode used is the opposite as the branch condition, because the generated code jumps to the 'else' part
-        val branchIns = when(branch.condition) {
-            BranchCondition.CS -> IRInstruction(Opcode.BSTCC, labelSymbol = elseLabel)
-            BranchCondition.CC -> IRInstruction(Opcode.BSTCS, labelSymbol = elseLabel)
-            BranchCondition.EQ, BranchCondition.Z -> IRInstruction(Opcode.BSTNE, labelSymbol = elseLabel)
-            BranchCondition.NE, BranchCondition.NZ -> IRInstruction(Opcode.BSTEQ, labelSymbol = elseLabel)
-            BranchCondition.MI, BranchCondition.NEG -> IRInstruction(Opcode.BSTPOS, labelSymbol = elseLabel)
-            BranchCondition.PL, BranchCondition.POS -> IRInstruction(Opcode.BSTNEG, labelSymbol = elseLabel)
-            BranchCondition.VC -> IRInstruction(Opcode.BSTVS, labelSymbol = elseLabel)
-            BranchCondition.VS -> IRInstruction(Opcode.BSTVC, labelSymbol = elseLabel)
-        }
+        val branchIns = IRInvertedBranchInstr(branch.condition, label = elseLabel)
         addInstr(result, branchIns, null)
         result += translateNode(branch.trueScope)
         if(branch.falseScope.children.isNotEmpty()) {
@@ -337,6 +324,60 @@ class IRCodeGen(
         return result
     }
 
+    private fun IRBranchInstr(condition: BranchCondition, label: String?=null, address: Int?=null): IRInstruction {
+        if(label!=null)
+            return when(condition) {
+                BranchCondition.CS -> IRInstruction(Opcode.BSTCS, labelSymbol = label)
+                BranchCondition.CC -> IRInstruction(Opcode.BSTCC, labelSymbol = label)
+                BranchCondition.EQ, BranchCondition.Z -> IRInstruction(Opcode.BSTEQ, labelSymbol = label)
+                BranchCondition.NE, BranchCondition.NZ -> IRInstruction(Opcode.BSTNE, labelSymbol = label)
+                BranchCondition.MI, BranchCondition.NEG -> IRInstruction(Opcode.BSTNEG, labelSymbol = label)
+                BranchCondition.PL, BranchCondition.POS -> IRInstruction(Opcode.BSTPOS, labelSymbol = label)
+                BranchCondition.VC -> IRInstruction(Opcode.BSTVC, labelSymbol = label)
+                BranchCondition.VS -> IRInstruction(Opcode.BSTVS, labelSymbol = label)
+            }
+        else if(address!=null) {
+            return when(condition) {
+                BranchCondition.CS -> IRInstruction(Opcode.BSTCS, address = address)
+                BranchCondition.CC -> IRInstruction(Opcode.BSTCC, address = address)
+                BranchCondition.EQ, BranchCondition.Z -> IRInstruction(Opcode.BSTEQ, address = address)
+                BranchCondition.NE, BranchCondition.NZ -> IRInstruction(Opcode.BSTNE, address = address)
+                BranchCondition.MI, BranchCondition.NEG -> IRInstruction(Opcode.BSTNEG, address = address)
+                BranchCondition.PL, BranchCondition.POS -> IRInstruction(Opcode.BSTPOS, address = address)
+                BranchCondition.VC -> IRInstruction(Opcode.BSTVC, address = address)
+                BranchCondition.VS -> IRInstruction(Opcode.BSTVS, address = address)
+            }
+        }
+        else throw AssemblyError("need label or address for branch")
+    }
+
+    private fun IRInvertedBranchInstr(condition: BranchCondition, label: String?=null, address: Int?=null): IRInstruction {
+        if(label!=null)
+            return when(condition) {
+                BranchCondition.CS -> IRInstruction(Opcode.BSTCC, labelSymbol = label)
+                BranchCondition.CC -> IRInstruction(Opcode.BSTCS, labelSymbol = label)
+                BranchCondition.EQ, BranchCondition.Z -> IRInstruction(Opcode.BSTNE, labelSymbol = label)
+                BranchCondition.NE, BranchCondition.NZ -> IRInstruction(Opcode.BSTEQ, labelSymbol = label)
+                BranchCondition.MI, BranchCondition.NEG -> IRInstruction(Opcode.BSTPOS, labelSymbol = label)
+                BranchCondition.PL, BranchCondition.POS -> IRInstruction(Opcode.BSTNEG, labelSymbol = label)
+                BranchCondition.VC -> IRInstruction(Opcode.BSTVS, labelSymbol = label)
+                BranchCondition.VS -> IRInstruction(Opcode.BSTVC, labelSymbol = label)
+            }
+        else if(address!=null) {
+            return when(condition) {
+                BranchCondition.CS -> IRInstruction(Opcode.BSTCC, address = address)
+                BranchCondition.CC -> IRInstruction(Opcode.BSTCS, address = address)
+                BranchCondition.EQ, BranchCondition.Z -> IRInstruction(Opcode.BSTNE, address = address)
+                BranchCondition.NE, BranchCondition.NZ -> IRInstruction(Opcode.BSTEQ, address = address)
+                BranchCondition.MI, BranchCondition.NEG -> IRInstruction(Opcode.BSTPOS, address = address)
+                BranchCondition.PL, BranchCondition.POS -> IRInstruction(Opcode.BSTNEG, address = address)
+                BranchCondition.VC -> IRInstruction(Opcode.BSTVS, address = address)
+                BranchCondition.VS -> IRInstruction(Opcode.BSTVC, address = address)
+            }
+        }
+        else throw AssemblyError("need label or address for branch")
+    }
+
     private fun labelFirstChunk(chunks: IRCodeChunks, label: String): IRCodeChunks {
         if(chunks.isEmpty()) {
             return listOf(
@@ -430,8 +471,8 @@ class IRCodeGen(
                 require(forLoop.variable.name == loopvar.scopedName)
                 val iterableLength = symbolTable.getLength(iterable.name)
                 val loopvarSymbol = forLoop.variable.name
-                val indexReg = registers.nextFree()
-                val tmpReg = registers.nextFree()
+                val indexReg = registers.next(IRDataType.BYTE)
+                val tmpReg = registers.next(IRDataType.BYTE)
                 val loopLabel = createLabelName()
                 val endLabel = createLabelName()
                 when {
@@ -457,9 +498,9 @@ class IRCodeGen(
                             throw AssemblyError("weird dt")
                         addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=indexReg, immediate = 0), null)
                         result += IRCodeChunk(loopLabel, null).also {
-                            val tmpRegLsb = registers.nextFree()
-                            val tmpRegMsb = registers.nextFree()
-                            val concatReg = registers.nextFree()
+                            val tmpRegLsb = registers.next(IRDataType.BYTE)
+                            val tmpRegMsb = registers.next(IRDataType.BYTE)
+                            val concatReg = registers.next(IRDataType.WORD)
                             it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1=tmpRegMsb, reg2=indexReg, labelSymbol=iterable.name+"_msb")
                             it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1=tmpRegLsb, reg2=indexReg, labelSymbol=iterable.name+"_lsb")
                             it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1=concatReg, reg2=tmpRegMsb, reg3=tmpRegLsb)
@@ -595,7 +636,6 @@ class IRCodeGen(
         val loopLabel = createLabelName()
         require(forLoop.variable.name == loopvar.scopedName)
         val loopvarSymbol = forLoop.variable.name
-        val indexReg = registers.nextFree()
         val loopvarDt = when(loopvar) {
             is StMemVar -> loopvar.dt
             is StStaticVariable -> loopvar.dt
@@ -611,6 +651,7 @@ class IRCodeGen(
         val rangeEndExclusiveWrapped = if(loopvarDtIr==IRDataType.BYTE) rangeEndExclusiveUntyped and 255 else rangeEndExclusiveUntyped and 65535
         val result = mutableListOf<IRCodeChunkBase>()
         val chunk = IRCodeChunk(null, null)
+        val indexReg = registers.next(loopvarDtIr)
         chunk += IRInstruction(Opcode.LOAD, loopvarDtIr, reg1=indexReg, immediate = iterable.first)
         chunk += IRInstruction(Opcode.STOREM, loopvarDtIr, reg1=indexReg, labelSymbol=loopvarSymbol)
         result += chunk
@@ -703,7 +744,7 @@ class IRCodeGen(
                 }
             }
             else -> {
-                val valueReg = registers.nextFree()
+                val valueReg = registers.next(dt)
                 if(value>0) {
                     code += IRInstruction(Opcode.LOAD, dt, reg1=valueReg, immediate = value)
                     code += if(knownAddress!=null)
@@ -745,7 +786,7 @@ class IRCodeGen(
             else
                 IRInstruction(Opcode.STOREZM, IRDataType.FLOAT, labelSymbol = symbol)
         } else {
-            val factorReg = registers.nextFreeFloat()
+            val factorReg = registers.next(IRDataType.FLOAT)
             code += IRInstruction(Opcode.LOAD, IRDataType.FLOAT, fpReg1=factorReg, immediateFp = factor)
             code += if(knownAddress!=null)
                 IRInstruction(Opcode.MULM, IRDataType.FLOAT, fpReg1 = factorReg, address = knownAddress)
@@ -766,8 +807,8 @@ class IRCodeGen(
         }
         else if(pow2>=1) {
             // just shift multiple bits
-            val pow2reg = registers.nextFree()
-            code += IRInstruction(Opcode.LOAD, dt, reg1=pow2reg, immediate = pow2)
+            val pow2reg = registers.next(IRDataType.BYTE)
+            code += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=pow2reg, immediate = pow2)
             code += IRInstruction(Opcode.LSLN, dt, reg1=reg, reg2=pow2reg)
         } else {
             code += if (factor == 0) {
@@ -793,7 +834,7 @@ class IRCodeGen(
         }
         else if(pow2>=1) {
             // just shift multiple bits
-            val pow2reg = registers.nextFree()
+            val pow2reg = registers.next(dt)
             code += IRInstruction(Opcode.LOAD, dt, reg1=pow2reg, immediate = pow2)
             code += if(knownAddress!=null)
                 IRInstruction(Opcode.LSLNM, dt, reg1=pow2reg, address = knownAddress)
@@ -807,7 +848,7 @@ class IRCodeGen(
                     IRInstruction(Opcode.STOREZM, dt, labelSymbol = symbol)
             }
             else {
-                val factorReg = registers.nextFree()
+                val factorReg = registers.next(dt)
                 code += IRInstruction(Opcode.LOAD, dt, reg1=factorReg, immediate = factor)
                 code += if(knownAddress!=null)
                     IRInstruction(Opcode.MULM, dt, reg1=factorReg, address = knownAddress)
@@ -835,14 +876,14 @@ class IRCodeGen(
         if(factor==1.0)
             return code
         if(factor==0.0) {
-            val maxvalueReg = registers.nextFreeFloat()
+            val maxvalueReg = registers.next(IRDataType.FLOAT)
             code += IRInstruction(Opcode.LOAD, IRDataType.FLOAT, fpReg1 = maxvalueReg, immediateFp = Double.MAX_VALUE)
             code += if(knownAddress!=null)
                 IRInstruction(Opcode.STOREM, IRDataType.FLOAT, fpReg1 = maxvalueReg, address = knownAddress)
             else
                 IRInstruction(Opcode.STOREM, IRDataType.FLOAT, fpReg1 = maxvalueReg, labelSymbol = symbol)
         } else {
-            val factorReg = registers.nextFreeFloat()
+            val factorReg = registers.next(IRDataType.FLOAT)
             code += IRInstruction(Opcode.LOAD, IRDataType.FLOAT, fpReg1=factorReg, immediateFp = factor)
             code += if(knownAddress!=null)
                 IRInstruction(Opcode.DIVSM, IRDataType.FLOAT, fpReg1 = factorReg, address = knownAddress)
@@ -864,8 +905,8 @@ class IRCodeGen(
                     code += IRInstruction(Opcode.ASR, dt, reg1=reg)
                 } else {
                     // just shift multiple bits (signed)
-                    val pow2reg = registers.nextFree()
-                    code += IRInstruction(Opcode.LOAD, dt, reg1=pow2reg, immediate = pow2)
+                    val pow2reg = registers.next(IRDataType.BYTE)
+                    code += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=pow2reg, immediate = pow2)
                     code += IRInstruction(Opcode.ASRN, dt, reg1=reg, reg2=pow2reg)
                 }
             } else {
@@ -874,8 +915,8 @@ class IRCodeGen(
                     code += IRInstruction(Opcode.LSR, dt, reg1=reg)
                 } else {
                     // just shift multiple bits (unsigned)
-                    val pow2reg = registers.nextFree()
-                    code += IRInstruction(Opcode.LOAD, dt, reg1 = pow2reg, immediate = pow2)
+                    val pow2reg = registers.next(IRDataType.BYTE)
+                    code += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = pow2reg, immediate = pow2)
                     code += IRInstruction(Opcode.LSRN, dt, reg1 = reg, reg2 = pow2reg)
                 }
             }
@@ -910,7 +951,7 @@ class IRCodeGen(
                         IRInstruction(Opcode.ASRM, dt, labelSymbol = symbol)
                 } else {
                     // just shift multiple bits (signed)
-                    val pow2reg = registers.nextFree()
+                    val pow2reg = registers.next(dt)
                     code += IRInstruction(Opcode.LOAD, dt, reg1 = pow2reg, immediate = pow2)
                     code += if (knownAddress != null)
                                 IRInstruction(Opcode.ASRNM, dt, reg1 = pow2reg, address = knownAddress)
@@ -927,7 +968,7 @@ class IRCodeGen(
                 }
                 else {
                     // just shift multiple bits (unsigned)
-                    val pow2reg = registers.nextFree()
+                    val pow2reg = registers.next(dt)
                     code += IRInstruction(Opcode.LOAD, dt, reg1=pow2reg, immediate = pow2)
                     code += if(knownAddress!=null)
                                 IRInstruction(Opcode.LSRNM, dt, reg1 = pow2reg, address = knownAddress)
@@ -941,7 +982,7 @@ class IRCodeGen(
         {
             // regular div
             if (factor == 0) {
-                val reg = registers.nextFree()
+                val reg = registers.next(dt)
                 code += IRInstruction(Opcode.LOAD, dt, reg1=reg, immediate = 0xffff)
                 code += if(knownAddress!=null)
                     IRInstruction(Opcode.STOREM, dt, reg1=reg, address = knownAddress)
@@ -949,7 +990,7 @@ class IRCodeGen(
                     IRInstruction(Opcode.STOREM, dt, reg1=reg, labelSymbol = symbol)
             }
             else {
-                val factorReg = registers.nextFree()
+                val factorReg = registers.next(dt)
                 code += IRInstruction(Opcode.LOAD, dt, reg1=factorReg, immediate = factor)
                 code += if(signed) {
                     if(knownAddress!=null)
@@ -986,6 +1027,7 @@ class IRCodeGen(
                 ifWithOnlyNormalJump_IntegerCond(ifElse, goto)
         }
 
+        // floating-point condition only from here!
         // we assume only a binary expression can contain a floating point.
         val result = mutableListOf<IRCodeChunkBase>()
         val leftTr = expressionEval.translateExpression(condition.left)
@@ -994,7 +1036,7 @@ class IRCodeGen(
         addToResult(result, rightTr, -1, rightTr.resultFpReg)
         var afterIfLabel = ""
         result += IRCodeChunk(null, null).also {
-            val compResultReg = registers.nextFree()
+            val compResultReg = registers.next(IRDataType.BYTE)
             it += IRInstruction(
                 Opcode.FCOMP,
                 IRDataType.FLOAT,
@@ -1056,7 +1098,7 @@ class IRCodeGen(
                         else if(goto.target is PtIdentifier && !isIndirectJump(goto))
                             IRInstruction(gotoOpcode, IRDataType.BYTE, reg1 = compResultReg, immediate = 0, labelSymbol = (goto.target as PtIdentifier).name)
                         else
-                            TODO("JUMP to expression address ${goto.target}")  // keep in mind the branch insruction that may need to precede this!
+                            throw AssemblyError("non-indirect jump shouldn't have an expression as target")
                     }
                 }
             }
@@ -1075,7 +1117,7 @@ class IRCodeGen(
             if(identifier!=null && !isIndirectJump(goto))
                 IRInstruction(branchOpcode, labelSymbol = identifier.name)
             else
-                TODO("JUMP to expression address ${goto.target}")  // keep in mind the branch insruction that may need to precede this!
+                TODO("JUMP to expression address ${goto.target}")
         }
     }
 
@@ -1124,7 +1166,6 @@ class IRCodeGen(
                     }
                 }
             } else {
-
                 val rightTr = expressionEval.translateExpression(condition.right)
                 addToResult(result, rightTr, rightTr.resultReg, -1)
                 val firstReg: Int
@@ -1254,7 +1295,7 @@ class IRCodeGen(
                         else if(goto.target is PtIdentifier && !isIndirectJump(goto))
                             addInstr(result, IRInstruction(opcode, irDt, reg1 = firstReg, immediate = number, labelSymbol = (goto.target as PtIdentifier).name), null)
                         else
-                            TODO("JUMP to expression address ${goto.target}")   // keep in mind the branch insruction that may need to precede this!
+                            throw AssemblyError("non-indirect jump shouldn't have an expression as target")
                     }
                 }
             } else {
@@ -1313,7 +1354,7 @@ class IRCodeGen(
                     else if(goto.target is PtIdentifier && !isIndirectJump(goto))
                         addInstr(result, IRInstruction(opcode, irDt, reg1 = firstReg, reg2 = secondReg, labelSymbol = (goto.target as PtIdentifier).name), null)
                     else
-                        TODO("JUMP to expression address ${goto.target}")  // keep in mind the branch insruction that may need to precede this!
+                        throw AssemblyError("non-indirect jump shouldn't have an expression as target")
                 }
             }
         }
@@ -1357,7 +1398,7 @@ class IRCodeGen(
         addToResult(result, leftTr, -1, leftTr.resultFpReg)
         val rightTr = expressionEval.translateExpression(condition.right)
         addToResult(result, rightTr, -1, rightTr.resultFpReg)
-        val compResultReg = registers.nextFree()
+        val compResultReg = registers.next(IRDataType.BYTE)
         addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1 = compResultReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null)
         val elseBranch: Opcode
         var useCmpi = false     // for the branch opcodes that have been converted to CMPI + BSTxx form already
@@ -1412,10 +1453,6 @@ class IRCodeGen(
         val result = mutableListOf<IRCodeChunkBase>()
 
         fun translateSimple(condition: PtExpression, jumpFalseOpcode: Opcode, addCmpiZero: Boolean) {
-
-            if(condition is PtBuiltinFunctionCall && condition.name.startsWith("prog8_ifelse_bittest_"))
-                throw AssemblyError("IR codegen doesn't have special instructions for dedicated BIT tests and should just still use normal AND")
-
             val tr = expressionEval.translateExpression(condition)
             if(addCmpiZero)
                 tr.chunks.last().instructions.add(IRInstruction(Opcode.CMPI, tr.dt, reg1 = tr.resultReg, immediate = 0))
@@ -1440,6 +1477,41 @@ class IRCodeGen(
             if(condition.operator in LogicalOperators)
                 return translateSimple(condition, Opcode.BSTEQ, false)
 
+            val useBIT = expressionEval.checkIfConditionCanUseBIT(condition)
+            if(useBIT!=null) {
+                // use a BIT instruction to test for bit 7 or 6 set/clear
+                val (testBitSet, variable, bitmask) = useBIT
+                addInstr(result, IRInstruction(Opcode.BIT, IRDataType.BYTE, labelSymbol = variable.name), null)
+                val bitBranchOpcode = when(testBitSet) {
+                    true -> when(bitmask) {
+                        64 -> Opcode.BSTVC
+                        128 -> Opcode.BSTPOS
+                        else -> throw AssemblyError("need bit 6 or 7")
+                    }
+                    false -> when(bitmask) {
+                        64 -> Opcode.BSTVS
+                        128 -> Opcode.BSTNEG
+                        else -> throw AssemblyError("need bit 6 or 7")
+                    }
+                }
+
+                if(ifElse.hasElse()) {
+                    val elseLabel = createLabelName()
+                    val afterIfLabel = createLabelName()
+                    addInstr(result, IRInstruction(bitBranchOpcode, labelSymbol = elseLabel), null)
+                    result += translateNode(ifElse.ifScope)
+                    addInstr(result, IRInstruction(Opcode.JUMP, labelSymbol = afterIfLabel), null)
+                    result += labelFirstChunk(translateNode(ifElse.elseScope), elseLabel)
+                    result += IRCodeChunk(afterIfLabel, null)
+                } else {
+                    val afterIfLabel = createLabelName()
+                    addInstr(result, IRInstruction(bitBranchOpcode, labelSymbol = afterIfLabel), null)
+                    result += translateNode(ifElse.ifScope)
+                    result += IRCodeChunk(afterIfLabel, null)
+                }
+                return
+            }
+
             val signed = condition.left.type.isSigned
             val elseBranchFirstReg: Int
             val elseBranchSecondReg: Int
@@ -1618,7 +1690,7 @@ class IRCodeGen(
         val result = mutableListOf<IRCodeChunkBase>()
         if(constRepeats==65536) {
             // make use of the word wrap around to count to 65536
-            val resultRegister = registers.nextFree()
+            val resultRegister = registers.next(IRDataType.WORD)
             addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.WORD, reg1=resultRegister, immediate = 0), null)
             result += labelFirstChunk(translateNode(repeat.statements), repeatLabel)
             result += IRCodeChunk(null, null).also {
@@ -1686,10 +1758,23 @@ class IRCodeGen(
 
     private fun translate(ret: PtReturn): IRCodeChunks {
         val result = mutableListOf<IRCodeChunkBase>()
-        val value = ret.value
+        if(ret.children.size>1) {
+            // multi-value returns are passed throug cx16.R15 down to R0 (allows unencumbered use of many Rx registers if you don't return that many values)
+            val registersReverseOrder = Cx16VirtualRegisters.reversed()
+            for ((value, register) in ret.children.zip(registersReverseOrder)) {
+                val tr = expressionEval.translateExpression(value as PtExpression)
+                addToResult(result, tr, tr.resultReg, -1)
+                addInstr(result, IRInstruction(Opcode.STOREM, tr.dt, reg1=tr.resultReg, labelSymbol = "cx16.${register.toString().lowercase()}"), null)
+            }
+            addInstr(result, IRInstruction(Opcode.RETURN), null)
+            return result
+        }
+
+        val value = ret.children.singleOrNull()
         if(value==null) {
             addInstr(result, IRInstruction(Opcode.RETURN), null)
         } else {
+            value as PtExpression
             if(value.type.isFloat) {
                 if(value is PtNumber) {
                     addInstr(result, IRInstruction(Opcode.RETURNI, IRDataType.FLOAT, immediateFp = value.number), null)
@@ -1728,7 +1813,7 @@ class IRCodeGen(
                 is PtVariable, is PtConstant, is PtMemMapped -> { /* vars should be looked up via symbol table */ }
                 is PtAlign -> TODO("ir support for inline %align")
                 is PtSub -> {
-                    val sub = IRSubroutine(child.name, translate(child.parameters), child.returntype, child.position)
+                    val sub = IRSubroutine(child.name, translate(child.parameters), child.returns, child.position)
                     for (subchild in child.children) {
                         translateNode(subchild).forEach { sub += it }
                     }
@@ -1769,6 +1854,14 @@ class IRCodeGen(
                 is PtLabel -> {
                     irBlock += IRCodeChunk(child.name, null)
                 }
+                is PtJmpTable -> {
+                    irBlock += IRCodeChunk(null, null).also {
+                        for(addr in child.children) {
+                            addr as PtIdentifier
+                            it += IRInstruction(Opcode.JUMP, labelSymbol = addr.name)
+                        }
+                    }
+                }
                 else -> TODO("weird block child node $child")
             }
         }
@@ -1818,4 +1911,6 @@ class IRCodeGen(
             it += IRInstruction(Opcode.SYSCALL, immediate = syscall.number, fcallArgs = FunctionCallArgs(args, returnSpec))
         }
     }
+
+    fun registerTypes(): Map<Int, IRDataType> = registers.getTypes()
 }

codeGenIntermediate/src/prog8/codegen/intermediate/IRPeepholeOptimizer.kt

@@ -199,6 +199,8 @@ class IRPeepholeOptimizer(private val irprog: IRProgram) {
                             IRInlineAsmChunk(label, candidate.assembly, candidate.isIR, candidate.next)
                         else
                             candidate
+                    } else {
+                        chunks += candidate
                     }
                 }
                 is IRInlineBinaryChunk -> {
@@ -210,6 +212,8 @@ class IRPeepholeOptimizer(private val irprog: IRProgram) {
                             IRInlineBinaryChunk(label, candidate.data, candidate.next)
                         else
                             candidate
+                    } else {
+                        chunks += candidate
                     }
                 }
             }
@@ -351,33 +355,10 @@ class IRPeepholeOptimizer(private val irprog: IRProgram) {
                     }
                 }
             }
-
-            // a SNZ etc. whose target register is not used can be removed altogether
-            if(ins.opcode in OpcodesThatSetRegFromStatusbits) {
-                val usages = regUsages(ins.reg1!!)
-                if(usages.toList().sumOf { it.second } <= 1) {
-                    chunk.instructions.removeAt(idx)
-                    changed = true
-                }
-            }
         }
         return changed
     }
 
-    private fun regUsages(register: Int): Map<IRCodeChunkBase, Int> {
-        val chunks = mutableMapOf<IRCodeChunkBase, Int>()
-        irprog.foreachSub { sub ->
-            sub.chunks.forEach { chunk ->
-                val used = chunk.usedRegisters()
-                val numUsages = used.readRegs.getOrDefault(register, 0) + used.writeRegs.getOrDefault(register, 0)
-                if(numUsages>0) {
-                    chunks[chunk] = numUsages
-                }
-            }
-        }
-        return chunks
-    }
-
     private fun removeUselessArithmetic(chunk: IRCodeChunk, indexedInstructions: List<IndexedValue<IRInstruction>>): Boolean {
         // note: this is hard to solve for the non-immediate instructions atm because the values are loaded into registers first
         var changed = false

codeGenIntermediate/src/prog8/codegen/intermediate/RegisterPool.kt

@@ -1,22 +1,31 @@
 package prog8.codegen.intermediate
 
+import prog8.code.core.AssemblyError
+import prog8.intermediate.IRDataType
+
 internal class RegisterPool {
-    // reserve 0,1,2 for return values of subroutine calls and syscalls in IR assembly code
-    private var firstFree: Int=3
-    private var firstFreeFloat: Int=3
+    // everything from 99000 onwards is reserved for special purposes:
+    // 99000 - 99099 : WORD registers for syscall arguments and response value(s)
+    // 99100 - 99199 : BYTE registers for syscall arguments and response value(s)
 
-    fun peekNext() = firstFree
-    fun peekNextFloat() = firstFreeFloat
+    private var nextRegister: Int=1
+    private val registerTypes: MutableMap<Int, IRDataType> = mutableMapOf()
 
-    fun nextFree(): Int {
-        val result = firstFree
-        firstFree++
-        return result
+    fun getTypes(): Map<Int, IRDataType> = registerTypes
+
+    init {
+        for(i in 99000..99099)
+            registerTypes[i] = IRDataType.WORD
+        for(i in 99100..99199)
+            registerTypes[i] = IRDataType.BYTE
     }
 
-    fun nextFreeFloat(): Int {
-        val result = firstFreeFloat
-        firstFreeFloat++
+    fun next(type: IRDataType): Int {
+        if(nextRegister>=99000)
+            throw AssemblyError("register pool depleted")
+        val result = nextRegister
+        nextRegister++
+        registerTypes[result] = type
         return result
     }
 }

codeGenIntermediate/src/prog8/codegen/vm/VmCodeGen.kt

@@ -19,12 +19,18 @@ class VmCodeGen: ICodeGeneratorBackend {
     ): IAssemblyProgram {
         val irCodeGen = IRCodeGen(program, symbolTable, options, errors)
         val irProgram = irCodeGen.generate()
+
+        irProgram.verifyRegisterTypes(irCodeGen.registerTypes())
+
         return VmAssemblyProgram(irProgram.name, irProgram)
     }
 }
 
 
-internal class VmAssemblyProgram(override val name: String, internal val irProgram: IRProgram): IAssemblyProgram {
+internal class VmAssemblyProgram(
+    override val name: String,
+    internal val irProgram: IRProgram
+): IAssemblyProgram {
 
     override fun assemble(options: CompilationOptions, errors: IErrorReporter): Boolean {
         // the VM reads the IR file from disk.

codeGenIntermediate/test/TestIRPeepholeOpt.kt

@@ -9,7 +9,7 @@ class TestIRPeepholeOpt: FunSpec({
     fun makeIRProgram(chunks: List<IRCodeChunkBase>): IRProgram {
         require(chunks.first().label=="main.start")
         val block = IRBlock("main", false, IRBlock.Options(), Position.DUMMY)
-        val sub = IRSubroutine("main.start", emptyList(), null, Position.DUMMY)
+        val sub = IRSubroutine("main.start", emptyList(), emptyList(), Position.DUMMY)
         chunks.forEach { sub += it }
         block += sub
         val target = VMTarget()
@@ -22,7 +22,7 @@ class TestIRPeepholeOpt: FunSpec({
             floats = false,
             noSysInit = true,
             compTarget = target,
-            loadAddress = target.machine.PROGRAM_LOAD_ADDRESS,
+            loadAddress = target.PROGRAM_LOAD_ADDRESS,
             memtopAddress = 0xffffu
         )
         val prog = IRProgram("test", IRSymbolTable(), options, target)

codeGenIntermediate/test/TestVmCodeGen.kt

@@ -24,7 +24,7 @@ class TestVmCodeGen: FunSpec({
             floats = true,
             noSysInit = false,
             compTarget = target,
-            loadAddress = target.machine.PROGRAM_LOAD_ADDRESS,
+            loadAddress = target.PROGRAM_LOAD_ADDRESS,
             memtopAddress = 0xffffu
         )
     }
@@ -45,13 +45,13 @@ class TestVmCodeGen: FunSpec({
         val codegen = VmCodeGen()
         val program = PtProgram("test", DummyMemsizer, DummyStringEncoder)
         val block = PtBlock("main", false, SourceCode.Generated("test"), PtBlock.Options(), Position.DUMMY)
-        val sub = PtSub("start", emptyList(), null, Position.DUMMY)
+        val sub = PtSub("start", emptyList(), emptyList(), Position.DUMMY)
         sub.add(PtVariable(
             "pi",
             DataType.forDt(BaseDataType.UBYTE),
             ZeropageWish.DONTCARE,
             0u,
-            PtNumber(BaseDataType.UBYTE, 0.0, Position.DUMMY),
+            null,
             null,
             Position.DUMMY
         ))
@@ -78,7 +78,7 @@ class TestVmCodeGen: FunSpec({
             DataType.forDt(BaseDataType.WORD),
             ZeropageWish.DONTCARE,
             0u,
-            PtNumber(BaseDataType.WORD, 1.0, Position.DUMMY),
+            null,
             null,
             Position.DUMMY
         ))
@@ -160,7 +160,7 @@ class TestVmCodeGen: FunSpec({
         val codegen = VmCodeGen()
         val program = PtProgram("test", DummyMemsizer, DummyStringEncoder)
         val block = PtBlock("main", false, SourceCode.Generated("test"), PtBlock.Options(), Position.DUMMY)
-        val sub = PtSub("start", emptyList(), null, Position.DUMMY)
+        val sub = PtSub("start", emptyList(), emptyList(), Position.DUMMY)
         sub.add(PtVariable(
             "f1",
             DataType.forDt(BaseDataType.FLOAT),
@@ -231,7 +231,7 @@ class TestVmCodeGen: FunSpec({
         val codegen = VmCodeGen()
         val program = PtProgram("test", DummyMemsizer, DummyStringEncoder)
         val block = PtBlock("main", false, SourceCode.Generated("test"), PtBlock.Options(), Position.DUMMY)
-        val sub = PtSub("start", emptyList(), null, Position.DUMMY)
+        val sub = PtSub("start", emptyList(), emptyList(), Position.DUMMY)
         sub.add(PtVariable(
             "f1",
             DataType.forDt(BaseDataType.FLOAT),
@@ -298,7 +298,7 @@ class TestVmCodeGen: FunSpec({
         val codegen = VmCodeGen()
         val program = PtProgram("test", DummyMemsizer, DummyStringEncoder)
         val block = PtBlock("main", false, SourceCode.Generated("test"), PtBlock.Options(), Position.DUMMY)
-        val sub = PtSub("start", emptyList(), null, Position.DUMMY)
+        val sub = PtSub("start", emptyList(), emptyList(), Position.DUMMY)
         sub.add(PtVariable(
             "f1",
             DataType.forDt(BaseDataType.FLOAT),
@@ -353,7 +353,7 @@ class TestVmCodeGen: FunSpec({
         val codegen = VmCodeGen()
         val program = PtProgram("test", DummyMemsizer, DummyStringEncoder)
         val block = PtBlock("main", false, SourceCode.Generated("test"), PtBlock.Options(), Position.DUMMY)
-        val sub = PtSub("start", emptyList(), null, Position.DUMMY)
+        val sub = PtSub("start", emptyList(), emptyList(), Position.DUMMY)
         sub.add(PtVariable(
             "sb1",
             DataType.forDt(BaseDataType.BYTE),
@@ -424,7 +424,7 @@ class TestVmCodeGen: FunSpec({
         val codegen = VmCodeGen()
         val program = PtProgram("test", DummyMemsizer, DummyStringEncoder)
         val block = PtBlock("main", false, SourceCode.Generated("test"), PtBlock.Options(), Position.DUMMY)
-        val sub = PtSub("start", emptyList(), null, Position.DUMMY)
+        val sub = PtSub("start", emptyList(), emptyList(), Position.DUMMY)
         sub.add(PtVariable(
             "sb1",
             DataType.forDt(BaseDataType.BYTE),
@@ -491,7 +491,7 @@ class TestVmCodeGen: FunSpec({
         val codegen = VmCodeGen()
         val program = PtProgram("test", DummyMemsizer, DummyStringEncoder)
         val block = PtBlock("main", false, SourceCode.Generated("test"), PtBlock.Options(), Position.DUMMY)
-        val sub = PtSub("start", emptyList(), null, Position.DUMMY)
+        val sub = PtSub("start", emptyList(), emptyList(), Position.DUMMY)
         sub.add(PtVariable(
             "ub1",
             DataType.forDt(BaseDataType.BYTE),
@@ -541,7 +541,7 @@ class TestVmCodeGen: FunSpec({
         val block = PtBlock("main", false, SourceCode.Generated("test"), PtBlock.Options(), Position.DUMMY)
         val extsub = PtAsmSub("routine", PtAsmSub.Address(null, null, 0x5000u), setOf(CpuRegister.Y), emptyList(), emptyList(), false, Position.DUMMY)
         block.add(extsub)
-        val sub = PtSub("start", emptyList(), null, Position.DUMMY)
+        val sub = PtSub("start", emptyList(), emptyList(), Position.DUMMY)
         val call = PtFunctionCall("main.routine", true, DataType.forDt(BaseDataType.UNDEFINED), Position.DUMMY)
         sub.add(call)
         block.add(sub)

codeOptimizers/build.gradle.kts

@@ -8,7 +8,7 @@ dependencies {
     implementation(project(":codeCore"))
     implementation(project(":compilerAst"))
     // implementation("org.jetbrains.kotlin:kotlin-stdlib-jdk8")
-    implementation("com.michael-bull.kotlin-result:kotlin-result-jvm:2.0.0")
+    implementation("com.michael-bull.kotlin-result:kotlin-result-jvm:2.0.1")
     // implementation "org.jetbrains.kotlin:kotlin-reflect"
 }
 
@@ -23,4 +23,4 @@ sourceSets {
     }
 }
 
-// note: there are no unit tests in this module!
+// note: there are no unit tests in this module!

codeOptimizers/src/prog8/optimizer/ConstantIdentifierReplacer.kt

@@ -21,7 +21,12 @@ class VarConstantValueTypeAdjuster(
     private val errors: IErrorReporter
 ) : AstWalker() {
 
-    private val callGraph by lazy { CallGraph(program) }
+    private lateinit var callGraph : CallGraph
+
+    override fun before(program: Program) : Iterable<IAstModification> {
+        callGraph = CallGraph(program)
+        return noModifications
+    }
 
     override fun after(decl: VarDecl, parent: Node): Iterable<IAstModification> {
 
@@ -56,15 +61,32 @@ class VarConstantValueTypeAdjuster(
                             || it.parent is AddressOf
                             || (it.parent as? IFunctionCall)?.target?.nameInSource?.singleOrNull() in InplaceModifyingBuiltinFunctions
                 }
-            val singleAssignment =
-                writes.singleOrNull()?.parent?.parent as? Assignment ?: writes.singleOrNull()?.parent as? Assignment
+
+            var singleAssignment: Assignment? = null
+            val singleWrite=writes.singleOrNull()
+            if(singleWrite!=null) {
+                singleAssignment = singleWrite.parent as? Assignment
+                if(singleAssignment==null) {
+                    singleAssignment = singleWrite.parent.parent as? Assignment
+                    if(singleAssignment==null) {
+                        // we could be part of a multi-assign
+                        if(singleWrite.parent is AssignTarget && singleWrite.parent.parent is AssignTarget)
+                            singleAssignment = singleWrite.parent.parent.parent as? Assignment
+                    }
+                }
+            }
+
             if (singleAssignment == null) {
                 if (writes.isEmpty()) {
                     if(reads.isEmpty()) {
-                        // variable is never used AT ALL so we just remove it altogether
-                        if("ignore_unused" !in decl.definingBlock.options())
-                            errors.info("removing unused variable '${decl.name}'", decl.position)
-                        return listOf(IAstModification.Remove(decl, parent as IStatementContainer))
+                        if(decl.names.size>1) {
+                            errors.info("unused variable '${decl.name}'", decl.position)
+                        } else {
+                            // variable is never used AT ALL so we just remove it altogether
+                            if ("ignore_unused" !in decl.definingBlock.options())
+                                errors.info("removing unused variable '${decl.name}'", decl.position)
+                            return listOf(IAstModification.Remove(decl, parent as IStatementContainer))
+                        }
                     }
                     val declValue = decl.value?.constValue(program)
                     if (declValue != null) {
@@ -80,15 +102,20 @@ class VarConstantValueTypeAdjuster(
             } else {
                 if (singleAssignment.origin == AssignmentOrigin.VARINIT && singleAssignment.value.constValue(program) != null) {
                     if(reads.isEmpty()) {
-                        // variable is never used AT ALL so we just remove it altogether, including the single assignment
-                        if("ignore_unused" !in decl.definingBlock.options())
-                            errors.info("removing unused variable '${decl.name}'", decl.position)
-                        return listOf(
-                            IAstModification.Remove(decl, parent as IStatementContainer),
-                            IAstModification.Remove(singleAssignment, singleAssignment.parent as IStatementContainer)
-                        )
+                        if(decl.names.size>1) {
+                            errors.info("unused variable '${decl.name}'", decl.position)
+                        } else {
+                            // variable is never used AT ALL so we just remove it altogether, including the single assignment
+                            if("ignore_unused" !in decl.definingBlock.options())
+                                errors.info("removing unused variable '${decl.name}'", decl.position)
+                            return listOf(
+                                IAstModification.Remove(decl, parent as IStatementContainer),
+                                IAstModification.Remove(singleAssignment, singleAssignment.parent as IStatementContainer)
+                            )
+                        }
                     }
-                    // variable only has a single write, and it is the initialization value, so it can be replaced with a constant, IF the value is a constant
+
+                    // variable only has a single write, and it is the initialization value, so it can be replaced with a constant, but only IF the value is a constant
                     errors.info("variable '${decl.name}' is never written to and was replaced by a constant", decl.position)
                     val const = VarDecl(VarDeclType.CONST, decl.origin, decl.datatype, decl.zeropage, decl.splitwordarray, decl.arraysize, decl.name, decl.names, singleAssignment.value, decl.sharedWithAsm, decl.alignment, decl.dirty, decl.position)
                     return listOf(

codeOptimizers/src/prog8/optimizer/Inliner.kt

@@ -13,7 +13,7 @@ import prog8.code.core.InternalCompilerException
 import prog8.code.target.VMTarget
 
 
-private  fun isEmptyReturn(stmt: Statement): Boolean = stmt is Return && stmt.value==null
+private  fun isEmptyReturn(stmt: Statement): Boolean = stmt is Return && stmt.values.size==0
 
 
 // inliner potentially enables *ONE LINED* subroutines, wihtout to be inlined.
@@ -38,26 +38,21 @@ class Inliner(private val program: Program, private val options: CompilationOpti
                             // subroutine is possible candidate to be inlined
                             subroutine.inline =
                                 when (val stmt = subroutine.statements[0]) {
-                                    is Return -> {
-                                        if (stmt.value is NumericLiteral)
+                                    // TODO consider multi-value returns as well
+                                    is Return -> stmt.values.isEmpty() || stmt.values.size==1 &&
+                                        if (stmt.values[0] is NumericLiteral)
                                             true
-                                        else if (stmt.value == null)
+                                        else if (stmt.values[0] is IdentifierReference) {
+                                            makeFullyScoped(stmt.values[0] as IdentifierReference)
                                             true
-                                        else if (stmt.value is IdentifierReference) {
-                                            makeFullyScoped(stmt.value as IdentifierReference)
-                                            true
-                                        } else if (stmt.value!! is IFunctionCall && (stmt.value as IFunctionCall).args.size <= 1 && (stmt.value as IFunctionCall).args.all { it is NumericLiteral || it is IdentifierReference }) {
-                                            when (stmt.value) {
-                                                is FunctionCallExpression -> {
-                                                    makeFullyScoped(stmt.value as FunctionCallExpression)
-                                                    true
-                                                }
-
-                                                else -> false
+                                        } else if (stmt.values[0]!! is IFunctionCall && (stmt.values[0] as IFunctionCall).args.size <= 1 && (stmt.values[0] as IFunctionCall).args.all { it is NumericLiteral || it is IdentifierReference }) {
+                                            if (stmt.values[0] is FunctionCallExpression) {
+                                                makeFullyScoped(stmt.values[0] as FunctionCallExpression)
+                                                true
                                             }
+                                            else false
                                         } else
                                             false
-                                    }
 
                                     is Assignment -> {
                                         if (stmt.value.isSimple) {
@@ -182,14 +177,19 @@ class Inliner(private val program: Program, private val options: CompilationOpti
                 // note that we don't have to process any args, because we online inline parameterless subroutines.
                 when (val toInline = sub.statements.first()) {
                     is Return -> {
-                        val fcall = toInline.value as? FunctionCallExpression
-                        if(fcall!=null) {
-                            // insert the function call expression as a void function call directly
-                            sub.hasBeenInlined=true
-                            val call = FunctionCallStatement(fcall.target.copy(), fcall.args.map { it.copy() }.toMutableList(), true, fcall.position)
-                            listOf(IAstModification.ReplaceNode(origNode, call, parent))
-                        } else
+                        // TODO consider multi-value returns as well
+                        if(toInline.values.size!=1)
                             noModifications
+                        else {
+                            val fcall = toInline.values[0] as? FunctionCallExpression
+                            if(fcall!=null) {
+                                // insert the function call expression as a void function call directly
+                                sub.hasBeenInlined=true
+                                val call = FunctionCallStatement(fcall.target.copy(), fcall.args.map { it.copy() }.toMutableList(), true, fcall.position)
+                                listOf(IAstModification.ReplaceNode(origNode, call, parent))
+                            } else
+                                noModifications
+                        }
                     }
                     else -> {
                         if(origNode !== toInline) {
@@ -226,9 +226,10 @@ class Inliner(private val program: Program, private val options: CompilationOpti
                     is Return -> {
                         // is an expression, so we have to have a Return here in the inlined sub
                         // note that we don't have to process any args, because we online inline parameterless subroutines.
-                        if(toInline.value!=null && functionCallExpr!==toInline.value) {
+                        // TODO consider multi-value returns as well
+                        if(toInline.values.size==1 && functionCallExpr!==toInline.values[0]) {
                             sub.hasBeenInlined=true
-                            listOf(IAstModification.ReplaceNode(functionCallExpr, toInline.value!!.copy(), parent))
+                            listOf(IAstModification.ReplaceNode(functionCallExpr, toInline.values[0].copy(), parent))
                         }
                         else
                             noModifications

codeOptimizers/src/prog8/optimizer/StatementOptimizer.kt

@@ -9,6 +9,7 @@ import prog8.code.core.AssociativeOperators
 import prog8.code.core.BaseDataType
 import prog8.code.core.CompilationOptions
 import prog8.code.core.IErrorReporter
+import prog8.code.core.Position
 
 
 class StatementOptimizer(private val program: Program,
@@ -400,9 +401,91 @@ class StatementOptimizer(private val program: Program,
             }
         }
 
+        val funcName = (assignment.value as? FunctionCallExpression)?.target?.nameInSource
+        if(funcName?.size==1) {
+            if(funcName[0].startsWith("min__")) {
+                val (v1, v2) = (assignment.value as FunctionCallExpression).args
+                if(v1 isSameAs v2)
+                    errors.err("identical values given, function is useless", assignment.value.position)
+                if ((v1 is NumericLiteral || v1 is IdentifierReference) && v2 isSameAs assignment.target) {
+                    // x = min(100, x)  ->  if x>100  x=100
+                    val ifstmt = makeMinMaxCheckAndAssignRight(v2, ">", v1, assignment.target, assignment.position)
+                    return listOf(IAstModification.ReplaceNode(assignment, ifstmt, parent))
+                } else if ((v2 is NumericLiteral || v2 is IdentifierReference) && v1 isSameAs assignment.target) {
+                    // x = min(x, 100)  ->  if x>100  x=100
+                    val ifstmt = makeMinMaxCheckAndAssignRight(v1, ">", v2, assignment.target, assignment.position)
+                    return listOf(IAstModification.ReplaceNode(assignment, ifstmt, parent))
+                }
+
+                if(v2 is NumericLiteral || v2 is IdentifierReference) {
+                    // x = min(expression, 100)  ->  x=expression,  if x>100  x=100
+                    val assign = Assignment(assignment.target.copy(), v1, AssignmentOrigin.OPTIMIZER, assignment.position)
+                    val ifstmt = makeMinMaxCheckAndAssignRight(assign.target.toExpression(), ">", v2, assignment.target, assignment.position)
+                    return listOf(
+                        IAstModification.InsertAfter(assignment, ifstmt, parent as IStatementContainer),
+                        IAstModification.ReplaceNode(assignment, assign, parent)
+                    )
+                } else if(v1 is NumericLiteral || v1 is IdentifierReference) {
+                    // x = min(100, expression)  ->  x=expression,  if x>100  x=100
+                    val assign = Assignment(assignment.target.copy(), v2, AssignmentOrigin.OPTIMIZER, assignment.position)
+                    val ifstmt = makeMinMaxCheckAndAssignRight(assign.target.toExpression(), ">", v1, assignment.target, assignment.position)
+                    return listOf(
+                        IAstModification.InsertAfter(assignment, ifstmt, parent as IStatementContainer),
+                        IAstModification.ReplaceNode(assignment, assign, parent)
+                    )
+                }
+
+            }
+            else if(funcName[0].startsWith("max__")) {
+                val (v1, v2) = (assignment.value as FunctionCallExpression).args
+                if(v1 isSameAs v2)
+                    errors.err("identical values given, function is useless", assignment.value.position)
+                if ((v1 is NumericLiteral || v1 is IdentifierReference) && v2 isSameAs assignment.target) {
+                    // x = max(100, x)  ->  if x<100  x=100
+                    val ifstmt = makeMinMaxCheckAndAssignRight(v2, "<", v1, assignment.target, assignment.position)
+                    return listOf(IAstModification.ReplaceNode(assignment, ifstmt, parent))
+                } else if ((v2 is NumericLiteral || v2 is IdentifierReference) && v1 isSameAs assignment.target) {
+                    // x = max(x, 100)  ->  if x<100  x=100
+                    val ifstmt = makeMinMaxCheckAndAssignRight(v1, "<", v2, assignment.target, assignment.position)
+                    return listOf(IAstModification.ReplaceNode(assignment, ifstmt, parent))
+                }
+
+                if(v2 is NumericLiteral || v2 is IdentifierReference) {
+                    // x = max(expression, 100)  ->  x=expression,  if x<100  x=100
+                    val assign = Assignment(assignment.target.copy(), v1, AssignmentOrigin.OPTIMIZER, assignment.position)
+                    val ifstmt = makeMinMaxCheckAndAssignRight(assign.target.toExpression(), "<", v2, assignment.target, assignment.position)
+                    return listOf(
+                        IAstModification.InsertAfter(assignment, ifstmt, parent as IStatementContainer),
+                        IAstModification.ReplaceNode(assignment, assign, parent)
+                    )
+                } else if(v1 is NumericLiteral || v1 is IdentifierReference) {
+                    // x = max(100, expression)  ->  x=expression,  if x<100  x=100
+                    val assign = Assignment(assignment.target.copy(), v2, AssignmentOrigin.OPTIMIZER, assignment.position)
+                    val ifstmt = makeMinMaxCheckAndAssignRight(assign.target.toExpression(), "<", v1, assignment.target, assignment.position)
+                    return listOf(
+                        IAstModification.InsertAfter(assignment, ifstmt, parent as IStatementContainer),
+                        IAstModification.ReplaceNode(assignment, assign, parent)
+                    )
+                }
+
+            }
+        }
+
         return noModifications
     }
 
+    private fun makeMinMaxCheckAndAssignRight(left: Expression, operator: String, right: Expression, target: AssignTarget, position: Position): IfElse {
+        require(right is NumericLiteral || right is IdentifierReference)
+        val compare = BinaryExpression(left, operator, right, position)
+        val assign = Assignment(target, right.copy(), AssignmentOrigin.OPTIMIZER, position)
+        return IfElse(
+            compare,
+            AnonymousScope(mutableListOf(assign), position),
+            AnonymousScope(mutableListOf(), position),
+            position
+        )
+    }
+
     override fun before(unrollLoop: UnrollLoop, parent: Node): Iterable<IAstModification> {
         val iterations = unrollLoop.iterations.constValue(program)?.number?.toInt()
         return if(iterations!=null && iterations<1)

codeOptimizers/src/prog8/optimizer/UnusedCodeRemover.kt

@@ -101,7 +101,7 @@ class UnusedCodeRemover(private val program: Program,
             }
             if (callgraph.unused(block)) {
                 if (block.statements.any { it !is VarDecl || it.type == VarDeclType.VAR } && "ignore_unused" !in block.options()) {
-                    if (!block.statements.any { it is Subroutine && it.hasBeenInlined })
+                    if (!block.statements.any { it is Subroutine && !it.hasBeenInlined })
                         errors.info("removing unused block '${block.name}'", block.position)
                 }
                 if (!block.statements.any { it is Subroutine && it.hasBeenInlined }) {
@@ -148,9 +148,13 @@ class UnusedCodeRemover(private val program: Program,
             if (!forceOutput && decl.origin==VarDeclOrigin.USERCODE && !decl.sharedWithAsm) {
                 val usages = callgraph.usages(decl)
                 if (usages.isEmpty()) {
-                    if("ignore_unused" !in decl.definingBlock.options())
-                        errors.info("removing unused variable '${decl.name}'", decl.position)
-                    return listOf(IAstModification.Remove(decl, parent as IStatementContainer))
+                    if(decl.names.size>1) {
+                        errors.info("unused variable '${decl.name}'", decl.position)
+                    } else {
+                        if ("ignore_unused" !in decl.definingBlock.options())
+                            errors.info("removing unused variable '${decl.name}'", decl.position)
+                        return listOf(IAstModification.Remove(decl, parent as IStatementContainer))
+                    }
                 }
                 else {
                     if(usages.size==1) {
@@ -159,13 +163,17 @@ class UnusedCodeRemover(private val program: Program,
                             val assignment = singleUse.parent as? Assignment
                             if(assignment!=null && assignment.origin==AssignmentOrigin.VARINIT) {
                                 if(assignment.value.isSimple) {
-                                    // remove the vardecl
-                                    if("ignore_unused" !in decl.definingBlock.options())
-                                        errors.info("removing unused variable '${decl.name}'", decl.position)
-                                    return listOf(
-                                        IAstModification.Remove(decl, parent as IStatementContainer),
-                                        IAstModification.Remove(assignment, assignment.parent as IStatementContainer)
-                                    )
+                                    if(decl.names.size>1) {
+                                        errors.info("unused variable '${decl.name}'", decl.position)
+                                    } else {
+                                        // remove the vardecl
+                                        if("ignore_unused" !in decl.definingBlock.options())
+                                            errors.info("removing unused variable '${decl.name}'", decl.position)
+                                        return listOf(
+                                            IAstModification.Remove(decl, parent as IStatementContainer),
+                                            IAstModification.Remove(assignment, assignment.parent as IStatementContainer)
+                                        )
+                                    }
                                 } else if(assignment.value is IFunctionCall) {
                                     // replace the unused variable's initializer function call by a void
                                     // but only if the vardecl immediately precedes it!
@@ -298,7 +306,7 @@ class UnusedCodeRemover(private val program: Program,
                         else -> {}
                     }
                 } else {
-                    if (assign1.target.isSameAs(assign2.target, program) && !assign1.target.isIOAddress(compTarget.machine))  {
+                    if (assign1.target.isSameAs(assign2.target, program) && !assign1.target.isIOAddress(compTarget))  {
                         if(assign2.target.identifier==null || !assign2.value.referencesIdentifier(assign2.target.identifier!!.nameInSource))
                             // only remove the second assignment if its value is a simple expression!
                             when(assign2.value) {

compiler/build.gradle.kts

@@ -21,7 +21,7 @@ dependencies {
     // implementation("org.jetbrains.kotlin:kotlin-stdlib-jdk8")
     // implementation("org.jetbrains.kotlin:kotlin-reflect")
     implementation("org.jetbrains.kotlinx:kotlinx-cli:0.3.6")
-    implementation("com.michael-bull.kotlin-result:kotlin-result-jvm:2.0.0")
+    implementation("com.michael-bull.kotlin-result:kotlin-result-jvm:2.0.1")
 
     testImplementation(project(":codeCore"))
     testImplementation(project(":intermediate"))
@@ -94,4 +94,4 @@ tasks.compileKotlin {
 
 tasks.compileJava {
     dependsOn(tasks.createVersionFile)
-}
+}

compiler/res/prog8lib/c128/syslib.p8

@@ -585,7 +585,7 @@ _setup_raster_irq
 		ora  #%10000000
 		sta  c64.SCROLY     ; set most significant bit of raster position
 +		lda  #%00000001
-		sta  c64.IREQMASK   ;enable raster interrupt signals from vic
+		sta  c64.IREQMASK   ; enable raster interrupt signals from vic
 		rts
 	}}
 }

compiler/res/prog8lib/c128/textio.p8

@@ -81,15 +81,15 @@ asmsub get_row() -> ubyte @X {
     }}
 }
 
-sub get_cursor(uword colptr, uword rowptr) {
+asmsub get_cursor() -> ubyte @X, ubyte @Y {
     %asm {{
         sec
-        jsr cbm.PLOT
+        jsr  cbm.PLOT
+        stx  P8ZP_SCRATCH_REG  ; swap X and Y
         tya
-        ldy #$00
-        sta (colptr),y
-        txa
-        sta (rowptr),y
+        tax
+        ldy  P8ZP_SCRATCH_REG
+        rts
     }}
 }
 

compiler/res/prog8lib/c64/syslib.p8

@@ -600,7 +600,7 @@ _setup_raster_irq
 		ora  #%10000000
 		sta  c64.SCROLY     ; set most significant bit of raster position
 +		lda  #%00000001
-		sta  c64.IREQMASK   ;enable raster interrupt signals from vic
+		sta  c64.IREQMASK   ; enable raster interrupt signals from vic
 		rts
 	}}
 }

compiler/res/prog8lib/c64/textio.p8

@@ -86,15 +86,15 @@ asmsub get_row() -> ubyte @X {
     }}
 }
 
-sub get_cursor(uword colptr, uword rowptr) {
+asmsub get_cursor() -> ubyte @X, ubyte @Y {
     %asm {{
         sec
-        jsr cbm.PLOT
+        jsr  cbm.PLOT
+        stx  P8ZP_SCRATCH_REG  ; swap X and Y
         tya
-        ldy #$00
-        sta (colptr),y
-        txa
-        sta (rowptr),y
+        tax
+        ldy  P8ZP_SCRATCH_REG
+        rts
     }}
 }
 

compiler/res/prog8lib/coroutines.p8

@@ -35,6 +35,8 @@
 ;   Those are all shared in the different tasks! You HAVE to use a mechanism around the userdata value (pointer?) to keep separate state elsewhere!
 
 coroutines {
+    %option ignore_unused
+
     const ubyte MAX_TASKS = 64
     uword[MAX_TASKS] tasklist
     uword[MAX_TASKS] userdatas

compiler/res/prog8lib/cx16/diskio.p8

@@ -49,6 +49,7 @@ diskio {
         ; -- Prints the directory contents to the screen. Returns success.
 
         cbm.SETNAM(1, "$")
+internal_dir:
         cbm.SETLFS(READ_IO_CHANNEL, drivenumber, 0)
         ubyte status = 1
         void cbm.OPEN()          ; open 12,8,0,"$"
@@ -103,6 +104,18 @@ io_error:
         return true
     }
 
+    sub directory_dirs() -> bool {
+        ; -- Prints all entries on the disk to the screen, but only directories.  Returns success.
+        cbm.SETNAM(5, "$:*=d")
+        goto diskio.directory.internal_dir
+    }
+
+    sub directory_files() -> bool {
+        ; -- Prints all entries on the disk to the screen, but only actual files.  Returns success.
+        cbm.SETNAM(5, "$:*=p")
+        goto diskio.directory.internal_dir
+    }
+
     sub diskname() -> uword {
         ; -- Returns pointer to disk name string or 0 if failure.
 
@@ -161,7 +174,11 @@ io_error:
         ;    Files in the buffer are separated by a 0 byte. You can provide an optional pattern to match against.
         ;    After the last filename one additional 0 byte is placed to indicate the end of the list.
         ;    Returns number of files (it skips 'dir' entries i.e. subdirectories).
+        ;    Note: NO case-folding is done in this routine! (unlike DOS"$ which does case folding on the basic prompt)
         ;    Also sets carry on exit: Carry clear = all files returned, Carry set = directory has more files that didn't fit in the buffer.
+        ;    Note that no list of pointers of some form is returned, the names are just squashed together.
+        ;    If you really need a list of pointers to the names, that is pretty straightforward to construct by iterating over the names
+        ;    and registering when the next one starts after the 0-byte separator.
         uword buffer_start = filenames_buffer
         ubyte files_found = 0
         filenames_buffer[0]=0
@@ -190,12 +207,14 @@ io_error:
     sub lf_start_list(uword pattern_ptr) -> bool {
         ; -- start an iterative file listing with optional pattern matching.
         ;    note: only a single iteration loop can be active at a time!
+        cbm.SETNAM(1, "$")
+
+start_list_internal:
         lf_end_list()
         list_pattern = pattern_ptr
         list_skip_disk_name = true
         iteration_in_progress = true
 
-        cbm.SETNAM(1, "$")
         cbm.SETLFS(READ_IO_CHANNEL, drivenumber, 0)
         void cbm.OPEN()          ; open 12,8,0,"$"
         if_cs
@@ -215,10 +234,27 @@ io_error:
         return false
     }
 
+    sub lf_start_list_dirs(uword pattern_ptr) -> bool {
+        ; -- start an iterative directory contents listing with optional pattern matching.
+        ;    this version it only returns directory entries!
+        ;    note: only a single iteration loop can be active at a time!
+        cbm.SETNAM(5, "$:*=d")
+        goto diskio.lf_start_list.start_list_internal
+    }
+
+    sub lf_start_list_files(uword pattern_ptr) -> bool {
+        ; -- start an iterative directory contents listing with optional pattern matching.
+        ;    this version only returns actual file entries!
+        ;    note: only a single iteration loop can be active at a time!
+        cbm.SETNAM(5, "$:*=p")
+        goto diskio.lf_start_list.start_list_internal
+    }
+
     sub lf_next_entry() -> bool {
         ; -- retrieve the next entry from an iterative file listing session.
         ;    results will be found in list_blocks, list_filename, and list_filetype.
         ;    if it returns false though, there are no more entries (or an error occurred).
+        ;    Note: NO case-folding is done in this routine! (unlike DOS"$ which does case folding on the basic prompt)
 
         if not iteration_in_progress
             return false
@@ -576,12 +612,11 @@ return_status:
         @(messageptr) = 0
 
 done:
-        cbm.CLRCHN()        ; restore default i/o devices
         cbm.CLOSE(15)
+        cbm.CLRCHN()        ; restore default i/o devices
         return list_filename
 
 io_error:
-        cbm.CLOSE(15)
         list_filename = "io error"
         goto done
     }

compiler/res/prog8lib/cx16/monogfx.p8

@@ -16,6 +16,7 @@ monogfx {
     ; read-only control variables:
     uword width = 0
     uword height = 0
+    bool lores_mode
     ubyte mode
     const ubyte MODE_NORMAL  = %00000000
     const ubyte MODE_STIPPLE = %00000001
@@ -32,6 +33,7 @@ monogfx {
         cx16.VERA_L1_TILEBASE = 0
         width = 320
         height = 240
+        lores_mode = true
         mode = MODE_NORMAL
         clear_screen(false)
     }
@@ -47,6 +49,7 @@ monogfx {
         cx16.VERA_L1_TILEBASE = %00000001
         width = 640
         height = 480
+        lores_mode = false
         mode = MODE_NORMAL
         clear_screen(false)
     }
@@ -64,15 +67,12 @@ monogfx {
 
     sub clear_screen(bool draw) {
         position(0, 0)
-        when width {
-            320 -> {
-                repeat 240/2/8
-                    cs_innerloop640(draw)
-            }
-            640 -> {
-                repeat 480/8
-                    cs_innerloop640(draw)
-            }
+        if lores_mode {
+            repeat 240/2/8
+                cs_innerloop640(draw)
+        } else {
+            repeat 480/8
+                cs_innerloop640(draw)
         }
         position(0, 0)
     }
@@ -109,7 +109,7 @@ monogfx {
             return
         if length<=8 {
             ; just use 2 byte writes with shifted mask
-            position2(xx,yy,true)
+            position2(xx,yy)
             %asm {{
                 ldy  p8v_length
                 lda  p8v_masked_ends,y
@@ -309,8 +309,8 @@ _done
          }}
             if mode!=MODE_STIPPLE {
                 ; draw continuous line.
-                position2(xx,yy,true)
-                if width==320
+                position2(xx,yy)
+                if lores_mode
                     set_both_strides(11)    ; 40 increment = 1 line in 320 px monochrome
                 else
                     set_both_strides(12)    ; 80 increment = 1 line in 640 px monochrome
@@ -328,8 +328,8 @@ drawmode:               ora  cx16.r15L
                     lheight--
                 }
                 lheight++   ; because it is divided by 2 later, don't round off the last pixel
-                position2(xx,yy,true)
-                if width==320
+                position2(xx,yy)
+                if lores_mode
                     set_both_strides(12)    ; 80 increment = 2 line in 320 px monochrome
                 else
                     set_both_strides(13)    ; 160 increment = 2 line in 640 px monochrome
@@ -342,9 +342,9 @@ drawmode:               ora  cx16.r15L
                 }
             }
         } else {
-            position2(xx,yy,true)
+            position2(xx,yy)
             cx16.r15 = ~cx16.r15    ; erase pixels
-            if width==320
+            if lores_mode
                 set_both_strides(11)    ; 40 increment = 1 line in 320 px monochrome
             else
                 set_both_strides(12)    ; 80 increment = 1 line in 640 px monochrome
@@ -401,15 +401,14 @@ drawmode:               ora  cx16.r15L
         }
         word @zp dx2 = dx*2
         word @zp dy2 = dy*2
-        cx16.r14 = x1       ; internal plot X
 
         if dx >= dy {
             if cx16.r1L!=0 {
                 repeat {
-                    plot(cx16.r14, y1, draw)
-                    if cx16.r14==x2
+                    plot(x1, y1, draw)
+                    if x1==x2
                         return
-                    cx16.r14++
+                    x1++
                     d += dy2
                     if d > dx {
                         y1++
@@ -418,10 +417,10 @@ drawmode:               ora  cx16.r15L
                 }
             } else {
                 repeat {
-                    plot(cx16.r14, y1, draw)
-                    if cx16.r14==x2
+                    plot(x1, y1, draw)
+                    if x1==x2
                         return
-                    cx16.r14--
+                    x1--
                     d += dy2
                     if d > dx {
                         y1++
@@ -433,25 +432,25 @@ drawmode:               ora  cx16.r15L
         else {
             if cx16.r1L!=0 {
                 repeat {
-                    plot(cx16.r14, y1, draw)
+                    plot(x1, y1, draw)
                     if y1 == y2
                         return
                     y1++
                     d += dx2
                     if d > dy {
-                        cx16.r14++
+                        x1++
                         d -= dy2
                     }
                 }
             } else {
                 repeat {
-                    plot(cx16.r14, y1, draw)
+                    plot(x1, y1, draw)
                     if y1 == y2
                         return
                     y1++
                     d += dx2
                     if d > dy {
-                        cx16.r14--
+                        x1--
                         d -= dy2
                     }
                 }
@@ -655,6 +654,11 @@ nostipple:
                 %asm {{
                     tsb  cx16.VERA_DATA0
                 }}
+            } else {
+                prepare()
+                %asm {{
+                    trb  cx16.VERA_DATA0
+                }}
             }
         } else {
             ; only erase
@@ -675,26 +679,51 @@ invert:
         return
 
         sub prepare() {
-            %asm {{
-                lda  p8v_xx
-                and  #7
-                pha     ; xbits
-            }}
-            xx /= 8
-            if width==320
-                xx += yy*(320/8)
-            else
+            if lores_mode {
+                %asm {{
+                    stz  cx16.VERA_CTRL
+                    stz  cx16.VERA_ADDR_H
+
+                    lda  p8v_xx+1
+                    lsr  a
+                    lda  p8v_xx
+                    ror  a
+                    lsr  a
+                    lsr  a
+
+                    clc
+                    ldy  p8v_yy
+                    adc  p8v_times40_lsb,y
+                    sta  cx16.VERA_ADDR_L
+                    lda  p8v_times40_msb,y
+                    adc  #0
+                    sta  cx16.VERA_ADDR_M
+
+                    lda  p8v_xx
+                    and  #7
+                    tax
+                    lda  p8v_maskbits,x
+                }}
+            } else {
+                ; width=640 (hires)
+                %asm {{
+                    stz  cx16.VERA_CTRL
+                    stz  cx16.VERA_ADDR_H
+                    lda  p8v_xx
+                    and  #7
+                    pha     ; xbits
+                }}
+                xx /= 8
                 xx += yy*(640/8)
-            %asm {{
-                stz  cx16.VERA_CTRL
-                stz  cx16.VERA_ADDR_H
-                lda  p8v_xx+1
-                sta  cx16.VERA_ADDR_M
-                lda  p8v_xx
-                sta  cx16.VERA_ADDR_L
-                ply     ; xbits
-                lda  p8v_maskbits,y
-            }}
+                %asm {{
+                    lda  p8v_xx+1
+                    sta  cx16.VERA_ADDR_M
+                    lda  p8v_xx
+                    sta  cx16.VERA_ADDR_L
+                    plx     ; xbits
+                    lda  p8v_maskbits,x
+                }}
+            }
         }
     }
 
@@ -714,8 +743,19 @@ invert:
             pha     ; xbits
         }}
         xx /= 8
-        if width==320
-            xx += yy*(320/8)
+        if lores_mode {
+            %asm {{
+                ; xx += yy * 40
+                ldy  p8v_yy
+                lda  p8v_xx
+                clc
+                adc  p8v_times40_lsb,y
+                sta  p8v_xx
+                lda  p8v_xx+1
+                adc  p8v_times40_msb,y
+                sta  p8v_xx+1
+            }}
+        }
         else
             xx += yy*(640/8)
 
@@ -826,8 +866,19 @@ skip:
                 pha     ; xbits
             }}
             xpos /= 8
-            if width==320
-                xpos += yy*(320/8) as uword
+            if lores_mode {
+                %asm {{
+                    ; xpos += yy*40
+                    ldy  p8v_yy
+                    lda  p8v_xpos
+                    clc
+                    adc  p8v_times40_lsb,y
+                    sta  p8v_xpos
+                    lda  p8v_xpos+1
+                    adc  p8v_times40_msb,y
+                    sta  p8v_xpos+1
+                }}
+            }
             else
                 xpos += yy*(640/8) as uword
 
@@ -848,10 +899,23 @@ skip:
                 eor  cx16.r11L
                 beq  +
                 rts
-+               ; cx16.r10L = new color to set
++               ; cx16.r10L = new color to set, check stipple mode
+                lda  p8v_mode
+                and  #1
+                beq  _normal
+                ; stipple drawing
+                lda  p8v_xx
+                eor  p8v_yy
+                and  #1
+                php
+                lda  p8s_plot.p8v_maskbits,y
+                plp
+                bra  _doplot
+
+_normal         ; cx16.r10L = new color to set
                 lda  p8s_plot.p8v_maskbits,y
                 ldx  cx16.r10L
-                beq  +
+_doplot         beq  +
                 tsb  cx16.VERA_DATA0
                 bra  ++
 +               trb  cx16.VERA_DATA0
@@ -861,20 +925,63 @@ skip:
         }
     }
 
-    sub position(uword @zp xx, uword yy) {
-        if width==320
-            cx16.r0 = yy*(320/8)
-        else
+    sub position(uword xx, uword yy) {
+        if lores_mode {
+            %asm {{
+                stz  cx16.VERA_CTRL
+                lda  p8v_xx+1
+                lsr  a
+                lda  p8v_xx
+                ror  a
+                lsr  a
+                lsr  a
+                clc
+                ldy  p8v_yy
+                adc  p8v_times40_lsb,y
+                sta  cx16.VERA_ADDR_L
+                lda  p8v_times40_msb,y
+                adc  #0
+                sta  cx16.VERA_ADDR_M
+                lda  #%00010000     ; autoincr
+                sta  cx16.VERA_ADDR_H
+            }}
+        }
+        else {
             cx16.r0 = yy*(640/8)
-        cx16.vaddr(0, cx16.r0+(xx/8), 0, 1)
+            cx16.vaddr(0, cx16.r0+(xx/8), 0, 1)
+        }
+        return
     }
 
-    sub position2(uword @zp xx, uword yy, bool also_port_1) {
+    sub position2(uword xx, uword yy) {
         position(xx, yy)
-        if also_port_1
-            cx16.vaddr_clone(0)
+        ; also set port 1 like that
+        cx16.vaddr_clone(0)
     }
 
+    ; y*40 lookup table. Pretty compact because it all fits in a word and we only need 240 y positions.
+    ; a y*80 lookup table would be very large (lo,mid,hi for 480 values...)
+    uword[240] @split @shared times40 = [
+        0, 40, 80, 120, 160, 200, 240, 280, 320, 360, 400, 440, 480, 520, 560, 600,
+        640, 680, 720, 760, 800, 840, 880, 920, 960, 1000, 1040, 1080, 1120, 1160,
+        1200, 1240, 1280, 1320, 1360, 1400, 1440, 1480, 1520, 1560, 1600, 1640, 1680,
+        1720, 1760, 1800, 1840, 1880, 1920, 1960, 2000, 2040, 2080, 2120, 2160, 2200,
+        2240, 2280, 2320, 2360, 2400, 2440, 2480, 2520, 2560, 2600, 2640, 2680, 2720,
+        2760, 2800, 2840, 2880, 2920, 2960, 3000, 3040, 3080, 3120, 3160, 3200, 3240,
+        3280, 3320, 3360, 3400, 3440, 3480, 3520, 3560, 3600, 3640, 3680, 3720, 3760,
+        3800, 3840, 3880, 3920, 3960, 4000, 4040, 4080, 4120, 4160, 4200, 4240, 4280,
+        4320, 4360, 4400, 4440, 4480, 4520, 4560, 4600, 4640, 4680, 4720, 4760, 4800,
+        4840, 4880, 4920, 4960, 5000, 5040, 5080, 5120, 5160, 5200, 5240, 5280, 5320,
+        5360, 5400, 5440, 5480, 5520, 5560, 5600, 5640, 5680, 5720, 5760, 5800, 5840,
+        5880, 5920, 5960, 6000, 6040, 6080, 6120, 6160, 6200, 6240, 6280, 6320, 6360,
+        6400, 6440, 6480, 6520, 6560, 6600, 6640, 6680, 6720, 6760, 6800, 6840, 6880,
+        6920, 6960, 7000, 7040, 7080, 7120, 7160, 7200, 7240, 7280, 7320, 7360, 7400,
+        7440, 7480, 7520, 7560, 7600, 7640, 7680, 7720, 7760, 7800, 7840, 7880, 7920,
+        7960, 8000, 8040, 8080, 8120, 8160, 8200, 8240, 8280, 8320, 8360, 8400, 8440,
+        8480, 8520, 8560, 8600, 8640, 8680, 8720, 8760, 8800, 8840, 8880, 8920, 8960,
+        9000, 9040, 9080, 9120, 9160, 9200, 9240, 9280, 9320, 9360, 9400, 9440, 9480,
+        9520, 9560]
+
     const ubyte charset_bank = $1
     const uword charset_addr = $f000       ; in bank 1, so $1f000
 
@@ -931,7 +1038,7 @@ skip:
                 bne  --
             }}
             ; left part of shifted char
-            position2(xx, yy, true)
+            position2(xx, yy)
             set_autoincrs()
             if draw {
                 %asm {{
@@ -957,7 +1064,7 @@ cdraw_mod1          ora  cx16.VERA_DATA1
             }
             ; right part of shifted char
             if lsb(xx) & 7 !=0 {
-                position2(xx+8, yy, true)
+                position2(xx+8, yy)
                 set_autoincrs()
                 if draw {
                     %asm {{
@@ -988,7 +1095,7 @@ cdraw_mod2              ora  cx16.VERA_DATA1
 
         sub set_autoincrs() {
             ; set autoincrements to go to next pixel row (40 or 80 increment)
-            if width==320 {
+            if lores_mode {
                 cx16.VERA_CTRL = 1
                 cx16.VERA_ADDR_H = cx16.VERA_ADDR_H & $0f | (11<<4)
                 cx16.VERA_CTRL = 0

compiler/res/prog8lib/cx16/psg.p8

@@ -73,6 +73,8 @@ psg {
     sub pulse_width(ubyte voice_num, ubyte pw) {
         ; -- Modifies the pulse width of this voice (when waveform=PULSE)
         ;    voice_num = 0-15, pw = 0-63  where 0=narrow, 63=50%cycle so square wave.
+        ;    When Waveform is TRIANGLE or SAWTOOTH, it sets the XOR mode parameter instead.
+        ;    (see the Vera reference manual for the exact description of this)
         cx16.vpoke_mask(1, $f9c3 + voice_num * 4, %11000000, pw)
     }
 

compiler/res/prog8lib/cx16/sprites.p8

@@ -1,7 +1,9 @@
 ; Simple routines to control sprites.
+
 ; They're not written for high performance, but for simplicity.
-; That's why they control 1 sprite at a time. The exception is pos_batch().
-; which is quite efficient to update sprite positions of multiple sprites in one go.
+; That's why they control 1 sprite at a time. \
+; The exceptions are pos_batch() and pos_batch_split(); these are quite efficient
+; to update sprite positions of multiple sprites in one call.
 
 ; note: sprites z-order will be in front of all layers.
 ; note: collision mask is not supported here yet.
@@ -173,6 +175,14 @@ sprites {
         return mkword(cx16.vpeek(1, sprite_reg+1), cx16.vpeek(1, sprite_reg)) as word
     }
 
+    sub getxy(ubyte spritenum) -> word, word {
+        sprite_reg = VERA_SPRITEREGS + 2 + spritenum*$0008
+        cx16.r0s = mkword(cx16.vpeek(1, sprite_reg+1), cx16.vpeek(1, sprite_reg)) as word
+        sprite_reg += 2
+        cx16.r1s = mkword(cx16.vpeek(1, sprite_reg+1), cx16.vpeek(1, sprite_reg)) as word
+        return cx16.r0s, cx16.r1s
+    }
+
     sub hide(ubyte spritenum) {
         cx16.vpoke_and(1, VERA_SPRITEREGS + 6 + spritenum*$0008, %11110011)
     }

compiler/res/prog8lib/cx16/syslib.p8

@@ -484,6 +484,7 @@ extsub $C006 = x16edit_loadfile_options(ubyte firstbank @X, ubyte lastbank @Y, s
                 uword disknumberAndColors @R3, uword headerAndStatusColors @R4) clobbers(A,X,Y)
 
 ; Audio (rom bank 10)
+; NOTE: because these are auto-banked, you should not call them from an IRQ handler routine (due to jsrfar race condition).
 extsub @bank 10  $C09F = audio_init() clobbers(A,X,Y) -> bool @Pc     ; (re)initialize both vera PSG and YM audio chips
 extsub @bank 10  $C000 = bas_fmfreq(ubyte channel @A, uword freq @XY, bool noretrigger @Pc) clobbers(A,X,Y) -> bool @Pc
 extsub @bank 10  $C003 = bas_fmnote(ubyte channel @A, ubyte note @X, ubyte fracsemitone @Y, bool noretrigger @Pc) clobbers(A,X,Y) -> bool @Pc
@@ -556,6 +557,7 @@ const ubyte  EXTAPI_led_update = $0B
 const ubyte  EXTAPI_mouse_set_position = $0C
 const ubyte  EXTAPI_scnsiz = $0D
 const ubyte  EXTAPI_kbd_leds = $0E
+const ubyte  EXTAPI_memory_decompress_from_func = $0F
 
 ; extapi16 call numbers
 const ubyte  EXTAPI16_test = $00
@@ -666,6 +668,30 @@ asmsub scnsiz(ubyte width @X, ubyte heigth @Y) clobbers(A,X,Y) {
     }}
 }
 
+asmsub get_charset() -> ubyte @A {
+    ;Get charset mode.  result: 0=unknown, 1=ISO, 2=PETSCII upper case/gfx, 3=PETSCII lowercase.
+    %asm {{
+
+KERNAL_MODE = $0372         ; internal kernal variable, risky to read it, but it's ben stable for many releases.
+        lda  KERNAL_MODE
+        beq  _end
+
+        bit  #$40                ;ISO mode flag
+        beq  +                   ;usually KERNAL_MODE 1 or 6 (| $40)
+        lda  #1
+        bra  _end
+
++       bit  #1                  ;PETSCII upper case/graphics
+        bne  +                   ;usually KERNAL_MODE 2 or 4
+        lda  #2
+        bra  _end
+
++       lda  #3                   ;PETSCII upper/lower case
+_end:
+        rts
+    }}
+}
+
 ; TODO : implement shims for the remaining extapi calls.
 
 
@@ -1948,6 +1974,8 @@ asmsub  cleanup_at_exit() {
         lda  #4
         sta  $01        ; rom bank 4 (basic)
         jsr  cbm.CLRCHN		; reset i/o channels
+        lda  #9
+        jsr  cbm.CHROUT     ; enable charset switch
 _exitcodeCarry = *+1
         lda  #0
         lsr  a

compiler/res/prog8lib/cx16/textio.p8

@@ -81,15 +81,15 @@ asmsub get_row() -> ubyte @X {
     }}
 }
 
-sub get_cursor(uword colptr, uword rowptr) {
+asmsub get_cursor() -> ubyte @X, ubyte @Y {
     %asm {{
         sec
-        jsr cbm.PLOT
-        tya
-        ldy #$00
-        sta (colptr),y
-        txa
-        sta (rowptr),y
+        jsr  cbm.PLOT
+        phx     ; swap X and Y
+        phy
+        plx
+        ply
+        rts
     }}
 }
 

compiler/res/prog8lib/math.asm

@@ -508,7 +508,6 @@ mul_word_9	.proc
 		tay
 		lda  P8ZP_SCRATCH_W1
 		rts
-		rts
 		.pend
 
 mul_byte_10	.proc

compiler/res/prog8lib/prog8_lib.asm

@@ -31,6 +31,13 @@ read_byte_from_address_in_AY_into_A	.proc
 		rts
 		.pend
 
+read_byte_from_address_in_AY_into_A_65c02	.proc
+		sta  P8ZP_SCRATCH_W2
+		sty  P8ZP_SCRATCH_W2+1
+		lda  (P8ZP_SCRATCH_W2)
+		rts
+		.pend
+
 
 write_byte_X_to_address_in_AY	.proc
 		sta  P8ZP_SCRATCH_W2
@@ -41,6 +48,14 @@ write_byte_X_to_address_in_AY	.proc
 		rts
 		.pend
 
+write_byte_X_to_address_in_AY_65c02	.proc
+		sta  P8ZP_SCRATCH_W2
+		sty  P8ZP_SCRATCH_W2+1
+		txa
+		sta  (P8ZP_SCRATCH_W2)
+		rts
+		.pend
+
 
 reg_less_uw	.proc
 		;  AY < P8ZP_SCRATCH_W2?

compiler/res/prog8lib/shared_cbm_diskio.p8

@@ -27,6 +27,7 @@ diskio {
         ; -- Prints the directory contents to the screen. Returns success.
 
         cbm.SETNAM(1, "$")
+internal_dir:
         cbm.SETLFS(READ_IO_CHANNEL, drivenumber, 0)
         ubyte status = 1
         void cbm.OPEN()          ; open 12,8,0,"$"
@@ -81,6 +82,19 @@ io_error:
         return true
     }
 
+    sub directory_dirs() -> bool {
+        ; -- Prints all entries on the disk to the screen, but only directories.  Returns success.
+        cbm.SETNAM(5, "$:*=c")      ; on C64 (1581 diskdrive) the type for directories is CBM
+        goto diskio.directory.internal_dir
+    }
+
+    sub directory_files() -> bool {
+        ; -- Prints all entries on the disk to the screen, but only actual files.  Returns success.
+        cbm.SETNAM(5, "$:*=p")
+        goto diskio.directory.internal_dir
+    }
+
+
     sub diskname() -> uword {
         ; -- Returns pointer to disk name string or 0 if failure.
 
@@ -140,7 +154,10 @@ io_error:
         ;    After the last filename one additional 0 byte is placed to indicate the end of the list.
         ;    Returns number of files (it skips 'dir' entries i.e. subdirectories).
         ;    Also sets carry on exit: Carry clear = all files returned, Carry set = directory has more files that didn't fit in the buffer.
-        uword buffer_start = filenames_buffer
+        ;    Note that no list of pointers of some form is returned, the names are just squashed together.
+        ;    If you really need a list of pointers to the names, that is pretty straightforward to construct by iterating over the names
+        ;    and registering when the next one starts after the 0-byte separator.
+    uword buffer_start = filenames_buffer
         ubyte files_found = 0
         if lf_start_list(pattern_ptr) {
             while lf_next_entry() {
@@ -167,12 +184,14 @@ io_error:
     sub lf_start_list(uword pattern_ptr) -> bool {
         ; -- start an iterative file listing with optional pattern matching.
         ;    note: only a single iteration loop can be active at a time!
+        cbm.SETNAM(1, "$")
+
+start_list_internal:
         lf_end_list()
         list_pattern = pattern_ptr
         list_skip_disk_name = true
         iteration_in_progress = true
 
-        cbm.SETNAM(1, "$")
         cbm.SETLFS(READ_IO_CHANNEL, drivenumber, 0)
         void cbm.OPEN()          ; open 12,8,0,"$"
         if_cs
@@ -192,6 +211,22 @@ io_error:
         return false
     }
 
+    sub lf_start_list_dirs(uword pattern_ptr) -> bool {
+        ; -- start an iterative directory contents listing with optional pattern matching.
+        ;    this version it only returns directory entries!
+        ;    note: only a single iteration loop can be active at a time!
+        cbm.SETNAM(5, "$:*=c")  ; on C64 (1581 diskdrive) the type for directories is CBM
+        goto diskio.lf_start_list.start_list_internal
+    }
+
+    sub lf_start_list_files(uword pattern_ptr) -> bool {
+        ; -- start an iterative directory contents listing with optional pattern matching.
+        ;    this version only returns actual file entries!
+        ;    note: only a single iteration loop can be active at a time!
+        cbm.SETNAM(5, "$:*=p")
+        goto diskio.lf_start_list.start_list_internal
+    }
+
     sub lf_next_entry() -> bool {
         ; -- retrieve the next entry from an iterative file listing session.
         ;    results will be found in list_blocks, list_filename, and list_filetype.
@@ -500,12 +535,11 @@ _end        jsr  cbm.READST
         @(messageptr) = 0
 
 done:
-        cbm.CLRCHN()        ; restore default i/o devices
         cbm.CLOSE(15)
+        cbm.CLRCHN()        ; restore default i/o devices
         return list_filename
 
 io_error:
-        cbm.CLOSE(15)
         list_filename = "io error"
         goto done
     }

compiler/res/prog8lib/sorting.p8

@@ -1,6 +1,7 @@
 ; **experimental** data sorting routines, API subject to change!!
 
 sorting {
+    %option ignore_unused
 
     ; GNOME SORT is tiny and extremely fast if the initial values are already almost sorted.
     ; SHELL SORT is quite a bit faster if the initial values are more randomly distributed.
@@ -19,12 +20,10 @@ sorting {
             dey
 +           dec  P8ZP_SCRATCH_W2
             sty  P8ZP_SCRATCH_W2+1
-            ldy  #0     ; pos
+            ldy  #1     ; pos
 _loop
             cpy  #0     ; modified
             beq  _done
-            cpy  #0
-            beq  +
             lda  (P8ZP_SCRATCH_W1),y
             cmp  (P8ZP_SCRATCH_W2),y
             bcs  +
@@ -35,7 +34,7 @@ _loop
             txa
             sta  (P8ZP_SCRATCH_W2),y
             dey
-            jmp  _loop
+            bne  _loop
 +           iny
             bne  _loop
 _done
@@ -47,11 +46,9 @@ _done
     prog8 source code for the above routine:
 
     sub gnomesort_ub(uword @requirezp values, ubyte num_elements) {
-        ubyte @zp pos
+        ubyte @zp pos=1
         while pos != num_elements {
-            if pos==0
-                pos++
-            else if values[pos]>=values[pos-1]
+            if values[pos]>=values[pos-1]
                 pos++
             else {
                 ; swap elements
@@ -59,6 +56,8 @@ _done
                 values[pos-1] = values[pos]
                 values[pos] = cx16.r0L
                 pos--
+                if_z
+                    pos++
             }
         }
     }
@@ -66,22 +65,22 @@ _done
 
     sub gnomesort_uw(uword values, ubyte num_elements) {
         ; TODO optimize this more, rewrite in asm?
-        uword @zp pos
-        cx16.r2 = num_elements*$0002
-        while pos != cx16.r2 {
-            uword @requirezp ptr = values+pos
-            if pos==0
-                pos += 2
+        ubyte @zp pos = 1
+        uword @requirezp ptr = values+2
+        while pos != num_elements {
+            cx16.r0 = peekw(ptr-2)
+            cx16.r1 = peekw(ptr)
+            if cx16.r0<=cx16.r1 {
+                pos++
+                ptr+=2
+            }
             else {
-                cx16.r0 = peekw(ptr-2)
-                cx16.r1 = peekw(ptr)
-                if cx16.r0<=cx16.r1
-                    pos += 2
-                else {
-                    ; swap elements
-                    pokew(ptr-2, cx16.r1)
-                    pokew(ptr, cx16.r0)
-                    pos -= 2
+                ; swap elements
+                pokew(ptr-2, cx16.r1)
+                pokew(ptr, cx16.r0)
+                if pos>1 {
+                    pos--
+                    ptr-=2
                 }
             }
         }
@@ -120,10 +119,9 @@ _done
                 uword @zp temp = peekw(values+i*$0002)
                 ubyte @zp j = i
                 ubyte @zp k = j-gap
-                repeat {
+                while j>=gap {
                     uword @zp v = peekw(values+k*2)
                     if v <= temp break
-                    if j < gap break
                     pokew(values+j*2, v)
                     j = k
                     k -= gap
@@ -144,11 +142,10 @@ _done
                 cx16.r1 = peekw(pointers+i*$0002)
                 ubyte @zp j = i
                 ubyte @zp k = j-gap
-                repeat {
+                while j>=gap {
                     cx16.r0 = peekw(pointers+k*2)
                     void call(comparefunc)
                     if_cs break
-                    if j < gap break
                     pokew(pointers+j*2, cx16.r0)
                     j = k
                     k -= gap

compiler/res/prog8lib/virtual/conv.p8

@@ -212,9 +212,9 @@ sub  str2uword(str string) -> uword {
     ;    the number may NOT be preceded by a + sign and may NOT contain spaces
     ;    (any non-digit character will terminate the number string that is parsed)
     %ir {{
-        loadm.w r65535,conv.str2uword.string
-        syscall 11 (r65535.w) : r0.w
-        returnr.w r0
+        loadm.w r99000,conv.str2uword.string
+        syscall 11 (r99000.w) : r99000.w
+        returnr.w r99000
     }}
 }
 
@@ -223,9 +223,9 @@ sub  str2word(str string) -> word {
     ;    the number may be preceded by a + or - sign but may NOT contain spaces
     ;    (any non-digit character will terminate the number string that is parsed)
     %ir {{
-        loadm.w r65535,conv.str2word.string
-        syscall 12 (r65535.w) : r0.w
-        returnr.w r0
+        loadm.w r99000,conv.str2word.string
+        syscall 12 (r99000.w) : r99000.w
+        returnr.w r99000
     }}
 }
 

compiler/res/prog8lib/virtual/diskio.p8

@@ -13,10 +13,8 @@ diskio {
     sub directory() -> bool {
         ; -- Prints the directory contents to the screen. Returns success.
         %ir {{
-            loadm.w r65534,diskio.load.filenameptr
-            loadm.w r65535,diskio.load.address_override
-            syscall 45 (): r0.b
-            returnr.b r0
+            syscall 45 (): r99100.b
+            returnr.b r99100
         }}
     }
 
@@ -26,6 +24,9 @@ diskio {
         ;    After the last filename one additional 0 byte is placed to indicate the end of the list.
         ;    Returns number of files (it skips 'dir' entries i.e. subdirectories).
         ;    Also sets carry on exit: Carry clear = all files returned, Carry set = directory has more files that didn't fit in the buffer.
+        ;    Note that no list of pointers of some form is returned, the names are just squashed together.
+        ;    If you really need a list of pointers to the names, that is pretty straightforward to construct by iterating over the names
+        ;    and registering when the next one starts after the 0-byte separator.
         txt.print("@TODO: list_filenames\n")
         sys.clear_carry()
         return 0
@@ -64,9 +65,9 @@ diskio {
         ;          if you're going to read from it yourself instead of using f_read()!
 
         %ir {{
-            loadm.w r65535,diskio.f_open.filenameptr
-            syscall 52 (r65535.w): r0.b
-            returnr.b r0
+            loadm.w r99000,diskio.f_open.filenameptr
+            syscall 52 (r99000.w): r99100.b
+            returnr.b r99100
         }}
     }
 
@@ -76,8 +77,8 @@ diskio {
         uword actual
         repeat num_bytes {
             %ir {{
-                syscall 54 (): r0.w
-                storem.w r0,$ff02
+                syscall 54 (): r99000.w
+                storem.w r99000,$ff02
             }}
             if cx16.r0H==0
                 return actual
@@ -94,8 +95,8 @@ diskio {
         uword actual
         repeat {
             %ir {{
-                syscall 54 (): r0.w
-                storem.w r0,$ff02
+                syscall 54 (): r99000.w
+                storem.w r99000,$ff02
             }}
             if cx16.r0H==0
                 return actual
@@ -114,8 +115,8 @@ diskio {
         ubyte size
         repeat {
             %ir {{
-                syscall 54 (): r0.w
-                storem.w r0,$ff02
+                syscall 54 (): r99000.w
+                storem.w r99000,$ff02
             }}
 
             if cx16.r0H==0 {
@@ -157,9 +158,9 @@ diskio {
         ;    To be 100% sure if this call was successful, you have to use status()
         ;    and check the drive's status message!
         %ir {{
-            loadm.w r65535,diskio.f_open_w.filenameptr
-            syscall 53 (r65535.w): r0.b
-            returnr.b r0
+            loadm.w r99000,diskio.f_open_w.filenameptr
+            syscall 53 (r99000.w): r99100.b
+            returnr.b r99100
         }}
     }
 
@@ -169,9 +170,9 @@ diskio {
         repeat num_bytes {
             %ir {{
                 loadm.w r0,diskio.f_write.bufferpointer
-                loadi.b r1,r0
-                syscall 55 (r1.b): r0.b
-                storem.b r0,$ff02
+                loadi.b r99100,r0
+                syscall 55 (r99100.b): r99100.b
+                storem.b r99100,$ff02
             }}
             if cx16.r0L==0
                 return false
@@ -194,32 +195,32 @@ diskio {
     sub chdir(str path) {
         ; -- change current directory.
         %ir {{
-            loadm.w r65535,diskio.chdir.path
-            syscall 50 (r65535.w)
+            loadm.w r99000,diskio.chdir.path
+            syscall 50 (r99000.w)
         }}
     }
 
     sub mkdir(str name) {
         ; -- make a new subdirectory.
         %ir {{
-            loadm.w r65535,diskio.mkdir.name
-            syscall 49 (r65535.w)
+            loadm.w r99000,diskio.mkdir.name
+            syscall 49 (r99000.w)
         }}
     }
 
     sub rmdir(str name) {
         ; -- remove a subdirectory.
         %ir {{
-            loadm.w r65535,diskio.rmdir.name
-            syscall 51 (r65535.w)
+            loadm.w r99000,diskio.rmdir.name
+            syscall 51 (r99000.w)
         }}
     }
 
     sub curdir() -> uword {
         ; return current directory name or 0 if error
         %ir {{
-            syscall 48 (): r0.w
-            returnr.w r0
+            syscall 48 (): r99000.w
+            returnr.w r99000
         }}
     }
 
@@ -236,24 +237,24 @@ diskio {
 
     sub save(uword filenameptr, uword start_address, uword savesize) -> bool {
         %ir {{
-            load.b r65532,0
-            loadm.w r65533,diskio.save.filenameptr
-            loadm.w r65534,diskio.save.start_address
-            loadm.w r65535,diskio.save.savesize
-            syscall 42 (r65532.b, r65533.w, r65534.w, r65535.w): r0.b
-            returnr.b r0
+            load.b r99100,0
+            loadm.w r99000,diskio.save.filenameptr
+            loadm.w r99001,diskio.save.start_address
+            loadm.w r99002,diskio.save.savesize
+            syscall 42 (r99100.b, r99000.w, r99001.w, r99002.w): r99100.b
+            returnr.b r99100
         }}
     }
 
     ; like save() but omits the 2 byte prg header.
     sub save_raw(uword filenameptr, uword startaddress, uword savesize) -> bool {
         %ir {{
-            load.b r65532,1
-            loadm.w r65533,diskio.save.filenameptr
-            loadm.w r65534,diskio.save.start_address
-            loadm.w r65535,diskio.save.savesize
-            syscall 42 (r65532.b, r65533.w, r65534.w, r65535.w): r0.b
-            returnr.b r0
+            load.b r99100,1
+            loadm.w r99000,diskio.save.filenameptr
+            loadm.w r99001,diskio.save.start_address
+            loadm.w r99002,diskio.save.savesize
+            syscall 42 (r99100.b, r99000.w, r99001.w, r99002.w): r99100.b
+            returnr.b r99100
         }}
     }
 
@@ -265,10 +266,10 @@ diskio {
     ; Returns the end load address+1 if successful or 0 if a load error occurred.
     sub load(uword filenameptr, uword address_override) -> uword {
         %ir {{
-            loadm.w r65534,diskio.load.filenameptr
-            loadm.w r65535,diskio.load.address_override
-            syscall 40 (r65534.w, r65535.w): r0.w
-            returnr.w r0
+            loadm.w r99000,diskio.load.filenameptr
+            loadm.w r99001,diskio.load.address_override
+            syscall 40 (r99000.w, r99001.w): r99002.w
+            returnr.w r99002
         }}
     }
 
@@ -277,27 +278,27 @@ diskio {
     ; See comments on load() for more details.
     sub load_raw(uword filenameptr, uword start_address) -> uword {
         %ir {{
-            loadm.w r65534,diskio.load_raw.filenameptr
-            loadm.w r65535,diskio.load_raw.start_address
-            syscall 41 (r65534.w, r65535.w): r0.w
-            returnr.w r0
+            loadm.w r99000,diskio.load_raw.filenameptr
+            loadm.w r99001,diskio.load_raw.start_address
+            syscall 41 (r99000.w, r99001.w): r99002.w
+            returnr.w r99002
         }}
     }
 
     sub delete(uword filenameptr) {
         ; -- delete a file on the drive
         %ir {{
-            loadm.w r65535,diskio.delete.filenameptr
-            syscall 43 (r65535.w)
+            loadm.w r99000,diskio.delete.filenameptr
+            syscall 43 (r99000.w)
         }}
     }
 
     sub rename(uword oldfileptr, uword newfileptr) {
         ; -- rename a file on the drive
         %ir {{
-            loadm.w r65534,diskio.rename.oldfileptr
-            loadm.w r65535,diskio.rename.newfileptr
-            syscall 44 (r65534.w, r65535.w)
+            loadm.w r99000,diskio.rename.oldfileptr
+            loadm.w r99001,diskio.rename.newfileptr
+            syscall 44 (r99000.w, r99001.w)
         }}
     }
 

compiler/res/prog8lib/virtual/floats.p8

@@ -35,8 +35,8 @@ floats {
 sub print(float value) {
     ; ---- prints the floating point value (without a newline and no leading spaces).
     %ir {{
-        loadm.f fr65535,floats.print.value
-        syscall 15 (fr65535.f)
+        loadm.f fr99000,floats.print.value
+        syscall 15 (fr99000.f)
         return
     }}
 }
@@ -45,20 +45,20 @@ sub tostr(float value) -> str {
     ; ---- converts the floating point value to a string (no leading spaces)
     str @shared buffer=" "*20
     %ir {{
-        load.w r65535,floats.tostr.buffer
-        loadm.f fr65535,floats.tostr.value
-        syscall 34 (r65535.w, fr65535.f)
-        load.w r0,floats.tostr.buffer
-        returnr.w r0
+        load.w r99000,floats.tostr.buffer
+        loadm.f fr99000,floats.tostr.value
+        syscall 34 (r99000.w, fr99000.f)
+        load.w r99000,floats.tostr.buffer
+        returnr.w r99000
     }}
 }
 
 sub parse(str value) -> float {
     ; -- parse a string value of a number to float
     %ir {{
-        loadm.w  r65535,floats.parse.value
-        syscall 32 (r65535.w): fr0.f
-        returnr.f fr0
+        loadm.w  r99000,floats.parse.value
+        syscall 32 (r99000.w): fr99000.f
+        returnr.f fr99000
     }}
 }
 
@@ -170,15 +170,15 @@ sub ceil(float value) -> float {
 
 sub rnd() -> float {
     %ir {{
-        syscall 22 () : fr0.f
-        returnr.f fr0
+        syscall 22 () : fr99000.f
+        returnr.f fr99000
     }}
 }
 
 sub rndseed(float seed) {
     %ir {{
-        loadm.f  fr65535,floats.rndseed.seed
-        syscall 19 (fr65535.f)
+        loadm.f  fr99000,floats.rndseed.seed
+        syscall 19 (fr99000.f)
         return
     }}
 }
@@ -213,16 +213,16 @@ sub normalize(float value) -> float {
 sub push(float value) {
     ; note: this *should* be inlined, however since the VM has separate program counter and value stacks, this also works
     %ir {{
-        loadm.f  fr65535,floats.push.value
-        push.f  fr65535
+        loadm.f  fr99000,floats.push.value
+        push.f  fr99000
     }}
 }
 
 sub pop() -> float {
     ; note: this *should* be inlined, however since the VM has separate program counter and value stacks, this also works
     %ir {{
-        pop.f  fr65535
-        returnr.f fr65535
+        pop.f  fr99000
+        returnr.f fr99000
     }}
 }