Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N|Running in 64-bit mode
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:61:130:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:55:129:64|Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:38:127:40|Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ...
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register SM_AMIGA
Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.