68030tk/Logic/68030_tk.rpt

|--------------------------------------------|
|- ispLEVER Fitter Report File              -|
|- Version 1.7.00.05.28.13                       -|
|- (c)Copyright, Lattice Semiconductor 2002 -|
|--------------------------------------------|




Project_Summary
~~~~~~~~~~~~~~~

Project Name :          68030_tk
Project Path :          C:\Users\Matze\Documents\GitHub\68030tk\Logic
Project Fitted on :     Sun Jun 15 16:36:48 2014

Device :                M4A5-128/64
Package :               100TQFP
Speed :                 -10
Partnumber :            M4A5-128/64-10VC
Source Format :         Pure_VHDL


// Project '68030_tk' was Fitted Successfully! //


Compilation_Times
~~~~~~~~~~~~~~~~~
Reading/DRC                                   0 sec
Partition                                     0 sec
Place                                         0 sec
Route                                         0 sec
Jedec/Report generation                       0 sec
                                         --------
Fitter                                   00:00:00


Design_Summary
~~~~~~~~~~~~~~
  Total Input Pins :                 30
  Total Output Pins :                17
  Total Bidir I/O Pins :             12
  Total Flip-Flops :                 64
  Total Product Terms :             158
  Total Reserved Pins :               0
  Total Reserved Blocks :             0


Device_Resource_Summary
~~~~~~~~~~~~~~~~~~~~~~~
                                 Total
                               Available  Used  Available  Utilization
Dedicated Pins
  Input-Only Pins                 2        2      0    -->   100%
  Clock/Input Pins                4        4      0    -->   100%
I/O Pins                         64       53     11    -->    82%
Logic Macrocells                128       74     54    -->    57%
  Input Registers                64        0     64    -->     0%
  Unusable Macrocells            ..        0     ..

CSM Outputs/Total Block Inputs  264      193     71    -->    73%
Logical Product Terms           640      162    478    -->    25%
Product Term Clusters           128       44     84    -->    34%


Blocks_Resource_Summary
~~~~~~~~~~~~~~~~~~~~~~~
                                                                  # of PT  
                   I/O    Inp    Macrocells   Macrocells   logic  clusters 
          Fanin    Pins   Reg   Used Unusable  available    PTs   available  Pwr
---------------------------------------------------------------------------------
Maximum     33      8      8     --     --         16       80       16       -
---------------------------------------------------------------------------------
Block  A    19      7      0     10      0          6       24        9       Hi 
Block  B    26      8      0      9      0          7       20       11       Hi 
Block  C    21      8      0      9      0          7       13       13       Hi 
Block  D    28      8      0      9      0          7       21       10       Hi 
Block  E    25      3      0     10      0          6       13       14       Hi 
Block  F    22      4      0      9      0          7       35        5       Hi 
Block  G    24      7      0      9      0          7       17       13       Hi 
Block  H    28      8      0      9      0          7       19       10       Hi 
---------------------------------------------------------------------------------

<Note> Four rightmost columns above reflect last status of the placement process.
<Note> Pwr (Power) : Hi = High
                     Lo = Low.


Optimizer_and_Fitter_Options
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Pin Assignment :                       Yes
Group Assignment :                     No
Pin Reservation :                      No (1)
Block Reservation :                    No

@Ignore_Project_Constraints :
  Pin Assignments :                    No
      Keep Block Assignment            --
      Keep Segment Assignment          --
  Group Assignments :                  No
  Macrocell Assignment :               No
      Keep Block Assignment            --
      Keep Segment Assignment          --

@Backannotate_Project_Constraints
  Pin Assignments :                    No
  Pin And Block Assignments :          No
  Pin, Macrocell and Block :           No

@Timing_Constraints :                  No

@Global_Project_Optimization :
  Balanced Partitioning :              Yes
  Spread Placement :                   Yes

  Note :
    Pack Design :
       Balanced Partitioning = No
       Spread Placement      = No
    Spread Design :
       Balanced Partitioning = Yes
       Spread Placement      = Yes

@Logic_Synthesis :
  Logic Reduction :                    Yes
  Node Collapsing :                    Yes
  D/T Synthesis :                      Yes
  Clock Optimization :                 No
  Input Register Optimization :        Yes
  XOR Synthesis :                      Yes
  Max. P-Term for Collapsing :         16
  Max. P-Term for Splitting :          16
  Max. Equation Fanin :                32
  Keep Xor :                           Yes

@Utilization_options
  Max. % of macrocells used :          100
  Max. % of block inputs used :        100
  Max. % of segment lines used :       ---
  Max. % of macrocells used :          ---


@Import_Source_Constraint_Option       No

@Zero_Hold_Time                        Yes

@Pull_up                               Yes

@User_Signature                        #H0

@Output_Slew_Rate                      Default = Slow(2)

@Power                                 Default = High(2)


Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
           follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output, 
           Bidir and Burried Signal Lists.




Pinout_Listing
~~~~~~~~~~~~~~
      | Pin  |Blk |Assigned|
Pin No| Type |Pad |Pin     | Signal name
---------------------------------------------------------------
    1 |  GND |    |        |
    2 | JTAG |    |        |
    3 |  I_O | B7 |   *    |RESET
4     |  I_O | B6 |   *    |A_31_
5     |  I_O | B5 |   *    |A_30_
6     |  I_O | B4 |   *    |A_29_
7     |  I_O | B3 |   *    |IPL_030_1_
8     |  I_O | B2 |   *    |IPL_030_0_
9     |  I_O | B1 |   *    |IPL_030_2_
10    |  I_O | B0 |   *    |CLK_EXP
11    | CkIn |    |   *    |CLK_000
12    |  Vcc |    |        |
13    |  GND |    |        |
14    | CkIn |    |   *    |nEXP_SPACE
15    |  I_O | C0 |   *    |A_28_
16    |  I_O | C1 |   *    |A_27_
17    |  I_O | C2 |   *    |A_26_
18    |  I_O | C3 |   *    |A_25_
19    |  I_O | C4 |   *    |A_24_
20    |  I_O | C5 |   *    |AMIGA_BUS_ENABLE_LOW
21    |  I_O | C6 |   *    |BG_030
22    |  I_O | C7 |   *    |AVEC_EXP
23    | JTAG |    |        |
24    | JTAG |    |        |
25    |  GND |    |        |
26    |  GND |    |        |
27    |  GND |    |        |
28    |  I_O | D7 |   *    |BGACK_000
29    |  I_O | D6 |   *    |BG_000
30    |  I_O | D5 |   *    |DTACK
31    |  I_O | D4 |   *    |LDS_000
32    |  I_O | D3 |   *    |UDS_000
33    |  I_O | D2 |   *    |AS_000
34    |  I_O | D1 |   *    |AMIGA_BUS_ENABLE
35    |  I_O | D0 |   *    |VMA
36    |  Inp |    |   *    |VPA
37    |  Vcc |    |        |
38    |  GND |    |        |
39    |  GND |    |        |
40    |  Vcc |    |        |
41    |  I_O | E0 |   *    |BERR
42    |  I_O | E1 |        |
43    |  I_O | E2 |        |
44    |  I_O | E3 |        |
45    |  I_O | E4 |        |
46    |  I_O | E5 |        |
47    |  I_O | E6 |   *    |CIIN
48    |  I_O | E7 |   *    |AMIGA_BUS_DATA_DIR
49    |  GND |    |        |
50    |  GND |    |        |
51    |  GND |    |        |
52    | JTAG |    |        |
53    |  I_O | F7 |        |
54    |  I_O | F6 |        |
55    |  I_O | F5 |        |
56    |  I_O | F4 |   *    |IPL_1_
57    |  I_O | F3 |   *    |FC_0_
58    |  I_O | F2 |   *    |FC_1_
59    |  I_O | F1 |   *    |A_17_
60    |  I_O | F0 |        |
61    | CkIn |    |   *    |CLK_OSZI
62    |  Vcc |    |        |
63    |  GND |    |        |
64    | CkIn |    |   *    |CLK_030
65    |  I_O | G0 |   *    |CLK_DIV_OUT
66    |  I_O | G1 |   *    |E
67    |  I_O | G2 |   *    |IPL_0_
68    |  I_O | G3 |   *    |IPL_2_
69    |  I_O | G4 |   *    |A0
70    |  I_O | G5 |   *    |SIZE_0_
71    |  I_O | G6 |   *    |RW
72    |  I_O | G7 |        |
73    | JTAG |    |        |
74    | JTAG |    |        |
75    |  GND |    |        |
76    |  GND |    |        |
77    |  GND |    |        |
78    |  I_O | H7 |   *    |FPU_CS
79    |  I_O | H6 |   *    |SIZE_1_
80    |  I_O | H5 |   *    |RW_000
81    |  I_O | H4 |   *    |DSACK1
82    |  I_O | H3 |   *    |AS_030
83    |  I_O | H2 |   *    |BGACK_030
84    |  I_O | H1 |   *    |A_23_
85    |  I_O | H0 |   *    |A_22_
86    |  Inp |    |   *    |RST
87    |  Vcc |    |        |
88    |  GND |    |        |
89    |  GND |    |        |
90    |  Vcc |    |        |
91    |  I_O | A0 |        |
92    |  I_O | A1 |   *    |AVEC
93    |  I_O | A2 |   *    |A_20_
94    |  I_O | A3 |   *    |A_21_
95    |  I_O | A4 |   *    |A_18_
96    |  I_O | A5 |   *    |A_16_
97    |  I_O | A6 |   *    |A_19_
98    |  I_O | A7 |   *    |DS_030
99    |  GND |    |        |
100   |  GND |    |        |

---------------------------------------------------------------------------

<Note> Blk Pad : This notation refers to the Block I/O pad number in the device.
<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
<Note> Pin Type : 
           CkIn : Dedicated input or clock pin 
           CLK  : Dedicated clock pin
           INP  : Dedicated input pin
           JTAG : JTAG Control and test pin
           NC   : No connected



Input_Signal_List
~~~~~~~~~~~~~~~~~
                 P R
            Pin  r e O   Input 
Pin Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
----------------------------------------------------------------------
 96  A   .  I/O          -B-----H   Hi Slow      A_16_   
 59  F   .  I/O          -B-----H   Hi Slow      A_17_   
 95  A   .  I/O          -B-----H   Hi Slow      A_18_   
 97  A   .  I/O          -B-----H   Hi Slow      A_19_   
 93  A   .  I/O          ----E---   Hi Slow      A_20_   
 94  A   .  I/O          ----E---   Hi Slow      A_21_   
 85  H   .  I/O          ----E---   Hi Slow      A_22_   
 84  H   .  I/O          ----E---   Hi Slow      A_23_   
 19  C   .  I/O          ----E---   Hi Slow      A_24_   
 18  C   .  I/O          ----E---   Hi Slow      A_25_   
 17  C   .  I/O          ----E---   Hi Slow      A_26_   
 16  C   .  I/O          ----E---   Hi Slow      A_27_   
 15  C   .  I/O          ----E---   Hi Slow      A_28_   
  6  B   .  I/O          ----E---   Hi Slow      A_29_   
  5  B   .  I/O          ----E---   Hi Slow      A_30_   
  4  B   .  I/O          ----E---   Hi Slow      A_31_   
 41  E   .  I/O          -BCD-F-H   Hi Slow      BERR   
 28  D   .  I/O          -B-----H   Hi Slow      BGACK_000   
 21  C   .  I/O          ---D----   Hi Slow      BG_030   
 57  F   .  I/O          -B-----H   Hi Slow      FC_0_   
 58  F   .  I/O          -B-----H   Hi Slow      FC_1_   
 67  G   .  I/O          -B------   Hi Slow      IPL_0_   
 56  F   .  I/O          -B------   Hi Slow      IPL_1_   
 68  G   .  I/O          -B------   Hi Slow      IPL_2_   
 11  .   . Ck/I          --C-----   -  Slow      CLK_000   
 14  .   . Ck/I          AB-DEFGH   -  Slow      nEXP_SPACE   
 36  .   .  Ded          -B---F--   -  Slow      VPA   
 61  .   . Ck/I          ABCDEFGH   -  Slow      CLK_OSZI   
 64  .   . Ck/I          A-----GH   -  Slow      CLK_030   
 86  .   .  Ded          ABCDEFGH   -  Slow      RST   
----------------------------------------------------------------------

<Note> Power : Hi = High
               MH = Medium High
               ML = Medium Low
               Lo = Low



Output_Signal_List
~~~~~~~~~~~~~~~~~~
                 P R
            Pin  r e O   Output 
Pin Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
----------------------------------------------------------------------
 48  E   2  COM          --------   Hi Slow      AMIGA_BUS_DATA_DIR   
 34  D   6  DFF  *       --------   Hi Slow      AMIGA_BUS_ENABLE   
 20  C   1  DFF    *     --------   Hi Slow      AMIGA_BUS_ENABLE_LOW   
 92  A   1  COM          --------   Hi Slow      AVEC   
 22  C   1  DFF    *     --------   Hi Slow      AVEC_EXP   
 83  H   2  DFF  *       --------   Hi Slow      BGACK_030   
 29  D   2  DFF  *       --------   Hi Slow      BG_000   
 47  E   1  COM          --------   Hi Slow      CIIN   
 65  G   1  DFF    *     --------   Hi Slow      CLK_DIV_OUT   
 10  B   1  DFF    *     --------   Hi Slow      CLK_EXP   
 66  G   3  DFF    *     --------   Hi Slow      E   
 78  H   1  COM          --------   Hi Slow      FPU_CS   
  8  B   3  DFF  *       --------   Hi Slow      IPL_030_0_   
  7  B   3  DFF  *       --------   Hi Slow      IPL_030_1_   
  9  B   3  DFF  *       --------   Hi Slow      IPL_030_2_   
  3  B   1  DFF    *     --------   Hi Slow      RESET   
 35  D   2  DFF  *       --------   Hi Slow      VMA   
----------------------------------------------------------------------

<Note> Power : Hi = High
               MH = Medium High
               ML = Medium Low
               Lo = Low



Bidir_Signal_List
~~~~~~~~~~~~~~~~~
                 P R
            Pin  r e O   Bidir 
Pin Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
----------------------------------------------------------------------
 69  G   1  DFF  *       A-C-----   Hi Slow      A0   
 33  D   2  DFF  *       A---E-GH   Hi Slow      AS_000   
 82  H   4  DFF  *       -BCDE--H   Hi Slow      AS_030   
 81  H   2  DFF  *       ---D----   Hi Slow      DSACK1   
 98  A   7  DFF  *       A-C-----   Hi Slow      DS_030   
 30  D   1  COM          -----F--   Hi Slow      DTACK   
 31  D   1  COM          A-----GH   Hi Slow      LDS_000   
 71  G   4  DFF  *       --C-E--H   Hi Slow      RW   
 80  H   3  DFF  *       A-----G-   Hi Slow      RW_000   
 70  G   1  DFF  *       --C-----   Hi Slow      SIZE_0_   
 79  H   2  DFF  *       --C-----   Hi Slow      SIZE_1_   
 32  D   1  COM          A-----GH   Hi Slow      UDS_000   
----------------------------------------------------------------------

<Note> Power : Hi = High
               MH = Medium High
               ML = Medium Low
               Lo = Low



Buried_Signal_List
~~~~~~~~~~~~~~~~~~
                 P R
            Pin  r e O   Node 
#Mc Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
----------------------------------------------------------------------
 A1  A   2  COM          --C-----   Hi Slow      AMIGA_BUS_ENABLE_LOW_0   
 G2  G   1  DFF    *     -B------   Hi Slow      CLK_000_P_SYNC_0_   
 B13  B   1  DFF    *     ----E---   Hi Slow      CLK_000_P_SYNC_1_   
 E9  E   1  DFF    *     --C-----   Hi Slow      CLK_000_P_SYNC_2_   
 C2  C   1  DFF    *     ----E---   Hi Slow      CLK_000_P_SYNC_3_   
 E5  E   1  DFF    *     --C-----   Hi Slow      CLK_000_P_SYNC_4_   
 C13  C   1  DFF    *     ----E---   Hi Slow      CLK_000_P_SYNC_5_   
 E1  E   1  DFF    *     ------G-   Hi Slow      CLK_000_P_SYNC_6_   
 G13  G   1  DFF    *     ------G-   Hi Slow      CLK_000_P_SYNC_7_   
 G9  G   1  DFF    *     A-------   Hi Slow      CLK_000_P_SYNC_8_   
 A6  A   1  DFF    *     --C-----   Hi Slow      CLK_000_P_SYNC_9_   
 A9  A   2  DFF    *     A-------   Hi Slow      CLK_CNT_N_0_   
 A13  A   1  DFF  *       A-------   Hi Slow      CLK_CNT_N_1_   
 A5  A   2  DFF    *     A-------   Hi Slow      CLK_CNT_P_0_   
 A2  A   1  DFF    *     A-------   Hi Slow      CLK_CNT_P_1_   
 D5  D   6  DFF  *       ---D----   Hi  -        RN_AMIGA_BUS_ENABLE   --> AMIGA_BUS_ENABLE
 C12  C   1  DFF    *     --C-----   Hi  -        RN_AMIGA_BUS_ENABLE_LOW   --> AMIGA_BUS_ENABLE_LOW
 D4  D   2  DFF  *       ---D----   Hi  -        RN_AS_000   --> AS_000
 H8  H   4  DFF  *       A--D--GH   Hi  -        RN_AS_030   --> AS_030
 H4  H   2  DFF  *       AB-DE-GH   Hi  -        RN_BGACK_030   --> BGACK_030
 D13  D   2  DFF  *       ---D----   Hi  -        RN_BG_000   --> BG_000
 H12  H   2  DFF  *       -------H   Hi  -        RN_DSACK1   --> DSACK1
 A0  A   7  DFF  *       A-------   Hi  -        RN_DS_030   --> DS_030
 G4  G   3  DFF    *     ---D-FG-   Hi  -        RN_E   --> E
 B8  B   3  DFF  *       -B------   Hi  -        RN_IPL_030_0_   --> IPL_030_0_
 B12  B   3  DFF  *       -B------   Hi  -        RN_IPL_030_1_   --> IPL_030_1_
 B4  B   3  DFF  *       -B------   Hi  -        RN_IPL_030_2_   --> IPL_030_2_
 G0  G   4  DFF  *       ------G-   Hi  -        RN_RW   --> RW
 H0  H   3  DFF  *       -------H   Hi  -        RN_RW_000   --> RW_000
 D1  D   2  DFF  *       ---D-F--   Hi  -        RN_VMA   --> VMA
 F5  F   2  DFF    *     ---D-F--   Hi Slow      SM_AMIGA_0_   
 F12  F   2  DFF    *     ---D-F-H   Hi Slow      SM_AMIGA_1_   
 F2  F   3  DFF    *     -----F--   Hi Slow      SM_AMIGA_2_   
 F9  F   5  TFF    *     -----F--   Hi Slow      SM_AMIGA_3_   
 F1  F   2  DFF    *     --C--F--   Hi Slow      SM_AMIGA_4_   
 C5  C   2  DFF    *     --C--F--   Hi Slow      SM_AMIGA_5_   
 F4  F   2  DFF    *     --CD-F-H   Hi Slow      SM_AMIGA_6_   
 F0  F  11  DFF  *       -B-D-F-H   Hi Slow      SM_AMIGA_7_   
 F13  F   3  COM          -----F--   Hi Slow      SM_AMIGA_7__0   
 H9  H   3  DFF    *     ---D-FGH   Hi Slow      cpu_est_0_   
 F8  F   4  TFF    *     ---D-FG-   Hi Slow      cpu_est_1_   
 D2  D   3  DFF    *     ---D-FG-   Hi Slow      cpu_est_2_   
 B5  B   6  DFF  *       -B-D-F--   Hi Slow      inst_AS_030_000_SYNC   
 H2  H   1  DFF  *       ---D----   Hi Slow      inst_BGACK_030_INT_D   
 C4  C   1  DFF  *       -BCD-FGH   Hi Slow      inst_CLK_000_D0   
 D9  D   1  DFF  *       -B-D-FGH   Hi Slow      inst_CLK_000_D1   
 H13  H   1  DFF  *       --C---G-   Hi Slow      inst_CLK_000_D2   
 C8  C   1  DFF  *       ----E-GH   Hi Slow      inst_CLK_000_D3   
 E2  E   1  DFF  *       -------H   Hi Slow      inst_CLK_000_D4   
 A12  A   5  DFF          A-------   Hi Slow      inst_CLK_030_H   
 E13  E   1  DFF    *     -B------   Hi Slow      inst_CLK_OUT_PRE   
 G5  G   3  DFF    *     ----E-G-   Hi Slow      inst_CLK_OUT_PRE_25   
 E4  E   1  DFF    *     ----E-G-   Hi Slow      inst_CLK_OUT_PRE_50   
 E6  E   1  DFF    *     ------G-   Hi Slow      inst_CLK_OUT_PRE_50_D   
 B9  B   1  DFF    *     -B----G-   Hi Slow      inst_CLK_OUT_PRE_D   
 C1  C   3  DFF    *     --CD----   Hi Slow      inst_DS_000_ENABLE   
 C9  C   2  DFF  *       --CD----   Hi Slow      inst_LDS_000_INT   
 A8  A   2  DFF  *       A--D----   Hi Slow      inst_UDS_000_INT   
 B2  B   1  DFF  *       ---D----   Hi Slow      inst_VPA_D   
 E8  E   3  COM          ----E---   Hi Slow      un16_ciin   
----------------------------------------------------------------------

<Note> Power : Hi = High
               MH = Medium High
               ML = Medium Low
               Lo = Low




Signals_Fanout_List
~~~~~~~~~~~~~~~~~~~
Signal Source  :    Fanout List
-----------------------------------------------------------------------------
      A_28_{ D}:           CIIN{ E}      un16_ciin{ E}
      A_27_{ D}:           CIIN{ E}      un16_ciin{ E}
      A_26_{ D}:           CIIN{ E}      un16_ciin{ E}
      A_25_{ D}:           CIIN{ E}      un16_ciin{ E}
      A_31_{ C}:           CIIN{ E}      un16_ciin{ E}
      A_24_{ D}:           CIIN{ E}      un16_ciin{ E}
      A_23_{ I}:           CIIN{ E}      un16_ciin{ E}
      A_22_{ I}:           CIIN{ E}      un16_ciin{ E}
      A_21_{ B}:           CIIN{ E}      un16_ciin{ E}
     IPL_2_{ H}:     IPL_030_2_{ B}
      A_20_{ B}:           CIIN{ E}      un16_ciin{ E}
      A_19_{ B}:         FPU_CS{ H}inst_AS_030_000_SYNC{ B}
      FC_1_{ G}:         FPU_CS{ H}inst_AS_030_000_SYNC{ B}
      A_18_{ B}:         FPU_CS{ H}inst_AS_030_000_SYNC{ B}
      A_17_{ G}:         FPU_CS{ H}inst_AS_030_000_SYNC{ B}
      A_16_{ B}:         FPU_CS{ H}inst_AS_030_000_SYNC{ B}
    UDS_000{ E}:        SIZE_1_{ H}         AS_030{ H}         DS_030{ A}
               :             A0{ G}             RW{ G}        SIZE_0_{ G}
               : inst_CLK_030_H{ A}
     IPL_1_{ G}:     IPL_030_1_{ B}
    LDS_000{ E}:        SIZE_1_{ H}         AS_030{ H}         DS_030{ A}
               :             A0{ G}             RW{ G}        SIZE_0_{ G}
               : inst_CLK_030_H{ A}
     IPL_0_{ H}:     IPL_030_0_{ B}
      FC_0_{ G}:         FPU_CS{ H}inst_AS_030_000_SYNC{ B}
 nEXP_SPACE{. }:          DTACK{ D}AMIGA_BUS_DATA_DIR{ E}        SIZE_1_{ H}
               :         AS_030{ H}         DS_030{ A}             A0{ G}
               :         BG_000{ D}         DSACK1{ H}AMIGA_BUS_ENABLE{ D}
               :        SIZE_0_{ G}inst_AS_030_000_SYNC{ B}    SM_AMIGA_7_{ F}
               :    SM_AMIGA_6_{ F}      un16_ciin{ E}
       BERR{ F}:         AS_000{ D}         DSACK1{ H}inst_AS_030_000_SYNC{ B}
               :    SM_AMIGA_7_{ F}    SM_AMIGA_6_{ F}    SM_AMIGA_1_{ F}
               :    SM_AMIGA_0_{ F}    SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C}
               :    SM_AMIGA_5_{ C}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
     BG_030{ D}:         BG_000{ D}
  BGACK_000{ E}:         FPU_CS{ H}      BGACK_030{ H}inst_AS_030_000_SYNC{ B}
    CLK_030{. }:         AS_030{ H}         DS_030{ A}             RW{ G}
               : inst_CLK_030_H{ A}
    CLK_000{. }:inst_CLK_000_D0{ C}
      DTACK{ E}:    SM_AMIGA_7_{ F}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
        VPA{. }:     inst_VPA_D{ B}    SM_AMIGA_7_{ F}    SM_AMIGA_3_{ F}
               :    SM_AMIGA_2_{ F}
        RST{. }:    CLK_DIV_OUT{ G}        SIZE_1_{ H}     IPL_030_2_{ B}
               :         AS_030{ H}         AS_000{ D}         RW_000{ H}
               :     IPL_030_1_{ B}         DS_030{ A}     IPL_030_0_{ B}
               :             A0{ G}         BG_000{ D}      BGACK_030{ H}
               :        CLK_EXP{ B}         DSACK1{ H}       AVEC_EXP{ C}
               :              E{ G}            VMA{ D}          RESET{ B}
               :             RW{ G}AMIGA_BUS_ENABLE{ D}AMIGA_BUS_ENABLE_LOW{ C}
               :        SIZE_0_{ G}inst_AS_030_000_SYNC{ B}inst_BGACK_030_INT_D{ H}
               :     inst_VPA_D{ B}inst_CLK_OUT_PRE_50_D{ E}inst_CLK_000_D0{ C}
               :inst_CLK_000_D1{ D}inst_CLK_000_D4{ E}   CLK_CNT_N_0_{ A}
               :inst_CLK_OUT_PRE_50{ E}inst_CLK_OUT_PRE_25{ G}inst_CLK_000_D2{ H}
               :inst_CLK_000_D3{ C}inst_CLK_OUT_PRE_D{ B}inst_CLK_OUT_PRE{ E}
               :CLK_000_P_SYNC_9_{ A}    SM_AMIGA_7_{ F}    SM_AMIGA_6_{ F}
               :    SM_AMIGA_1_{ F}    SM_AMIGA_0_{ F}    SM_AMIGA_4_{ F}
               : inst_CLK_030_H{ A}   CLK_CNT_P_1_{ A}   CLK_CNT_N_1_{ A}
               :   CLK_CNT_P_0_{ A}inst_LDS_000_INT{ C}inst_DS_000_ENABLE{ C}
               :inst_UDS_000_INT{ A}CLK_000_P_SYNC_0_{ G}CLK_000_P_SYNC_1_{ B}
               :CLK_000_P_SYNC_2_{ E}CLK_000_P_SYNC_3_{ C}CLK_000_P_SYNC_4_{ E}
               :CLK_000_P_SYNC_5_{ C}CLK_000_P_SYNC_6_{ E}CLK_000_P_SYNC_7_{ G}
               :CLK_000_P_SYNC_8_{ G}    SM_AMIGA_5_{ C}    SM_AMIGA_3_{ F}
               :    SM_AMIGA_2_{ F}     cpu_est_0_{ H}     cpu_est_1_{ F}
               :     cpu_est_2_{ D}
      A_30_{ C}:           CIIN{ E}      un16_ciin{ E}
      A_29_{ C}:           CIIN{ E}      un16_ciin{ E}
    SIZE_1_{ I}:inst_LDS_000_INT{ C}
RN_IPL_030_2_{ C}:     IPL_030_2_{ B}
     AS_030{ I}:         FPU_CS{ H}           CIIN{ E}         AS_000{ D}
               :         BG_000{ D}         DSACK1{ H}AMIGA_BUS_ENABLE{ D}
               :inst_AS_030_000_SYNC{ B}inst_DS_000_ENABLE{ C}      un16_ciin{ E}
  RN_AS_030{ I}:          DTACK{ D}        SIZE_1_{ H}         AS_030{ H}
               :         DS_030{ A}             A0{ G}        SIZE_0_{ G}
               : inst_CLK_030_H{ A}
     AS_000{ E}:AMIGA_BUS_DATA_DIR{ E}        SIZE_1_{ H}         AS_030{ H}
               :         DS_030{ A}             A0{ G}             RW{ G}
               :        SIZE_0_{ G} inst_CLK_030_H{ A}
  RN_AS_000{ E}:         AS_000{ D}            VMA{ D}
     RW_000{ I}:         DS_030{ A}             RW{ G}
  RN_RW_000{ I}:         RW_000{ H}
RN_IPL_030_1_{ C}:     IPL_030_1_{ B}
     DS_030{ B}:inst_LDS_000_INT{ C}inst_UDS_000_INT{ A}
  RN_DS_030{ B}:         DS_030{ A}
RN_IPL_030_0_{ C}:     IPL_030_0_{ B}
         A0{ H}:inst_LDS_000_INT{ C}inst_UDS_000_INT{ A}
  RN_BG_000{ E}:         BG_000{ D}
RN_BGACK_030{ I}:        UDS_000{ D}        LDS_000{ D}          DTACK{ D}
               :AMIGA_BUS_DATA_DIR{ E}        SIZE_1_{ H}         AS_030{ H}
               :         AS_000{ D}         RW_000{ H}         DS_030{ A}
               :             A0{ G}      BGACK_030{ H}             RW{ G}
               :AMIGA_BUS_ENABLE{ D}        SIZE_0_{ G}inst_AS_030_000_SYNC{ B}
               :inst_BGACK_030_INT_D{ H} inst_CLK_030_H{ A}
     DSACK1{ I}:          DTACK{ D}
  RN_DSACK1{ I}:         DSACK1{ H}
       RN_E{ H}:              E{ G}            VMA{ D}    SM_AMIGA_7_{ F}
               :    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}     cpu_est_1_{ F}
               :     cpu_est_2_{ D}
     RN_VMA{ E}:            VMA{ D}    SM_AMIGA_7_{ F}    SM_AMIGA_3_{ F}
               :    SM_AMIGA_2_{ F}
         RW{ H}:AMIGA_BUS_DATA_DIR{ E}         RW_000{ H}inst_DS_000_ENABLE{ C}
      RN_RW{ H}:             RW{ G}
RN_AMIGA_BUS_ENABLE{ E}:AMIGA_BUS_ENABLE{ D}
RN_AMIGA_BUS_ENABLE_LOW{ D}:AMIGA_BUS_ENABLE_LOW{ C}
    SIZE_0_{ H}:inst_LDS_000_INT{ C}
inst_AS_030_000_SYNC{ C}:AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ B}    SM_AMIGA_7_{ F}
               :    SM_AMIGA_6_{ F}
inst_BGACK_030_INT_D{ I}:AMIGA_BUS_ENABLE{ D}
 inst_VPA_D{ C}:            VMA{ D}
inst_CLK_OUT_PRE_50_D{ F}:inst_CLK_OUT_PRE_25{ G}
inst_CLK_000_D0{ D}:     IPL_030_2_{ B}         AS_000{ D}         RW_000{ H}
               :     IPL_030_1_{ B}     IPL_030_0_{ B}         BG_000{ D}
               :      BGACK_030{ H}              E{ G}            VMA{ D}
               :AMIGA_BUS_ENABLE{ D}inst_CLK_000_D1{ D}    SM_AMIGA_7_{ F}
               :    SM_AMIGA_6_{ F}    SM_AMIGA_1_{ F}    SM_AMIGA_0_{ F}
               :    SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C}CLK_000_P_SYNC_0_{ G}
               :    SM_AMIGA_5_{ C}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
               :     cpu_est_0_{ H}     cpu_est_1_{ F}     cpu_est_2_{ D}
               :  SM_AMIGA_7__0{ F}
inst_CLK_000_D1{ E}:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
               :         BG_000{ D}      BGACK_030{ H}              E{ G}
               :AMIGA_BUS_ENABLE{ D}inst_CLK_000_D2{ H}    SM_AMIGA_7_{ F}
               :    SM_AMIGA_6_{ F}CLK_000_P_SYNC_0_{ G}    SM_AMIGA_3_{ F}
               :    SM_AMIGA_2_{ F}     cpu_est_0_{ H}     cpu_est_1_{ F}
               :     cpu_est_2_{ D}
inst_CLK_000_D4{ F}:         DSACK1{ H}
CLK_CNT_N_0_{ B}:   CLK_CNT_N_0_{ A}   CLK_CNT_N_1_{ A}AMIGA_BUS_ENABLE_LOW_0{ A}
inst_CLK_OUT_PRE_50{ F}:inst_CLK_OUT_PRE_50_D{ E}inst_CLK_OUT_PRE_50{ E}inst_CLK_OUT_PRE_25{ G}
inst_CLK_OUT_PRE_25{ H}:inst_CLK_OUT_PRE_25{ G}inst_CLK_OUT_PRE{ E}
inst_CLK_000_D2{ I}:inst_CLK_000_D3{ C}CLK_000_P_SYNC_0_{ G}
inst_CLK_000_D3{ D}:         DSACK1{ H}inst_CLK_000_D4{ E}CLK_000_P_SYNC_0_{ G}
inst_CLK_OUT_PRE_D{ C}:    CLK_DIV_OUT{ G}        CLK_EXP{ B}
inst_CLK_OUT_PRE{ F}:inst_CLK_OUT_PRE_D{ B}
CLK_000_P_SYNC_9_{ B}:       AVEC_EXP{ C}
SM_AMIGA_7_{ G}:         RW_000{ H}AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ B}
               :    SM_AMIGA_6_{ F}
SM_AMIGA_6_{ G}:         AS_000{ D}         RW_000{ H}    SM_AMIGA_7_{ F}
               :    SM_AMIGA_6_{ F}inst_DS_000_ENABLE{ C}    SM_AMIGA_5_{ C}
               :  SM_AMIGA_7__0{ F}
SM_AMIGA_1_{ G}:         DSACK1{ H}AMIGA_BUS_ENABLE{ D}    SM_AMIGA_7_{ F}
               :    SM_AMIGA_1_{ F}    SM_AMIGA_0_{ F}  SM_AMIGA_7__0{ F}
SM_AMIGA_0_{ G}:AMIGA_BUS_ENABLE{ D}    SM_AMIGA_7_{ F}    SM_AMIGA_0_{ F}
               :  SM_AMIGA_7__0{ F}
SM_AMIGA_4_{ G}:    SM_AMIGA_7_{ F}    SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C}
               :    SM_AMIGA_3_{ F}  SM_AMIGA_7__0{ F}
inst_CLK_030_H{ B}:         DS_030{ A} inst_CLK_030_H{ A}
CLK_CNT_P_1_{ B}:   CLK_CNT_P_0_{ A}AMIGA_BUS_ENABLE_LOW_0{ A}
CLK_CNT_N_1_{ B}:   CLK_CNT_N_0_{ A}AMIGA_BUS_ENABLE_LOW_0{ A}
CLK_CNT_P_0_{ B}:   CLK_CNT_P_1_{ A}   CLK_CNT_P_0_{ A}AMIGA_BUS_ENABLE_LOW_0{ A}
inst_LDS_000_INT{ D}:        LDS_000{ D}inst_LDS_000_INT{ C}
inst_DS_000_ENABLE{ D}:        UDS_000{ D}        LDS_000{ D}inst_DS_000_ENABLE{ C}
inst_UDS_000_INT{ B}:        UDS_000{ D}inst_UDS_000_INT{ A}
CLK_000_P_SYNC_0_{ H}:CLK_000_P_SYNC_1_{ B}
CLK_000_P_SYNC_1_{ C}:CLK_000_P_SYNC_2_{ E}
CLK_000_P_SYNC_2_{ F}:CLK_000_P_SYNC_3_{ C}
CLK_000_P_SYNC_3_{ D}:CLK_000_P_SYNC_4_{ E}
CLK_000_P_SYNC_4_{ F}:CLK_000_P_SYNC_5_{ C}
CLK_000_P_SYNC_5_{ D}:CLK_000_P_SYNC_6_{ E}
CLK_000_P_SYNC_6_{ F}:CLK_000_P_SYNC_7_{ G}
CLK_000_P_SYNC_7_{ H}:CLK_000_P_SYNC_8_{ G}
CLK_000_P_SYNC_8_{ H}:CLK_000_P_SYNC_9_{ A}
  un16_ciin{ F}:           CIIN{ E}
SM_AMIGA_5_{ D}:    SM_AMIGA_7_{ F}    SM_AMIGA_4_{ F}    SM_AMIGA_5_{ C}
               :  SM_AMIGA_7__0{ F}
SM_AMIGA_3_{ G}:    SM_AMIGA_7_{ F}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
               :  SM_AMIGA_7__0{ F}
SM_AMIGA_2_{ G}:    SM_AMIGA_7_{ F}    SM_AMIGA_1_{ F}    SM_AMIGA_2_{ F}
               :  SM_AMIGA_7__0{ F}
 cpu_est_0_{ I}:              E{ G}            VMA{ D}     cpu_est_0_{ H}
               :     cpu_est_1_{ F}     cpu_est_2_{ D}
 cpu_est_1_{ G}:              E{ G}            VMA{ D}    SM_AMIGA_7_{ F}
               :    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}     cpu_est_1_{ F}
               :     cpu_est_2_{ D}
 cpu_est_2_{ E}:              E{ G}            VMA{ D}     cpu_est_1_{ F}
               :     cpu_est_2_{ D}
AMIGA_BUS_ENABLE_LOW_0{ B}:AMIGA_BUS_ENABLE_LOW{ C}
SM_AMIGA_7__0{ G}:    SM_AMIGA_7_{ F}
-----------------------------------------------------------------------------

<Note> {.} : Indicates block location of signal


Set_Reset_Summary
~~~~~~~~~~~~~~~~~

Block  A
block level set pt   : !RST
block level reset pt : 
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | DS_030
|     |     |     |     | AVEC
|  *  |  S  | BS  | BR  | inst_UDS_000_INT
|  *  |  S  | BS  | BR  | RN_DS_030
|  *  |  S  | BR  | BR  | inst_CLK_030_H
|     |     |     |     | AMIGA_BUS_ENABLE_LOW_0
|  *  |  S  | BR  | BS  | CLK_CNT_P_0_
|  *  |  S  | BR  | BS  | CLK_CNT_N_0_
|  *  |  S  | BS  | BR  | CLK_CNT_N_1_
|  *  |  S  | BR  | BS  | CLK_CNT_P_1_
|  *  |  S  | BR  | BS  | CLK_000_P_SYNC_9_
|     |     |     |     | A_19_
|     |     |     |     | A_16_
|     |     |     |     | A_18_
|     |     |     |     | A_21_
|     |     |     |     | A_20_


Block  B
block level set pt   : !RST
block level reset pt : 
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | IPL_030_2_
|  *  |  S  | BS  | BR  | IPL_030_0_
|  *  |  S  | BS  | BR  | IPL_030_1_
|  *  |  S  | BR  | BS  | CLK_EXP
|  *  |  S  | BR  | BS  | RESET
|  *  |  S  | BS  | BR  | inst_AS_030_000_SYNC
|  *  |  S  | BR  | BS  | inst_CLK_OUT_PRE_D
|  *  |  S  | BS  | BR  | RN_IPL_030_0_
|  *  |  S  | BS  | BR  | RN_IPL_030_1_
|  *  |  S  | BS  | BR  | RN_IPL_030_2_
|  *  |  S  | BR  | BS  | CLK_000_P_SYNC_1_
|  *  |  S  | BS  | BR  | inst_VPA_D
|     |     |     |     | A_29_
|     |     |     |     | A_30_
|     |     |     |     | A_31_


Block  C
block level set pt   : 
block level reset pt : !RST
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | AVEC_EXP
|  *  |  A  |     |     | AMIGA_BUS_ENABLE_LOW
|  *  |  S  | BR  | BS  | inst_CLK_000_D0
|  *  |  S  | BR  | BS  | inst_CLK_000_D3
|  *  |  S  | BS  | BR  | inst_DS_000_ENABLE
|  *  |  S  | BS  | BR  | SM_AMIGA_5_
|  *  |  S  | BR  | BS  | inst_LDS_000_INT
|  *  |  A  |     |     | RN_AMIGA_BUS_ENABLE_LOW
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_5_
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_3_
|     |     |     |     | BG_030
|     |     |     |     | A_24_
|     |     |     |     | A_25_
|     |     |     |     | A_26_
|     |     |     |     | A_27_
|     |     |     |     | A_28_


Block  D
block level set pt   : !RST
block level reset pt : 
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | AS_000
|     |     |     |     | UDS_000
|     |     |     |     | LDS_000
|     |     |     |     | DTACK
|  *  |  S  | BS  | BR  | AMIGA_BUS_ENABLE
|  *  |  S  | BS  | BR  | VMA
|  *  |  S  | BS  | BR  | BG_000
|  *  |  S  | BS  | BR  | inst_CLK_000_D1
|  *  |  S  | BR  | BS  | cpu_est_2_
|  *  |  S  | BS  | BR  | RN_VMA
|  *  |  S  | BS  | BR  | RN_AMIGA_BUS_ENABLE
|  *  |  S  | BS  | BR  | RN_BG_000
|  *  |  S  | BS  | BR  | RN_AS_000
|     |     |     |     | BGACK_000


Block  E
block level set pt   : 
block level reset pt : !RST
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|     |     |     |     | AMIGA_BUS_DATA_DIR
|     |     |     |     | CIIN
|  *  |  S  | BS  | BR  | inst_CLK_OUT_PRE_50
|     |     |     |     | un16_ciin
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_6_
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_4_
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_2_
|  *  |  S  | BS  | BR  | inst_CLK_OUT_PRE
|  *  |  S  | BR  | BS  | inst_CLK_000_D4
|  *  |  S  | BS  | BR  | inst_CLK_OUT_PRE_50_D
|     |     |     |     | BERR


Block  F
block level set pt   : !RST
block level reset pt : 
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | SM_AMIGA_7_
|  *  |  S  | BR  | BS  | SM_AMIGA_6_
|  *  |  S  | BR  | BS  | cpu_est_1_
|  *  |  S  | BR  | BS  | SM_AMIGA_1_
|  *  |  S  | BR  | BS  | SM_AMIGA_4_
|  *  |  S  | BR  | BS  | SM_AMIGA_0_
|  *  |  S  | BR  | BS  | SM_AMIGA_3_
|     |     |     |     | SM_AMIGA_7__0
|  *  |  S  | BR  | BS  | SM_AMIGA_2_
|     |     |     |     | A_17_
|     |     |     |     | FC_1_
|     |     |     |     | FC_0_
|     |     |     |     | IPL_1_


Block  G
block level set pt   : !RST
block level reset pt : 
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | RW
|  *  |  S  | BS  | BR  | A0
|  *  |  S  | BS  | BR  | SIZE_0_
|  *  |  S  | BR  | BS  | E
|  *  |  S  | BR  | BS  | CLK_DIV_OUT
|  *  |  S  | BR  | BS  | RN_E
|  *  |  S  | BR  | BS  | inst_CLK_OUT_PRE_25
|  *  |  S  | BS  | BR  | RN_RW
|  *  |  S  | BR  | BS  | CLK_000_P_SYNC_8_
|  *  |  S  | BR  | BS  | CLK_000_P_SYNC_7_
|  *  |  S  | BR  | BS  | CLK_000_P_SYNC_0_
|     |     |     |     | IPL_2_
|     |     |     |     | IPL_0_


Block  H
block level set pt   : !RST
block level reset pt : 
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | AS_030
|  *  |  S  | BS  | BR  | RW_000
|  *  |  S  | BS  | BR  | DSACK1
|  *  |  S  | BS  | BR  | SIZE_1_
|  *  |  S  | BS  | BR  | BGACK_030
|     |     |     |     | FPU_CS
|  *  |  S  | BS  | BR  | RN_BGACK_030
|  *  |  S  | BS  | BR  | RN_AS_030
|  *  |  S  | BR  | BS  | cpu_est_0_
|  *  |  S  | BS  | BR  | inst_CLK_000_D2
|  *  |  S  | BS  | BR  | RN_RW_000
|  *  |  S  | BS  | BR  | RN_DSACK1
|  *  |  S  | BS  | BR  | inst_BGACK_030_INT_D
|     |     |     |     | A_22_
|     |     |     |     | A_23_


<Note> (S) means the macrocell is configured in synchronous mode
       i.e. it uses the block-level set and reset pt.
       (A) means the macrocell is configured in asynchronous mode
       i.e. it can have its independant set or reset pt.
       (BS) means the block-level set pt is selected.
       (BR) means the block-level reset pt is selected.




BLOCK_A_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx A0              A0        pin 69     mx A17             ...           ...
mx A1             ...           ...     mx A18    CLK_CNT_P_0_     mcell  A5
mx A2    CLK_CNT_N_0_     mcell  A9     mx A19             ...           ...
mx A3inst_UDS_000_INT     mcell  A8     mx A20    RN_BGACK_030     mcell  H4
mx A4         CLK_030        pin 64     mx A21             RST        pin 86
mx A5      nEXP_SPACE        pin 14     mx A22    CLK_CNT_P_1_     mcell  A2
mx A6          RW_000        pin 80     mx A23          AS_000        pin 33
mx A7             ...           ...     mx A24         LDS_000        pin 31
mx A8         UDS_000        pin 32     mx A25    CLK_CNT_N_1_    mcell  A13
mx A9  inst_CLK_030_H    mcell  A12     mx A26             ...           ...
mx A10CLK_000_P_SYNC_8_     mcell  G9     mx A27             ...           ...
mx A11             ...           ...     mx A28             ...           ...
mx A12          DS_030        pin 98     mx A29             ...           ...
mx A13       RN_AS_030     mcell  H8     mx A30             ...           ...
mx A14             ...           ...     mx A31             ...           ...
mx A15       RN_DS_030     mcell  A0     mx A32             ...           ...
mx A16             ...           ...
----------------------------------------------------------------------------


BLOCK_B_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx B0          IPL_0_        pin 67     mx B17           A_18_        pin 95
mx B1           FC_1_        pin 58     mx B18       BGACK_000        pin 28
mx B2inst_CLK_OUT_PRE    mcell  E13     mx B19             ...           ...
mx B3          IPL_1_        pin 56     mx B20    RN_BGACK_030     mcell  H4
mx B4          IPL_2_        pin 68     mx B21             RST        pin 86
mx B5      nEXP_SPACE        pin 14     mx B22             ...           ...
mx B6           FC_0_        pin 57     mx B23CLK_000_P_SYNC_0_     mcell  G2
mx B7 inst_CLK_000_D1     mcell  D9     mx B24             ...           ...
mx B8   RN_IPL_030_0_     mcell  B8     mx B25            BERR        pin 41
mx B9          AS_030        pin 82     mx B26   RN_IPL_030_1_    mcell  B12
mx B10             VPA        pin 36     mx B27   RN_IPL_030_2_     mcell  B4
mx B11           A_16_        pin 96     mx B28inst_AS_030_000_SYNC     mcell  B5
mx B12           A_19_        pin 97     mx B29             ...           ...
mx B13           A_17_        pin 59     mx B30             ...           ...
mx B14 inst_CLK_000_D0     mcell  C4     mx B31     SM_AMIGA_7_     mcell  F0
mx B15             ...           ...     mx B32             ...           ...
mx B16inst_CLK_OUT_PRE_D     mcell  B9
----------------------------------------------------------------------------


BLOCK_C_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx C0             RST        pin 86     mx C17         SIZE_0_        pin 70
mx C1            BERR        pin 41     mx C18              A0        pin 69
mx C2CLK_000_P_SYNC_2_     mcell  E9     mx C19          AS_030        pin 82
mx C3         CLK_000        pin 11     mx C20         SIZE_1_        pin 79
mx C4RN_AMIGA_BUS_ENABLE_LOW    mcell  C12     mx C21             ...           ...
mx C5          DS_030        pin 98     mx C22inst_DS_000_ENABLE     mcell  C1
mx C6 inst_CLK_000_D0     mcell  C4     mx C23             ...           ...
mx C7 inst_CLK_000_D2    mcell  H13     mx C24             ...           ...
mx C8              RW        pin 71     mx C25             ...           ...
mx C9AMIGA_BUS_ENABLE_LOW_0     mcell  A1     mx C26             ...           ...
mx C10CLK_000_P_SYNC_9_     mcell  A6     mx C27             ...           ...
mx C11             ...           ...     mx C28     SM_AMIGA_5_     mcell  C5
mx C12             ...           ...     mx C29     SM_AMIGA_6_     mcell  F4
mx C13inst_LDS_000_INT     mcell  C9     mx C30             ...           ...
mx C14CLK_000_P_SYNC_4_     mcell  E5     mx C31             ...           ...
mx C15     SM_AMIGA_4_     mcell  F1     mx C32             ...           ...
mx C16             ...           ...
----------------------------------------------------------------------------


BLOCK_D_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx D0             RST        pin 86     mx D17     SM_AMIGA_1_    mcell  F12
mx D1            BERR        pin 41     mx D18      inst_VPA_D     mcell  B2
mx D2          RN_VMA     mcell  D1     mx D19          AS_030        pin 82
mx D3inst_UDS_000_INT     mcell  A8     mx D20      cpu_est_1_     mcell  F8
mx D4          BG_030        pin 21     mx D21       RN_AS_000     mcell  D4
mx D5     SM_AMIGA_7_     mcell  F0     mx D22inst_DS_000_ENABLE     mcell  C1
mx D6 inst_CLK_000_D0     mcell  C4     mx D23    RN_BGACK_030     mcell  H4
mx D7RN_AMIGA_BUS_ENABLE     mcell  D5     mx D24             ...           ...
mx D8             ...           ...     mx D25       RN_AS_030     mcell  H8
mx D9     SM_AMIGA_0_     mcell  F5     mx D26             ...           ...
mx D10     SM_AMIGA_6_     mcell  F4     mx D27      cpu_est_0_     mcell  H9
mx D11            RN_E     mcell  G4     mx D28inst_AS_030_000_SYNC     mcell  B5
mx D12 inst_CLK_000_D1     mcell  D9     mx D29       RN_BG_000    mcell  D13
mx D13inst_LDS_000_INT     mcell  C9     mx D30             ...           ...
mx D14inst_BGACK_030_INT_D     mcell  H2     mx D31             ...           ...
mx D15      nEXP_SPACE        pin 14     mx D32          DSACK1        pin 81
mx D16      cpu_est_2_     mcell  D2
----------------------------------------------------------------------------


BLOCK_E_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx E0             RST        pin 86     mx E17           A_26_        pin 17
mx E1           A_31_         pin 4     mx E18             ...           ...
mx E2CLK_000_P_SYNC_3_     mcell  C2     mx E19          AS_030        pin 82
mx E3           A_27_        pin 16     mx E20    RN_BGACK_030     mcell  H4
mx E4           A_29_         pin 6     mx E21      nEXP_SPACE        pin 14
mx E5           A_24_        pin 19     mx E22inst_CLK_OUT_PRE_25     mcell  G5
mx E6inst_CLK_OUT_PRE_50     mcell  E4     mx E23          AS_000        pin 33
mx E7 inst_CLK_000_D3     mcell  C8     mx E24             ...           ...
mx E8           A_22_        pin 85     mx E25              RW        pin 71
mx E9           A_30_         pin 5     mx E26             ...           ...
mx E10CLK_000_P_SYNC_1_    mcell  B13     mx E27             ...           ...
mx E11           A_23_        pin 84     mx E28             ...           ...
mx E12           A_25_        pin 18     mx E29           A_20_        pin 93
mx E13             ...           ...     mx E30CLK_000_P_SYNC_5_    mcell  C13
mx E14           A_28_        pin 15     mx E31             ...           ...
mx E15           A_21_        pin 94     mx E32             ...           ...
mx E16       un16_ciin     mcell  E8
----------------------------------------------------------------------------


BLOCK_F_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx F0             RST        pin 86     mx F17     SM_AMIGA_1_    mcell  F12
mx F1            BERR        pin 41     mx F18     SM_AMIGA_3_     mcell  F9
mx F2          RN_VMA     mcell  D1     mx F19             ...           ...
mx F3      cpu_est_2_     mcell  D2     mx F20      cpu_est_1_     mcell  F8
mx F4             ...           ...     mx F21             ...           ...
mx F5      nEXP_SPACE        pin 14     mx F22             ...           ...
mx F6 inst_CLK_000_D0     mcell  C4     mx F23           DTACK        pin 30
mx F7     SM_AMIGA_5_     mcell  C5     mx F24             ...           ...
mx F8             ...           ...     mx F25     SM_AMIGA_7_     mcell  F0
mx F9     SM_AMIGA_2_     mcell  F2     mx F26             ...           ...
mx F10     SM_AMIGA_4_     mcell  F1     mx F27      cpu_est_0_     mcell  H9
mx F11            RN_E     mcell  G4     mx F28inst_AS_030_000_SYNC     mcell  B5
mx F12 inst_CLK_000_D1     mcell  D9     mx F29     SM_AMIGA_6_     mcell  F4
mx F13             VPA        pin 36     mx F30             ...           ...
mx F14     SM_AMIGA_0_     mcell  F5     mx F31             ...           ...
mx F15   SM_AMIGA_7__0    mcell  F13     mx F32             ...           ...
mx F16             ...           ...
----------------------------------------------------------------------------


BLOCK_G_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx G0             RST        pin 86     mx G17           RN_RW     mcell  G0
mx G1             ...           ...     mx G18             ...           ...
mx G2            RN_E     mcell  G4     mx G19inst_CLK_OUT_PRE_50_D     mcell  E6
mx G3inst_CLK_OUT_PRE_25     mcell  G5     mx G20      cpu_est_1_     mcell  F8
mx G4         CLK_030        pin 64     mx G21          RW_000        pin 80
mx G5      nEXP_SPACE        pin 14     mx G22             ...           ...
mx G6inst_CLK_OUT_PRE_50     mcell  E4     mx G23    RN_BGACK_030     mcell  H4
mx G7 inst_CLK_000_D2    mcell  H13     mx G24         LDS_000        pin 31
mx G8         UDS_000        pin 32     mx G25       RN_AS_030     mcell  H8
mx G9CLK_000_P_SYNC_7_    mcell  G13     mx G26          AS_000        pin 33
mx G10             ...           ...     mx G27             ...           ...
mx G11      cpu_est_0_     mcell  H9     mx G28      cpu_est_2_     mcell  D2
mx G12 inst_CLK_000_D1     mcell  D9     mx G29 inst_CLK_000_D3     mcell  C8
mx G13CLK_000_P_SYNC_6_     mcell  E1     mx G30             ...           ...
mx G14 inst_CLK_000_D0     mcell  C4     mx G31             ...           ...
mx G15             ...           ...     mx G32             ...           ...
mx G16inst_CLK_OUT_PRE_D     mcell  B9
----------------------------------------------------------------------------


BLOCK_H_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx H0          AS_000        pin 33     mx H17            BERR        pin 41
mx H1           FC_1_        pin 58     mx H18       BGACK_000        pin 28
mx H2             ...           ...     mx H19             ...           ...
mx H3 inst_CLK_000_D4     mcell  E2     mx H20    RN_BGACK_030     mcell  H4
mx H4           A_18_        pin 95     mx H21             RST        pin 86
mx H5     SM_AMIGA_7_     mcell  F0     mx H22             ...           ...
mx H6           FC_0_        pin 57     mx H23       RN_RW_000     mcell  H0
mx H7 inst_CLK_000_D1     mcell  D9     mx H24         LDS_000        pin 31
mx H8              RW        pin 71     mx H25       RN_AS_030     mcell  H8
mx H9          AS_030        pin 82     mx H26           A_16_        pin 96
mx H10     SM_AMIGA_6_     mcell  F4     mx H27           A_19_        pin 97
mx H11      cpu_est_0_     mcell  H9     mx H28         CLK_030        pin 64
mx H12         UDS_000        pin 32     mx H29       RN_DSACK1    mcell  H12
mx H13           A_17_        pin 59     mx H30             ...           ...
mx H14 inst_CLK_000_D0     mcell  C4     mx H31     SM_AMIGA_1_    mcell  F12
mx H15      nEXP_SPACE        pin 14     mx H32             ...           ...
mx H16 inst_CLK_000_D3     mcell  C8
----------------------------------------------------------------------------

<Note> CSM indicates the mux inputs from the Central Switch Matrix.
<Note> Source indicates where the signal comes from (pin or macrocell). 




PostFit_Equations
~~~~~~~~~~~~~~~~~


 P-Terms   Fan-in  Fan-out  Type  Name (attributes)
---------  ------  -------  ----  -----------------
   1          2        1    Pin   UDS_000- 
   1          1        1    Pin   UDS_000.OE 
   1          2        1    Pin   LDS_000- 
   1          1        1    Pin   LDS_000.OE 
   1          1        1    Pin   CLK_DIV_OUT.AR 
   1          1        1    Pin   CLK_DIV_OUT.D 
   1          1        1    Pin   CLK_DIV_OUT.C 
   1          8        1    Pin   FPU_CS- 
   1          1        1    Pin   DTACK 
   1          3        1    Pin   DTACK.OE 
   1          0        1    Pin   AVEC 
   2          4        1    Pin   AMIGA_BUS_DATA_DIR 
   1         13        1    Pin   CIIN 
   1          1        1    Pin   CIIN.OE 
   1          3        1    Pin   SIZE_1_.OE 
   2          4        1    Pin   SIZE_1_.D- 
   1          1        1    Pin   SIZE_1_.AP 
   1          1        1    Pin   SIZE_1_.C 
   3          4        1    Pin   IPL_030_2_.D 
   1          1        1    Pin   IPL_030_2_.AP 
   1          1        1    Pin   IPL_030_2_.C 
   1          3        1    Pin   AS_030.OE 
   4          6        1    Pin   AS_030.D 
   1          1        1    Pin   AS_030.AP 
   1          1        1    Pin   AS_030.C 
   1          1        1    Pin   AS_000.OE 
   2          5        1    Pin   AS_000.D- 
   1          1        1    Pin   AS_000.AP 
   1          1        1    Pin   AS_000.C 
   1          1        1    Pin   RW_000.OE 
   3          5        1    Pin   RW_000.D- 
   1          1        1    Pin   RW_000.AP 
   1          1        1    Pin   RW_000.C 
   3          4        1    Pin   IPL_030_1_.D 
   1          1        1    Pin   IPL_030_1_.AP 
   1          1        1    Pin   IPL_030_1_.C 
   1          3        1    Pin   DS_030.OE 
   7          9        1    Pin   DS_030.D 
   1          1        1    Pin   DS_030.AP 
   1          1        1    Pin   DS_030.C 
   3          4        1    Pin   IPL_030_0_.D 
   1          1        1    Pin   IPL_030_0_.AP 
   1          1        1    Pin   IPL_030_0_.C 
   1          3        1    Pin   A0.OE 
   1          4        1    Pin   A0.D 
   1          1        1    Pin   A0.AP 
   1          1        1    Pin   A0.C 
   2          6        1    Pin   BG_000.D- 
   1          1        1    Pin   BG_000.AP 
   1          1        1    Pin   BG_000.C 
   2          4        1    Pin   BGACK_030.D 
   1          1        1    Pin   BGACK_030.AP 
   1          1        1    Pin   BGACK_030.C 
   1          1        1    Pin   CLK_EXP.AR 
   1          1        1    Pin   CLK_EXP.D 
   1          1        1    Pin   CLK_EXP.C 
   1          1        1    Pin   DSACK1.OE 
   2          6        1    Pin   DSACK1.D- 
   1          1        1    Pin   DSACK1.AP 
   1          1        1    Pin   DSACK1.C 
   1          1        1    Pin   AVEC_EXP.AR 
   1          1        1    Pin   AVEC_EXP.D 
   1          1        1    Pin   AVEC_EXP.C 
   3          6        1    PinX1  E.D.X1 
   1          1        1    PinX2  E.D.X2 
   1          1        1    Pin   E.AR 
   1          1        1    Pin   E.C 
   2          7        1    PinX1  VMA.D.X1 
   1          5        1    PinX2  VMA.D.X2 
   1          1        1    Pin   VMA.AP 
   1          1        1    Pin   VMA.C 
   1          1        1    Pin   RESET.AR 
   1          0        1    Pin   RESET.D 
   1          1        1    Pin   RESET.C 
   1          1        1    Pin   RW.OE 
   4          7        1    Pin   RW.D- 
   1          1        1    Pin   RW.AP 
   1          1        1    Pin   RW.C 
   6         11        1    Pin   AMIGA_BUS_ENABLE.D- 
   1          1        1    Pin   AMIGA_BUS_ENABLE.AP 
   1          1        1    Pin   AMIGA_BUS_ENABLE.C 
   1          1        1    Pin   AMIGA_BUS_ENABLE_LOW.AR 
   1          1        1    Pin   AMIGA_BUS_ENABLE_LOW.D 
   1          1        1    Pin   AMIGA_BUS_ENABLE_LOW.C 
   1          3        1    Pin   SIZE_0_.OE 
   1          4        1    Pin   SIZE_0_.D- 
   1          1        1    Pin   SIZE_0_.AP 
   1          1        1    Pin   SIZE_0_.C 
   6         13        1    Node  inst_AS_030_000_SYNC.D 
   1          1        1    Node  inst_AS_030_000_SYNC.AP 
   1          1        1    Node  inst_AS_030_000_SYNC.C 
   1          1        1    Node  inst_BGACK_030_INT_D.D 
   1          1        1    Node  inst_BGACK_030_INT_D.AP 
   1          1        1    Node  inst_BGACK_030_INT_D.C 
   1          1        1    Node  inst_VPA_D.D 
   1          1        1    Node  inst_VPA_D.AP 
   1          1        1    Node  inst_VPA_D.C 
   1          1        1    Node  inst_CLK_OUT_PRE_50_D.AR 
   1          1        1    Node  inst_CLK_OUT_PRE_50_D.D 
   1          1        1    Node  inst_CLK_OUT_PRE_50_D.C 
   1          1        1    Node  inst_CLK_000_D0.D 
   1          1        1    Node  inst_CLK_000_D0.AP 
   1          1        1    Node  inst_CLK_000_D0.C 
   1          1        1    Node  inst_CLK_000_D1.D 
   1          1        1    Node  inst_CLK_000_D1.AP 
   1          1        1    Node  inst_CLK_000_D1.C 
   1          1        1    Node  inst_CLK_000_D4.D 
   1          1        1    Node  inst_CLK_000_D4.AP 
   1          1        1    Node  inst_CLK_000_D4.C 
   1          1        1    Node  CLK_CNT_N_0_.AR 
   2          2        1    Node  CLK_CNT_N_0_.D 
   1          1        1    Node  CLK_CNT_N_0_.C 
   1          1        1    Node  inst_CLK_OUT_PRE_50.AR 
   1          1        1    Node  inst_CLK_OUT_PRE_50.D 
   1          1        1    Node  inst_CLK_OUT_PRE_50.C 
   1          1        1    Node  inst_CLK_OUT_PRE_25.AR 
   3          3        1    Node  inst_CLK_OUT_PRE_25.D 
   1          1        1    Node  inst_CLK_OUT_PRE_25.C 
   1          1        1    Node  inst_CLK_000_D2.D 
   1          1        1    Node  inst_CLK_000_D2.AP 
   1          1        1    Node  inst_CLK_000_D2.C 
   1          1        1    Node  inst_CLK_000_D3.D 
   1          1        1    Node  inst_CLK_000_D3.AP 
   1          1        1    Node  inst_CLK_000_D3.C 
   1          1        1    Node  inst_CLK_OUT_PRE_D.AR 
   1          1        1    Node  inst_CLK_OUT_PRE_D.D 
   1          1        1    Node  inst_CLK_OUT_PRE_D.C 
   1          1        1    Node  inst_CLK_OUT_PRE.AR 
   1          1        1    Node  inst_CLK_OUT_PRE.D 
   1          1        1    Node  inst_CLK_OUT_PRE.C 
   1          1        1    Node  CLK_000_P_SYNC_9_.AR 
   1          1        1    Node  CLK_000_P_SYNC_9_.D 
   1          1        1    Node  CLK_000_P_SYNC_9_.C 
  11         18        1    Node  SM_AMIGA_7_.D- 
   1          1        1    Node  SM_AMIGA_7_.AP 
   1          1        1    Node  SM_AMIGA_7_.C 
   1          1        1    Node  SM_AMIGA_6_.AR 
   2          7        1    Node  SM_AMIGA_6_.D 
   1          1        1    Node  SM_AMIGA_6_.C 
   1          1        1    Node  SM_AMIGA_1_.AR 
   2          4        1    Node  SM_AMIGA_1_.D 
   1          1        1    Node  SM_AMIGA_1_.C 
   1          1        1    Node  SM_AMIGA_0_.AR 
   2          4        1    Node  SM_AMIGA_0_.D 
   1          1        1    Node  SM_AMIGA_0_.C 
   1          1        1    Node  SM_AMIGA_4_.AR 
   2          4        1    Node  SM_AMIGA_4_.D 
   1          1        1    Node  SM_AMIGA_4_.C 
   5          8        1    Node  inst_CLK_030_H.D 
   1          1        1    Node  inst_CLK_030_H.C 
   1          1        1    Node  CLK_CNT_P_1_.AR 
   1          1        1    Node  CLK_CNT_P_1_.D 
   1          1        1    Node  CLK_CNT_P_1_.C 
   1          1        1    Node  CLK_CNT_N_1_.D 
   1          1        1    Node  CLK_CNT_N_1_.AP 
   1          1        1    Node  CLK_CNT_N_1_.C 
   1          1        1    Node  CLK_CNT_P_0_.AR 
   2          2        1    Node  CLK_CNT_P_0_.D 
   1          1        1    Node  CLK_CNT_P_0_.C 
   2          5        1    Node  inst_LDS_000_INT.D 
   1          1        1    Node  inst_LDS_000_INT.AP 
   1          1        1    Node  inst_LDS_000_INT.C 
   1          1        1    Node  inst_DS_000_ENABLE.AR 
   3          7        1    Node  inst_DS_000_ENABLE.D 
   1          1        1    Node  inst_DS_000_ENABLE.C 
   2          3        1    Node  inst_UDS_000_INT.D 
   1          1        1    Node  inst_UDS_000_INT.AP 
   1          1        1    Node  inst_UDS_000_INT.C 
   1          1        1    Node  CLK_000_P_SYNC_0_.AR 
   1          4        1    Node  CLK_000_P_SYNC_0_.D 
   1          1        1    Node  CLK_000_P_SYNC_0_.C 
   1          1        1    Node  CLK_000_P_SYNC_1_.AR 
   1          1        1    Node  CLK_000_P_SYNC_1_.D 
   1          1        1    Node  CLK_000_P_SYNC_1_.C 
   1          1        1    Node  CLK_000_P_SYNC_2_.AR 
   1          1        1    Node  CLK_000_P_SYNC_2_.D 
   1          1        1    Node  CLK_000_P_SYNC_2_.C 
   1          1        1    Node  CLK_000_P_SYNC_3_.AR 
   1          1        1    Node  CLK_000_P_SYNC_3_.D 
   1          1        1    Node  CLK_000_P_SYNC_3_.C 
   1          1        1    Node  CLK_000_P_SYNC_4_.AR 
   1          1        1    Node  CLK_000_P_SYNC_4_.D 
   1          1        1    Node  CLK_000_P_SYNC_4_.C 
   1          1        1    Node  CLK_000_P_SYNC_5_.AR 
   1          1        1    Node  CLK_000_P_SYNC_5_.D 
   1          1        1    Node  CLK_000_P_SYNC_5_.C 
   1          1        1    Node  CLK_000_P_SYNC_6_.AR 
   1          1        1    Node  CLK_000_P_SYNC_6_.D 
   1          1        1    Node  CLK_000_P_SYNC_6_.C 
   1          1        1    Node  CLK_000_P_SYNC_7_.AR 
   1          1        1    Node  CLK_000_P_SYNC_7_.D 
   1          1        1    Node  CLK_000_P_SYNC_7_.C 
   1          1        1    Node  CLK_000_P_SYNC_8_.AR 
   1          1        1    Node  CLK_000_P_SYNC_8_.D 
   1          1        1    Node  CLK_000_P_SYNC_8_.C 
   3         14        1    Node  un16_ciin- 
   1          1        1    Node  SM_AMIGA_5_.AR 
   2          4        1    Node  SM_AMIGA_5_.D 
   1          1        1    Node  SM_AMIGA_5_.C 
   1          1        1    Node  SM_AMIGA_3_.AR 
   5         10        1    Node  SM_AMIGA_3_.T 
   1          1        1    Node  SM_AMIGA_3_.C 
   1          1        1    Node  SM_AMIGA_2_.AR 
   3         10        1    Node  SM_AMIGA_2_.D 
   1          1        1    Node  SM_AMIGA_2_.C 
   1          1        1    Node  cpu_est_0_.AR 
   3          3        1    Node  cpu_est_0_.D 
   1          1        1    Node  cpu_est_0_.C 
   1          1        1    Node  cpu_est_1_.AR 
   4          6        1    Node  cpu_est_1_.T 
   1          1        1    Node  cpu_est_1_.C 
   3          6        1    NodeX1  cpu_est_2_.D.X1 
   1          1        1    NodeX2  cpu_est_2_.D.X2 
   1          1        1    Node  cpu_est_2_.AR 
   1          1        1    Node  cpu_est_2_.C 
   2          4        1    Node  AMIGA_BUS_ENABLE_LOW_0 
   3          8        1    NodeX1  SM_AMIGA_7__0.X1 
   1          5        1    NodeX2  SM_AMIGA_7__0.X2 
=========
 302                 P-Term Total: 302
                       Total Pins: 59
                      Total Nodes: 45
            Average P-Term/Output: 2


Equations:

!UDS_000 = (inst_DS_000_ENABLE.Q & !inst_UDS_000_INT.Q);

UDS_000.OE = (BGACK_030.Q);

!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q);

LDS_000.OE = (BGACK_030.Q);

CLK_DIV_OUT.AR = (!RST);

CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);

CLK_DIV_OUT.C = (CLK_OSZI);

!FPU_CS = (FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);

DTACK = (DSACK1.PIN);

DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);

AVEC = (1);

AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW.PIN
     # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW.PIN);

CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !AS_030.PIN);

CIIN.OE = (!un16_ciin);

SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);

!SIZE_1_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & LDS_000.PIN
     # !BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN);

SIZE_1_.AP = (!RST);

SIZE_1_.C = (CLK_OSZI);

IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q
     # inst_CLK_000_D1.Q & IPL_030_2_.Q
     # IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);

IPL_030_2_.AP = (!RST);

IPL_030_2_.C = (CLK_OSZI);

AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);

AS_030.D = (BGACK_030.Q
     # AS_000.PIN
     # !CLK_030 & AS_030.Q
     # UDS_000.PIN & LDS_000.PIN);

AS_030.AP = (!RST);

AS_030.C = (CLK_OSZI);

AS_000.OE = (BGACK_030.Q);

!AS_000.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q
     # BERR & !AS_000.Q & !AS_030.PIN);

AS_000.AP = (!RST);

AS_000.C = (CLK_OSZI);

RW_000.OE = (BGACK_030.Q);

!RW_000.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q & !RW_000.Q
     # !SM_AMIGA_7_.Q & !SM_AMIGA_6_.Q & !RW_000.Q
     # inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q & !RW.PIN);

RW_000.AP = (!RST);

RW_000.C = (CLK_OSZI);

IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q
     # inst_CLK_000_D1.Q & IPL_030_1_.Q
     # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);

IPL_030_1_.AP = (!RST);

IPL_030_1_.C = (CLK_OSZI);

DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);

DS_030.D = (BGACK_030.Q
     # AS_000.PIN
     # AS_030.Q & RW_000.PIN
     # UDS_000.PIN & LDS_000.PIN
     # CLK_030 & AS_030.Q & inst_CLK_030_H.Q
     # !CLK_030 & DS_030.Q & !RW_000.PIN
     # !inst_CLK_030_H.Q & DS_030.Q & !RW_000.PIN);

DS_030.AP = (!RST);

DS_030.C = (CLK_OSZI);

IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q
     # inst_CLK_000_D1.Q & IPL_030_0_.Q
     # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);

IPL_030_0_.AP = (!RST);

IPL_030_0_.C = (CLK_OSZI);

A0.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);

A0.D = (!BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN);

A0.AP = (!RST);

A0.C = (CLK_OSZI);

!BG_000.D = (!BG_030 & !BG_000.Q
     # nEXP_SPACE & !BG_030 & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & AS_030.PIN);

BG_000.AP = (!RST);

BG_000.C = (CLK_OSZI);

BGACK_030.D = (BGACK_000 & BGACK_030.Q
     # BGACK_000 & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);

BGACK_030.AP = (!RST);

BGACK_030.C = (CLK_OSZI);

CLK_EXP.AR = (!RST);

CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q);

CLK_EXP.C = (CLK_OSZI);

DSACK1.OE = (nEXP_SPACE);

!DSACK1.D = (!inst_CLK_000_D4.Q & inst_CLK_000_D3.Q & SM_AMIGA_1_.Q
     # BERR & !DSACK1.Q & !AS_030.PIN);

DSACK1.AP = (!RST);

DSACK1.C = (CLK_OSZI);

AVEC_EXP.AR = (!RST);

AVEC_EXP.D = (CLK_000_P_SYNC_9_.Q);

AVEC_EXP.C = (CLK_OSZI);

E.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_1_.Q & cpu_est_2_.Q & E.Q
     # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & !E.Q
     # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q);

E.D.X2 = (E.Q);

E.AR = (!RST);

E.C = (CLK_OSZI);

VMA.D.X1 = (VMA.Q
     # !VMA.Q & inst_CLK_000_D0.Q & AS_000.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & !E.Q);

VMA.D.X2 = (VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & cpu_est_0_.Q & !cpu_est_1_.Q);

VMA.AP = (!RST);

VMA.C = (CLK_OSZI);

RESET.AR = (!RST);

RESET.D = (1);

RESET.C = (CLK_OSZI);

RW.OE = (!BGACK_030.Q);

!RW.D = (!CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !UDS_000.PIN
     # CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN
     # !CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !LDS_000.PIN
     # CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN);

RW.AP = (!RST);

RW.C = (CLK_OSZI);

!AMIGA_BUS_ENABLE.D = (!BGACK_030.Q
     # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_1_.Q & !AS_030.PIN
     # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_0_.Q & !AS_030.PIN
     # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q
     # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q
     # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_7_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q);

AMIGA_BUS_ENABLE.AP = (!RST);

AMIGA_BUS_ENABLE.C = (CLK_OSZI);

AMIGA_BUS_ENABLE_LOW.AR = (!RST);

AMIGA_BUS_ENABLE_LOW.D = (!AMIGA_BUS_ENABLE_LOW.Q);

AMIGA_BUS_ENABLE_LOW.C = (AMIGA_BUS_ENABLE_LOW_0);

SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);

!SIZE_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN);

SIZE_0_.AP = (!RST);

SIZE_0_.C = (CLK_OSZI);

inst_AS_030_000_SYNC.D = (!BERR
     # AS_030.PIN
     # !nEXP_SPACE & inst_AS_030_000_SYNC.Q
     # !BGACK_030.Q & inst_AS_030_000_SYNC.Q
     # inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q
     # FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q);

inst_AS_030_000_SYNC.AP = (!RST);

inst_AS_030_000_SYNC.C = (CLK_OSZI);

inst_BGACK_030_INT_D.D = (BGACK_030.Q);

inst_BGACK_030_INT_D.AP = (!RST);

inst_BGACK_030_INT_D.C = (CLK_OSZI);

inst_VPA_D.D = (VPA);

inst_VPA_D.AP = (!RST);

inst_VPA_D.C = (CLK_OSZI);

inst_CLK_OUT_PRE_50_D.AR = (!RST);

inst_CLK_OUT_PRE_50_D.D = (inst_CLK_OUT_PRE_50.Q);

inst_CLK_OUT_PRE_50_D.C = (CLK_OSZI);

inst_CLK_000_D0.D = (CLK_000);

inst_CLK_000_D0.AP = (!RST);

inst_CLK_000_D0.C = (CLK_OSZI);

inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);

inst_CLK_000_D1.AP = (!RST);

inst_CLK_000_D1.C = (CLK_OSZI);

inst_CLK_000_D4.D = (inst_CLK_000_D3.Q);

inst_CLK_000_D4.AP = (!RST);

inst_CLK_000_D4.C = (CLK_OSZI);

CLK_CNT_N_0_.AR = (!RST);

CLK_CNT_N_0_.D = (CLK_CNT_N_0_.Q & CLK_CNT_N_1_.Q
     # !CLK_CNT_N_0_.Q & !CLK_CNT_N_1_.Q);

CLK_CNT_N_0_.C = (!CLK_OSZI);

inst_CLK_OUT_PRE_50.AR = (!RST);

inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);

inst_CLK_OUT_PRE_50.C = (CLK_OSZI);

inst_CLK_OUT_PRE_25.AR = (!RST);

inst_CLK_OUT_PRE_25.D = (inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_25.Q
     # !inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q
     # !inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_50.Q & !inst_CLK_OUT_PRE_25.Q);

inst_CLK_OUT_PRE_25.C = (CLK_OSZI);

inst_CLK_000_D2.D = (inst_CLK_000_D1.Q);

inst_CLK_000_D2.AP = (!RST);

inst_CLK_000_D2.C = (CLK_OSZI);

inst_CLK_000_D3.D = (inst_CLK_000_D2.Q);

inst_CLK_000_D3.AP = (!RST);

inst_CLK_000_D3.C = (CLK_OSZI);

inst_CLK_OUT_PRE_D.AR = (!RST);

inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE.Q);

inst_CLK_OUT_PRE_D.C = (CLK_OSZI);

inst_CLK_OUT_PRE.AR = (!RST);

inst_CLK_OUT_PRE.D = (inst_CLK_OUT_PRE_25.Q);

inst_CLK_OUT_PRE.C = (CLK_OSZI);

CLK_000_P_SYNC_9_.AR = (!RST);

CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q);

CLK_000_P_SYNC_9_.C = (CLK_OSZI);

!SM_AMIGA_7_.D = (SM_AMIGA_7__0
     # BERR & !inst_CLK_000_D0.Q & SM_AMIGA_0_.Q
     # BERR & SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q
     # BERR & SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q
     # BERR & !SM_AMIGA_0_.Q & SM_AMIGA_4_.Q
     # BERR & !SM_AMIGA_0_.Q & SM_AMIGA_5_.Q
     # BERR & !SM_AMIGA_0_.Q & SM_AMIGA_3_.Q
     # BERR & !SM_AMIGA_0_.Q & SM_AMIGA_2_.Q
     # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
     # VPA & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !DTACK.PIN
     # !VPA & !VMA.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !cpu_est_1_.Q & E.Q);

SM_AMIGA_7_.AP = (!RST);

SM_AMIGA_7_.C = (CLK_OSZI);

SM_AMIGA_6_.AR = (!RST);

SM_AMIGA_6_.D = (BERR & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q
     # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_7_.Q);

SM_AMIGA_6_.C = (CLK_OSZI);

SM_AMIGA_1_.AR = (!RST);

SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
     # BERR & inst_CLK_000_D0.Q & SM_AMIGA_1_.Q);

SM_AMIGA_1_.C = (CLK_OSZI);

SM_AMIGA_0_.AR = (!RST);

SM_AMIGA_0_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_1_.Q
     # BERR & !inst_CLK_000_D0.Q & SM_AMIGA_0_.Q);

SM_AMIGA_0_.C = (CLK_OSZI);

SM_AMIGA_4_.AR = (!RST);

SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q
     # BERR & !inst_CLK_000_D0.Q & SM_AMIGA_4_.Q);

SM_AMIGA_4_.C = (CLK_OSZI);

inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q
     # !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
     # !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
     # !CLK_030 & RST & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !UDS_000.PIN
     # !CLK_030 & RST & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !LDS_000.PIN);

inst_CLK_030_H.C = (CLK_OSZI);

CLK_CNT_P_1_.AR = (!RST);

CLK_CNT_P_1_.D = (CLK_CNT_P_0_.Q);

CLK_CNT_P_1_.C = (CLK_OSZI);

CLK_CNT_N_1_.D = (CLK_CNT_N_0_.Q);

CLK_CNT_N_1_.AP = (!RST);

CLK_CNT_N_1_.C = (!CLK_OSZI);

CLK_CNT_P_0_.AR = (!RST);

CLK_CNT_P_0_.D = (CLK_CNT_P_1_.Q & CLK_CNT_P_0_.Q
     # !CLK_CNT_P_1_.Q & !CLK_CNT_P_0_.Q);

CLK_CNT_P_0_.C = (CLK_OSZI);

inst_LDS_000_INT.D = (inst_LDS_000_INT.Q & DS_030.PIN
     # !DS_030.PIN & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN);

inst_LDS_000_INT.AP = (!RST);

inst_LDS_000_INT.C = (CLK_OSZI);

inst_DS_000_ENABLE.AR = (!RST);

inst_DS_000_ENABLE.D = (inst_CLK_000_D0.Q & SM_AMIGA_4_.Q
     # BERR & inst_DS_000_ENABLE.Q & !AS_030.PIN
     # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & RW.PIN);

inst_DS_000_ENABLE.C = (CLK_OSZI);

inst_UDS_000_INT.D = (inst_UDS_000_INT.Q & DS_030.PIN
     # !DS_030.PIN & A0.PIN);

inst_UDS_000_INT.AP = (!RST);

inst_UDS_000_INT.C = (CLK_OSZI);

CLK_000_P_SYNC_0_.AR = (!RST);

CLK_000_P_SYNC_0_.D = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & !inst_CLK_000_D3.Q);

CLK_000_P_SYNC_0_.C = (CLK_OSZI);

CLK_000_P_SYNC_1_.AR = (!RST);

CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q);

CLK_000_P_SYNC_1_.C = (CLK_OSZI);

CLK_000_P_SYNC_2_.AR = (!RST);

CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q);

CLK_000_P_SYNC_2_.C = (CLK_OSZI);

CLK_000_P_SYNC_3_.AR = (!RST);

CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q);

CLK_000_P_SYNC_3_.C = (CLK_OSZI);

CLK_000_P_SYNC_4_.AR = (!RST);

CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q);

CLK_000_P_SYNC_4_.C = (CLK_OSZI);

CLK_000_P_SYNC_5_.AR = (!RST);

CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q);

CLK_000_P_SYNC_5_.C = (CLK_OSZI);

CLK_000_P_SYNC_6_.AR = (!RST);

CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q);

CLK_000_P_SYNC_6_.C = (CLK_OSZI);

CLK_000_P_SYNC_7_.AR = (!RST);

CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q);

CLK_000_P_SYNC_7_.C = (CLK_OSZI);

CLK_000_P_SYNC_8_.AR = (!RST);

CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q);

CLK_000_P_SYNC_8_.C = (CLK_OSZI);

!un16_ciin = (nEXP_SPACE & AS_030.PIN
     # !A_31_ & nEXP_SPACE & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_
     # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !AS_030.PIN);

SM_AMIGA_5_.AR = (!RST);

SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q
     # BERR & inst_CLK_000_D0.Q & SM_AMIGA_5_.Q);

SM_AMIGA_5_.C = (CLK_OSZI);

SM_AMIGA_3_.AR = (!RST);

SM_AMIGA_3_.T = (!BERR & !inst_CLK_000_D0.Q & SM_AMIGA_3_.Q
     # !BERR & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q
     # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
     # VPA & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !DTACK.PIN
     # !VPA & !VMA.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q);

SM_AMIGA_3_.C = (CLK_OSZI);

SM_AMIGA_2_.AR = (!RST);

SM_AMIGA_2_.D = (BERR & !inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
     # VPA & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !DTACK.PIN
     # !VPA & !VMA.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q);

SM_AMIGA_2_.C = (CLK_OSZI);

cpu_est_0_.AR = (!RST);

cpu_est_0_.D = (!inst_CLK_000_D0.Q & cpu_est_0_.Q
     # inst_CLK_000_D1.Q & cpu_est_0_.Q
     # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q);

cpu_est_0_.C = (CLK_OSZI);

cpu_est_1_.AR = (!RST);

cpu_est_1_.T = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & cpu_est_2_.Q & E.Q
     # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q
     # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & cpu_est_2_.Q & !E.Q
     # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q);

cpu_est_1_.C = (CLK_OSZI);

cpu_est_2_.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q
     # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q
     # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q & !E.Q);

cpu_est_2_.D.X2 = (cpu_est_2_.Q);

cpu_est_2_.AR = (!RST);

cpu_est_2_.C = (CLK_OSZI);

AMIGA_BUS_ENABLE_LOW_0 = (CLK_CNT_P_1_.Q & CLK_CNT_N_1_.Q
     # !CLK_CNT_N_0_.Q & CLK_CNT_P_0_.Q);

SM_AMIGA_7__0.X1 = (!inst_CLK_000_D0.Q & !SM_AMIGA_6_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
     # !inst_CLK_000_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
     # inst_CLK_000_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);

SM_AMIGA_7__0.X2 = (inst_CLK_000_D0.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q);


Reverse-Polarity Equations: