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68030tk
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Working at 254Mhz in CDTV!

This commit is contained in:
MHeinrichs 2016-08-24 23:34:13 +02:00
parent 7b64ad431c
commit 00726c0582
66 changed files with 50597 additions and 28791 deletions
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23
Logic/68030-68000-bus.vhd
View File

@ -62,7 +62,8 @@ end BUS68030;
architecture Behavioral of BUS68030 is
-- values are determined empirically
constant DS_SAMPLE : integer := 12; -- for 7.09 MHz Clock with a base clock of 100Mhz and CPU running at 50MHZ
constant DS_SAMPLE : integer := 10; -- for 7.09 MHz Clock with a base clock of 100Mhz and CPU running at 25MHZ
--constant DS_SAMPLE : integer := 12; -- for 7.09 MHz Clock with a base clock of 100Mhz and CPU running at 50MHZ
@ -160,8 +161,8 @@ begin
--here the clock is selected
--CLK_OUT_PRE_D <= CLK_OUT_PRE_25;
CLK_OUT_PRE_D <= CLK_OUT_PRE_50;
CLK_OUT_PRE_D <= CLK_OUT_PRE_25;
--CLK_OUT_PRE_D <= CLK_OUT_PRE_50;
-- the external clock to the processor is generated here
CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
@ -257,12 +258,13 @@ begin
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
if(BGACK_000='0') then
BGACK_030_INT <= '0';
--BGACK_030_INT_PRE<= '0';
elsif ( BGACK_000='1'
AND CLK_000_PE='1'
AND AS_000 = '1' --the amiga AS can be still active while bgack is deasserted, so wait for this signal too!
) then -- BGACK_000 is high here!
BGACK_030_INT_PRE<= '1';
BGACK_030_INT <= BGACK_030_INT_PRE; --hold this signal high until 7m clock goes low
--BGACK_030_INT_PRE<= '1';
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes low
end if;
BGACK_030_INT_D <= BGACK_030_INT;
@ -339,7 +341,7 @@ begin
case (SM_AMIGA) is
when IDLE_P => --68000:S0 wait for a falling edge
RW_000_INT <= '1';
if( CLK_000_D(1)='0' and CLK_000_D(2)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
if( CLK_000_D(0)='0' and CLK_000_D(1)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
SM_AMIGA<=IDLE_N; --go to s1
end if;
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
@ -363,7 +365,6 @@ begin
SM_AMIGA <= SAMPLE_DTACK_P;
end if;
when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
DS_000_ENABLE <= '1';
if( CLK_000_NE='1' and --falling edge
((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
@ -371,18 +372,17 @@ begin
SM_AMIGA<=DATA_FETCH_N;
end if;
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
DS_000_ENABLE <= '1';
if(CLK_000_PE = '1')then --go to s6
SM_AMIGA<=DATA_FETCH_P;
end if;
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
DS_000_ENABLE <= '1';
if( (CLK_000_D(DS_SAMPLE-2)='0' AND CLK_000_D((DS_SAMPLE-1))='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
(CLK_000_D(DS_SAMPLE-1)='0' AND CLK_000_D((DS_SAMPLE-0))='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
DSACK1_INT <='0';
end if;
if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
SM_AMIGA<=END_CYCLE_N;
DSACK1_INT <='0';
end if;
when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
if(CLK_000_PE='1')then --go to s0
@ -434,10 +434,8 @@ begin
and AS_000='0'
and(UDS_000='0' or LDS_000='0')
and (
--CYCLE_DMA ="00" or
CYCLE_DMA ="01"
or CYCLE_DMA ="10"
--or CYCLE_DMA ="11"
)
)then
--set AS_000
@ -460,7 +458,8 @@ begin
DS_000_DMA <= '1';
CLK_030_H <= '0';
end if;
end if;
end if;
end if;
end process pos_clk;

2
Logic/68030_TK.STY
View File

@ -2,5 +2,3 @@
tool=Synplify
[STRATEGY-LIST]
Normal=True, 1412327082
[TOUCHED-REPORT]
Design.tt4File=1471555574

10
Logic/68030_TK.cmi
View File

@ -1,8 +1,8 @@
[WINDOWS]
MAIN_WINDOW_POSITION=-7,0,967,1167
MAIN_WINDOW_POSITION=0,0,967,1167
LEFT_PANE_WIDTH=245
CHILD_FRAME_STATE=Maximal
CHILD_WINDOW_SIZE=974,941
CHILD_WINDOW_SIZE=967,941
CHILD_WINDOW_POS=-8,-31
[GUI SETTING]
Remember_Setting=1
@ -40,10 +40,10 @@ State=43,no
Constraint Name=162,no
Constraint Value=115,no
[OPT WINDOWS]
MAIN_WINDOW_POSITION=0,0,1920,1200
MAIN_WINDOW_POSITION=293,579,755,1330
CHILD_FRAME_STATE=Maximal
CHILD_WINDOW_SIZE=1920,974
CHILD_WINDOW_POS=-8,-30
CHILD_WINDOW_SIZE=462,525
CHILD_WINDOW_POS=-8,-31
[OPT GUI SETTING]
Remember_Setting=1
ACTIVE_SHEET=Opt Global Constraints

20
Logic/68030_TK.lci
View File

@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
[Revision]
Parent = m4a5.lci;
DATE = 08/18/2016;
TIME = 23:26:14;
DATE = 08/23/2016;
TIME = 20:07:14;
Source_Format = Pure_VHDL;
Synthesis = Synplify;
@ -26,14 +26,17 @@ Synthesis = Synplify;
[Global Constraints]
Spread_placement = Yes;
Zero_hold_time = Yes;
Max_pterm_split = 16;
Max_pterm_collapse = 16;
Max_pterm_split = 20;
Max_pterm_collapse = 20;
Nodes_collapsing_mode = Speed;
Max_fanin = 32;
Set_reset_dont_care = No;
Set_reset_dont_care = Yes;
Balanced_partitioning = Yes;
Max_macrocell_percent = 100;
Dt_synthesis = Yes;
Xor_synthesis = Yes;
Logic_reduction = Yes;
Node_collapse = Yes;
[Location Assignments]
layer = OFF;
@ -150,7 +153,12 @@ Default = UP;
[Slewrate]
FAST = CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW,
AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH;
AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH, AS_030, A_16_, A_17_, A_18_,
A_19_, RW, SIZE_1_, SIZE_0_, AVEC, BGACK_030, BG_000, E, IPL_030_0_, IPL_030_1_,
IPL_030_2_, LDS_000, UDS_000, VMA, RESET, CIIN, A_20_, A_21_, A_22_, A_24_,
A_25_, A_26_, A_27_, A_28_, A_29_, A_30_, A_31_, DS_030, BERR, A0, DSACK1,
RW_000, AS_000, A_23_, A1, A_3_, A_2_, AHIGH_24_, AHIGH_25_, AHIGH_26_,
AHIGH_27_, AHIGH_28_, AHIGH_29_, AHIGH_30_, AHIGH_31_, A_0_;
Default = Slow;
[Region]

20
Logic/68030_TK.lct
View File

@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
[Revision]
Parent = m4a5.lci;
DATE = 08/18/2016;
TIME = 23:26:14;
DATE = 08/23/2016;
TIME = 20:07:14;
Source_Format = Pure_VHDL;
Synthesis = Synplify;
@ -26,14 +26,17 @@ Synthesis = Synplify;
[Global Constraints]
Spread_placement = Yes;
Zero_hold_time = Yes;
Max_pterm_split = 16;
Max_pterm_collapse = 16;
Max_pterm_split = 20;
Max_pterm_collapse = 20;
Nodes_collapsing_mode = Speed;
Max_fanin = 32;
Set_reset_dont_care = No;
Set_reset_dont_care = Yes;
Balanced_partitioning = Yes;
Max_macrocell_percent = 100;
Dt_synthesis = Yes;
Xor_synthesis = Yes;
Logic_reduction = Yes;
Node_collapse = Yes;
[Location Assignments]
layer = OFF;
@ -150,7 +153,12 @@ Default = UP;
[Slewrate]
FAST = CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW,
AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH;
AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH, AS_030, A_16_, A_17_, A_18_,
A_19_, RW, SIZE_1_, SIZE_0_, AVEC, BGACK_030, BG_000, E, IPL_030_0_, IPL_030_1_,
IPL_030_2_, LDS_000, UDS_000, VMA, RESET, CIIN, A_20_, A_21_, A_22_, A_24_,
A_25_, A_26_, A_27_, A_28_, A_29_, A_30_, A_31_, DS_030, BERR, A0, DSACK1,
RW_000, AS_000, A_23_, A1, A_3_, A_2_, AHIGH_24_, AHIGH_25_, AHIGH_26_,
AHIGH_27_, AHIGH_28_, AHIGH_29_, AHIGH_30_, AHIGH_31_, A_0_;
Default = Slow;
[Region]

24523
Logic/68030_TK.tcl
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File diff suppressed because it is too large Load Diff

2
Logic/68030_tk.b2_
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@ -1 +1 @@
-collapse all -pterms 16 -nmax 32 -clust 5 -reduce bypin choose -xorsyn -dev M4A5_clk
-collapse all -pterms 20 -nmax 32 -clust 5 -reduce bypin choose -xorsyn -dev M4A5_clk

3046
Logic/68030_tk.bl2
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File diff suppressed because it is too large Load Diff

473
Logic/68030_tk.bl3
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@ -1,26 +1,25 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Fri Aug 19 00:39:35 2016
#$ DATE Wed Aug 24 22:17:49 2016
#$ MODULE 68030_tk
#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 \
# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 SIZE_0_ BGACK_030 AHIGH_30_ \
# BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT \
# AHIGH_25_ CLK_EXP AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 \
# A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ VMA \
# RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
# AMIGA_BUS_ENABLE_HIGH CIIN A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_
#$ NODES 63 inst_BGACK_030_INTreg inst_VMA_INTreg cpu_est_3_ cpu_est_0_ cpu_est_1_ \
#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 SIZE_0_ \
# AS_000 AHIGH_30_ RW_000 AHIGH_29_ DS_030 AHIGH_28_ UDS_000 AHIGH_27_ LDS_000 AHIGH_26_ \
# nEXP_SPACE AHIGH_25_ BERR AHIGH_24_ BG_030 A_DECODE_22_ BG_000 A_DECODE_21_ BGACK_030 \
# A_DECODE_20_ BGACK_000 A_DECODE_19_ CLK_030 A_DECODE_18_ CLK_000 A_DECODE_17_ \
# CLK_OSZI A_DECODE_16_ CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST \
# RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR A_0_ AMIGA_BUS_ENABLE_LOW IPL_030_1_ \
# AMIGA_BUS_ENABLE_HIGH IPL_030_0_ CIIN IPL_1_ IPL_0_ FC_0_ A_1_
#$ NODES 62 inst_BGACK_030_INTreg inst_VMA_INTreg cpu_est_3_ cpu_est_0_ cpu_est_1_ \
# cpu_est_2_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 \
# inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA \
# CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT \
# inst_LDS_000_INT inst_CLK_OUT_PRE_D CLK_000_D_1_ CLK_000_D_10_ CLK_000_D_11_ \
# inst_DTACK_D0 inst_RESET_OUT CLK_000_D_0_ inst_CLK_OUT_PRE_50 IPL_D0_0_ IPL_D0_1_ \
# IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_ CLK_000_D_6_ \
# CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ \
# inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg inst_DS_000_ENABLE SM_AMIGA_6_ \
# SM_AMIGA_0_ SM_AMIGA_4_ inst_RW_000_INT inst_RW_000_DMA RST_DLY_0_ RST_DLY_1_ \
# RST_DLY_2_ inst_A0_DMA inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_5_ SM_AMIGA_3_ \
# SM_AMIGA_2_ SM_AMIGA_i_7_ BG_000DFFreg CLK_OUT_INTreg IPL_030DFF_0_reg \
# IPL_030DFF_1_reg IPL_030DFF_2_reg
# inst_LDS_000_INT inst_CLK_OUT_PRE_D CLK_000_D_8_ CLK_000_D_9_ inst_DTACK_D0 \
# inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 \
# IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_ \
# CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_10_ inst_AMIGA_BUS_ENABLE_DMA_HIGH \
# inst_DSACK1_INTreg inst_DS_000_ENABLE SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_0_ \
# inst_RW_000_INT inst_RW_000_DMA RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_A0_DMA \
# inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ \
# BG_000DFFreg CLK_OUT_INTreg IPL_030DFF_0_reg IPL_030DFF_1_reg IPL_030DFF_2_reg
.model bus68030
.inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \
@ -33,13 +32,13 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \
inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF \
inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF SIZE_DMA_0_.BLIF \
SIZE_DMA_1_.BLIF inst_VPA_D.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \
inst_CLK_OUT_PRE_D.BLIF CLK_000_D_1_.BLIF CLK_000_D_10_.BLIF \
CLK_000_D_11_.BLIF inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF CLK_000_D_0_.BLIF \
inst_CLK_OUT_PRE_50.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF \
CLK_000_D_2_.BLIF CLK_000_D_3_.BLIF CLK_000_D_4_.BLIF CLK_000_D_5_.BLIF \
CLK_000_D_6_.BLIF CLK_000_D_7_.BLIF CLK_000_D_8_.BLIF CLK_000_D_9_.BLIF \
CLK_000_D_12_.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_DSACK1_INTreg.BLIF \
inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF \
inst_CLK_OUT_PRE_D.BLIF CLK_000_D_8_.BLIF CLK_000_D_9_.BLIF inst_DTACK_D0.BLIF \
inst_RESET_OUT.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \
inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF IPL_D0_0_.BLIF \
IPL_D0_1_.BLIF IPL_D0_2_.BLIF CLK_000_D_2_.BLIF CLK_000_D_3_.BLIF \
CLK_000_D_4_.BLIF CLK_000_D_5_.BLIF CLK_000_D_6_.BLIF CLK_000_D_7_.BLIF \
CLK_000_D_10_.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_DSACK1_INTreg.BLIF \
inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_0_.BLIF \
inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
RST_DLY_2_.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF SM_AMIGA_1_.BLIF \
SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF \
@ -57,29 +56,29 @@ SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \
SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C \
IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \
IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D \
IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C CLK_000_D_6_.D CLK_000_D_6_.C \
CLK_000_D_7_.D CLK_000_D_7_.C CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D \
CLK_000_D_9_.C CLK_000_D_10_.D CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C \
CLK_000_D_12_.D CLK_000_D_12_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \
IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C CLK_000_D_4_.D CLK_000_D_4_.C \
CLK_000_D_5_.D CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D \
CLK_000_D_7_.C CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C \
CLK_000_D_10_.D CLK_000_D_10_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \
CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C RST_DLY_1_.C RST_DLY_2_.D \
RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \
CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D \
CLK_000_D_4_.C CLK_000_D_5_.D CLK_000_D_5_.C RST_DLY_0_.D RST_DLY_0_.C \
inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_030_000_SYNC.D \
inst_AS_030_000_SYNC.C inst_AS_000_INT.D inst_AS_000_INT.C \
inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D inst_DS_000_DMA.C \
inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \
inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C \
inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C \
CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C RST_DLY_0_.D \
RST_DLY_0_.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \
inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C \
inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_000_INT.D \
inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \
inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C \
inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.D \
inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \
inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C BG_000DFFreg.D BG_000DFFreg.C \
inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \
inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \
inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \
inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_DMA.D inst_RW_000_DMA.C \
inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \
inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D \
inst_RW_000_INT.D inst_RW_000_INT.C inst_BGACK_030_INT_D.D \
inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \
CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \
SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ \
AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ \
AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE \
@ -89,19 +88,19 @@ CIIN.OE cpu_est_2_.D.X1 cpu_est_2_.D.X2 RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 \
inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 \
SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2
.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF CLK_000_D_2_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF \
BERR.PIN.BLIF SM_AMIGA_6_.D
1100-1-0- 1
-1--0-111 1
-1-1--111 1
---01--1- 0
------01- 0
-----0-0- 0
---1---0- 0
--1----0- 0
0------0- 0
-0------- 0
-------10 0
CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF \
SM_AMIGA_6_.D
11010-0- 1
-1--0111 1
-1-1-111 1
-----01- 0
---01--- 0
--1---0- 0
0-----0- 0
----1-0- 0
---0--0- 0
------10 0
-0------ 0
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \
SM_AMIGA_5_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D
1011-- 1
@ -129,21 +128,21 @@ SM_AMIGA_5_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D
--1--0 0
-0---0 0
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF \
cpu_est_1_.BLIF cpu_est_2_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \
inst_DTACK_D0.BLIF CLK_000_D_0_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \
cpu_est_1_.BLIF cpu_est_2_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \
BERR.PIN.BLIF SM_AMIGA_2_.D
10100001-01-- 1
1-----11001-- 1
1010000-101-- 1
1-----10101-- 1
1--------0-11 1
1------1---11 1
------1-1--0- 0
1-------1--11 1
------11---0- 0
-----10----0- 0
----1-0----0- 0
---1--0----0- 0
--0---0----0- 0
-1----0----0- 0
------1-1---0 0
-------0-1--- 0
------11----0 0
--------01--- 0
-----10-----0 0
----1-0-----0 0
---1--0-----0 0
@ -151,11 +150,11 @@ BERR.PIN.BLIF SM_AMIGA_2_.D
-1----0-----0 0
----------00- 0
---------1-0- 0
-------0---0- 0
--------0--0- 0
----------0-0 0
0------------ 0
---------1--0 0
-------0----0 0
--------0---0 0
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF \
SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_1_.D
101-1- 1
@ -355,6 +354,24 @@ RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_0_.D
--10-- 0
-0-0-- 0
0----- 0
.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \
SIZE_1_.PIN.BLIF A_0_.PIN.BLIF inst_LDS_000_INT.D
--1100 1
-10--- 1
0----- 1
100--- 0
1-1-1- 0
1-10-- 0
1-1--1 0
.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
1--011 1
1-1--- 1
-0---- 1
-10-0- 0
-101-- 0
01---- 0
-10--0 0
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
LDS_000.PIN.BLIF inst_AS_000_DMA.D
@ -407,25 +424,36 @@ CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF BERR.PIN.BLIF inst_AS_000_INT.D
1--011- 0
100---1 0
.names CLK_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_CLK_OUT_PRE_D.BLIF \
CLK_000_D_10_.BLIF CLK_000_D_11_.BLIF CLK_000_D_12_.BLIF \
inst_DSACK1_INTreg.BLIF SM_AMIGA_1_.BLIF BERR.PIN.BLIF inst_DSACK1_INTreg.D
1--0-1-1-- 1
-----001-- 1
----11-1-- 1
1-10-1---- 1
-------10- 1
1--0-1---0 1
--1--00--- 1
--1-11---- 1
-----00--0 1
----11---0 1
--1-----0- 1
-0-------- 1
--------00 1
-1-101--1- 0
01--01--1- 0
-1---01-1- 0
-10----0-1 0
CLK_000_D_8_.BLIF CLK_000_D_9_.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \
CLK_000_D_10_.BLIF inst_DSACK1_INTreg.BLIF SM_AMIGA_1_.BLIF BERR.PIN.BLIF \
inst_DSACK1_INTreg.D
1--0-1-1-1-- 1
1--0-10--1-- 1
-----0-101-- 1
-----00-01-- 1
----11-1-1-- 1
----110--1-- 1
1-10-1-1---- 1
1-10-10----- 1
1--0-1-1---0 1
1--0-10----0 1
--1--0-10--- 1
--1--00-0--- 1
--1-11-1---- 1
--1-110----- 1
---------10- 1
-----0-10--0 1
-----00-0--0 1
----11-1---0 1
----110----0 1
--1-------0- 1
-0---------- 1
----------00 1
-1-101----1- 0
01--01----1- 0
-1---0--1-1- 0
-1----10--1- 0
-10------0-1 0
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF \
AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
@ -467,56 +495,42 @@ inst_DS_000_DMA.D
1- 1
-0 1
01 0
.names RST.BLIF CLK_000_D_1_.BLIF inst_RESET_OUT.BLIF CLK_000_D_0_.BLIF \
.names RST.BLIF inst_RESET_OUT.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \
RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D
11-0111 1
1-1---- 1
1-10111 1
11----- 1
0------ 0
--0--0- 0
--0-0-- 0
--01--- 0
-0---0- 0
-0--0-- 0
-0-1--- 0
-00---- 0
--0---0 0
-0----0 0
.names RST.BLIF inst_AS_030_D0.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \
inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF \
SM_AMIGA_5_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF RW.PIN.BLIF \
inst_DS_000_ENABLE.D
1-01-00-01-- 1
1-01--0-01-1 1
1----00001-- 1
10--1-----1- 1
---0---1--0- 0
--1----1--0- 0
---00--1---- 0
--1-0--1---- 0
-1-0---1---- 0
-11----1---- 0
---0-1----0- 0
--1--1----0- 0
---001------ 0
--1-01------ 0
-1-0-1------ 0
-11--1------ 0
---------00- 0
--------1-0- 0
------1---0- 0
----0----0-- 0
-1-------0-- 0
----0---1--- 0
-1------1--- 0
----0-1----- 0
-1----1----- 0
-----1----00 0
----01-----0 0
-1---1-----0 0
0----------- 0
inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF BERR.PIN.BLIF \
RW.PIN.BLIF inst_DS_000_ENABLE.D
10--1--1- 1
1-01--1-- 1
1-01-1--1 1
-----000- 0
----000-- 0
-1---00-- 0
------000 0
---0---0- 0
--1----0- 0
----0-0-0 0
-1----0-0 0
---00---- 0
--1-0---- 0
-1-0----- 0
-11------ 0
0-------- 0
.names nEXP_SPACE.BLIF BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF \
CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D
--0--- 1
-1---- 1
----01 1
---0-1 1
0----1 1
--0--- 1
-1---- 1
10111- 0
-01--0 0
.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
@ -556,13 +570,13 @@ cpu_est_1_.BLIF cpu_est_2_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF inst_VMA_INTreg.D
--0000-01 1
-1----1-- 1
-1------1 1
-1-----0- 1
-1---1--- 1
-1--0---- 1
-1-0----- 1
-11------ 1
0-------- 1
-1-----0- 1
-1--0---- 1
-1-0----- 1
-1------1 1
1-0110010 0
10---1--- 0
101------ 0
@ -581,9 +595,9 @@ inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D
.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \
SM_AMIGA_0_.BLIF inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF \
inst_RW_000_INT.D
---0-1-- 1
-01-1--- 1
-011---1 1
---0-1-- 1
--0--1-- 1
-1---1-- 1
------0- 1
@ -592,24 +606,6 @@ inst_RW_000_INT.D
1--0001- 0
1-0--01- 0
11---01- 0
.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \
SIZE_1_.PIN.BLIF A_0_.PIN.BLIF inst_LDS_000_INT.D
--1100 1
-10--- 1
0----- 1
100--- 0
1-1-1- 0
1-10-- 0
1-1--1 0
.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF CLK_000_D_1_.BLIF \
CLK_000_D_0_.BLIF AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
1--011 1
1-1--- 1
-0---- 1
-10-0- 0
-101-- 0
01---- 0
-10--0 0
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
0- 1
-1 1
@ -758,6 +754,18 @@ AHIGH_31_.PIN.BLIF CIIN
.names CLK_OSZI.BLIF IPL_D0_2_.C
1 1
0 0
.names CLK_000_D_3_.BLIF CLK_000_D_4_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_4_.C
1 1
0 0
.names CLK_000_D_4_.BLIF CLK_000_D_5_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_5_.C
1 1
0 0
.names CLK_000_D_5_.BLIF CLK_000_D_6_.D
1 1
0 0
@ -788,18 +796,6 @@ AHIGH_31_.PIN.BLIF CIIN
.names CLK_OSZI.BLIF CLK_000_D_10_.C
1 1
0 0
.names CLK_000_D_10_.BLIF CLK_000_D_11_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_11_.C
1 1
0 0
.names CLK_000_D_11_.BLIF CLK_000_D_12_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_12_.C
1 1
0 0
.names CLK_OSZI.BLIF CYCLE_DMA_0_.C
1 1
0 0
@ -848,21 +844,15 @@ AHIGH_31_.PIN.BLIF CIIN
.names CLK_OSZI.BLIF CLK_000_D_3_.C
1 1
0 0
.names CLK_000_D_3_.BLIF CLK_000_D_4_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_4_.C
1 1
0 0
.names CLK_000_D_4_.BLIF CLK_000_D_5_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_000_D_5_.C
1 1
0 0
.names CLK_OSZI.BLIF RST_DLY_0_.C
1 1
0 0
.names CLK_OSZI.BLIF inst_LDS_000_INT.C
1 1
0 0
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
1 1
0 0
.names CLK_OSZI.BLIF inst_AS_000_DMA.C
1 1
0 0
@ -896,6 +886,14 @@ AHIGH_31_.PIN.BLIF CIIN
.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C
1 1
0 0
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D
10 1
01 1
00 0
11 0
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_25.C
1 1
0 0
.names CLK_OSZI.BLIF BG_000DFFreg.C
1 1
0 0
@ -920,30 +918,24 @@ AHIGH_31_.PIN.BLIF CIIN
.names CLK_OSZI.BLIF inst_RW_000_INT.C
1 1
0 0
.names CLK_OSZI.BLIF inst_LDS_000_INT.C
1 1
0 0
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
1 1
0 0
.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C
1 1
0 0
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D
.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_D.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_D.C
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C
1 1
0 0
.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_OUT_INTreg.C
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C
1 1
0 0
.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_1_
01 1
1- 0
@ -1181,75 +1173,72 @@ UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_CLK_030_H.D.X2
-0- 0
--0 0
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF \
cpu_est_1_.BLIF cpu_est_2_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \
inst_DTACK_D0.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \
cpu_est_1_.BLIF cpu_est_2_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \
BERR.PIN.BLIF SM_AMIGA_3_.D.X2
1------0-110- 1
1------0-11-0 1
10100001-0-11 1
1-----1100-11 1
1-------0110- 1
1-------011-0 1
1010000-10-11 1
1-----1010-11 1
0------------ 0
-------1-1--- 0
-------0-0--- 0
-------0--0-- 0
-------1---0- 0
-------1----0 0
-1----01----- 0
--0---01----- 0
---1--01----- 0
----1-01----- 0
-----101----- 0
--------11--- 0
--------00--- 0
--------0-0-- 0
--------1--0- 0
--------1---0 0
-1----0-1---- 0
--0---0-1---- 0
---1--0-1---- 0
----1-0-1---- 0
-----10-1---- 0
------111---- 0
-------0---11 0
--------0--11 0
.names RST.BLIF BERR.PIN.BLIF SM_AMIGA_i_7_.D.X1
11 1
0- 0
-0 0
.names nEXP_SPACE.BLIF RST.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF \
cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF inst_AS_030_000_SYNC.BLIF \
inst_VPA_D.BLIF CLK_000_D_1_.BLIF inst_DTACK_D0.BLIF CLK_000_D_0_.BLIF \
CLK_000_D_2_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF \
SM_AMIGA_1_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \
BERR.PIN.BLIF SM_AMIGA_i_7_.D.X2
11-----0-0--100000000 1
-1-------0-1-------10 1
-1-------0-1---1----0 1
-1-------0-1-1------0 1
-1-------1-0----1---0 1
-1-------1-0-----1--0 1
-101000-01-0------1-0 1
-1------1100------1-0 1
01-----------00000001 1
-1-----1-----00000001 1
-1-------1---00000001 1
-1----------000000001 1
-1-------0-1-01000001 1
-0------------------- 0
-------------1------1 0
---------------1----1 0
----------------1---1 0
-----------------1--1 0
------------------1-1 0
-------------------11 0
---------0-0-1------- 0
---------0-0---1----- 0
---------0-0-------1- 0
---------1----1-----1 0
-----------0--1-----1 0
---------1-1--------0 0
---------0---0-01--0- 0
---------0---0-0-1-0- 0
---------0---0-0--10- 0
---------1------000-0 0
1------0-0--1-0-----1 0
--1-----01------00--0 0
---0----01------00--0 0
----1---01------00--0 0
-----1--01------00--0 0
------1-01------00--0 0
--------111-----00--0 0
0--------0---0-0---00 0
-------1-0---0-0---00 0
---------0--00-0---00 0
---------0---010---00 0
inst_VPA_D.BLIF inst_DTACK_D0.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \
SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_1_.BLIF \
SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF \
SM_AMIGA_i_7_.D.X2
-1--------011------0 1
-1--------01-1-----0 1
-1--------01------10 1
-1--------10---1---0 1
-1--------10----1--0 1
11-----0--10000--000 1
-101000-0-10-----1-0 1
-1------1010-----1-0 1
-1--------0100-00001 1
01----------00000001 1
-1-----1----00000001 1
-1--------0-00000001 1
-1---------100000001 1
-0------------------ 0
------------1------1 0
-------------1-----1 0
---------------1---1 0
----------------1--1 0
-----------------1-1 0
------------------11 0
----------1---1----1 0
-----------0--1----1 0
----------11-------0 0
----------00-------0 0
----------1-1--000-- 0
----------1--1-000-- 0
----------1---1000-- 0
----------1----0001- 0
1------0--10-------1 0
----------0-00----00 0
--1-----0-1----001-- 0
---0----0-1----001-- 0
----1---0-1----001-- 0
-----1--0-1----001-- 0
------1-0-1----001-- 0
--------111----001-- 0
0---------1----000-0 0
-------1--1----000-0 0
.end

2
Logic/68030_tk.crf
View File

@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 2.0.00.17.20.15
// Design '68030_tk' created Fri Aug 19 00:39:35 2016
// Design '68030_tk' created Wed Aug 24 22:17:49 2016
// LEGEND: '>' Functional Block Port Separator

193
Logic/68030_tk.eq3
View File

@ -2,7 +2,7 @@
Copyright(C), 1992-2015, Lattice Semiconductor Corp.
All Rights Reserved.
Design bus68030 created Fri Aug 19 00:39:35 2016
Design bus68030 created Wed Aug 24 22:17:49 2016
P-Terms Fan-in Fan-out Type Name (attributes)
@ -13,34 +13,34 @@ Design bus68030 created Fri Aug 19 00:39:35 2016
1 3 1 Pin AHIGH_31_.OE
1 2 1 Pin AS_030-
1 3 1 Pin AS_030.OE
1 2 1 Pin AS_000-
1 2 1 Pin AS_000.OE
1 2 1 Pin DS_030-
1 3 1 Pin DS_030.OE
1 2 1 Pin UDS_000-
1 2 1 Pin UDS_000.OE
1 2 1 Pin LDS_000-
1 2 1 Pin LDS_000.OE
0 0 1 Pin BERR
1 9 1 Pin BERR.OE
1 2 1 Pin SIZE_0_
1 2 1 Pin SIZE_0_.OE
1 2 1 Pin AS_000-
1 2 1 Pin AS_000.OE
0 0 1 Pin AHIGH_30_
1 3 1 Pin AHIGH_30_.OE
0 0 1 Pin AHIGH_29_
1 3 1 Pin AHIGH_29_.OE
1 2 1 Pin DS_030-
1 3 1 Pin DS_030.OE
0 0 1 Pin AHIGH_28_
1 3 1 Pin AHIGH_28_.OE
1 2 1 Pin UDS_000-
1 2 1 Pin UDS_000.OE
0 0 1 Pin AHIGH_27_
1 3 1 Pin AHIGH_27_.OE
1 2 1 Pin LDS_000-
1 2 1 Pin LDS_000.OE
0 0 1 Pin AHIGH_26_
1 3 1 Pin AHIGH_26_.OE
1 1 1 Pin CLK_DIV_OUT.D
1 1 1 Pin CLK_DIV_OUT.C
0 0 1 Pin AHIGH_25_
1 3 1 Pin AHIGH_25_.OE
0 0 1 Pin BERR
1 9 1 Pin BERR.OE
0 0 1 Pin AHIGH_24_
1 3 1 Pin AHIGH_24_.OE
1 1 1 Pin CLK_DIV_OUT.D
1 1 1 Pin CLK_DIV_OUT.C
1 9 1 Pin FPU_CS-
1 0 1 Pin AVEC
2 3 1 Pin E
@ -64,7 +64,7 @@ Design bus68030 created Fri Aug 19 00:39:35 2016
1 1 1 Pin CLK_EXP.D
1 1 1 Pin CLK_EXP.C
1 1 1 Pin DSACK1.OE
4 10 1 Pin DSACK1.D-
5 12 1 Pin DSACK1.D-
1 1 1 Pin DSACK1.C
3 9 1 Pin VMA.T
1 1 1 Pin VMA.C
@ -117,20 +117,22 @@ Design bus68030 created Fri Aug 19 00:39:35 2016
1 1 1 Node inst_LDS_000_INT.C
1 1 1 Node inst_CLK_OUT_PRE_D.D
1 1 1 Node inst_CLK_OUT_PRE_D.C
1 1 1 Node CLK_000_D_1_.D
1 1 1 Node CLK_000_D_1_.C
1 1 1 Node CLK_000_D_10_.D
1 1 1 Node CLK_000_D_10_.C
1 1 1 Node CLK_000_D_11_.D
1 1 1 Node CLK_000_D_11_.C
1 1 1 Node CLK_000_D_8_.D
1 1 1 Node CLK_000_D_8_.C
1 1 1 Node CLK_000_D_9_.D
1 1 1 Node CLK_000_D_9_.C
1 2 1 Node inst_DTACK_D0.D-
1 1 1 Node inst_DTACK_D0.C
2 7 1 Node inst_RESET_OUT.D
1 1 1 Node inst_RESET_OUT.C
1 1 1 Node CLK_000_D_1_.D
1 1 1 Node CLK_000_D_1_.C
1 1 1 Node CLK_000_D_0_.D
1 1 1 Node CLK_000_D_0_.C
1 1 1 Node inst_CLK_OUT_PRE_50.D
1 1 1 Node inst_CLK_OUT_PRE_50.C
2 2 1 Node inst_CLK_OUT_PRE_25.D
1 1 1 Node inst_CLK_OUT_PRE_25.C
1 2 1 Node IPL_D0_0_.D-
1 1 1 Node IPL_D0_0_.C
1 2 1 Node IPL_D0_1_.D-
@ -149,22 +151,18 @@ Design bus68030 created Fri Aug 19 00:39:35 2016
1 1 1 Node CLK_000_D_6_.C
1 1 1 Node CLK_000_D_7_.D
1 1 1 Node CLK_000_D_7_.C
1 1 1 Node CLK_000_D_8_.D
1 1 1 Node CLK_000_D_8_.C
1 1 1 Node CLK_000_D_9_.D
1 1 1 Node CLK_000_D_9_.C
1 1 1 Node CLK_000_D_12_.D
1 1 1 Node CLK_000_D_12_.C
1 1 1 Node CLK_000_D_10_.D
1 1 1 Node CLK_000_D_10_.C
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
4 12 1 Node inst_DS_000_ENABLE.D
3 9 1 Node inst_DS_000_ENABLE.D
1 1 1 Node inst_DS_000_ENABLE.C
3 9 1 Node SM_AMIGA_6_.D
3 8 1 Node SM_AMIGA_6_.D
1 1 1 Node SM_AMIGA_6_.C
3 6 1 Node SM_AMIGA_0_.D
1 1 1 Node SM_AMIGA_0_.C
3 6 1 Node SM_AMIGA_4_.D
1 1 1 Node SM_AMIGA_4_.C
3 6 1 Node SM_AMIGA_0_.D
1 1 1 Node SM_AMIGA_0_.C
4 6 1 Node RST_DLY_0_.D
1 1 1 Node RST_DLY_0_.C
2 6 1 NodeX1 RST_DLY_1_.D.X1
@ -183,14 +181,14 @@ Design bus68030 created Fri Aug 19 00:39:35 2016
1 1 1 Node SM_AMIGA_3_.C
4 13 1 Node SM_AMIGA_2_.D
1 1 1 Node SM_AMIGA_2_.C
13 21 1 NodeX1 SM_AMIGA_i_7_.D.X1
13 20 1 NodeX1 SM_AMIGA_i_7_.D.X1
1 2 1 NodeX2 SM_AMIGA_i_7_.D.X2
1 1 1 Node SM_AMIGA_i_7_.C
2 14 1 Node CIIN_0
=========
301 P-Term Total: 301
300 P-Term Total: 300
Total Pins: 61
Total Nodes: 53
Total Nodes: 52
Average P-Term/Output: 2
@ -208,30 +206,14 @@ AHIGH_31_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);
AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN);
DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q);
UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q);
LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
BERR = (0);
BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q);
!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);
AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_30_ = (0);
AHIGH_30_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
@ -240,30 +222,46 @@ AHIGH_29_ = (0);
AHIGH_29_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN);
DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_28_ = (0);
AHIGH_28_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q);
UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_27_ = (0);
AHIGH_27_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q);
LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_26_ = (0);
AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
CLK_DIV_OUT.C = (CLK_OSZI);
AHIGH_25_ = (0);
AHIGH_25_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
BERR = (0);
BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
AHIGH_24_ = (0);
AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
CLK_DIV_OUT.C = (CLK_OSZI);
!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
AVEC = (1);
@ -328,10 +326,11 @@ CLK_EXP.C = (CLK_OSZI);
DSACK1.OE = (nEXP_SPACE);
!DSACK1.D = (RST & !CLK_000_D_11_.Q & CLK_000_D_12_.Q & SM_AMIGA_1_.Q
!DSACK1.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q
# RST & !CLK_000_D_9_.Q & CLK_000_D_10_.Q & SM_AMIGA_1_.Q
# RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN
# !CLK_030 & RST & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q
# RST & inst_CLK_OUT_PRE_D.Q & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q);
# !CLK_030 & RST & !CLK_000_D_8_.Q & CLK_000_D_9_.Q & SM_AMIGA_1_.Q
# RST & inst_CLK_OUT_PRE_D.Q & !CLK_000_D_8_.Q & CLK_000_D_9_.Q & SM_AMIGA_1_.Q);
DSACK1.C = (CLK_OSZI);
@ -498,21 +497,17 @@ inst_LDS_000_INT.D = (!RST
inst_LDS_000_INT.C = (CLK_OSZI);
inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q);
inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_25.Q);
inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
CLK_000_D_1_.D = (CLK_000_D_0_.Q);
CLK_000_D_8_.D = (CLK_000_D_7_.Q);
CLK_000_D_1_.C = (CLK_OSZI);
CLK_000_D_8_.C = (CLK_OSZI);
CLK_000_D_10_.D = (CLK_000_D_9_.Q);
CLK_000_D_9_.D = (CLK_000_D_8_.Q);
CLK_000_D_10_.C = (CLK_OSZI);
CLK_000_D_11_.D = (CLK_000_D_10_.Q);
CLK_000_D_11_.C = (CLK_OSZI);
CLK_000_D_9_.C = (CLK_OSZI);
!inst_DTACK_D0.D = (!DTACK & RST);
@ -523,6 +518,10 @@ inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q
inst_RESET_OUT.C = (CLK_OSZI);
CLK_000_D_1_.D = (CLK_000_D_0_.Q);
CLK_000_D_1_.C = (CLK_OSZI);
CLK_000_D_0_.D = (CLK_000);
CLK_000_D_0_.C = (CLK_OSZI);
@ -531,6 +530,11 @@ inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
inst_CLK_OUT_PRE_25.D = (!inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q
# inst_CLK_OUT_PRE_50.Q & !inst_CLK_OUT_PRE_25.Q);
inst_CLK_OUT_PRE_25.C = (CLK_OSZI);
!IPL_D0_0_.D = (RST & !IPL_0_);
IPL_D0_0_.C = (CLK_OSZI);
@ -567,48 +571,39 @@ CLK_000_D_7_.D = (CLK_000_D_6_.Q);
CLK_000_D_7_.C = (CLK_OSZI);
CLK_000_D_8_.D = (CLK_000_D_7_.Q);
CLK_000_D_10_.D = (CLK_000_D_9_.Q);
CLK_000_D_8_.C = (CLK_OSZI);
CLK_000_D_9_.D = (CLK_000_D_8_.Q);
CLK_000_D_9_.C = (CLK_OSZI);
CLK_000_D_12_.D = (CLK_000_D_11_.Q);
CLK_000_D_12_.C = (CLK_OSZI);
CLK_000_D_10_.C = (CLK_OSZI);
!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);
inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN
# RST & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_i_7_.Q
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_i_7_.Q
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_i_7_.Q & RW.PIN);
inst_DS_000_ENABLE.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q
# RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & RW.PIN);
inst_DS_000_ENABLE.C = (CLK_OSZI);
SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & BERR.PIN
# RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & BERR.PIN
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & CLK_000_D_2_.Q & !SM_AMIGA_i_7_.Q);
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_i_7_.Q);
SM_AMIGA_6_.C = (CLK_OSZI);
SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q
# RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q & BERR.PIN
# RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q & BERR.PIN);
SM_AMIGA_0_.C = (CLK_OSZI);
SM_AMIGA_4_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q
# RST & CLK_000_D_1_.Q & SM_AMIGA_4_.Q & BERR.PIN
# RST & !CLK_000_D_0_.Q & SM_AMIGA_4_.Q & BERR.PIN);
SM_AMIGA_4_.C = (CLK_OSZI);
SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q
# RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q & BERR.PIN
# RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q & BERR.PIN);
SM_AMIGA_0_.C = (CLK_OSZI);
RST_DLY_0_.D = (RST & !CLK_000_D_1_.Q & RST_DLY_0_.Q
# RST & CLK_000_D_0_.Q & RST_DLY_0_.Q
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !RST_DLY_0_.Q
@ -653,7 +648,7 @@ SM_AMIGA_5_.C = (CLK_OSZI);
SM_AMIGA_3_.D.X1 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !BERR.PIN
# RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN
# RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN);
SM_AMIGA_3_.D.X2 = (RST & SM_AMIGA_3_.Q & BERR.PIN);
@ -662,7 +657,7 @@ SM_AMIGA_3_.C = (CLK_OSZI);
SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q & BERR.PIN
# RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q & BERR.PIN
# RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q
# RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q);
SM_AMIGA_2_.C = (CLK_OSZI);
@ -672,14 +667,14 @@ SM_AMIGA_i_7_.D.X1 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q & !BERR.PIN
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q & !BERR.PIN
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q & !BERR.PIN
# RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
# !nEXP_SPACE & RST & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & inst_AS_030_000_SYNC.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & CLK_000_D_1_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & !CLK_000_D_2_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# !nEXP_SPACE & RST & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & inst_AS_030_000_SYNC.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & !CLK_000_D_1_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & CLK_000_D_2_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !BERR.PIN);
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !BERR.PIN);
SM_AMIGA_i_7_.D.X2 = (RST & BERR.PIN);

243
Logic/68030_tk.fti
View File

@ -1,5 +1,5 @@
#PLAFILE 68030_tk.tt4
#DATE 08/18/2016
#DATE 08/23/2016
#DESIGN <no design name>
#DEVICE mach447a
@ -8,7 +8,7 @@ DATA LOCATION AHIGH_25_:C_12_18 // IO
DATA LOCATION AHIGH_26_:C_5_17 // IO
DATA LOCATION AHIGH_27_:C_9_16 // IO
DATA LOCATION AHIGH_28_:C_0_15 // IO
DATA LOCATION AHIGH_29_:B_13_6 // IO
DATA LOCATION AHIGH_29_:B_8_6 // IO
DATA LOCATION AHIGH_30_:B_0_5 // IO
DATA LOCATION AHIGH_31_:B_12_4 // IO
DATA LOCATION AMIGA_ADDR_ENABLE:D_5_33 // OUT
@ -34,34 +34,32 @@ DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030}
DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000}
DATA LOCATION BG_030:C_*_21 // INP
DATA LOCATION CIIN:E_12_47 // OUT
DATA LOCATION CIIN_0:E_10 // NOD
DATA LOCATION CIIN_0:E_9 // NOD
DATA LOCATION CLK_000:*_*_11 // INP
DATA LOCATION CLK_000_D_0_:C_13 // NOD
DATA LOCATION CLK_000_D_10_:C_14 // NOD
DATA LOCATION CLK_000_D_11_:H_0 // NOD
DATA LOCATION CLK_000_D_12_:G_14 // NOD
DATA LOCATION CLK_000_D_1_:H_3 // NOD
DATA LOCATION CLK_000_D_2_:E_2 // NOD
DATA LOCATION CLK_000_D_3_:E_9 // NOD
DATA LOCATION CLK_000_D_4_:C_11 // NOD
DATA LOCATION CLK_000_D_5_:E_5 // NOD
DATA LOCATION CLK_000_D_6_:D_14 // NOD
DATA LOCATION CLK_000_D_7_:A_14 // NOD
DATA LOCATION CLK_000_D_8_:G_3 // NOD
DATA LOCATION CLK_000_D_9_:A_10 // NOD
DATA LOCATION CLK_000_D_0_:E_8 // NOD
DATA LOCATION CLK_000_D_10_:F_6 // NOD
DATA LOCATION CLK_000_D_1_:H_5 // NOD
DATA LOCATION CLK_000_D_2_:H_6 // NOD
DATA LOCATION CLK_000_D_3_:E_2 // NOD
DATA LOCATION CLK_000_D_4_:D_3 // NOD
DATA LOCATION CLK_000_D_5_:B_14 // NOD
DATA LOCATION CLK_000_D_6_:B_10 // NOD
DATA LOCATION CLK_000_D_7_:E_13 // NOD
DATA LOCATION CLK_000_D_8_:E_6 // NOD
DATA LOCATION CLK_000_D_9_:H_13 // NOD
DATA LOCATION CLK_030:*_*_64 // INP
DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT
DATA LOCATION CLK_EXP:B_1_10 // OUT
DATA LOCATION CLK_OSZI:*_*_61 // Cin
DATA LOCATION CYCLE_DMA_0_:A_13 // NOD
DATA LOCATION CYCLE_DMA_1_:A_9 // NOD
DATA LOCATION CYCLE_DMA_0_:C_14 // NOD
DATA LOCATION CYCLE_DMA_1_:C_10 // NOD
DATA LOCATION DSACK1:H_9_81 // IO {RN_DSACK1}
DATA LOCATION DS_030:A_0_98 // OUT
DATA LOCATION DTACK:D_*_30 // INP
DATA LOCATION E:G_4_66 // OUT
DATA LOCATION FC_0_:F_*_57 // INP
DATA LOCATION FC_1_:F_*_58 // INP
DATA LOCATION FPU_CS:H_5_78 // OUT
DATA LOCATION FPU_CS:H_1_78 // OUT
DATA LOCATION FPU_SENSE:A_*_91 // INP
DATA LOCATION IPL_030_0_:B_5_8 // IO {RN_IPL_030_0_}
DATA LOCATION IPL_030_1_:B_9_7 // IO {RN_IPL_030_1_}
@ -69,9 +67,9 @@ DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_}
DATA LOCATION IPL_0_:G_*_67 // INP
DATA LOCATION IPL_1_:F_*_56 // INP
DATA LOCATION IPL_2_:G_*_68 // INP
DATA LOCATION IPL_D0_0_:B_3 // NOD
DATA LOCATION IPL_D0_1_:B_14 // NOD
DATA LOCATION IPL_D0_2_:A_3 // NOD
DATA LOCATION IPL_D0_0_:A_13 // NOD
DATA LOCATION IPL_D0_1_:B_3 // NOD
DATA LOCATION IPL_D0_2_:G_7 // NOD
DATA LOCATION LDS_000:D_12_31 // IO
DATA LOCATION RESET:B_2_3 // OUT
DATA LOCATION RN_A_0_:G_8 // NOD {A_0_}
@ -82,50 +80,51 @@ DATA LOCATION RN_IPL_030_0_:B_5 // NOD {IPL_030_0_}
DATA LOCATION RN_IPL_030_1_:B_9 // NOD {IPL_030_1_}
DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_}
DATA LOCATION RN_RW:G_0 // NOD {RW}
DATA LOCATION RN_RW_000:H_1 // NOD {RW_000}
DATA LOCATION RN_RW_000:H_0 // NOD {RW_000}
DATA LOCATION RN_VMA:D_0 // NOD {VMA}
DATA LOCATION RST:*_*_86 // INP
DATA LOCATION RST_DLY_0_:F_0 // NOD
DATA LOCATION RST_DLY_1_:F_13 // NOD
DATA LOCATION RST_DLY_2_:F_9 // NOD
DATA LOCATION RST_DLY_0_:G_10 // NOD
DATA LOCATION RST_DLY_1_:G_3 // NOD
DATA LOCATION RST_DLY_2_:G_14 // NOD
DATA LOCATION RW:G_0_71 // IO {RN_RW}
DATA LOCATION RW_000:H_1_80 // IO {RN_RW_000}
DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000}
DATA LOCATION SIZE_0_:G_12_70 // IO
DATA LOCATION SIZE_1_:H_12_79 // IO
DATA LOCATION SIZE_DMA_0_:G_2 // NOD
DATA LOCATION SIZE_DMA_1_:G_9 // NOD
DATA LOCATION SM_AMIGA_0_:G_5 // NOD
DATA LOCATION SM_AMIGA_1_:F_1 // NOD
DATA LOCATION SM_AMIGA_2_:F_6 // NOD
DATA LOCATION SM_AMIGA_3_:F_10 // NOD
DATA LOCATION SM_AMIGA_4_:B_10 // NOD
DATA LOCATION SM_AMIGA_5_:F_5 // NOD
DATA LOCATION SM_AMIGA_6_:C_2 // NOD
DATA LOCATION SIZE_DMA_1_:G_13 // NOD
DATA LOCATION SM_AMIGA_0_:F_12 // NOD
DATA LOCATION SM_AMIGA_1_:F_8 // NOD
DATA LOCATION SM_AMIGA_2_:F_5 // NOD
DATA LOCATION SM_AMIGA_3_:F_9 // NOD
DATA LOCATION SM_AMIGA_4_:F_2 // NOD
DATA LOCATION SM_AMIGA_5_:F_13 // NOD
DATA LOCATION SM_AMIGA_6_:A_8 // NOD
DATA LOCATION SM_AMIGA_i_7_:F_4 // NOD
DATA LOCATION UDS_000:D_8_32 // IO
DATA LOCATION VMA:D_0_35 // IO {RN_VMA}
DATA LOCATION VPA:*_*_36 // INP
DATA LOCATION cpu_est_0_:D_2 // NOD
DATA LOCATION cpu_est_1_:F_8 // NOD
DATA LOCATION cpu_est_2_:D_13 // NOD
DATA LOCATION cpu_est_3_:D_9 // NOD
DATA LOCATION cpu_est_0_:D_10 // NOD
DATA LOCATION cpu_est_1_:D_13 // NOD
DATA LOCATION cpu_est_2_:D_6 // NOD
DATA LOCATION cpu_est_3_:D_2 // NOD
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:G_6 // NOD
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:G_10 // NOD
DATA LOCATION inst_AS_000_DMA:A_12 // NOD
DATA LOCATION inst_AS_000_INT:C_15 // NOD
DATA LOCATION inst_AS_030_000_SYNC:C_6 // NOD
DATA LOCATION inst_AS_030_D0:A_6 // NOD
DATA LOCATION inst_BGACK_030_INT_D:H_13 // NOD
DATA LOCATION inst_CLK_030_H:A_5 // NOD
DATA LOCATION inst_CLK_OUT_PRE_50:E_6 // NOD
DATA LOCATION inst_CLK_OUT_PRE_D:E_8 // NOD
DATA LOCATION inst_DS_000_DMA:A_1 // NOD
DATA LOCATION inst_DS_000_ENABLE:B_6 // NOD
DATA LOCATION inst_DTACK_D0:G_7 // NOD
DATA LOCATION inst_LDS_000_INT:D_6 // NOD
DATA LOCATION inst_RESET_OUT:A_8 // NOD
DATA LOCATION inst_UDS_000_INT:D_10 // NOD
DATA LOCATION inst_VPA_D:F_2 // NOD
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:C_3 // NOD
DATA LOCATION inst_AS_000_DMA:C_2 // NOD
DATA LOCATION inst_AS_000_INT:A_5 // NOD
DATA LOCATION inst_AS_030_000_SYNC:A_12 // NOD
DATA LOCATION inst_AS_030_D0:D_9 // NOD
DATA LOCATION inst_BGACK_030_INT_D:F_0 // NOD
DATA LOCATION inst_CLK_030_H:C_6 // NOD
DATA LOCATION inst_CLK_OUT_PRE_25:A_1 // NOD
DATA LOCATION inst_CLK_OUT_PRE_50:A_2 // NOD
DATA LOCATION inst_CLK_OUT_PRE_D:B_13 // NOD
DATA LOCATION inst_DS_000_DMA:C_13 // NOD
DATA LOCATION inst_DS_000_ENABLE:F_1 // NOD
DATA LOCATION inst_DTACK_D0:C_7 // NOD
DATA LOCATION inst_LDS_000_INT:B_6 // NOD
DATA LOCATION inst_RESET_OUT:G_9 // NOD
DATA LOCATION inst_UDS_000_INT:D_14 // NOD
DATA LOCATION inst_VPA_D:A_9 // NOD
DATA LOCATION nEXP_SPACE:*_*_14 // INP
DATA IO_DIR AHIGH_24_:BI
DATA IO_DIR AHIGH_25_:BI
@ -190,9 +189,9 @@ DATA IO_DIR VPA:IN
DATA IO_DIR nEXP_SPACE:IN
DATA GLB_CLOCK CLK_OSZI
DATA PW_LEVEL SIZE_1_:1
DATA SLEW SIZE_1_:1
DATA SLEW SIZE_1_:0
DATA PW_LEVEL AHIGH_31_:1
DATA SLEW AHIGH_31_:1
DATA SLEW AHIGH_31_:0
DATA PW_LEVEL A_DECODE_23_:1
DATA SLEW A_DECODE_23_:1
DATA PW_LEVEL IPL_2_:1
@ -200,71 +199,71 @@ DATA SLEW IPL_2_:1
DATA PW_LEVEL FC_1_:1
DATA SLEW FC_1_:1
DATA PW_LEVEL AS_030:1
DATA SLEW AS_030:1
DATA SLEW AS_030:0
DATA PW_LEVEL SIZE_0_:1
DATA SLEW SIZE_0_:0
DATA PW_LEVEL AS_000:1
DATA SLEW AS_000:1
DATA SLEW AS_000:0
DATA PW_LEVEL AHIGH_30_:1
DATA SLEW AHIGH_30_:0
DATA PW_LEVEL AHIGH_29_:1
DATA SLEW AHIGH_29_:0
DATA PW_LEVEL DS_030:1
DATA SLEW DS_030:1
DATA SLEW DS_030:0
DATA PW_LEVEL AHIGH_28_:1
DATA SLEW AHIGH_28_:0
DATA PW_LEVEL UDS_000:1
DATA SLEW UDS_000:1
DATA SLEW UDS_000:0
DATA PW_LEVEL AHIGH_27_:1
DATA SLEW AHIGH_27_:0
DATA PW_LEVEL LDS_000:1
DATA SLEW LDS_000:1
DATA SLEW LDS_000:0
DATA PW_LEVEL AHIGH_26_:1
DATA SLEW AHIGH_26_:0
DATA SLEW nEXP_SPACE:1
DATA PW_LEVEL AHIGH_25_:1
DATA SLEW AHIGH_25_:0
DATA PW_LEVEL BERR:1
DATA SLEW BERR:1
DATA SLEW BERR:0
DATA PW_LEVEL AHIGH_24_:1
DATA SLEW AHIGH_24_:0
DATA PW_LEVEL BG_030:1
DATA SLEW BG_030:1
DATA PW_LEVEL SIZE_0_:1
DATA SLEW SIZE_0_:1
DATA PW_LEVEL AHIGH_30_:1
DATA SLEW AHIGH_30_:1
DATA PW_LEVEL BGACK_000:1
DATA SLEW BGACK_000:1
DATA PW_LEVEL AHIGH_29_:1
DATA SLEW AHIGH_29_:1
DATA SLEW CLK_030:1
DATA PW_LEVEL AHIGH_28_:1
DATA SLEW AHIGH_28_:1
DATA SLEW CLK_000:1
DATA PW_LEVEL AHIGH_27_:1
DATA SLEW AHIGH_27_:1
DATA SLEW CLK_OSZI:1
DATA PW_LEVEL AHIGH_26_:1
DATA SLEW AHIGH_26_:1
DATA PW_LEVEL CLK_DIV_OUT:1
DATA SLEW CLK_DIV_OUT:0
DATA PW_LEVEL AHIGH_25_:1
DATA SLEW AHIGH_25_:1
DATA PW_LEVEL AHIGH_24_:1
DATA SLEW AHIGH_24_:1
DATA PW_LEVEL FPU_CS:1
DATA SLEW FPU_CS:0
DATA PW_LEVEL A_DECODE_22_:1
DATA SLEW A_DECODE_22_:1
DATA PW_LEVEL FPU_SENSE:1
DATA SLEW FPU_SENSE:1
DATA PW_LEVEL A_DECODE_21_:1
DATA SLEW A_DECODE_21_:1
DATA PW_LEVEL A_DECODE_20_:1
DATA SLEW A_DECODE_20_:1
DATA PW_LEVEL DTACK:1
DATA SLEW DTACK:1
DATA PW_LEVEL BGACK_000:1
DATA SLEW BGACK_000:1
DATA PW_LEVEL A_DECODE_19_:1
DATA SLEW A_DECODE_19_:1
DATA PW_LEVEL AVEC:1
DATA SLEW AVEC:1
DATA SLEW CLK_030:1
DATA PW_LEVEL A_DECODE_18_:1
DATA SLEW A_DECODE_18_:1
DATA PW_LEVEL E:1
DATA SLEW E:1
DATA SLEW CLK_000:1
DATA PW_LEVEL A_DECODE_17_:1
DATA SLEW A_DECODE_17_:1
DATA SLEW VPA:1
DATA SLEW CLK_OSZI:1
DATA PW_LEVEL A_DECODE_16_:1
DATA SLEW A_DECODE_16_:1
DATA PW_LEVEL CLK_DIV_OUT:1
DATA SLEW CLK_DIV_OUT:0
DATA PW_LEVEL FPU_CS:1
DATA SLEW FPU_CS:0
DATA PW_LEVEL FPU_SENSE:1
DATA SLEW FPU_SENSE:1
DATA PW_LEVEL DTACK:1
DATA SLEW DTACK:1
DATA PW_LEVEL AVEC:1
DATA SLEW AVEC:0
DATA PW_LEVEL E:1
DATA SLEW E:0
DATA SLEW VPA:1
DATA SLEW RST:1
DATA PW_LEVEL RESET:1
DATA SLEW RESET:1
DATA SLEW RESET:0
DATA PW_LEVEL AMIGA_ADDR_ENABLE:1
DATA SLEW AMIGA_ADDR_ENABLE:0
DATA PW_LEVEL AMIGA_BUS_DATA_DIR:1
@ -274,7 +273,7 @@ DATA SLEW AMIGA_BUS_ENABLE_LOW:0
DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1
DATA SLEW AMIGA_BUS_ENABLE_HIGH:0
DATA PW_LEVEL CIIN:1
DATA SLEW CIIN:1
DATA SLEW CIIN:0
DATA PW_LEVEL IPL_1_:1
DATA SLEW IPL_1_:1
DATA PW_LEVEL IPL_0_:1
@ -284,27 +283,27 @@ DATA SLEW FC_0_:1
DATA PW_LEVEL A_1_:1
DATA SLEW A_1_:1
DATA PW_LEVEL IPL_030_2_:1
DATA SLEW IPL_030_2_:1
DATA SLEW IPL_030_2_:0
DATA PW_LEVEL RW_000:1
DATA SLEW RW_000:1
DATA SLEW RW_000:0
DATA PW_LEVEL BG_000:1
DATA SLEW BG_000:1
DATA SLEW BG_000:0
DATA PW_LEVEL BGACK_030:1
DATA SLEW BGACK_030:1
DATA SLEW BGACK_030:0
DATA PW_LEVEL CLK_EXP:1
DATA SLEW CLK_EXP:0
DATA PW_LEVEL DSACK1:1
DATA SLEW DSACK1:1
DATA SLEW DSACK1:0
DATA PW_LEVEL VMA:1
DATA SLEW VMA:1
DATA SLEW VMA:0
DATA PW_LEVEL RW:1
DATA SLEW RW:1
DATA SLEW RW:0
DATA PW_LEVEL A_0_:1
DATA SLEW A_0_:1
DATA SLEW A_0_:0
DATA PW_LEVEL IPL_030_1_:1
DATA SLEW IPL_030_1_:1
DATA SLEW IPL_030_1_:0
DATA PW_LEVEL IPL_030_0_:1
DATA SLEW IPL_030_0_:1
DATA SLEW IPL_030_0_:0
DATA PW_LEVEL cpu_est_3_:1
DATA SLEW cpu_est_3_:1
DATA PW_LEVEL cpu_est_0_:1
@ -343,20 +342,22 @@ DATA PW_LEVEL inst_LDS_000_INT:1
DATA SLEW inst_LDS_000_INT:1
DATA PW_LEVEL inst_CLK_OUT_PRE_D:1
DATA SLEW inst_CLK_OUT_PRE_D:1
DATA PW_LEVEL CLK_000_D_1_:1
DATA SLEW CLK_000_D_1_:1
DATA PW_LEVEL CLK_000_D_10_:1
DATA SLEW CLK_000_D_10_:1
DATA PW_LEVEL CLK_000_D_11_:1
DATA SLEW CLK_000_D_11_:1
DATA PW_LEVEL CLK_000_D_8_:1
DATA SLEW CLK_000_D_8_:1
DATA PW_LEVEL CLK_000_D_9_:1
DATA SLEW CLK_000_D_9_:1
DATA PW_LEVEL inst_DTACK_D0:1
DATA SLEW inst_DTACK_D0:1
DATA PW_LEVEL inst_RESET_OUT:1
DATA SLEW inst_RESET_OUT:1
DATA PW_LEVEL CLK_000_D_1_:1
DATA SLEW CLK_000_D_1_:1
DATA PW_LEVEL CLK_000_D_0_:1
DATA SLEW CLK_000_D_0_:1
DATA PW_LEVEL inst_CLK_OUT_PRE_50:1
DATA SLEW inst_CLK_OUT_PRE_50:1
DATA PW_LEVEL inst_CLK_OUT_PRE_25:1
DATA SLEW inst_CLK_OUT_PRE_25:1
DATA PW_LEVEL IPL_D0_0_:1
DATA SLEW IPL_D0_0_:1
DATA PW_LEVEL IPL_D0_1_:1
@ -375,22 +376,18 @@ DATA PW_LEVEL CLK_000_D_6_:1
DATA SLEW CLK_000_D_6_:1
DATA PW_LEVEL CLK_000_D_7_:1
DATA SLEW CLK_000_D_7_:1
DATA PW_LEVEL CLK_000_D_8_:1
DATA SLEW CLK_000_D_8_:1
DATA PW_LEVEL CLK_000_D_9_:1
DATA SLEW CLK_000_D_9_:1
DATA PW_LEVEL CLK_000_D_12_:1
DATA SLEW CLK_000_D_12_:1
DATA PW_LEVEL CLK_000_D_10_:1
DATA SLEW CLK_000_D_10_:1
DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
DATA PW_LEVEL inst_DS_000_ENABLE:1
DATA SLEW inst_DS_000_ENABLE:1
DATA PW_LEVEL SM_AMIGA_6_:1
DATA SLEW SM_AMIGA_6_:1
DATA PW_LEVEL SM_AMIGA_0_:1
DATA SLEW SM_AMIGA_0_:1
DATA PW_LEVEL SM_AMIGA_4_:1
DATA SLEW SM_AMIGA_4_:1
DATA PW_LEVEL SM_AMIGA_0_:1
DATA SLEW SM_AMIGA_0_:1
DATA PW_LEVEL RST_DLY_0_:1
DATA SLEW RST_DLY_0_:1
DATA PW_LEVEL RST_DLY_1_:1

41
Logic/68030_tk.grp
View File

@ -1,23 +1,22 @@
GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA inst_RESET_OUT
CYCLE_DMA_1_ CYCLE_DMA_0_ inst_AS_030_D0 IPL_D0_2_ CLK_000_D_7_ CLK_000_D_9_
DS_030 AVEC
GROUP MACH_SEG_A DS_030 AVEC inst_AS_030_000_SYNC SM_AMIGA_6_ inst_AS_000_INT
inst_CLK_OUT_PRE_25 inst_VPA_D IPL_D0_0_ inst_CLK_OUT_PRE_50
GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_
RN_IPL_030_2_ CLK_EXP inst_DS_000_ENABLE SM_AMIGA_4_ IPL_D0_0_ IPL_D0_1_
AHIGH_31_ AHIGH_30_ AHIGH_29_ RESET
GROUP MACH_SEG_C inst_AS_030_000_SYNC SM_AMIGA_6_ inst_AS_000_INT CLK_000_D_10_
CLK_000_D_0_ CLK_000_D_4_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_
AHIGH_24_ AMIGA_BUS_ENABLE_LOW
GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 inst_LDS_000_INT cpu_est_3_
cpu_est_2_ inst_UDS_000_INT cpu_est_0_ CLK_000_D_6_ LDS_000 UDS_000
AMIGA_BUS_ENABLE_HIGH AMIGA_ADDR_ENABLE
GROUP MACH_SEG_E CLK_000_D_5_ inst_CLK_OUT_PRE_D inst_CLK_OUT_PRE_50 CLK_000_D_3_
CLK_000_D_2_ CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0
GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ RST_DLY_0_ RST_DLY_1_
RST_DLY_2_ SM_AMIGA_1_ SM_AMIGA_5_ cpu_est_1_ inst_VPA_D
GROUP MACH_SEG_G A_0_ RN_A_0_ RW RN_RW CLK_DIV_OUT SIZE_DMA_0_ SIZE_DMA_1_
SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AMIGA_BUS_ENABLE_DMA_HIGH
inst_DTACK_D0 CLK_000_D_8_ CLK_000_D_12_ SIZE_0_ E
GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 BGACK_030 RN_BGACK_030
inst_BGACK_030_INT_D CLK_000_D_11_ CLK_000_D_1_ FPU_CS AS_030 SIZE_1_
RN_IPL_030_2_ AHIGH_31_ AHIGH_30_ AHIGH_29_ CLK_EXP RESET inst_LDS_000_INT
IPL_D0_1_ CLK_000_D_5_ CLK_000_D_6_ inst_CLK_OUT_PRE_D
GROUP MACH_SEG_C AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AMIGA_BUS_ENABLE_LOW
inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA CYCLE_DMA_1_ CYCLE_DMA_0_
inst_AMIGA_BUS_ENABLE_DMA_LOW inst_DTACK_D0
GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH
AMIGA_ADDR_ENABLE cpu_est_3_ cpu_est_1_ cpu_est_2_ inst_UDS_000_INT
cpu_est_0_ inst_AS_030_D0 CLK_000_D_4_
GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 CLK_000_D_8_
CLK_000_D_0_ CLK_000_D_3_ CLK_000_D_7_
GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ inst_DS_000_ENABLE
SM_AMIGA_4_ SM_AMIGA_0_ SM_AMIGA_1_ SM_AMIGA_5_ inst_BGACK_030_INT_D
CLK_000_D_10_
GROUP MACH_SEG_G A_0_ RN_A_0_ RW RN_RW SIZE_0_ E CLK_DIV_OUT inst_RESET_OUT
SIZE_DMA_0_ SIZE_DMA_1_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
IPL_D0_2_
GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 FPU_CS BGACK_030 RN_BGACK_030
AS_030 SIZE_1_ CLK_000_D_9_ CLK_000_D_2_ CLK_000_D_1_

2
Logic/68030_tk.ipr
View File

@ -1 +1 @@
<LATTICE_ENCRYPTED_BLIF>56;:107Kjg9j
<LATTICE_ENCRYPTED_BLIF>97::254)ch7m\r

1090
Logic/68030_tk.jed
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File diff suppressed because it is too large Load Diff

2
Logic/68030_tk.l0
View File

@ -1 +1 @@
-ck Min -ce On -ar On -ap On -oe On -split 16 -clust 5 -xor on -speed -ifb yes -sr no -device M4A5
-ck Min -ce On -ar On -ap On -oe On -split 20 -clust 5 -xor on -speed -ifb yes -sr no -device M4A5

147
Logic/68030_tk.lco
View File

@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $";
Parent = m4a5.lci;
SDS_File = m4a5.sds;
Design = 68030_tk.tt4;
DATE = 8/19/16;
TIME = 00:39:40;
DATE = 8/24/16;
TIME = 22:17:53;
Source_Format = Pure_VHDL;
Type = TT2;
Pre_Fit_Time = 1;
@ -54,8 +54,8 @@ Pin_Macrocell_Block = No;
Routing = No;
[GLOBAL CONSTRAINTS]
Max_PTerm_Split = 16;
Max_PTerm_Collapse = 16;
Max_PTerm_Split = 20;
Max_PTerm_Collapse = 20;
Max_Pin_Percent = 100;
Max_Macrocell_Percent = 100;
Max_GLB_Input_Percent = 100;
@ -65,7 +65,7 @@ XOR_Synthesis = Yes;
DT_Synthesis = Yes;
Node_Collapse = Yes;
Run_Time = 0;
Set_Reset_Dont_Care = No;
Set_Reset_Dont_Care = Yes;
Clock_Optimize = No;
In_Reg_Optimize = Yes;
Balanced_Partitioning = Yes;
@ -82,39 +82,39 @@ A_DECODE_23_ = pin,85,-,H,-;
IPL_2_ = pin,68,-,G,-;
FC_1_ = pin,58,-,F,-;
AS_030 = pin,82,-,H,-;
AS_000 = pin,42,-,E,-;
DS_030 = pin,98,-,A,-;
UDS_000 = pin,32,-,D,-;
LDS_000 = pin,31,-,D,-;
nEXP_SPACE = pin,14,-,-,-;
BERR = pin,41,-,E,-;
BG_030 = pin,21,-,C,-;
SIZE_0_ = pin,70,-,G,-;
AS_000 = pin,42,-,E,-;
AHIGH_30_ = pin,5,-,B,-;
BGACK_000 = pin,28,-,D,-;
AHIGH_29_ = pin,6,-,B,-;
CLK_030 = pin,64,-,-,-;
DS_030 = pin,98,-,A,-;
AHIGH_28_ = pin,15,-,C,-;
CLK_000 = pin,11,-,-,-;
UDS_000 = pin,32,-,D,-;
AHIGH_27_ = pin,16,-,C,-;
CLK_OSZI = pin,61,-,-,-;
LDS_000 = pin,31,-,D,-;
AHIGH_26_ = pin,17,-,C,-;
CLK_DIV_OUT = pin,65,-,G,-;
nEXP_SPACE = pin,14,-,-,-;
AHIGH_25_ = pin,18,-,C,-;
BERR = pin,41,-,E,-;
AHIGH_24_ = pin,19,-,C,-;
FPU_CS = pin,78,-,H,-;
BG_030 = pin,21,-,C,-;
A_DECODE_22_ = pin,84,-,H,-;
FPU_SENSE = pin,91,-,A,-;
A_DECODE_21_ = pin,94,-,A,-;
A_DECODE_20_ = pin,93,-,A,-;
DTACK = pin,30,-,D,-;
BGACK_000 = pin,28,-,D,-;
A_DECODE_19_ = pin,97,-,A,-;
AVEC = pin,92,-,A,-;
CLK_030 = pin,64,-,-,-;
A_DECODE_18_ = pin,95,-,A,-;
E = pin,66,-,G,-;
CLK_000 = pin,11,-,-,-;
A_DECODE_17_ = pin,59,-,F,-;
VPA = pin,36,-,-,-;
CLK_OSZI = pin,61,-,-,-;
A_DECODE_16_ = pin,96,-,A,-;
CLK_DIV_OUT = pin,65,-,G,-;
FPU_CS = pin,78,-,H,-;
FPU_SENSE = pin,91,-,A,-;
DTACK = pin,30,-,D,-;
AVEC = pin,92,-,A,-;
E = pin,66,-,G,-;
VPA = pin,36,-,-,-;
RST = pin,86,-,-,-;
RESET = pin,3,-,B,-;
AMIGA_ADDR_ENABLE = pin,33,-,D,-;
@ -137,59 +137,58 @@ RW = pin,71,-,G,-;
A_0_ = pin,69,-,G,-;
IPL_030_1_ = pin,7,-,B,-;
IPL_030_0_ = pin,8,-,B,-;
cpu_est_3_ = node,-,-,D,9;
cpu_est_0_ = node,-,-,D,2;
cpu_est_1_ = node,-,-,F,8;
cpu_est_2_ = node,-,-,D,13;
inst_AS_000_INT = node,-,-,C,15;
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,G,10;
inst_AS_030_D0 = node,-,-,A,6;
inst_AS_030_000_SYNC = node,-,-,C,6;
inst_BGACK_030_INT_D = node,-,-,H,13;
inst_AS_000_DMA = node,-,-,A,12;
inst_DS_000_DMA = node,-,-,A,1;
CYCLE_DMA_0_ = node,-,-,A,13;
CYCLE_DMA_1_ = node,-,-,A,9;
cpu_est_3_ = node,-,-,D,2;
cpu_est_0_ = node,-,-,D,10;
cpu_est_1_ = node,-,-,D,13;
cpu_est_2_ = node,-,-,D,6;
inst_AS_000_INT = node,-,-,A,5;
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,C,3;
inst_AS_030_D0 = node,-,-,D,9;
inst_AS_030_000_SYNC = node,-,-,A,12;
inst_BGACK_030_INT_D = node,-,-,F,0;
inst_AS_000_DMA = node,-,-,C,2;
inst_DS_000_DMA = node,-,-,C,13;
CYCLE_DMA_0_ = node,-,-,C,14;
CYCLE_DMA_1_ = node,-,-,C,10;
SIZE_DMA_0_ = node,-,-,G,2;
SIZE_DMA_1_ = node,-,-,G,9;
inst_VPA_D = node,-,-,F,2;
inst_UDS_000_INT = node,-,-,D,10;
inst_LDS_000_INT = node,-,-,D,6;
inst_CLK_OUT_PRE_D = node,-,-,E,8;
CLK_000_D_1_ = node,-,-,H,3;
CLK_000_D_10_ = node,-,-,C,14;
CLK_000_D_11_ = node,-,-,H,0;
inst_DTACK_D0 = node,-,-,G,7;
inst_RESET_OUT = node,-,-,A,8;
CLK_000_D_0_ = node,-,-,C,13;
inst_CLK_OUT_PRE_50 = node,-,-,E,6;
IPL_D0_0_ = node,-,-,B,3;
IPL_D0_1_ = node,-,-,B,14;
IPL_D0_2_ = node,-,-,A,3;
CLK_000_D_2_ = node,-,-,E,2;
CLK_000_D_3_ = node,-,-,E,9;
CLK_000_D_4_ = node,-,-,C,11;
CLK_000_D_5_ = node,-,-,E,5;
CLK_000_D_6_ = node,-,-,D,14;
CLK_000_D_7_ = node,-,-,A,14;
CLK_000_D_8_ = node,-,-,G,3;
CLK_000_D_9_ = node,-,-,A,10;
CLK_000_D_12_ = node,-,-,G,14;
SIZE_DMA_1_ = node,-,-,G,13;
inst_VPA_D = node,-,-,A,9;
inst_UDS_000_INT = node,-,-,D,14;
inst_LDS_000_INT = node,-,-,B,6;
inst_CLK_OUT_PRE_D = node,-,-,B,13;
CLK_000_D_8_ = node,-,-,E,6;
CLK_000_D_9_ = node,-,-,H,13;
inst_DTACK_D0 = node,-,-,C,7;
inst_RESET_OUT = node,-,-,G,9;
CLK_000_D_1_ = node,-,-,H,5;
CLK_000_D_0_ = node,-,-,E,8;
inst_CLK_OUT_PRE_50 = node,-,-,A,2;
inst_CLK_OUT_PRE_25 = node,-,-,A,1;
IPL_D0_0_ = node,-,-,A,13;
IPL_D0_1_ = node,-,-,B,3;
IPL_D0_2_ = node,-,-,G,7;
CLK_000_D_2_ = node,-,-,H,6;
CLK_000_D_3_ = node,-,-,E,2;
CLK_000_D_4_ = node,-,-,D,3;
CLK_000_D_5_ = node,-,-,B,14;
CLK_000_D_6_ = node,-,-,B,10;
CLK_000_D_7_ = node,-,-,E,13;
CLK_000_D_10_ = node,-,-,F,6;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,G,6;
inst_DS_000_ENABLE = node,-,-,B,6;
SM_AMIGA_6_ = node,-,-,C,2;
SM_AMIGA_0_ = node,-,-,G,5;
SM_AMIGA_4_ = node,-,-,B,10;
RST_DLY_0_ = node,-,-,F,0;
RST_DLY_1_ = node,-,-,F,13;
RST_DLY_2_ = node,-,-,F,9;
inst_CLK_030_H = node,-,-,A,5;
SM_AMIGA_1_ = node,-,-,F,1;
SM_AMIGA_5_ = node,-,-,F,5;
SM_AMIGA_3_ = node,-,-,F,10;
SM_AMIGA_2_ = node,-,-,F,6;
inst_DS_000_ENABLE = node,-,-,F,1;
SM_AMIGA_6_ = node,-,-,A,8;
SM_AMIGA_4_ = node,-,-,F,2;
SM_AMIGA_0_ = node,-,-,F,12;
RST_DLY_0_ = node,-,-,G,10;
RST_DLY_1_ = node,-,-,G,3;
RST_DLY_2_ = node,-,-,G,14;
inst_CLK_030_H = node,-,-,C,6;
SM_AMIGA_1_ = node,-,-,F,8;
SM_AMIGA_5_ = node,-,-,F,13;
SM_AMIGA_3_ = node,-,-,F,9;
SM_AMIGA_2_ = node,-,-,F,5;
SM_AMIGA_i_7_ = node,-,-,F,4;
CIIN_0 = node,-,-,E,10;
CIIN_0 = node,-,-,E,9;
[GROUP ASSIGNMENTS]
Layer = OFF;
@ -199,7 +198,7 @@ Layer = OFF;
[SLEWRATE]
Default = SLOW;
FAST = CLK_DIV_OUT,CLK_EXP,FPU_CS,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH;
FAST = CLK_DIV_OUT,CLK_EXP,FPU_CS,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH,AS_030,A_16_,A_17_,A_18_,A_19_,RW,SIZE_1_,SIZE_0_,AVEC,BGACK_030,BG_000,E,IPL_030_0_,IPL_030_1_,IPL_030_2_,LDS_000,UDS_000,VMA,RESET,CIIN,A_20_,A_21_,A_22_,A_24_,A_25_,A_26_,A_27_,A_28_,A_29_,A_30_,A_31_,DS_030,BERR,A0,DSACK1,RW_000,AS_000,A_23_,A1,A_3_,A_2_,AHIGH_24_,AHIGH_25_,AHIGH_26_,AHIGH_27_,AHIGH_28_,AHIGH_29_,AHIGH_30_,AHIGH_31_,A_0_;
[PULLUP]
Default = Up;

6
Logic/68030_tk.nrp
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@ -18,7 +18,7 @@ Note 18862: NODE name SM_AMIGA_i_7_bus.D.X1 being renamed to GATE_SM_AMIGA_i_7_b
Note 18862: NODE name SM_AMIGA_i_7_bus.D.X2 being renamed to GATE_SM_AMIGA_i_7_bus_D_X2.
Note 18862: NODE name CIIN_0 being renamed to GATE_CIIN_OE.
Utilization Estimate
Combinational Macros: 520
Flip-Flop and Latch Macros: 64
Combinational Macros: 524
Flip-Flop and Latch Macros: 61
I/O Pads: 61
Elapsed time: 2 seconds
Elapsed time: 1 seconds

24238
Logic/68030_tk.out
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153
Logic/68030_tk.plc
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@ -8,7 +8,7 @@
; Source file 68030_tk.tt4
; FITTER-generated Placements.
; DEVICE mach447a
; DATE Fri Aug 19 00:39:40 2016
; DATE Wed Aug 24 22:17:53 2016
Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287
@ -17,39 +17,39 @@ Pin 85 A_DECODE_23_
Pin 68 IPL_2_
Pin 58 FC_1_
Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281
Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203
Pin 98 DS_030 Comb ; S6=1 S9=1 Pair 101
Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185
Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191
Pin 14 nEXP_SPACE
Pin 41 BERR Comb ; S6=1 S9=1 Pair 197
Pin 21 BG_030
Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263
Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203
Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125
Pin 28 BGACK_000
Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 145
Pin 64 CLK_030
Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 137
Pin 98 DS_030 Comb ; S6=1 S9=1 Pair 101
Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149
Pin 11 CLK_000
Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185
Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 163
Pin 61 CLK_OSZI
Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191
Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 157
Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 247
Pin 14 nEXP_SPACE
Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167
Pin 41 BERR Comb ; S6=1 S9=1 Pair 197
Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161
Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 277
Pin 21 BG_030
Pin 84 A_DECODE_22_
Pin 91 FPU_SENSE
Pin 94 A_DECODE_21_
Pin 93 A_DECODE_20_
Pin 30 DTACK
Pin 28 BGACK_000
Pin 97 A_DECODE_19_
Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107
Pin 64 CLK_030
Pin 95 A_DECODE_18_
Pin 66 E Comb ; S6=1 S9=1 Pair 251
Pin 11 CLK_000
Pin 59 A_DECODE_17_
Pin 36 VPA
Pin 61 CLK_OSZI
Pin 96 A_DECODE_16_
Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 247
Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271
Pin 91 FPU_SENSE
Pin 30 DTACK
Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107
Pin 66 E Comb ; S6=1 S9=1 Pair 251
Pin 36 VPA
Pin 86 RST
Pin 3 RESET Comb ; S6=1 S9=1 Pair 128
Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 181
@ -62,7 +62,7 @@ Pin 67 IPL_0_
Pin 57 FC_0_
Pin 60 A_1_
Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131
Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 271
Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269
Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175
Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275
Pin 10 CLK_EXP Reg ; S6=1 S9=1 Pair 127
@ -75,20 +75,20 @@ Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 133
Node 287 RN_SIZE_1_ Comb ; S6=1 S9=1
Node 143 RN_AHIGH_31_ Comb ; S6=1 S9=1
Node 281 RN_AS_030 Comb ; S6=1 S9=1
Node 203 RN_AS_000 Comb ; S6=1 S9=1
Node 185 RN_UDS_000 Comb ; S6=1 S9=1
Node 191 RN_LDS_000 Comb ; S6=1 S9=1
Node 197 RN_BERR Comb ; S6=1 S9=1
Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1
Node 203 RN_AS_000 Comb ; S6=1 S9=1
Node 125 RN_AHIGH_30_ Comb ; S6=1 S9=1
Node 145 RN_AHIGH_29_ Comb ; S6=1 S9=1
Node 137 RN_AHIGH_29_ Comb ; S6=1 S9=1
Node 149 RN_AHIGH_28_ Comb ; S6=1 S9=1
Node 185 RN_UDS_000 Comb ; S6=1 S9=1
Node 163 RN_AHIGH_27_ Comb ; S6=1 S9=1
Node 191 RN_LDS_000 Comb ; S6=1 S9=1
Node 157 RN_AHIGH_26_ Comb ; S6=1 S9=1
Node 167 RN_AHIGH_25_ Comb ; S6=1 S9=1
Node 197 RN_BERR Comb ; S6=1 S9=1
Node 161 RN_AHIGH_24_ Comb ; S6=1 S9=1
Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1
Node 271 RN_RW_000 Reg ; S6=1 S9=1
Node 269 RN_RW_000 Reg ; S6=1 S9=1
Node 175 RN_BG_000 Reg ; S6=1 S9=1
Node 275 RN_BGACK_030 Reg ; S6=1 S9=1
Node 283 RN_DSACK1 Reg ; S6=1 S9=1
@ -97,58 +97,57 @@ Node 245 RN_RW Reg ; S6=1 S9=1
Node 257 RN_A_0_ Reg ; S6=1 S9=1
Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1
Node 133 RN_IPL_030_0_ Reg ; S6=1 S9=1
Node 187 cpu_est_3_ Reg ; S6=1 S9=1
Node 176 cpu_est_0_ Reg ; S6=1 S9=1
Node 233 cpu_est_1_ Reg ; S6=1 S9=1
Node 193 cpu_est_2_ Reg ; S6=1 S9=1
Node 172 inst_AS_000_INT Reg ; S6=1 S9=1
Node 260 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
Node 110 inst_AS_030_D0 Reg ; S6=1 S9=1
Node 158 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
Node 289 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
Node 119 inst_AS_000_DMA Reg ; S6=1 S9=1
Node 103 inst_DS_000_DMA Reg ; S6=1 S9=1
Node 121 CYCLE_DMA_0_ Reg ; S6=1 S9=1
Node 115 CYCLE_DMA_1_ Reg ; S6=1 S9=1
Node 176 cpu_est_3_ Reg ; S6=1 S9=1
Node 188 cpu_est_0_ Reg ; S6=1 S9=1
Node 193 cpu_est_1_ Reg ; S6=1 S9=1
Node 182 cpu_est_2_ Reg ; S6=1 S9=1
Node 109 inst_AS_000_INT Reg ; S6=1 S9=1
Node 154 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
Node 187 inst_AS_030_D0 Reg ; S6=1 S9=1
Node 119 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
Node 221 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
Node 152 inst_AS_000_DMA Reg ; S6=1 S9=1
Node 169 inst_DS_000_DMA Reg ; S6=1 S9=1
Node 170 CYCLE_DMA_0_ Reg ; S6=1 S9=1
Node 164 CYCLE_DMA_1_ Reg ; S6=1 S9=1
Node 248 SIZE_DMA_0_ Reg ; S6=1 S9=1
Node 259 SIZE_DMA_1_ Reg ; S6=1 S9=1
Node 224 inst_VPA_D Reg ; S6=1 S9=1
Node 188 inst_UDS_000_INT Reg ; S6=1 S9=1
Node 182 inst_LDS_000_INT Reg ; S6=1 S9=1
Node 209 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1
Node 274 CLK_000_D_1_ Reg ; S6=1 S9=1
Node 170 CLK_000_D_10_ Reg ; S6=1 S9=1
Node 269 CLK_000_D_11_ Reg ; S6=1 S9=1
Node 256 inst_DTACK_D0 Reg ; S6=1 S9=1
Node 113 inst_RESET_OUT Reg ; S6=1 S9=1
Node 169 CLK_000_D_0_ Reg ; S6=1 S9=1
Node 206 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
Node 130 IPL_D0_0_ Reg ; S6=1 S9=1
Node 146 IPL_D0_1_ Reg ; S6=1 S9=1
Node 106 IPL_D0_2_ Reg ; S6=1 S9=1
Node 200 CLK_000_D_2_ Reg ; S6=1 S9=1
Node 211 CLK_000_D_3_ Reg ; S6=1 S9=1
Node 166 CLK_000_D_4_ Reg ; S6=1 S9=1
Node 205 CLK_000_D_5_ Reg ; S6=1 S9=1
Node 194 CLK_000_D_6_ Reg ; S6=1 S9=1
Node 122 CLK_000_D_7_ Reg ; S6=1 S9=1
Node 250 CLK_000_D_8_ Reg ; S6=1 S9=1
Node 116 CLK_000_D_9_ Reg ; S6=1 S9=1
Node 266 CLK_000_D_12_ Reg ; S6=1 S9=1
Node 265 SIZE_DMA_1_ Reg ; S6=1 S9=1
Node 115 inst_VPA_D Reg ; S6=1 S9=1
Node 194 inst_UDS_000_INT Reg ; S6=1 S9=1
Node 134 inst_LDS_000_INT Reg ; S6=1 S9=1
Node 145 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1
Node 206 CLK_000_D_8_ Reg ; S6=1 S9=1
Node 289 CLK_000_D_9_ Reg ; S6=1 S9=1
Node 160 inst_DTACK_D0 Reg ; S6=1 S9=1
Node 259 inst_RESET_OUT Reg ; S6=1 S9=1
Node 277 CLK_000_D_1_ Reg ; S6=1 S9=1
Node 209 CLK_000_D_0_ Reg ; S6=1 S9=1
Node 104 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
Node 103 inst_CLK_OUT_PRE_25 Reg ; S6=1 S9=1
Node 121 IPL_D0_0_ Reg ; S6=1 S9=1
Node 130 IPL_D0_1_ Reg ; S6=1 S9=1
Node 256 IPL_D0_2_ Reg ; S6=1 S9=1
Node 278 CLK_000_D_2_ Reg ; S6=1 S9=1
Node 200 CLK_000_D_3_ Reg ; S6=1 S9=1
Node 178 CLK_000_D_4_ Reg ; S6=1 S9=1
Node 146 CLK_000_D_5_ Reg ; S6=1 S9=1
Node 140 CLK_000_D_6_ Reg ; S6=1 S9=1
Node 217 CLK_000_D_7_ Reg ; S6=1 S9=1
Node 230 CLK_000_D_10_ Reg ; S6=1 S9=1
Node 254 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1
Node 134 inst_DS_000_ENABLE Reg ; S6=1 S9=1
Node 152 SM_AMIGA_6_ Reg ; S6=1 S9=1
Node 253 SM_AMIGA_0_ Reg ; S6=1 S9=1
Node 140 SM_AMIGA_4_ Reg ; S6=1 S9=1
Node 221 RST_DLY_0_ Reg ; S6=1 S9=1
Node 241 RST_DLY_1_ Reg ; S6=1 S9=1
Node 235 RST_DLY_2_ Reg ; S6=1 S9=1
Node 109 inst_CLK_030_H Reg ; S6=1 S9=1
Node 223 SM_AMIGA_1_ Reg ; S6=1 S9=1
Node 229 SM_AMIGA_5_ Reg ; S6=1 S9=1
Node 236 SM_AMIGA_3_ Reg ; S6=1 S9=1
Node 230 SM_AMIGA_2_ Reg ; S6=1 S9=1
Node 223 inst_DS_000_ENABLE Reg ; S6=1 S9=1
Node 113 SM_AMIGA_6_ Reg ; S6=1 S9=1
Node 224 SM_AMIGA_4_ Reg ; S6=1 S9=1
Node 239 SM_AMIGA_0_ Reg ; S6=1 S9=1
Node 260 RST_DLY_0_ Reg ; S6=1 S9=1
Node 250 RST_DLY_1_ Reg ; S6=1 S9=1
Node 266 RST_DLY_2_ Reg ; S6=1 S9=1
Node 158 inst_CLK_030_H Reg ; S6=1 S9=1
Node 233 SM_AMIGA_1_ Reg ; S6=1 S9=1
Node 241 SM_AMIGA_5_ Reg ; S6=1 S9=1
Node 235 SM_AMIGA_3_ Reg ; S6=1 S9=1
Node 229 SM_AMIGA_2_ Reg ; S6=1 S9=1
Node 227 SM_AMIGA_i_7_ Reg ; S6=1 S9=1
Node 212 CIIN_0 Comb ; S6=1 S9=1
Node 211 CIIN_0 Comb ; S6=1 S9=1
; Unused Pins & Nodes
; -> None Found.

1197
Logic/68030_tk.prd
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1068
Logic/68030_tk.rpt
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13
Logic/68030_tk.tal
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@ -79,13 +79,14 @@ inst_AS_030_000_SYNC 1 1 1 1 .. .. 1 1
inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1
inst_VPA_D 1 1 .. .. .. .. 1 1
inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1
CLK_000_D_1_ .. .. .. .. .. .. 1 1
CLK_000_D_10_ .. .. .. .. .. .. 1 1
CLK_000_D_11_ .. .. .. .. .. .. 1 1
CLK_000_D_8_ .. .. .. .. .. .. 1 1
CLK_000_D_9_ .. .. .. .. .. .. 1 1
inst_DTACK_D0 1 1 .. .. .. .. 1 1
inst_RESET_OUT 1 1 .. .. .. .. .. ..
CLK_000_D_1_ .. .. .. .. .. .. 1 1
CLK_000_D_0_ 1 1 .. .. .. .. 1 1
inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1
inst_CLK_OUT_PRE_25 .. .. .. .. .. .. 1 1
IPL_D0_0_ 1 1 .. .. .. .. 1 1
IPL_D0_1_ 1 1 .. .. .. .. 1 1
IPL_D0_2_ 1 1 .. .. .. .. 1 1
@ -95,13 +96,11 @@ inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1
CLK_000_D_5_ .. .. .. .. .. .. 1 1
CLK_000_D_6_ .. .. .. .. .. .. 1 1
CLK_000_D_7_ .. .. .. .. .. .. 1 1
CLK_000_D_8_ .. .. .. .. .. .. 1 1
CLK_000_D_9_ .. .. .. .. .. .. 1 1
CLK_000_D_12_ .. .. .. .. .. .. 1 1
CLK_000_D_10_ .. .. .. .. .. .. 1 1
inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. ..
SM_AMIGA_6_ 1 1 .. .. .. .. 1 1
SM_AMIGA_0_ 1 1 .. .. .. .. 1 1
SM_AMIGA_4_ 1 1 .. .. .. .. 1 1
SM_AMIGA_0_ 1 1 .. .. .. .. 1 1
RST_DLY_0_ 1 1 .. .. .. .. 1 1
RST_DLY_1_ 1 1 .. .. .. .. 1 1
RST_DLY_2_ 1 1 .. .. .. .. 1 1

1163
Logic/68030_tk.tt2
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1163
Logic/68030_tk.tt3
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483
Logic/68030_tk.tt4
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@ -1,28 +1,28 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Fri Aug 19 00:39:35 2016
#$ DATE Wed Aug 24 22:17:49 2016
#$ MODULE BUS68030
#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030
UDS_000 LDS_000 nEXP_SPACE BERR BG_030 SIZE_0_ AHIGH_30_ BGACK_000 AHIGH_29_
CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_
AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ A_DECODE_20_ DTACK
A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ RST RESET
#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 SIZE_0_ AS_000
AHIGH_30_ AHIGH_29_ DS_030 AHIGH_28_ UDS_000 AHIGH_27_ LDS_000 AHIGH_26_
nEXP_SPACE AHIGH_25_ BERR AHIGH_24_ BG_030 A_DECODE_22_ A_DECODE_21_
A_DECODE_20_ BGACK_000 A_DECODE_19_ CLK_030 A_DECODE_18_ CLK_000 A_DECODE_17_
CLK_OSZI A_DECODE_16_ CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET
AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH
CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1
VMA RW A_0_ IPL_030_1_ IPL_030_0_
#$ NODES 53 cpu_est_3_ cpu_est_0_ cpu_est_1_ cpu_est_2_ inst_AS_000_INT
#$ NODES 52 cpu_est_3_ cpu_est_0_ cpu_est_1_ cpu_est_2_ inst_AS_000_INT
inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC
inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_
SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT
inst_CLK_OUT_PRE_D CLK_000_D_1_ CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0
inst_RESET_OUT CLK_000_D_0_ inst_CLK_OUT_PRE_50 IPL_D0_0_ IPL_D0_1_ IPL_D0_2_
CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_
CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
inst_DS_000_ENABLE SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_4_ RST_DLY_0_ RST_DLY_1_
inst_CLK_OUT_PRE_D CLK_000_D_8_ CLK_000_D_9_ inst_DTACK_D0 inst_RESET_OUT
CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 IPL_D0_0_
IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_
CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_10_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
inst_DS_000_ENABLE SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_
RST_DLY_2_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_
SM_AMIGA_i_7_ CIIN_0
.type f
.i 105
.o 180
.i 104
.o 178
.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000
CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_
@ -31,23 +31,23 @@
inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q
inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q
CLK_000_D_1_.Q CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q
CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q
CLK_000_D_2_.Q CLK_000_D_3_.Q CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q
CLK_000_D_7_.Q CLK_000_D_8_.Q CLK_000_D_9_.Q CLK_000_D_12_.Q
CLK_000_D_8_.Q CLK_000_D_9_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q
CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q IPL_D0_0_.Q
IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q CLK_000_D_4_.Q
CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_10_.Q
inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q inst_DS_000_ENABLE.Q SM_AMIGA_6_.Q
SM_AMIGA_0_.Q SM_AMIGA_4_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q
SM_AMIGA_4_.Q SM_AMIGA_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q
A_0_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q
SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN
AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN
AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0
.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030% AS_030.OE AS_000%
AS_000.OE DS_030% DS_030.OE UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE
SIZE_0_ SIZE_0_.OE AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE AHIGH_28_
AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE CLK_DIV_OUT.D
CLK_DIV_OUT.C AHIGH_25_ AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE FPU_CS% AVEC E RESET
RESET.OE AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW%
.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030% AS_030.OE SIZE_0_
SIZE_0_.OE AS_000% AS_000.OE AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE
DS_030% DS_030.OE AHIGH_28_ AHIGH_28_.OE UDS_000% UDS_000.OE AHIGH_27_
AHIGH_27_.OE LDS_000% LDS_000.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE
BERR BERR.OE AHIGH_24_ AHIGH_24_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS% AVEC E
RESET RESET.OE AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW%
AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE IPL_030_2_.D% IPL_030_2_.C RW_000.D% RW_000.C
RW_000.OE BG_000.D% BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C
DSACK1.D% DSACK1.C DSACK1.OE VMA.T VMA.C RW.D% RW.C RW.OE A_0_.D A_0_.C A_0_.OE
@ -61,226 +61,225 @@
CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D%
SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D% inst_VPA_D.C
inst_UDS_000_INT.D% inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_000_D_1_.D CLK_000_D_1_.C
CLK_000_D_10_.D CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C inst_DTACK_D0.D%
inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C CLK_000_D_0_.D CLK_000_D_0_.C
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D%
IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C
CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D
CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C
CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_12_.D
CLK_000_D_12_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D%
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_000_D_8_.D CLK_000_D_8_.C
CLK_000_D_9_.D CLK_000_D_9_.C inst_DTACK_D0.D% inst_DTACK_D0.C inst_RESET_OUT.D
inst_RESET_OUT.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_25.D
inst_CLK_OUT_PRE_25.C IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C
IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D
CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D CLK_000_D_5_.C
CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C CLK_000_D_10_.D
CLK_000_D_10_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D%
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C
SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_4_.D
SM_AMIGA_4_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 RST_DLY_1_.D.X2
SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_0_.D
SM_AMIGA_0_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 RST_DLY_1_.D.X2
RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.D inst_CLK_030_H.C
SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.D.X1
SM_AMIGA_3_.D.X2 SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.D.X1
SM_AMIGA_i_7_.D.X2 SM_AMIGA_i_7_.C CIIN_0
.phase 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
.p 204
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.phase 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
.p 203
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.end

483
Logic/68030_tk.tte
View File

@ -1,28 +1,28 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Fri Aug 19 00:39:35 2016
#$ DATE Wed Aug 24 22:17:49 2016
#$ MODULE BUS68030
#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030
UDS_000 LDS_000 nEXP_SPACE BERR BG_030 SIZE_0_ AHIGH_30_ BGACK_000 AHIGH_29_
CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_
AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ A_DECODE_20_ DTACK
A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ RST RESET
#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 SIZE_0_ AS_000
AHIGH_30_ AHIGH_29_ DS_030 AHIGH_28_ UDS_000 AHIGH_27_ LDS_000 AHIGH_26_
nEXP_SPACE AHIGH_25_ BERR AHIGH_24_ BG_030 A_DECODE_22_ A_DECODE_21_
A_DECODE_20_ BGACK_000 A_DECODE_19_ CLK_030 A_DECODE_18_ CLK_000 A_DECODE_17_
CLK_OSZI A_DECODE_16_ CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET
AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH
CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1
VMA RW A_0_ IPL_030_1_ IPL_030_0_
#$ NODES 53 cpu_est_3_ cpu_est_0_ cpu_est_1_ cpu_est_2_ inst_AS_000_INT
#$ NODES 52 cpu_est_3_ cpu_est_0_ cpu_est_1_ cpu_est_2_ inst_AS_000_INT
inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC
inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_
SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT
inst_CLK_OUT_PRE_D CLK_000_D_1_ CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0
inst_RESET_OUT CLK_000_D_0_ inst_CLK_OUT_PRE_50 IPL_D0_0_ IPL_D0_1_ IPL_D0_2_
CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_
CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
inst_DS_000_ENABLE SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_4_ RST_DLY_0_ RST_DLY_1_
inst_CLK_OUT_PRE_D CLK_000_D_8_ CLK_000_D_9_ inst_DTACK_D0 inst_RESET_OUT
CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 IPL_D0_0_
IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_
CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_10_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
inst_DS_000_ENABLE SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_
RST_DLY_2_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_
SM_AMIGA_i_7_ CIIN_0
.type f
.i 105
.o 180
.i 104
.o 178
.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000
CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_
@ -31,23 +31,23 @@
inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q
inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q
CLK_000_D_1_.Q CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q
CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q
CLK_000_D_2_.Q CLK_000_D_3_.Q CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q
CLK_000_D_7_.Q CLK_000_D_8_.Q CLK_000_D_9_.Q CLK_000_D_12_.Q
CLK_000_D_8_.Q CLK_000_D_9_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q
CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q IPL_D0_0_.Q
IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q CLK_000_D_4_.Q
CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_10_.Q
inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q inst_DS_000_ENABLE.Q SM_AMIGA_6_.Q
SM_AMIGA_0_.Q SM_AMIGA_4_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q
SM_AMIGA_4_.Q SM_AMIGA_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q
A_0_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q
SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN
AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN
AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0
.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE AS_000-
AS_000.OE DS_030- DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE
SIZE_0_ SIZE_0_.OE AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE AHIGH_28_
AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE CLK_DIV_OUT.D
CLK_DIV_OUT.C AHIGH_25_ AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE FPU_CS- AVEC E RESET
RESET.OE AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW-
.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE SIZE_0_
SIZE_0_.OE AS_000- AS_000.OE AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE
DS_030- DS_030.OE AHIGH_28_ AHIGH_28_.OE UDS_000- UDS_000.OE AHIGH_27_
AHIGH_27_.OE LDS_000- LDS_000.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE
BERR BERR.OE AHIGH_24_ AHIGH_24_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS- AVEC E
RESET RESET.OE AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW-
AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C
RW_000.OE BG_000.D- BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C
DSACK1.D- DSACK1.C DSACK1.OE VMA.T VMA.C RW.D- RW.C RW.OE A_0_.D A_0_.C A_0_.OE
@ -61,226 +61,225 @@
CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D-
SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D- inst_VPA_D.C
inst_UDS_000_INT.D- inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_000_D_1_.D CLK_000_D_1_.C
CLK_000_D_10_.D CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C inst_DTACK_D0.D-
inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C CLK_000_D_0_.D CLK_000_D_0_.C
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D-
IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C
CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D
CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C
CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_12_.D
CLK_000_D_12_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_000_D_8_.D CLK_000_D_8_.C
CLK_000_D_9_.D CLK_000_D_9_.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_RESET_OUT.D
inst_RESET_OUT.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_25.D
inst_CLK_OUT_PRE_25.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C
IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D
CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D CLK_000_D_5_.C
CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C CLK_000_D_10_.D
CLK_000_D_10_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C
SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_4_.D
SM_AMIGA_4_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 RST_DLY_1_.D.X2
SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_0_.D
SM_AMIGA_0_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 RST_DLY_1_.D.X2
RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.D inst_CLK_030_H.C
SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.D.X1
SM_AMIGA_3_.D.X2 SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.D.X1
SM_AMIGA_i_7_.D.X2 SM_AMIGA_i_7_.C CIIN_0
.phase 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
.p 204
---------------------------------------01---------------------------------------------------------------- 100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
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--------------------------------------------------------------------------------------------------------- 000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
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-----------------------------------0---------------------------------------------------0----------------- 000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
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------------------------1------------------------1------------------------------------------------------- 000000010001010000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
------------------------------------0--------------------------------------------------0----------------- 000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
------------------------------------------0-----------------------1-------------------------------------- 000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
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--------------------------0-11--------------------------------------------------------------------------- 000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
--------------------------1-00--------------------------------------------------------------------------- 000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-------------------------------------------------0------------------------------------------------------- 000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
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------------------------1---------------------------------------------------------------0---------------- 000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
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------------------------1--------1----------------------------------------------------------------------- 000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
------------------------0---------------------------------------1---------------------------------------- 000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
1------------111----------------0------------------------------------------------------------00000000---- 000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
--------------------------------------------------------------------------------------------------------1 000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
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-0----------1------------------------------------------------------------------------0------------------- 000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
------------1--------0------------------------------1--------------------------------0------------------- 000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
------------1--------1------------------------------0--------------------------------0------------------- 000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
------------1-------0--------------------------------1-------------------------------0------------------- 000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
------------1-------1--------------------------------0-------------------------------0------------------- 000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
------------1-----------------------------------------0------------------------------0------------------- 000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
------------1--------------------------------1------------------------0----------1----------------------- 000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
------------1-------------------------------------0-------------------0----------1----------------------- 000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
------------1------------------------------------------------------00-0----------1----------------------- 000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
------------1--------------------------------0----1----------------10------------1---------------------0- 000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
---10-------1-------------------1-----------------1------------------------------------------------------ 000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
----0-------1---------------------------------------------------------------------0---------------------- 000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
------------0-------------------------------------------------------------------------------------------- 000000000000000000000000000000000000000000000000000010000000000010000000000000000000000000101000000010000010000000000000000000000000000000000000000000000000000000000000000000000000
-----1------------------1-------------------------------------------------------------------------------- 000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
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.p 203
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.end

106
Logic/68030_tk.vcl
View File

@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 8/19/16;
TIME = 00:39:39;
DATE = 8/24/16;
TIME = 22:17:53;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;
@ -100,8 +100,8 @@ Page_Break = YES;
[OPTIMIZATION OPTIONS]
Logic_Reduction = YES;
Max_PTerm_Split = 16;
Max_PTerm_Collapse = 16;
Max_PTerm_Split = 20;
Max_PTerm_Collapse = 20;
XOR_Synthesis = YES;
Node_Collapse = Yes;
DT_Synthesis = Yes;
@ -109,7 +109,7 @@ DT_Synthesis = Yes;
[FITTER GLOBAL OPTIONS]
Run_Time = 0;
Set_Reset_Dont_Care = NO;
Set_Reset_Dont_Care = YES;
In_Reg_Optimize = YES;
Clock_Optimize = NO;
Conf_Unused_IOs = OUT_LOW;
@ -124,8 +124,13 @@ Type = GLB;
Zero_Hold_Time = Yes;
Signature_Word = 0;
Pull_up = Yes;
Out_Slew_Rate = SLOW, FAST, 7, CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW,
AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH;
Out_Slew_Rate = SLOW, FAST, 57, CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW,
AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH, AS_030, A_16_, A_17_, A_18_,
A_19_, RW, SIZE_1_, SIZE_0_, AVEC, BGACK_030, BG_000, E, IPL_030_0_, IPL_030_1_,
IPL_030_2_, LDS_000, UDS_000, VMA, RESET, CIIN, A_20_, A_21_, A_22_, A_24_,
A_25_, A_26_, A_27_, A_28_, A_29_, A_30_, A_31_, DS_030, BERR, A0, DSACK1,
RW_000, AS_000, A_23_, A1, A_3_, A_2_, AHIGH_24_, AHIGH_25_, AHIGH_26_,
AHIGH_27_, AHIGH_28_, AHIGH_29_, AHIGH_30_, AHIGH_31_, A_0_;
Device_max_fanin = 33;
Device_max_pterms = 20;
Usercode_Format = Hex;
@ -136,14 +141,14 @@ layer = OFF;
[LOCATION ASSIGNMENT]
Layer = OFF
BERR = OUTPUT,41,4,-;
AS_000 = OUTPUT,42,4,-;
RW_000 = BIDIR,80,7,-;
AS_030 = OUTPUT,82,7,-;
AS_000 = OUTPUT,42,4,-;
BERR = OUTPUT,41,4,-;
A_0_ = BIDIR,69,6,-;
RW = BIDIR,71,6,-;
UDS_000 = OUTPUT,32,3,-;
LDS_000 = OUTPUT,31,3,-;
A_0_ = BIDIR,69,6,-;
SIZE_1_ = OUTPUT,79,7,-;
SIZE_0_ = OUTPUT,70,6,-;
AHIGH_24_ = OUTPUT,19,2,-;
@ -173,67 +178,66 @@ AMIGA_ADDR_ENABLE = OUTPUT,33,3,-;
AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-;
CLK_EXP = OUTPUT,10,1,-;
RESET = OUTPUT,3,1,-;
CLK_000_D_1_ = NODE,*,7,-;
RN_BGACK_030 = NODE,-1,7,-;
inst_RESET_OUT = NODE,*,0,-;
CLK_000_D_0_ = NODE,*,2,-;
SM_AMIGA_6_ = NODE,*,2,-;
inst_AS_030_D0 = NODE,*,0,-;
SM_AMIGA_0_ = NODE,*,6,-;
SM_AMIGA_i_7_ = NODE,*,5,-;
inst_AS_030_000_SYNC = NODE,*,2,-;
cpu_est_1_ = NODE,*,5,-;
inst_RESET_OUT = NODE,*,6,-;
CLK_000_D_0_ = NODE,*,4,-;
CLK_000_D_1_ = NODE,*,7,-;
SM_AMIGA_6_ = NODE,*,0,-;
inst_AS_030_D0 = NODE,*,3,-;
inst_AS_030_000_SYNC = NODE,*,0,-;
cpu_est_1_ = NODE,*,3,-;
cpu_est_3_ = NODE,*,3,-;
SM_AMIGA_1_ = NODE,*,5,-;
CLK_000_D_2_ = NODE,*,4,-;
inst_CLK_OUT_PRE_D = NODE,*,4,-;
inst_CLK_OUT_PRE_D = NODE,*,1,-;
inst_BGACK_030_INT_D = NODE,*,5,-;
cpu_est_2_ = NODE,*,3,-;
inst_AS_000_DMA = NODE,*,0,-;
RST_DLY_0_ = NODE,*,5,-;
inst_DS_000_ENABLE = NODE,*,1,-;
SM_AMIGA_i_7_ = NODE,*,5,-;
inst_DS_000_DMA = NODE,*,2,-;
inst_AS_000_DMA = NODE,*,2,-;
RN_VMA = NODE,-1,3,-;
SM_AMIGA_5_ = NODE,*,5,-;
SM_AMIGA_4_ = NODE,*,1,-;
SM_AMIGA_1_ = NODE,*,5,-;
SM_AMIGA_0_ = NODE,*,5,-;
inst_DS_000_ENABLE = NODE,*,5,-;
inst_LDS_000_INT = NODE,*,1,-;
SIZE_DMA_1_ = NODE,*,6,-;
SIZE_DMA_0_ = NODE,*,6,-;
cpu_est_0_ = NODE,*,3,-;
RST_DLY_2_ = NODE,*,5,-;
RST_DLY_1_ = NODE,*,5,-;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,6,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,6,-;
inst_AS_000_INT = NODE,*,2,-;
CLK_000_D_11_ = NODE,*,7,-;
inst_VPA_D = NODE,*,5,-;
inst_BGACK_030_INT_D = NODE,*,7,-;
inst_CLK_OUT_PRE_25 = NODE,*,0,-;
inst_AS_000_INT = NODE,*,0,-;
CLK_000_D_9_ = NODE,*,7,-;
inst_VPA_D = NODE,*,0,-;
RN_IPL_030_0_ = NODE,-1,1,-;
RN_IPL_030_1_ = NODE,-1,1,-;
RN_IPL_030_2_ = NODE,-1,1,-;
inst_DS_000_DMA = NODE,*,0,-;
inst_CLK_030_H = NODE,*,0,-;
inst_CLK_030_H = NODE,*,2,-;
RN_DSACK1 = NODE,-1,7,-;
RN_RW_000 = NODE,-1,7,-;
SM_AMIGA_2_ = NODE,*,5,-;
SM_AMIGA_3_ = NODE,*,5,-;
CYCLE_DMA_1_ = NODE,*,0,-;
RST_DLY_0_ = NODE,*,6,-;
CYCLE_DMA_1_ = NODE,*,2,-;
RN_A_0_ = NODE,-1,6,-;
inst_LDS_000_INT = NODE,*,3,-;
CYCLE_DMA_0_ = NODE,*,0,-;
SM_AMIGA_5_ = NODE,*,5,-;
SM_AMIGA_4_ = NODE,*,5,-;
CYCLE_DMA_0_ = NODE,*,2,-;
RN_RW = NODE,-1,6,-;
RN_BG_000 = NODE,-1,3,-;
CIIN_0 = NODE,*,4,-;
RST_DLY_2_ = NODE,*,6,-;
RST_DLY_1_ = NODE,*,6,-;
inst_UDS_000_INT = NODE,*,3,-;
CLK_000_D_12_ = NODE,*,6,-;
CLK_000_D_9_ = NODE,*,0,-;
CLK_000_D_8_ = NODE,*,6,-;
CLK_000_D_7_ = NODE,*,0,-;
CLK_000_D_6_ = NODE,*,3,-;
CLK_000_D_5_ = NODE,*,4,-;
CLK_000_D_4_ = NODE,*,2,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,2,-;
CLK_000_D_10_ = NODE,*,5,-;
CLK_000_D_7_ = NODE,*,4,-;
CLK_000_D_6_ = NODE,*,1,-;
CLK_000_D_5_ = NODE,*,1,-;
CLK_000_D_4_ = NODE,*,3,-;
CLK_000_D_3_ = NODE,*,4,-;
IPL_D0_2_ = NODE,*,0,-;
CLK_000_D_2_ = NODE,*,7,-;
IPL_D0_2_ = NODE,*,6,-;
IPL_D0_1_ = NODE,*,1,-;
IPL_D0_0_ = NODE,*,1,-;
inst_CLK_OUT_PRE_50 = NODE,*,4,-;
inst_DTACK_D0 = NODE,*,6,-;
CLK_000_D_10_ = NODE,*,2,-;
IPL_D0_0_ = NODE,*,0,-;
inst_CLK_OUT_PRE_50 = NODE,*,0,-;
inst_DTACK_D0 = NODE,*,2,-;
CLK_000_D_8_ = NODE,*,4,-;
CLK_OSZI = INPUT,61,-,-;

154
Logic/68030_tk.vco
View File

@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 8/19/16;
TIME = 00:39:40;
DATE = 8/24/16;
TIME = 22:17:53;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;
@ -100,8 +100,8 @@ Page_Break = YES;
[OPTIMIZATION OPTIONS]
Logic_Reduction = YES;
Max_PTerm_Split = 16;
Max_PTerm_Collapse = 16;
Max_PTerm_Split = 20;
Max_PTerm_Collapse = 20;
XOR_Synthesis = YES;
Node_Collapse = Yes;
DT_Synthesis = Yes;
@ -109,7 +109,7 @@ DT_Synthesis = Yes;
[FITTER GLOBAL OPTIONS]
Run_Time = 0;
Set_Reset_Dont_Care = NO;
Set_Reset_Dont_Care = YES;
In_Reg_Optimize = YES;
Clock_Optimize = NO;
Conf_Unused_IOs = OUT_LOW;
@ -124,8 +124,13 @@ Type = GLB;
Zero_Hold_Time = Yes;
Signature_Word = 0;
Pull_up = Yes;
Out_Slew_Rate = SLOW, FAST, 7, CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW,
AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH;
Out_Slew_Rate = SLOW, FAST, 57, CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW,
AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH, AS_030, A_16_, A_17_, A_18_,
A_19_, RW, SIZE_1_, SIZE_0_, AVEC, BGACK_030, BG_000, E, IPL_030_0_, IPL_030_1_,
IPL_030_2_, LDS_000, UDS_000, VMA, RESET, CIIN, A_20_, A_21_, A_22_, A_24_,
A_25_, A_26_, A_27_, A_28_, A_29_, A_30_, A_31_, DS_030, BERR, A0, DSACK1,
RW_000, AS_000, A_23_, A1, A_3_, A_2_, AHIGH_24_, AHIGH_25_, AHIGH_26_,
AHIGH_27_, AHIGH_28_, AHIGH_29_, AHIGH_30_, AHIGH_31_, A_0_;
Device_max_fanin = 33;
Device_max_pterms = 20;
Usercode_Format = Hex;
@ -142,39 +147,39 @@ A_DECODE_23_ = INPUT,85, H,-;
IPL_2_ = INPUT,68, G,-;
FC_1_ = INPUT,58, F,-;
AS_030 = BIDIR,82, H,-;
AS_000 = BIDIR,42, E,-;
DS_030 = OUTPUT,98, A,-;
UDS_000 = BIDIR,32, D,-;
LDS_000 = BIDIR,31, D,-;
nEXP_SPACE = INPUT,14,-,-;
BERR = BIDIR,41, E,-;
BG_030 = INPUT,21, C,-;
SIZE_0_ = BIDIR,70, G,-;
AS_000 = BIDIR,42, E,-;
AHIGH_30_ = BIDIR,5, B,-;
BGACK_000 = INPUT,28, D,-;
AHIGH_29_ = BIDIR,6, B,-;
CLK_030 = INPUT,64,-,-;
DS_030 = OUTPUT,98, A,-;
AHIGH_28_ = BIDIR,15, C,-;
CLK_000 = INPUT,11,-,-;
UDS_000 = BIDIR,32, D,-;
AHIGH_27_ = BIDIR,16, C,-;
CLK_OSZI = INPUT,61,-,-;
LDS_000 = BIDIR,31, D,-;
AHIGH_26_ = BIDIR,17, C,-;
CLK_DIV_OUT = OUTPUT,65, G,-;
nEXP_SPACE = INPUT,14,-,-;
AHIGH_25_ = BIDIR,18, C,-;
BERR = BIDIR,41, E,-;
AHIGH_24_ = BIDIR,19, C,-;
FPU_CS = OUTPUT,78, H,-;
BG_030 = INPUT,21, C,-;
A_DECODE_22_ = INPUT,84, H,-;
FPU_SENSE = INPUT,91, A,-;
A_DECODE_21_ = INPUT,94, A,-;
A_DECODE_20_ = INPUT,93, A,-;
DTACK = INPUT,30, D,-;
BGACK_000 = INPUT,28, D,-;
A_DECODE_19_ = INPUT,97, A,-;
AVEC = OUTPUT,92, A,-;
CLK_030 = INPUT,64,-,-;
A_DECODE_18_ = INPUT,95, A,-;
E = OUTPUT,66, G,-;
CLK_000 = INPUT,11,-,-;
A_DECODE_17_ = INPUT,59, F,-;
VPA = INPUT,36,-,-;
CLK_OSZI = INPUT,61,-,-;
A_DECODE_16_ = INPUT,96, A,-;
CLK_DIV_OUT = OUTPUT,65, G,-;
FPU_CS = OUTPUT,78, H,-;
FPU_SENSE = INPUT,91, A,-;
DTACK = INPUT,30, D,-;
AVEC = OUTPUT,92, A,-;
E = OUTPUT,66, G,-;
VPA = INPUT,36,-,-;
RST = INPUT,86,-,-;
RESET = OUTPUT,3, B,-;
AMIGA_ADDR_ENABLE = OUTPUT,33, D,-;
@ -197,56 +202,55 @@ RW = BIDIR,71, G,-;
A_0_ = BIDIR,69, G,-;
IPL_030_1_ = OUTPUT,7, B,-;
IPL_030_0_ = OUTPUT,8, B,-;
cpu_est_3_ = NODE,9, D,-;
cpu_est_0_ = NODE,2, D,-;
cpu_est_1_ = NODE,8, F,-;
cpu_est_2_ = NODE,13, D,-;
inst_AS_000_INT = NODE,15, C,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,10, G,-;
inst_AS_030_D0 = NODE,6, A,-;
inst_AS_030_000_SYNC = NODE,6, C,-;
inst_BGACK_030_INT_D = NODE,13, H,-;
inst_AS_000_DMA = NODE,12, A,-;
inst_DS_000_DMA = NODE,1, A,-;
CYCLE_DMA_0_ = NODE,13, A,-;
CYCLE_DMA_1_ = NODE,9, A,-;
cpu_est_3_ = NODE,2, D,-;
cpu_est_0_ = NODE,10, D,-;
cpu_est_1_ = NODE,13, D,-;
cpu_est_2_ = NODE,6, D,-;
inst_AS_000_INT = NODE,5, A,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,3, C,-;
inst_AS_030_D0 = NODE,9, D,-;
inst_AS_030_000_SYNC = NODE,12, A,-;
inst_BGACK_030_INT_D = NODE,0, F,-;
inst_AS_000_DMA = NODE,2, C,-;
inst_DS_000_DMA = NODE,13, C,-;
CYCLE_DMA_0_ = NODE,14, C,-;
CYCLE_DMA_1_ = NODE,10, C,-;
SIZE_DMA_0_ = NODE,2, G,-;
SIZE_DMA_1_ = NODE,9, G,-;
inst_VPA_D = NODE,2, F,-;
inst_UDS_000_INT = NODE,10, D,-;
inst_LDS_000_INT = NODE,6, D,-;
inst_CLK_OUT_PRE_D = NODE,8, E,-;
CLK_000_D_1_ = NODE,3, H,-;
CLK_000_D_10_ = NODE,14, C,-;
CLK_000_D_11_ = NODE,0, H,-;
inst_DTACK_D0 = NODE,7, G,-;
inst_RESET_OUT = NODE,8, A,-;
CLK_000_D_0_ = NODE,13, C,-;
inst_CLK_OUT_PRE_50 = NODE,6, E,-;
IPL_D0_0_ = NODE,3, B,-;
IPL_D0_1_ = NODE,14, B,-;
IPL_D0_2_ = NODE,3, A,-;
CLK_000_D_2_ = NODE,2, E,-;
CLK_000_D_3_ = NODE,9, E,-;
CLK_000_D_4_ = NODE,11, C,-;
CLK_000_D_5_ = NODE,5, E,-;
CLK_000_D_6_ = NODE,14, D,-;
CLK_000_D_7_ = NODE,14, A,-;
CLK_000_D_8_ = NODE,3, G,-;
CLK_000_D_9_ = NODE,10, A,-;
CLK_000_D_12_ = NODE,14, G,-;
SIZE_DMA_1_ = NODE,13, G,-;
inst_VPA_D = NODE,9, A,-;
inst_UDS_000_INT = NODE,14, D,-;
inst_LDS_000_INT = NODE,6, B,-;
inst_CLK_OUT_PRE_D = NODE,13, B,-;
CLK_000_D_8_ = NODE,6, E,-;
CLK_000_D_9_ = NODE,13, H,-;
inst_DTACK_D0 = NODE,7, C,-;
inst_RESET_OUT = NODE,9, G,-;
CLK_000_D_1_ = NODE,5, H,-;
CLK_000_D_0_ = NODE,8, E,-;
inst_CLK_OUT_PRE_50 = NODE,2, A,-;
inst_CLK_OUT_PRE_25 = NODE,1, A,-;
IPL_D0_0_ = NODE,13, A,-;
IPL_D0_1_ = NODE,3, B,-;
IPL_D0_2_ = NODE,7, G,-;
CLK_000_D_2_ = NODE,6, H,-;
CLK_000_D_3_ = NODE,2, E,-;
CLK_000_D_4_ = NODE,3, D,-;
CLK_000_D_5_ = NODE,14, B,-;
CLK_000_D_6_ = NODE,10, B,-;
CLK_000_D_7_ = NODE,13, E,-;
CLK_000_D_10_ = NODE,6, F,-;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,6, G,-;
inst_DS_000_ENABLE = NODE,6, B,-;
SM_AMIGA_6_ = NODE,2, C,-;
SM_AMIGA_0_ = NODE,5, G,-;
SM_AMIGA_4_ = NODE,10, B,-;
RST_DLY_0_ = NODE,0, F,-;
RST_DLY_1_ = NODE,13, F,-;
RST_DLY_2_ = NODE,9, F,-;
inst_CLK_030_H = NODE,5, A,-;
SM_AMIGA_1_ = NODE,1, F,-;
SM_AMIGA_5_ = NODE,5, F,-;
SM_AMIGA_3_ = NODE,10, F,-;
SM_AMIGA_2_ = NODE,6, F,-;
inst_DS_000_ENABLE = NODE,1, F,-;
SM_AMIGA_6_ = NODE,8, A,-;
SM_AMIGA_4_ = NODE,2, F,-;
SM_AMIGA_0_ = NODE,12, F,-;
RST_DLY_0_ = NODE,10, G,-;
RST_DLY_1_ = NODE,3, G,-;
RST_DLY_2_ = NODE,14, G,-;
inst_CLK_030_H = NODE,6, C,-;
SM_AMIGA_1_ = NODE,8, F,-;
SM_AMIGA_5_ = NODE,13, F,-;
SM_AMIGA_3_ = NODE,9, F,-;
SM_AMIGA_2_ = NODE,5, F,-;
SM_AMIGA_i_7_ = NODE,4, F,-;
CIIN_0 = NODE,10, E,-;
CIIN_0 = NODE,9, E,-;

12
Logic/68030_tk.vct
View File

@ -15,8 +15,8 @@ Voltage = 5.0;
RCS = "$Revision: 1.2 $";
Parent = m4a5.lci;
SDS_File = m4a5.sds;
DATE = 08/18/2016;
TIME = 23:26:14;
DATE = 08/23/2016;
TIME = 20:07:14;
Source_Format = Pure_VHDL;
Type = TT2;
Pre_Fit_Time = 1;
@ -61,8 +61,8 @@ Max_Blk_In_Percent = 100;
[OPTIMIZATION OPTIONS]
Logic_Reduction = Yes;
Max_PTerm_Split = 16;
Max_PTerm_Collapse = 16;
Max_PTerm_Split = 20;
Max_PTerm_Collapse = 20;
XOR_Synthesis = Yes;
EN_XOR_Synthesis = Yes;
XOR_Gate = Yes;
@ -90,7 +90,7 @@ Max_Symbols = 32;
[FITTER GLOBAL OPTIONS]
Run_Time = 0;
Set_Reset_Dont_Care = No;
Set_Reset_Dont_Care = Yes;
EN_Set_Reset_Dont_Care = Yes;
In_Reg_Optimize = Yes;
EN_In_Reg_Optimize = No;
@ -104,7 +104,7 @@ Conf_Unused_IOs = Out_Low;
Zero_Hold_Time = Yes;
Signature_Word = 0;
Pull_up = Yes;
Out_Slew_Rate = SLOW,FAST,7,CLK_DIV_OUT,CLK_EXP,FPU_CS,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH;
Out_Slew_Rate = SLOW,FAST,57,CLK_DIV_OUT,CLK_EXP,FPU_CS,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH,AS_030,A_16_,A_17_,A_18_,A_19_,RW,SIZE_1_,SIZE_0_,AVEC,BGACK_030,BG_000,E,IPL_030_0_,IPL_030_1_,IPL_030_2_,LDS_000,UDS_000,VMA,RESET,CIIN,A_20_,A_21_,A_22_,A_24_,A_25_,A_26_,A_27_,A_28_,A_29_,A_30_,A_31_,DS_030,BERR,A0,DSACK1,RW_000,AS_000,A_23_,A1,A_3_,A_2_,AHIGH_24_,AHIGH_25_,AHIGH_26_,AHIGH_27_,AHIGH_28_,AHIGH_29_,AHIGH_30_,AHIGH_31_,A_0_;
Device_max_fanin = 33;
Device_max_pterms = 20;
Usercode_Format = Hex;

2157
Logic/68030_tk.vho
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2
Logic/68030_tk.xrf
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@ -2,7 +2,7 @@ Signal Name Cross Reference File
ispLEVER Classic 2.0.00.17.20.15
Design '68030_tk' created Fri Aug 19 00:39:35 2016
Design '68030_tk' created Wed Aug 24 22:17:49 2016
LEGEND: '>' Functional Block Port Separator

2851
Logic/BUS68030.bl0
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3046
Logic/BUS68030.bl1
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4664
Logic/BUS68030.edi
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20
Logic/BUS68030.fse
View File

@ -1,20 +1,20 @@
fsm_encoding {7130381301} onehot
fsm_encoding {7131381311} onehot
fsm_state_encoding {7130381301} idle_p {00000000}
fsm_state_encoding {7131381311} idle_p {00000000}
fsm_state_encoding {7130381301} idle_n {00000011}
fsm_state_encoding {7131381311} idle_n {00000011}
fsm_state_encoding {7130381301} as_set_p {00000101}
fsm_state_encoding {7131381311} as_set_p {00000101}
fsm_state_encoding {7130381301} as_set_n {00001001}
fsm_state_encoding {7131381311} as_set_n {00001001}
fsm_state_encoding {7130381301} sample_dtack_p {00010001}
fsm_state_encoding {7131381311} sample_dtack_p {00010001}
fsm_state_encoding {7130381301} data_fetch_n {00100001}
fsm_state_encoding {7131381311} data_fetch_n {00100001}
fsm_state_encoding {7130381301} data_fetch_p {01000001}
fsm_state_encoding {7131381311} data_fetch_p {01000001}
fsm_state_encoding {7130381301} end_cycle_n {10000001}
fsm_state_encoding {7131381311} end_cycle_n {10000001}
fsm_registers {7130381301} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]}
fsm_registers {7131381311} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]}

2
Logic/BUS68030.prj
View File

@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
#-- Written on Fri Aug 19 00:39:21 2016
#-- Written on Wed Aug 24 22:17:35 2016
#device options

5300
Logic/BUS68030.srm
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39
Logic/BUS68030.srr
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@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Fri Aug 19 00:39:28 2016
#Wed Aug 24 22:17:42 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N|Running in 64-bit mode
@ -18,17 +18,16 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed -
VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":69:10:69:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":86:14:86:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:7:127:17|Signal clk_out_pre is undriven
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:36:125:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":153:2:153:3|Pruning register CLK_030_D0_2
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register SM_AMIGA
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -39,14 +38,14 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Aug 19 00:39:28 2016
# Wed Aug 24 22:17:43 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@ -56,7 +55,7 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Aug 19 00:39:29 2016
# Wed Aug 24 22:17:44 2016
###########################################################]
Map & Optimize Report
@ -65,7 +64,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N: MF248 |Running in 64-bit mode.
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@ -80,15 +79,15 @@ original code -> new code
Resource Usage Report
Simple gate primitives:
DFF 63 uses
DFF 62 uses
BI_DIR 18 uses
BUFTH 4 uses
IBUF 38 uses
OBUF 15 uses
AND2 295 uses
INV 265 uses
AND2 289 uses
INV 262 uses
OR2 25 uses
XOR2 5 uses
XOR2 6 uses
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
@ -98,6 +97,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Aug 19 00:39:30 2016
# Wed Aug 24 22:17:44 2016
###########################################################]

BIN
Logic/BUS68030.srs
View File

Binary file not shown.

4
Logic/Programming.xcf
View File

@ -19,8 +19,8 @@
<BScanVal>0</BScanVal>
</Bypass>
<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
<FileTime>08/17/16 17:45:51</FileTime>
<JedecChecksum>0x2728</JedecChecksum>
<FileTime>08/19/16 00:39:40</FileTime>
<JedecChecksum>0x4245</JedecChecksum>
<Operation>Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>

1
Logic/automake.err
View File

@ -0,0 +1 @@
Need not generate svf file according to the constraints, exit

957
Logic/bus68030.exf
View File

File diff suppressed because it is too large Load Diff

69
Logic/bus68030.srf
View File

@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Fri Aug 19 00:39:28 2016
#Wed Aug 24 22:17:42 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N|Running in 64-bit mode
@ -18,17 +18,16 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed -
VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":69:10:69:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":86:14:86:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:7:127:17|Signal clk_out_pre is undriven
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:36:125:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":153:2:153:3|Pruning register CLK_030_D0_2
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register SM_AMIGA
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -39,14 +38,14 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Aug 19 00:39:28 2016
# Wed Aug 24 22:17:43 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@ -56,48 +55,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Aug 19 00:39:29 2016
###########################################################]
Map & Optimize Report
Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N: MF248 |Running in 64-bit mode.
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
001 -> 00000011
010 -> 00000101
011 -> 00001001
100 -> 00010001
101 -> 00100001
110 -> 01000001
111 -> 10000001
---------------------------------------
Resource Usage Report
Simple gate primitives:
DFF 63 uses
BI_DIR 18 uses
BUFTH 4 uses
IBUF 38 uses
OBUF 15 uses
AND2 295 uses
INV 265 uses
OR2 25 uses
XOR2 5 uses
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
I-2014.03LC
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Aug 19 00:39:30 2016
# Wed Aug 24 22:17:44 2016
###########################################################]

12
Logic/dm/BUS68030_comp.xdm
View File

@ -25,15 +25,11 @@ S7RCVMI="F3s Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S>
SR<WN(=""DRL=d"4"ORL=""(R=CD""4dR=CO""4cR
/>SqS<R"M=3ONsEDVHCP"R=""(/S>
SR<qM3="lkF8DHCVDRC"P(=""
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jc3jn6U("
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jd3j4j.6"
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=j43j66n."
/>SqS<R"M=3MOF#M0N0C_soP"R=J"&k;F0ABtqid_jjh_Qa)_u &R4J0kF;>"/
<SSq=RM"03#lH0D#H00lRC"Pj="3jjjj"jj/S>
SR<qMF="s_HoH0M#_"FVR"P=&FJk0z;A1jnUdJj&k;F0"
/>SqS<R"M=3HFsolhNCP"R=J"&k;F0Anz1Ujjd&FJk0/;">
/>SqS<R"M=3l#00#DH0l0HCP"R=3"jjjjjj/j">S
S<MqR=s"FHHo_M_#0FRV"P&="J0kF;1AzndUjjk&JF"0;/S>
SR<qM3="FosHhCNl"=RP"k&JFA0;zU1nj&djJ0kF;>"/
/S<7>CV
]</70p1s0kOk>sC

2
Logic/lattice_cmd.rs2
View File

@ -1 +1 @@
-src 68030_tk.tt4 -type PLA -devfile "E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447ace.dev" -lci "68030_tk.lct" -touch "68030_tk.tt4"
-src 68030_tk.tt4 -type PLA -devfile "E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447ace.dev" -postfit -lci 68030_tk.lco

2
Logic/run_options.txt
View File

@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version I-2014.03LC
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
#-- Written on Fri Aug 19 00:39:28 2016
#-- Written on Wed Aug 24 22:17:42 2016
#project files

41
Logic/syndos.env
View File

@ -1,41 +0,0 @@
ABEL5DEV=E:\ispLEVER_Classic2_0\ispcpld\lib5
DIOEDA_ABEL5DEV=E:\ispLEVER_Classic2_0\ispcpld\lib5
DIOEDA_ActiveHDL=E:\ispLEVER_Classic2_0\active-hdl\BIN
DIOEDA_ActiveHDLPath=E:\ispLEVER_Classic2_0\active-hdl\BIN
DIOEDA_AppNotes=E:\ispLEVER_Classic2_0\ispcpld\bin
DIOEDA_Bin=E:\ispLEVER_Classic2_0\ispcpld\bin
DIOEDA_Config=E:\ispLEVER_Classic2_0\ispcpld\config
DIOEDA_CONTEXT=ispLEVER CLASSIC
DIOEDA_DSPPATH=E:\ispLEVER_Classic2_0\ispLeverDSP
DIOEDA_EPICPATH=E:\ispLEVER_Classic2_0\ispfpga\bin\nt
DIOEDA_Examples=E:\ispLEVER_Classic2_0\examples
DIOEDA_FPGABinPath=E:\ispLEVER_Classic2_0\ispfpga\bin\nt
DIOEDA_FPGAPath=E:\ispLEVER_Classic2_0\ispfpga
DIOEDA_HDLExplorer=E:\ispLEVER_Classic2_0\hdle\win32
DIOEDA_INI=C:\lsc_env
DIOEDA_ispVM=E:\ispLEVER_Classic2_0\ispvmsystem
DIOEDA_ispVMSystem=E:\ispLEVER_Classic2_0\ispvmsystem
DIOEDA_License=E:\ispLEVER_Classic2_0\license
DIOEDA_LSEPath=E:\ispLEVER_Classic2_0\lse
DIOEDA_MachPath=E:\ispLEVER_Classic2_0\ispcpld\bin
DIOEDA_Manuals=E:\ispLEVER_Classic2_0\ispcpld\manuals
DIOEDA_ModelSim=E:\ispLEVER_Classic2_0\modelsim\win32loem
DIOEDA_ModelsimPath=E:\ispLEVER_Classic2_0\modelsim\win32loem
DIOEDA_PDSPath=E:\ispLEVER_Classic2_0\ispcomp
DIOEDA_Precision=C:\isptools\precision
DIOEDA_PrecisionPath=C:\isptools\precision
DIOEDA_ProductName=ispLEVER
DIOEDA_ProductPrefix=SYN
DIOEDA_ProductTitle=ispLEVER
DIOEDA_ProductType=2.0.00.17.20.15_LS_HDL_BASE_PC_N
DIOEDA_ProductVersion=2.0.00.17
DIOEDA_ProgramFolder=Lattice Semiconductor ispLEVER Classic 2.0
DIOEDA_Root=E:\ispLEVER_Classic2_0\ispcpld
DIOEDA_Spectrum=C:\isptools\spectrum
DIOEDA_SpectrumPath=C:\isptools\spectrum
DIOEDA_Synplify=E:\ispLEVER_Classic2_0\synpbase
DIOEDA_SynplifyPath=E:\ispLEVER_Classic2_0\synpbase
DIOEDA_Synthesis=E:\ispLEVER_Classic2_0\lse\bin\nt
DIOEDA_Tutorial=E:\ispLEVER_Classic2_0\ispcpld\tutorial
DIOPRODUCT=ispLEVER
PATH=E:\ispLEVER_Classic2_0\ispcpld\bin

2
Logic/synlog/BUS68030_multi_srs_gen.srr
View File

@ -5,6 +5,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Aug 19 00:39:29 2016
# Wed Aug 24 22:17:44 2016
###########################################################]

12
Logic/synlog/bus68030_fpga_mapper.srr
View File

@ -2,7 +2,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N: MF248 |Running in 64-bit mode.
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@ -17,15 +17,15 @@ original code -> new code
Resource Usage Report
Simple gate primitives:
DFF 63 uses
DFF 62 uses
BI_DIR 18 uses
BUFTH 4 uses
IBUF 38 uses
OBUF 15 uses
AND2 295 uses
INV 265 uses
AND2 289 uses
INV 262 uses
OR2 25 uses
XOR2 5 uses
XOR2 6 uses
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
@ -35,6 +35,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Aug 19 00:39:30 2016
# Wed Aug 24 22:17:44 2016
###########################################################]

2
Logic/synlog/report/BUS68030_compiler_errors.txt
View File

@ -1,3 +1,3 @@
@E: CD415 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":406:49:406:49|Expecting keyword then
@E: CD415 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":489:6:489:7|Expecting keyword process
@E|Parse errors encountered - exiting

8
Logic/synlog/report/BUS68030_compiler_notes.txt
View File

@ -2,8 +2,8 @@
@N: CD720 :"E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":69:10:69:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":86:14:86:15|Using sequential encoding for type sm_68000
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register SM_AMIGA
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register cpu_est
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est

6
Logic/synlog/report/BUS68030_compiler_runstatus.xml
View File

@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
</info>
<info name="Warnings">
<data>8</data>
<data>7</data>
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
</info>
<info name="Errors">
@ -29,13 +29,13 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data>
</info>
<info name="Real Time">
<data>0h:00m:00s</data>
<data>0h:00m:01s</data>
</info>
<info name="Peak Memory">
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1471559968</data>
<data type="timestamp">1472069863</data>
</info>
</job_info>
</job_run_status>

13
Logic/synlog/report/BUS68030_compiler_warnings.txt
View File

@ -1,9 +1,8 @@
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:7:127:17|Signal clk_out_pre is undriven
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:36:125:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":153:2:153:3|Pruning register CLK_030_D0_2
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused

2
Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
View File

@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the
<data>105MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1471559970</data>
<data type="timestamp">1472069864</data>
</info>
</job_info>
</job_run_status>

57
Logic/syntmp/BUS68030_srr.htm
View File

@ -1,5 +1,5 @@
<html><body><samp><pre>
<!@TC:1471559968>
<!@TC:1472069862>
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
#install: E:\ispLEVER_Classic2_0\synpbase
#OS: Windows 7 6.2
@ -8,29 +8,28 @@
#Implementation: logic
<a name=compilerReport1>$ Start of Compile</a>
#Fri Aug 19 00:39:28 2016
#Wed Aug 24 22:17:42 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N: : <!@TM:1471559968> | Running in 64-bit mode
@N: : <!@TM:1472069863> | Running in 64-bit mode
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1471559968> | Setting time resolution to ns
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1471559968> | Top entity is set to BUS68030.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1472069863> | Setting time resolution to ns
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1472069863> | Top entity is set to BUS68030.
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1471559968> | Synthesizing work.bus68030.behavioral
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:69:10:69:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(69)</a><!@TM:1471559968> | Using sequential encoding for type sm_e
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:86:14:86:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(86)</a><!@TM:1471559968> | Using sequential encoding for type sm_68000
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:127:7:127:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(127)</a><!@TM:1471559968> | Signal clk_out_pre is undriven </font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1472069863> | Synthesizing work.bus68030.behavioral
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:70:10:70:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(70)</a><!@TM:1472069863> | Using sequential encoding for type sm_e
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:87:14:87:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(87)</a><!@TM:1472069863> | Using sequential encoding for type sm_68000
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:128:7:128:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(128)</a><!@TM:1472069863> | Signal clk_out_pre is undriven </font>
Post processing for work.bus68030.behavioral
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:38:130:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1471559968> | Pruning register DS_030_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:38:130:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1471559968> | Pruning register nEXP_SPACE_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:129:34:129:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(129)</a><!@TM:1471559968> | Pruning register CLK_OUT_EXP_INT_1 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:125:36:125:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(125)</a><!@TM:1471559968> | Pruning register CLK_OUT_PRE_25_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:153:2:153:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(153)</a><!@TM:1471559968> | Pruning register CLK_030_D0_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:38:130:41:@W:CL189:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1471559968> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:38:130:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1471559968> | Trying to extract state machine for register SM_AMIGA
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472069863> | Pruning register DS_030_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472069863> | Pruning register nEXP_SPACE_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472069863> | Pruning register BGACK_030_INT_PRE_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1472069863> | Pruning register CLK_OUT_EXP_INT_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:154:2:154:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(154)</a><!@TM:1472069863> | Pruning register CLK_030_D0_2 </font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472069863> | Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -41,24 +40,24 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:38:130:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1471559968> | Trying to extract state machine for register cpu_est
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:24:1:24:9:@W:CL246:@XP_MSG">68030-68000-bus.vhd(24)</a><!@TM:1471559968> | Input port bits 15 to 2 of a_decode(23 downto 2) are unused </font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472069863> | Trying to extract state machine for register cpu_est
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:24:1:24:9:@W:CL246:@XP_MSG">68030-68000-bus.vhd(24)</a><!@TM:1472069863> | Input port bits 15 to 2 of a_decode(23 downto 2) are unused </font>
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Aug 19 00:39:28 2016
# Wed Aug 24 22:17:43 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@N: : <!@TM:1471559969> | Running in 64-bit mode
@N: : <!@TM:1472069864> | Running in 64-bit mode
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Aug 19 00:39:29 2016
# Wed Aug 24 22:17:44 2016
###########################################################]
Map & Optimize Report
@ -66,8 +65,8 @@ Map & Optimize Report
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1471559970> | Running in 64-bit mode.
@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:38:130:41:@N::@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1471559970> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1472069864> | Running in 64-bit mode.
@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:38:131:41:@N::@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1472069864> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@ -82,25 +81,25 @@ original code -> new code
<a name=resourceUsage3>Resource Usage Report</a>
Simple gate primitives:
DFF 63 uses
DFF 62 uses
BI_DIR 18 uses
BUFTH 4 uses
IBUF 38 uses
OBUF 15 uses
AND2 295 uses
INV 265 uses
AND2 289 uses
INV 262 uses
OR2 25 uses
XOR2 5 uses
XOR2 6 uses
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1471559970> | Timing Report not generated for this device, please use place and route tools for timing analysis.
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1472069864> | Timing Report not generated for this device, please use place and route tools for timing analysis.
I-2014.03LC
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Aug 19 00:39:30 2016
# Wed Aug 24 22:17:44 2016
###########################################################]

2
Logic/syntmp/BUS68030_toc.htm
View File

@ -16,7 +16,7 @@
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
<ul rel="open" >
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (00:39 19-Aug)</a>
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (22:17 24-Aug)</a>
<ul ></ul></li> </ul>
</li>
</ul>

2
Logic/syntmp/run_option.xml
View File

@ -3,7 +3,7 @@
Synopsys, Inc.
Version I-2014.03LC
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
Written on Fri Aug 19 00:39:28 2016
Written on Wed Aug 24 22:17:42 2016
-->

10
Logic/syntmp/statusReport.html
View File

@ -33,12 +33,12 @@
<tr>
<td class="optionTitle">Compile Input</td><td>Complete</td>
<td>8</td>
<td>8</td>
<td>7</td>
<td>0</td>
<td>-</td>
<td>0m:00s</td>
<td>0m:01s</td>
<td>-</td>
<td><font size="-1">19.08.2016</font><br/><font size="-2">00:39:28</font></td>
<td><font size="-1">24.08.2016</font><br/><font size="-2">22:17:43</font></td>
</tr>
<tr>
@ -49,12 +49,12 @@
<td>0m:00s</td>
<td>0m:00s</td>
<td>105MB</td>
<td><font size="-1">19.08.2016</font><br/><font size="-2">00:39:30</font></td>
<td><font size="-1">24.08.2016</font><br/><font size="-2">22:17:44</font></td>
</tr>
<tr>
<td class="optionTitle">Multi-srs Generator</td>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">19.08.2016</font><br/><font size="-2">00:39:29</font></td> </tbody>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">24.08.2016</font><br/><font size="-2">22:17:44</font></td> </tbody>
</table>
</td></tr></table></body>
</html>

2
Logic/synwork/BUS68030_comp.fdep
View File

@ -9,7 +9,7 @@
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471559957
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1472069842
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

2
Logic/synwork/BUS68030_comp.fdeporig
View File

@ -9,7 +9,7 @@
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471559957
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1472069842
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

BIN
Logic/synwork/BUS68030_comp.srs
View File

Binary file not shown.

21
Logic/synwork/BUS68030_comp.tlg
View File

@ -1,15 +1,14 @@
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":69:10:69:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":86:14:86:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:7:127:17|Signal clk_out_pre is undriven
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:7:128:17|Signal clk_out_pre is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_OUT_EXP_INT_1
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:36:125:38|Pruning register CLK_OUT_PRE_25_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":153:2:153:3|Pruning register CLK_030_D0_2
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register SM_AMIGA
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -20,5 +19,5 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused

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Logic/synwork/BUS68030_mult.srs
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Logic/synwork/BUS68030_mult_srs/skeleton.srs
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Logic/synwork/BUS68030_s.srs
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