mirror of https://github.com/kr239/68030tk.git
resetfix + pdfs
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MHeinrichs
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@ -0,0 +1,561 @@
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-- Copyright: Matthias Heinrichs 2014
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-- Free for non-comercial use
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-- No warranty just for fun
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-- If you want to earn money with this code, ask me first!
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity BUS68030 is
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port(
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AS_030: inout std_logic ;
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AS_000: inout std_logic ;
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RW_000: inout std_logic ;
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DS_030: inout std_logic ;
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UDS_000: inout std_logic;
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LDS_000: inout std_logic;
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SIZE: inout std_logic_vector ( 1 downto 0 );
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AHIGH: inout std_logic_vector ( 31 downto 24 );
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A_DECODE: in std_logic_vector ( 23 downto 2 );
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A: inout std_logic_vector ( 1 downto 0 );
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--A0: inout std_logic;
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--A1: in std_logic;
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nEXP_SPACE: in std_logic ;
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BERR: inout std_logic ;
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BG_030: in std_logic ;
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BG_000: out std_logic ;
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BGACK_030: out std_logic ;
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BGACK_000: in std_logic ;
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CLK_030: in std_logic ;
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CLK_000: in std_logic ;
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CLK_OSZI: in std_logic ;
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CLK_DIV_OUT: out std_logic ;
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CLK_EXP: out std_logic ;
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FPU_CS: out std_logic ;
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FPU_SENSE: in std_logic ;
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IPL_030: out std_logic_vector ( 2 downto 0 );
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IPL: in std_logic_vector ( 2 downto 0 );
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DSACK1: inout std_logic;
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DTACK: inout std_logic ;
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AVEC: out std_logic ;
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E: out std_logic ;
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VPA: in std_logic ;
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VMA: out std_logic ;
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RST: in std_logic ;
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RESET: inout std_logic ;
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RW: inout std_logic ;
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-- D: inout std_logic_vector ( 31 downto 28 );
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FC: in std_logic_vector ( 1 downto 0 );
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AMIGA_ADDR_ENABLE: out std_logic ;
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AMIGA_BUS_DATA_DIR: out std_logic ;
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AMIGA_BUS_ENABLE_LOW: out std_logic;
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AMIGA_BUS_ENABLE_HIGH: out std_logic;
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CIIN: out std_logic
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);
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end BUS68030;
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architecture Behavioral of BUS68030 is
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-- values are determined empirically
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constant DS_SAMPLE : integer := 12; -- for 7.09 MHz Clock with a base clock of 100Mhz and CPU running at 25MHZ
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--constant DS_SAMPLE : integer := 12; -- for 7.09 MHz Clock with a base clock of 100Mhz and CPU running at 50MHZ
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TYPE SM_E IS (
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E1,
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E2,
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E3,
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E4,
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E5,
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E6,
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E7,
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E8,
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E9,
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E10
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);
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signal cpu_est : SM_E;
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TYPE SM_68000 IS (
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IDLE_P,
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IDLE_N,
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AS_SET_P,
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AS_SET_N,
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SAMPLE_DTACK_P,
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DATA_FETCH_N,
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DATA_FETCH_P,
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END_CYCLE_N
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);
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signal SM_AMIGA : SM_68000;
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--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
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signal AS_000_INT:STD_LOGIC := '1';
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signal AS_000_D0:STD_LOGIC := '1';
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signal RW_000_INT:STD_LOGIC := '1';
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signal AMIGA_BUS_ENABLE_DMA_HIGH:STD_LOGIC := '1';
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signal AMIGA_BUS_ENABLE_DMA_LOW:STD_LOGIC := '1';
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signal AS_030_D0:STD_LOGIC := '1';
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signal nEXP_SPACE_D0:STD_LOGIC := '0';
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signal DS_030_D0:STD_LOGIC := '1';
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signal AS_030_000_SYNC:STD_LOGIC := '1';
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signal BGACK_030_INT:STD_LOGIC := '1';
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signal BGACK_030_INT_D:STD_LOGIC := '1';
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signal BGACK_030_INT_PRE:STD_LOGIC := '1';
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signal AS_000_DMA:STD_LOGIC := '1';
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signal DS_000_DMA:STD_LOGIC := '1';
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signal RW_000_DMA:STD_LOGIC := '1';
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signal CYCLE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
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signal SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
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signal IPL_D0: STD_LOGIC_VECTOR ( 2 downto 0 ) := "111";
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signal A0_DMA: STD_LOGIC := '1';
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signal VMA_INT: STD_LOGIC := '1';
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signal VPA_D: STD_LOGIC := '1';
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signal UDS_000_INT: STD_LOGIC := '1';
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signal LDS_000_INT: STD_LOGIC := '1';
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signal DS_000_ENABLE: STD_LOGIC := '0';
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signal DSACK1_INT: STD_LOGIC := '1';
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signal CLK_OUT_PRE_50: STD_LOGIC := '1';
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signal CLK_OUT_PRE_25: STD_LOGIC := '1';
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signal CLK_OUT_PRE: STD_LOGIC := '1';
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signal CLK_OUT_PRE_D: STD_LOGIC := '1';
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signal CLK_OUT_INT: STD_LOGIC := '1';
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signal CLK_OUT_EXP_INT: STD_LOGIC := '1';
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signal CLK_030_H: STD_LOGIC := '1';
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signal CLK_000_D: STD_LOGIC_VECTOR ( DS_SAMPLE downto 0 );
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signal CLK_000_PE: STD_LOGIC := '0';
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signal CLK_000_NE: STD_LOGIC := '0';
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signal DTACK_D0: STD_LOGIC := '1';
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signal RESET_OUT: STD_LOGIC := '0';
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signal CLK_030_D0: STD_LOGIC := '0';
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signal RST_DLY: STD_LOGIC_VECTOR ( 2 downto 0 ) := "000";
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signal CLK_030_PE: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
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signal AMIGA_DS: STD_LOGIC := '1';
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begin
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CLK_000_PE <= CLK_000_D(0) AND NOT CLK_000_D(1);
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CLK_000_NE <= NOT CLK_000_D(0) AND CLK_000_D(1);
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--pos edge clock process
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--no ansynchronious reset! the reset is sampled synchroniously
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--this mut be because of the e-clock: The E-Clock has to run CONSTANTLY
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--or the Amiga will fail to boot from a reset.
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--However a compilation with no resets on the E-Clock and resets on other signals does not work, either!
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pos_clk: process(CLK_OSZI)
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begin
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if(rising_edge(CLK_OSZI)) then
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--clk generation :
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CLK_030_D0 <=CLK_030;
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CLK_OUT_PRE_50 <= not CLK_OUT_PRE_50;
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if(CLK_OUT_PRE_50 = '1' )then
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CLK_OUT_PRE_25<= not CLK_OUT_PRE_25;
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end if;
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--here the clock is selected
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--CLK_OUT_PRE_D <= CLK_OUT_PRE_25;
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CLK_OUT_PRE_D <= CLK_OUT_PRE_50;
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-- the external clock to the processor is generated here
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CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
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CLK_OUT_EXP_INT <= CLK_OUT_PRE_D;
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--delayed Clocks and signals for edge detection
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CLK_000_D(0) <= CLK_000;
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CLK_000_D(DS_SAMPLE downto 1) <= CLK_000_D((DS_SAMPLE-1) downto 0);
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-- e-clock is changed on the FALLING edge!
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if(CLK_000_NE = '1' ) then
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case (cpu_est) is
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when E1 => cpu_est <= E2 ;
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when E2 => cpu_est <= E3 ;
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when E3 => cpu_est <= E4;
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when E4 => cpu_est <= E5 ;
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when E5 => cpu_est <= E6 ;
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when E6 => cpu_est <= E7 ;
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when E7 => cpu_est <= E8 ;
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when E8 => cpu_est <= E9 ;
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when E9 => cpu_est <= E10;
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when E10 => cpu_est <= E1 ;
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end case;
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end if;
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--the statemachine
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if(RST = '0' ) then
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VPA_D <= '1';
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DTACK_D0 <= '1';
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SM_AMIGA <= IDLE_P;
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AS_000_INT <= '1';
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RW_000_INT <= '1';
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RW_000_DMA <= '1';
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AS_030_000_SYNC <= '1';
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UDS_000_INT <= '1';
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LDS_000_INT <= '1';
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DS_000_ENABLE <= '0';
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VMA_INT <= '1';
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BG_000 <= '1';
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BGACK_030_INT <= '1';
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BGACK_030_INT_D <= '1';
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BGACK_030_INT_PRE<= '1';
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DSACK1_INT <= '1';
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IPL_D0 <= "111";
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IPL_030 <= "111";
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AS_000_DMA <= '1';
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DS_000_DMA <= '1';
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SIZE_DMA <= "11";
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A0_DMA <= '1';
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AMIGA_BUS_ENABLE_DMA_HIGH <= '1';
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AMIGA_BUS_ENABLE_DMA_LOW <= '1';
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AS_030_D0 <= '1';
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nEXP_SPACE_D0 <= '1';
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DS_030_D0 <= '1';
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CYCLE_DMA <= "00";
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RST_DLY <= "000";
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RESET_OUT <= '0';
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AS_000_D0 <='1';
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AMIGA_DS <='1';
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CLK_030_PE <= "00";
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else
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if(CLK_000_NE='1')then
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if(RST_DLY="111")then
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RESET_OUT <= '1';
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else
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RST_DLY <= RST_DLY+1;
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end if;
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end if;
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--now: 68000 state machine and signals
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--buffering signals
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AS_030_D0 <= AS_030;
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nEXP_SPACE_D0 <= nEXP_SPACE;
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DS_030_D0 <= DS_030;
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DTACK_D0 <= DTACK;
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VPA_D <= VPA;
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--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
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if(BGACK_000='0') then
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BGACK_030_INT <= '0';
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--BGACK_030_INT_PRE<= '0';
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elsif ( BGACK_000='1'
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AND CLK_000_NE='1'
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AND AS_000 = '1' --the amiga AS can be still active while bgack is deasserted, so wait for this signal too!
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) then -- BGACK_000 is high here!
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--BGACK_030_INT_PRE<= '1';
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BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes low
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end if;
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BGACK_030_INT_D <= BGACK_030_INT;
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--bus grant only in idle state
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if(BG_030= '1')then
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BG_000 <= '1';
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elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P)
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and nEXP_SPACE = '1' and AS_030_D0='1'
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and CLK_000_D(0)='1'
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) then --bus granted no local access and no AS_030 running!
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BG_000 <= '0';
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end if;
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--interrupt buffering to avoid ghost interrupts
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IPL_D0<=IPL;
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if(IPL = IPL_D0) then --and CLK_000_PE = '1')then
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IPL_030<=IPL;
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end if;
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-- as030-sampling and FPU-Select
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if(AS_030 ='1') then -- "async" reset of various signals
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AS_030_000_SYNC <= '1';
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DSACK1_INT <= '1';
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AS_000_INT <= '1';
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DS_000_ENABLE <= '0';
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--RW_000_INT <= '1';
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elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks
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AS_030_D0 = '0' AND --as set
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BGACK_030_INT='1' AND
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BGACK_030_INT_D='1' AND --no dma -cycle
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NOT (FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0') AND --FPU-Select
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nEXP_SPACE ='1' and --not an expansion space cycle
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SM_AMIGA = IDLE_P --last amiga cycle terminated
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) then
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AS_030_000_SYNC <= '0';
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end if;
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-- VMA generation
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if(CLK_000_NE='1' AND VPA_D='0' AND cpu_est = E4)then --assert
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VMA_INT <= '0';
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elsif(CLK_000_PE='1' AND cpu_est=E1)then --deassert
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VMA_INT <= '1';
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end if;
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--uds/lds precalculation
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if (SM_AMIGA = IDLE_N) then --DS: set udl/lds
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if(A(0)='0') then
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UDS_000_INT <= '0';
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else
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UDS_000_INT <= '1';
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end if;
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if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
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LDS_000_INT <= '0';
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else
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LDS_000_INT <= '1';
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end if;
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end if;
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--Amiga statemachine
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case (SM_AMIGA) is
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when IDLE_P => --68000:S0 wait for a falling edge
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RW_000_INT <= '1';
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if( CLK_000_D(3)='0' and CLK_000_D(4)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
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SM_AMIGA<=IDLE_N; --go to s1
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end if;
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when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
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if(CLK_000_PE='1')then --go to s2
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SM_AMIGA <= AS_SET_P; --as for amiga set!
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RW_000_INT <= RW;
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AS_000_INT <= '0';
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if (RW='1' ) then --read: set udl/lds
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DS_000_ENABLE <= '1';
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end if;
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end if;
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when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
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if(CLK_000_NE='1')then --go to s3
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SM_AMIGA<=AS_SET_N;
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end if;
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when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write
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if(CLK_000_PE='1')then --go to s4
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-- set DS-Enable without respect to rw: this simplifies the life for the syntesizer
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DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
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SM_AMIGA <= SAMPLE_DTACK_P;
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end if;
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when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
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if( CLK_000_NE='1' and --falling edge
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((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
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(BERR='0') OR --Bus error
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(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
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)then --go to s5
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SM_AMIGA<=DATA_FETCH_N;
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end if;
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when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
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if(CLK_000_PE = '1')then --go to s6
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SM_AMIGA<=DATA_FETCH_P;
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end if;
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when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
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--if( (CLK_000_D(DS_SAMPLE-2)='0' AND CLK_000_D((DS_SAMPLE-1))='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
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-- (CLK_000_D(DS_SAMPLE-1)='0' AND CLK_000_D((DS_SAMPLE-0))='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
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-- DSACK1_INT <='0';
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--end if;
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--go to s7 dsack is sampled at the falling edge of the 030-clock
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--if(CLK_000_D(0)='0' and CLK_000_D(1)='1')then
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if( CLK_000_NE ='1') then
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SM_AMIGA<=END_CYCLE_N;
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DSACK1_INT <='0';
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end if;
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when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
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if(CLK_000_PE='1')then --go to s0
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SM_AMIGA<=IDLE_P;
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RW_000_INT <= '1';
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end if;
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end case;
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--dma stuff
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AS_000_D0 <=AS_000;
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if(UDS_000='0' or LDS_000='0') then
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AMIGA_DS <='0';
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else
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AMIGA_DS <='1';
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end if;
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if(BGACK_030_INT='0')then
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--set some signals NOT linked to AS_000='0'
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RW_000_DMA <= RW_000;
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-- now determine the size: if both uds and lds is set its 16 bit else 8 bit!
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if(UDS_000='0' and LDS_000='0') then
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SIZE_DMA <= "10"; --16bit
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else
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SIZE_DMA <= "01"; --8 bit
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end if;
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--now calculate the offset:
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--if uds is set low, a0 is so too.
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||||
--if only lds is set a1 is high
|
||||
--therefore a1 = uds
|
||||
--great! life is simple here!
|
||||
A0_DMA <= UDS_000;
|
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--A0_DMA <= '0';
|
||||
--A1 is set by the amiga side
|
||||
--here we determine the upper or lower half of the databus
|
||||
AMIGA_BUS_ENABLE_DMA_HIGH <= A(1);
|
||||
AMIGA_BUS_ENABLE_DMA_LOW <= not A(1);
|
||||
|
||||
elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then
|
||||
RW_000_DMA <= '1';
|
||||
SIZE_DMA <= "00";
|
||||
A0_DMA <= '0';
|
||||
AMIGA_BUS_ENABLE_DMA_HIGH <= '1';
|
||||
AMIGA_BUS_ENABLE_DMA_LOW <= '1';
|
||||
end if;
|
||||
|
||||
if(BGACK_030_INT='0' and AS_000='0')then
|
||||
-- an 68000-memory cycle is three negative edges long!
|
||||
if(CLK_000_NE='1' and CYCLE_DMA<"11")then
|
||||
CYCLE_DMA <= CYCLE_DMA+1;
|
||||
end if;
|
||||
else
|
||||
CYCLE_DMA <= "00";
|
||||
end if;
|
||||
|
||||
--as can only be done if we know the uds/lds!
|
||||
if( CYCLE_DMA >"00"
|
||||
and AS_000 = '0'
|
||||
and AMIGA_DS ='0'
|
||||
and (
|
||||
CYCLE_DMA < "11"
|
||||
or RW_000 = '1')
|
||||
)then
|
||||
--set AS_000
|
||||
if( not(CLK_OUT_INT='0' and CLK_OUT_PRE_D ='1')) then --sampled on rising edges, so we can set AS only if the next clock is not rising!!
|
||||
AS_000_DMA <= '0';
|
||||
if(RW_000='1') then
|
||||
DS_000_DMA <='0';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if( CLK_OUT_INT='0' and CLK_OUT_PRE_D ='1' and CLK_030_PE <"11" and AS_000_DMA = '0') then --sample rising edges
|
||||
CLK_030_PE <= CLK_030_PE+1;
|
||||
end if;
|
||||
|
||||
if(RW_000='0' and CLK_030_PE="01" and CLK_030='1')then
|
||||
DS_000_DMA <= '0'; -- write: one clock delayed!
|
||||
end if;
|
||||
|
||||
else
|
||||
CLK_030_PE <= "00";
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process pos_clk;
|
||||
|
||||
--output clock assignment
|
||||
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||
CLK_EXP <= CLK_OUT_INT;--not CLK_OUT_EXP_INT;
|
||||
--CLK_DIV_OUT <= 'Z';
|
||||
--CLK_EXP <= CLK_030;
|
||||
|
||||
|
||||
RESET <= 'Z';
|
||||
--RESET <= 'Z' when RESET_OUT ='1' else '0';
|
||||
--RST <= '0' when RESET_OUT_AMIGA = '1' else 'Z';
|
||||
--RESET <= RESET_OUT;
|
||||
|
||||
-- bus drivers
|
||||
AMIGA_ADDR_ENABLE <= '0';
|
||||
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and AS_030_000_SYNC='0' and AS_030 = '0' else --not (SM_AMIGA = IDLE_P or (SM_AMIGA = END_CYCLE_N and CLK_000 = '1')) ELSE
|
||||
'0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE
|
||||
'1';
|
||||
AMIGA_BUS_ENABLE_LOW <= '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' ELSE
|
||||
'1';
|
||||
|
||||
|
||||
AMIGA_BUS_DATA_DIR <= not RW_000 WHEN (BGACK_030_INT ='1') ELSE --Amiga READ/WRITE
|
||||
--'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
|
||||
'1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
|
||||
--'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
|
||||
'0'; --Point towarts TK
|
||||
|
||||
|
||||
--dma stuff
|
||||
DTACK <= 'Z' when AS_000_DMA='1' else '0'; --DTACK will be generated by GARY!
|
||||
|
||||
AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else
|
||||
'0' when AS_000_DMA ='0' and AS_000 ='0' else
|
||||
'1';
|
||||
DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else
|
||||
'0' when DS_000_DMA ='0' and AS_000 ='0' else
|
||||
'1';
|
||||
A(0) <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' --tristate on CPU-Cycle
|
||||
else A0_DMA; --drive on DMA-Cycle
|
||||
A(1) <= 'Z';
|
||||
AHIGH <= "ZZZZZZZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR RESET = '0' else x"00";
|
||||
SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else
|
||||
SIZE_DMA;
|
||||
--rw
|
||||
RW <= 'Z' when BGACK_030_INT ='1' or RESET_OUT ='0' --tristate on CPU cycle
|
||||
else RW_000_DMA; --drive on DMA-Cycle
|
||||
|
||||
BGACK_030 <= BGACK_030_INT;
|
||||
|
||||
--fpu
|
||||
FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0' AND BGACK_000='1' AND FPU_SENSE ='0'
|
||||
else '1';
|
||||
|
||||
--if no copro is installed:
|
||||
BERR <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0' AND BGACK_000='1' AND FPU_SENSE ='1'
|
||||
else 'Z';
|
||||
|
||||
|
||||
--cache inhibit: Tristate for expansion (it decides) and off for the Amiga
|
||||
CIIN <= '1' WHEN AHIGH(31 downto 24) = x"00" and A_DECODE(23 downto 20) = x"F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom
|
||||
'Z' WHEN nEXP_SPACE = '0' ELSE --Tristate for expansion (it decides)
|
||||
'0'; --off for the Amiga
|
||||
|
||||
--e and VMA
|
||||
E <= '1' when
|
||||
cpu_est = E7 or
|
||||
cpu_est = E8 or
|
||||
cpu_est = E9 or
|
||||
cpu_est = E10
|
||||
else '0';
|
||||
VMA <= VMA_INT;
|
||||
|
||||
|
||||
--AVEC
|
||||
AVEC <= '1';
|
||||
|
||||
--as and uds/lds
|
||||
AS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else
|
||||
'0' when AS_000_INT ='0' and AS_030 ='0' else
|
||||
'1';
|
||||
RW_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' --tristate on DMA-cycle
|
||||
else RW_000_INT; -- drive on CPU cycle
|
||||
|
||||
UDS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else --tristate on DMA cycle
|
||||
--'1' when DS_000_ENABLE ='0' else
|
||||
UDS_000_INT when DS_000_ENABLE ='1' -- output on cpu cycle
|
||||
else '1'; -- datastrobe not ready jet
|
||||
LDS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else --tristate on DMA cycle
|
||||
--'1' when DS_000_ENABLE ='0' else
|
||||
LDS_000_INT when DS_000_ENABLE ='1' -- output on cpu cycle
|
||||
else '1'; -- datastrobe not ready jet
|
||||
|
||||
--dsack
|
||||
DSACK1 <= 'Z' when nEXP_SPACE = '0' else --tristate on expansionboard cycle
|
||||
DSACK1_INT when AS_030 = '0' else -- output on amiga cycle
|
||||
'1';
|
||||
|
||||
|
||||
end Behavioral;
|
||||
1281
Logic/68030_TK.tcl
1281
Logic/68030_TK.tcl
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
|
@ -1,5 +1,5 @@
|
|||
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
|
||||
#$ DATE Fri Nov 18 19:32:36 2016
|
||||
#$ DATE Thu Dec 29 16:01:56 2016
|
||||
#$ MODULE 68030_tk
|
||||
#$ PINS 75 A_DECODE_2_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ AHIGH_31_ IPL_1_ IPL_0_ \
|
||||
# A_DECODE_23_ FC_0_ A_1_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 \
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
|
||||
#$ DATE Fri Nov 18 19:32:36 2016
|
||||
#$ DATE Thu Dec 29 16:01:56 2016
|
||||
#$ MODULE 68030_tk
|
||||
#$ PINS 61 A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ \
|
||||
# FC_0_ A_1_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE \
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
// Signal Name Cross Reference File
|
||||
// ispLEVER Classic 2.0.00.17.20.15
|
||||
|
||||
// Design '68030_tk' created Fri Nov 18 19:32:36 2016
|
||||
// Design '68030_tk' created Thu Dec 29 16:01:56 2016
|
||||
|
||||
|
||||
// LEGEND: '>' Functional Block Port Separator
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
Copyright(C), 1992-2015, Lattice Semiconductor Corp.
|
||||
All Rights Reserved.
|
||||
|
||||
Design bus68030 created Fri Nov 18 19:32:36 2016
|
||||
Design bus68030 created Thu Dec 29 16:01:56 2016
|
||||
|
||||
|
||||
P-Terms Fan-in Fan-out Type Name (attributes)
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
<LATTICE_ENCRYPTED_BLIF>64;0=1?P_reM=E>
|
||||
<LATTICE_ENCRYPTED_BLIF>6050655){ N
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ AUTHOR:
|
|||
PATTERN:
|
||||
COMPANY:
|
||||
REVISION:
|
||||
DATE: Fri Nov 18 19:32:41 2016
|
||||
DATE: Thu Dec 29 16:02:00 2016
|
||||
|
||||
ABEL mach447a
|
||||
*
|
||||
|
|
|
|||
|
|
@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $";
|
|||
Parent = m4a5.lci;
|
||||
SDS_File = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
DATE = 11/18/16;
|
||||
TIME = 19:32:41;
|
||||
DATE = 12/29/16;
|
||||
TIME = 16:02:00;
|
||||
Source_Format = Pure_VHDL;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
|
|
|
|||
|
|
@ -8870,6 +8870,906 @@
|
|||
316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
314 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
306 inst_DTACK_D0 3 -1 1 1 2 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1
|
||||
95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1
|
||||
94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1
|
||||
58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 1 4 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 1 4 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
2 RESET 1 -1 -1 2 1 2 2 -1
|
||||
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
||||
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
||||
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
||||
63 CLK_030 1 -1 -1 1 0 63 -1
|
||||
59 A_1_ 1 -1 -1 1 5 59 -1
|
||||
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
||||
35 VPA 1 -1 -1 1 5 35 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
10 CLK_000 1 -1 -1 1 3 10 -1
|
||||
115 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
81 AS_030 5 -1 7 5 2 3 4 6 7 81 -1 1 0 21
|
||||
41 AS_000 5 -1 4 4 0 4 5 7 41 -1 1 0 21
|
||||
79 RW_000 5 339 7 3 4 5 6 79 -1 4 0 21
|
||||
31 UDS_000 5 -1 3 3 5 6 7 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 3 5 6 7 30 -1 1 0 21
|
||||
68 A_0_ 5 345 6 2 0 2 68 -1 3 0 21
|
||||
70 RW 5 344 6 2 3 7 70 -1 2 0 21
|
||||
78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21
|
||||
69 SIZE_0_ 5 340 6 1 2 69 -1 3 0 21
|
||||
40 BERR 5 -1 4 1 0 40 -1 1 0 21
|
||||
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
||||
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
||||
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
||||
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
||||
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
||||
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
||||
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
||||
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
||||
8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21
|
||||
7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21
|
||||
6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21
|
||||
82 BGACK_030 5 342 7 0 82 -1 3 0 21
|
||||
34 VMA 5 343 3 0 34 -1 3 0 21
|
||||
65 E 0 6 0 65 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 341 3 0 28 -1 2 0 21
|
||||
97 DS_030 0 0 0 97 -1 1 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
80 DSACK1 0 7 0 80 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
||||
322 SM_AMIGA_6_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 3 0 21
|
||||
309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
||||
311 CLK_000_D_0_ 3 -1 3 6 0 1 3 5 6 7 -1 -1 1 0 21
|
||||
310 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21
|
||||
300 inst_AS_030_000_SYNC 3 -1 2 3 1 2 3 -1 -1 7 0 21
|
||||
295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
|
||||
293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
|
||||
335 SM_AMIGA_i_7_ 3 -1 1 3 1 2 7 -1 -1 3 1 21
|
||||
324 SM_AMIGA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21
|
||||
301 inst_BGACK_030_INT_D 3 -1 7 3 2 6 7 -1 -1 1 0 21
|
||||
299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21
|
||||
296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21
|
||||
303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21
|
||||
302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21
|
||||
343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
|
||||
332 SM_AMIGA_5_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
||||
325 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21
|
||||
323 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21
|
||||
319 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
|
||||
304 CYCLE_DMA_0_ 3 -1 0 2 0 5 -1 -1 3 0 21
|
||||
294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
|
||||
331 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
|
||||
330 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21
|
||||
321 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
||||
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
||||
313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21
|
||||
307 CLK_000_D_3_ 3 -1 2 2 1 7 -1 -1 1 0 21
|
||||
306 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21
|
||||
347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21
|
||||
346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21
|
||||
338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21
|
||||
329 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21
|
||||
334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21
|
||||
333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
|
||||
339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
||||
326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
|
||||
305 CYCLE_DMA_1_ 3 -1 5 1 5 -1 -1 4 0 21
|
||||
345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
||||
340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
|
||||
337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
|
||||
320 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21
|
||||
344 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
||||
327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
|
||||
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
||||
318 CLK_000_D_4_ 3 -1 7 1 1 -1 -1 1 0 21
|
||||
317 CLK_000_D_2_ 3 -1 7 1 2 -1 -1 1 0 21
|
||||
316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
314 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
|
||||
312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
||||
308 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1
|
||||
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
||||
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
||||
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
||||
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
|
||||
59 A_1_ 1 -1 -1 2 2 6 59 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
||||
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
||||
63 CLK_030 1 -1 -1 1 5 63 -1
|
||||
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
||||
35 VPA 1 -1 -1 1 3 35 -1
|
||||
29 DTACK 1 -1 -1 1 0 29 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
10 CLK_000 1 -1 -1 1 3 10 -1
|
||||
119 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
81 AS_030 5 -1 7 6 0 1 2 3 4 7 81 -1 1 0 21
|
||||
79 RW_000 5 345 7 3 0 4 6 79 -1 4 0 21
|
||||
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
||||
31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21
|
||||
70 RW 5 350 6 2 2 7 70 -1 2 0 21
|
||||
78 SIZE_1_ 5 341 7 1 5 78 -1 3 0 21
|
||||
69 SIZE_0_ 5 348 6 1 5 69 -1 3 0 21
|
||||
68 A_0_ 5 340 6 1 5 68 -1 3 0 21
|
||||
40 BERR 5 -1 4 1 2 40 -1 1 0 21
|
||||
29 DTACK 5 -1 3 1 1 29 -1 1 0 21
|
||||
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
||||
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
||||
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
||||
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
||||
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
||||
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
||||
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
||||
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
||||
8 IPL_030_2_ 5 344 1 0 8 -1 10 0 21
|
||||
7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21
|
||||
6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21
|
||||
82 BGACK_030 5 347 7 0 82 -1 3 0 21
|
||||
34 VMA 5 349 3 0 34 -1 3 0 21
|
||||
65 E 0 6 0 65 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 346 3 0 28 -1 2 0 21
|
||||
97 DS_030 0 0 0 97 -1 1 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
80 DSACK1 0 7 0 80 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
347 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
||||
311 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21
|
||||
310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21
|
||||
307 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21
|
||||
322 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21
|
||||
301 inst_BGACK_030_INT_D 3 -1 7 4 1 5 6 7 -1 -1 1 0 21
|
||||
300 inst_AS_030_000_SYNC 3 -1 1 3 1 3 5 -1 -1 7 0 21
|
||||
302 inst_AS_000_DMA 3 -1 0 3 0 3 7 -1 -1 6 0 21
|
||||
295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
||||
293 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
||||
337 SM_AMIGA_i_7_ 3 -1 5 3 1 5 7 -1 -1 3 1 21
|
||||
325 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 3 0 21
|
||||
296 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21
|
||||
338 CLK_OUT_INTreg 3 -1 3 3 0 1 6 -1 -1 1 0 21
|
||||
299 inst_AS_030_D0 3 -1 7 3 1 3 4 -1 -1 1 0 21
|
||||
294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21
|
||||
336 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 5 0 21
|
||||
349 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
||||
334 SM_AMIGA_5_ 3 -1 6 2 0 6 -1 -1 3 0 21
|
||||
324 SM_AMIGA_1_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
||||
323 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21
|
||||
320 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21
|
||||
319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
||||
333 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
||||
332 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21
|
||||
321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
|
||||
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21
|
||||
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
|
||||
313 inst_CLK_OUT_PRE_D 3 -1 4 2 0 3 -1 -1 1 0 21
|
||||
312 inst_CLK_OUT_PRE_50 3 -1 6 2 4 6 -1 -1 1 0 21
|
||||
305 CLK_000_D_3_ 3 -1 5 2 2 5 -1 -1 1 0 21
|
||||
304 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21
|
||||
344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
||||
343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
||||
342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
||||
328 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21
|
||||
303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
||||
308 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21
|
||||
335 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
|
||||
345 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
||||
329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
|
||||
326 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 4 0 21
|
||||
348 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
|
||||
341 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
|
||||
340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
||||
350 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
339 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
||||
330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
|
||||
327 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 2 0 21
|
||||
309 inst_AMIGA_DS 3 -1 2 1 0 -1 -1 2 0 21
|
||||
318 CLK_000_D_4_ 3 -1 2 1 5 -1 -1 1 0 21
|
||||
317 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21
|
||||
316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
314 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
306 inst_DTACK_D0 3 -1 1 1 2 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1
|
||||
95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1
|
||||
94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1
|
||||
58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 1 4 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 1 4 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
2 RESET 1 -1 -1 2 1 2 2 -1
|
||||
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
||||
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
||||
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
||||
63 CLK_030 1 -1 -1 1 0 63 -1
|
||||
59 A_1_ 1 -1 -1 1 5 59 -1
|
||||
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
||||
35 VPA 1 -1 -1 1 5 35 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
10 CLK_000 1 -1 -1 1 3 10 -1
|
||||
125 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
81 AS_030 5 -1 7 6 1 2 3 4 5 7 81 -1 1 0 21
|
||||
41 AS_000 5 -1 4 4 0 4 5 7 41 -1 1 0 21
|
||||
79 RW_000 5 348 7 3 0 4 6 79 -1 4 0 21
|
||||
70 RW 5 355 6 2 5 7 70 -1 2 0 21
|
||||
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
|
||||
78 SIZE_1_ 5 346 7 1 5 78 -1 3 0 21
|
||||
69 SIZE_0_ 5 356 6 1 5 69 -1 3 0 21
|
||||
68 A_0_ 5 349 6 1 5 68 -1 3 0 21
|
||||
40 BERR 5 -1 4 1 2 40 -1 1 0 21
|
||||
29 DTACK 5 -1 3 1 6 29 -1 1 0 21
|
||||
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
||||
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
||||
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
||||
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
||||
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
||||
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
||||
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
||||
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
||||
8 IPL_030_2_ 5 347 1 0 8 -1 10 0 21
|
||||
7 IPL_030_0_ 5 351 1 0 7 -1 10 0 21
|
||||
6 IPL_030_1_ 5 350 1 0 6 -1 10 0 21
|
||||
82 BGACK_030 5 353 7 0 82 -1 3 0 21
|
||||
34 VMA 5 354 3 0 34 -1 3 0 21
|
||||
65 E 0 6 0 65 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 352 3 0 28 -1 2 0 21
|
||||
97 DS_030 0 0 0 97 -1 1 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
80 DSACK1 0 7 0 80 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
353 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
||||
314 CLK_000_D_0_ 3 -1 4 6 0 2 3 5 6 7 -1 -1 1 0 21
|
||||
313 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21
|
||||
310 inst_RESET_OUT 3 -1 0 5 0 3 4 6 7 -1 -1 2 0 21
|
||||
301 inst_BGACK_030_INT_D 3 -1 7 4 0 1 6 7 -1 -1 1 0 21
|
||||
300 inst_AS_030_000_SYNC 3 -1 1 3 1 3 5 -1 -1 7 0 21
|
||||
302 inst_AS_000_DMA 3 -1 0 3 0 3 7 -1 -1 6 0 21
|
||||
295 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21
|
||||
293 cpu_est_3_ 3 -1 6 3 2 3 6 -1 -1 4 0 21
|
||||
343 SM_AMIGA_i_7_ 3 -1 5 3 1 5 7 -1 -1 3 1 21
|
||||
330 SM_AMIGA_0_ 3 -1 6 3 5 6 7 -1 -1 3 0 21
|
||||
294 cpu_est_0_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
||||
344 CLK_OUT_INTreg 3 -1 2 3 0 1 6 -1 -1 1 0 21
|
||||
299 inst_AS_030_D0 3 -1 7 3 1 3 4 -1 -1 1 0 21
|
||||
296 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21
|
||||
342 SM_AMIGA_2_ 3 -1 2 2 2 6 -1 -1 5 0 21
|
||||
337 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 5 0 21
|
||||
331 CYCLE_DMA_0_ 3 -1 5 2 0 5 -1 -1 4 0 21
|
||||
354 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
||||
339 SM_AMIGA_1_ 3 -1 6 2 2 6 -1 -1 3 0 21
|
||||
329 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
||||
328 SM_AMIGA_6_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
||||
326 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
||||
325 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
||||
338 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
||||
332 CYCLE_DMA_1_ 3 -1 5 2 0 5 -1 -1 2 0 21
|
||||
327 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
|
||||
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
|
||||
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
||||
320 CLK_000_D_4_ 3 -1 1 2 1 5 -1 -1 1 0 21
|
||||
315 inst_CLK_OUT_PRE_50 3 -1 3 2 2 3 -1 -1 1 0 21
|
||||
307 CLK_000_D_8_ 3 -1 3 2 2 3 -1 -1 1 0 21
|
||||
306 CLK_000_D_3_ 3 -1 1 2 1 5 -1 -1 1 0 21
|
||||
305 inst_CLK_OUT_PRE_D 3 -1 2 2 0 2 -1 -1 1 0 21
|
||||
304 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21
|
||||
351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
||||
350 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
||||
347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
||||
333 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21
|
||||
303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
||||
311 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21
|
||||
341 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
|
||||
348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
||||
334 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21
|
||||
356 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
|
||||
349 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
||||
346 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
|
||||
340 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21
|
||||
355 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
345 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
336 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
||||
335 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21
|
||||
312 inst_AMIGA_DS 3 -1 7 1 0 -1 -1 2 0 21
|
||||
324 CLK_000_D_10_ 3 -1 2 1 2 -1 -1 1 0 21
|
||||
323 CLK_000_D_7_ 3 -1 6 1 3 -1 -1 1 0 21
|
||||
322 CLK_000_D_6_ 3 -1 3 1 6 -1 -1 1 0 21
|
||||
321 CLK_000_D_5_ 3 -1 1 1 3 -1 -1 1 0 21
|
||||
319 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21
|
||||
318 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
||||
309 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21
|
||||
308 CLK_000_D_9_ 3 -1 3 1 2 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1
|
||||
95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1
|
||||
94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1
|
||||
58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 1 4 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 1 4 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
||||
63 CLK_030 1 -1 -1 2 0 2 63 -1
|
||||
59 A_1_ 1 -1 -1 2 0 6 59 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
2 RESET 1 -1 -1 2 1 2 2 -1
|
||||
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
||||
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
||||
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
||||
35 VPA 1 -1 -1 1 3 35 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
10 CLK_000 1 -1 -1 1 4 10 -1
|
||||
127 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
81 AS_030 5 -1 7 7 0 1 3 4 5 6 7 81 -1 1 0 21
|
||||
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
||||
79 RW_000 5 350 7 3 2 4 6 79 -1 4 0 21
|
||||
70 RW 5 357 6 2 0 7 70 -1 2 0 21
|
||||
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
|
||||
78 SIZE_1_ 5 348 7 1 0 78 -1 3 0 21
|
||||
69 SIZE_0_ 5 358 6 1 0 69 -1 3 0 21
|
||||
68 A_0_ 5 351 6 1 0 68 -1 3 0 21
|
||||
40 BERR 5 -1 4 1 3 40 -1 1 0 21
|
||||
29 DTACK 5 -1 3 1 2 29 -1 1 0 21
|
||||
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
||||
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
||||
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
||||
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
||||
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
||||
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
||||
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
||||
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
||||
8 IPL_030_2_ 5 349 1 0 8 -1 10 0 21
|
||||
7 IPL_030_0_ 5 355 1 0 7 -1 10 0 21
|
||||
6 IPL_030_1_ 5 353 1 0 6 -1 10 0 21
|
||||
82 BGACK_030 5 354 7 0 82 -1 3 0 21
|
||||
34 VMA 5 356 3 0 34 -1 3 0 21
|
||||
65 E 0 6 0 65 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 352 3 0 28 -1 2 0 21
|
||||
97 DS_030 0 0 0 97 -1 1 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
80 DSACK1 0 7 0 80 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
354 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
||||
314 CLK_000_D_0_ 3 -1 2 6 0 1 3 5 6 7 -1 -1 1 0 21
|
||||
313 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21
|
||||
310 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21
|
||||
300 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 7 0 21
|
||||
302 inst_AS_000_DMA 3 -1 2 3 2 3 7 -1 -1 6 0 21
|
||||
345 SM_AMIGA_i_7_ 3 -1 0 3 0 5 7 -1 -1 3 1 21
|
||||
332 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 3 0 21
|
||||
330 SM_AMIGA_6_ 3 -1 0 3 0 6 7 -1 -1 3 0 21
|
||||
346 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21
|
||||
305 inst_CLK_OUT_PRE_D 3 -1 6 3 1 2 6 -1 -1 1 0 21
|
||||
301 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21
|
||||
299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21
|
||||
303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
||||
344 SM_AMIGA_2_ 3 -1 3 2 1 3 -1 -1 5 0 21
|
||||
339 inst_DSACK1_INT 3 -1 1 2 1 7 -1 -1 5 0 21
|
||||
333 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21
|
||||
295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21
|
||||
293 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21
|
||||
342 SM_AMIGA_5_ 3 -1 7 2 0 7 -1 -1 3 0 21
|
||||
341 SM_AMIGA_1_ 3 -1 1 2 1 5 -1 -1 3 0 21
|
||||
331 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21
|
||||
328 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21
|
||||
327 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
||||
294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 3 0 21
|
||||
340 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
|
||||
334 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 2 0 21
|
||||
329 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
||||
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21
|
||||
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
|
||||
315 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21
|
||||
306 CLK_000_D_3_ 3 -1 1 2 0 5 -1 -1 1 0 21
|
||||
296 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21
|
||||
355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
||||
353 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
||||
349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
||||
335 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21
|
||||
311 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21
|
||||
343 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21
|
||||
350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
||||
336 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
|
||||
358 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
|
||||
356 RN_VMA 3 34 3 1 3 34 -1 3 0 21
|
||||
351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
||||
348 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
|
||||
357 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
347 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
338 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
||||
337 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
|
||||
312 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21
|
||||
326 CLK_000_D_12_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
325 CLK_000_D_9_ 3 -1 5 1 2 -1 -1 1 0 21
|
||||
324 CLK_000_D_8_ 3 -1 2 1 5 -1 -1 1 0 21
|
||||
323 CLK_000_D_7_ 3 -1 1 1 2 -1 -1 1 0 21
|
||||
322 CLK_000_D_6_ 3 -1 6 1 1 -1 -1 1 0 21
|
||||
321 CLK_000_D_5_ 3 -1 0 1 6 -1 -1 1 0 21
|
||||
320 CLK_000_D_4_ 3 -1 5 1 0 -1 -1 1 0 21
|
||||
319 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21
|
||||
318 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
||||
317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
316 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21
|
||||
309 inst_DTACK_D0 3 -1 2 1 3 -1 -1 1 0 21
|
||||
308 CLK_000_D_11_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
307 CLK_000_D_10_ 3 -1 2 1 1 -1 -1 1 0 21
|
||||
304 inst_VPA_D 3 -1 3 1 3 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
||||
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
||||
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
|
||||
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
|
||||
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
|
||||
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
67 IPL_2_ 1 -1 -1 2 1 5 67 -1
|
||||
66 IPL_0_ 1 -1 -1 2 1 5 66 -1
|
||||
63 CLK_030 1 -1 -1 2 1 2 63 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
2 RESET 1 -1 -1 2 1 2 2 -1
|
||||
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
||||
59 A_1_ 1 -1 -1 1 5 59 -1
|
||||
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
||||
35 VPA 1 -1 -1 1 3 35 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
10 CLK_000 1 -1 -1 1 2 10 -1
|
||||
126 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
81 AS_030 5 -1 7 6 0 2 3 4 5 7 81 -1 1 0 21
|
||||
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
||||
79 RW_000 5 349 7 3 2 4 6 79 -1 4 0 21
|
||||
70 RW 5 356 6 2 0 7 70 -1 2 0 21
|
||||
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
|
||||
78 SIZE_1_ 5 347 7 1 3 78 -1 3 0 21
|
||||
69 SIZE_0_ 5 357 6 1 3 69 -1 3 0 21
|
||||
68 A_0_ 5 350 6 1 3 68 -1 3 0 21
|
||||
40 BERR 5 -1 4 1 0 40 -1 1 0 21
|
||||
29 DTACK 5 -1 3 1 2 29 -1 1 0 21
|
||||
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
||||
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
||||
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
||||
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
||||
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
||||
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
||||
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
||||
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
||||
8 IPL_030_2_ 5 348 1 0 8 -1 10 0 21
|
||||
7 IPL_030_0_ 5 353 1 0 7 -1 10 0 21
|
||||
6 IPL_030_1_ 5 351 1 0 6 -1 10 0 21
|
||||
82 BGACK_030 5 354 7 0 82 -1 3 0 21
|
||||
34 VMA 5 355 3 0 34 -1 3 0 21
|
||||
65 E 0 6 0 65 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 352 3 0 28 -1 2 0 21
|
||||
97 DS_030 0 0 0 97 -1 1 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
80 DSACK1 0 7 0 80 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
354 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
||||
314 CLK_000_D_0_ 3 -1 6 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
||||
313 CLK_000_D_1_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21
|
||||
310 inst_RESET_OUT 3 -1 5 6 0 3 4 5 6 7 -1 -1 2 0 21
|
||||
329 SM_AMIGA_6_ 3 -1 1 4 0 1 3 7 -1 -1 3 0 21
|
||||
300 inst_AS_030_000_SYNC 3 -1 5 3 1 3 5 -1 -1 7 0 21
|
||||
302 inst_AS_000_DMA 3 -1 2 3 2 3 7 -1 -1 6 0 21
|
||||
295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
|
||||
293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
|
||||
344 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21
|
||||
340 SM_AMIGA_1_ 3 -1 6 3 2 6 7 -1 -1 3 0 21
|
||||
345 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21
|
||||
301 inst_BGACK_030_INT_D 3 -1 7 3 5 6 7 -1 -1 1 0 21
|
||||
299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21
|
||||
296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21
|
||||
303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
||||
343 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21
|
||||
338 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 5 0 21
|
||||
332 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 4 0 21
|
||||
355 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
|
||||
331 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21
|
||||
327 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21
|
||||
294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
|
||||
339 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
||||
333 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21
|
||||
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
||||
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
||||
320 CLK_000_D_4_ 3 -1 5 2 0 1 -1 -1 1 0 21
|
||||
315 inst_CLK_OUT_PRE_50 3 -1 0 2 0 1 -1 -1 1 0 21
|
||||
308 CLK_000_D_10_ 3 -1 5 2 2 5 -1 -1 1 0 21
|
||||
307 CLK_000_D_9_ 3 -1 2 2 2 5 -1 -1 1 0 21
|
||||
306 CLK_000_D_3_ 3 -1 3 2 1 5 -1 -1 1 0 21
|
||||
305 inst_CLK_OUT_PRE_D 3 -1 1 2 2 6 -1 -1 1 0 21
|
||||
304 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21
|
||||
353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
||||
351 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
||||
348 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
||||
334 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21
|
||||
311 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21
|
||||
342 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21
|
||||
349 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
||||
335 RST_DLY_0_ 3 -1 5 1 5 -1 -1 4 0 21
|
||||
357 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
|
||||
350 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
||||
347 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
|
||||
341 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21
|
||||
330 SM_AMIGA_4_ 3 -1 0 1 0 -1 -1 3 0 21
|
||||
326 inst_LDS_000_INT 3 -1 3 1 3 -1 -1 3 0 21
|
||||
356 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
346 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
337 RST_DLY_2_ 3 -1 5 1 5 -1 -1 2 0 21
|
||||
336 RST_DLY_1_ 3 -1 5 1 5 -1 -1 2 1 21
|
||||
328 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21
|
||||
312 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21
|
||||
325 CLK_000_D_11_ 3 -1 5 1 2 -1 -1 1 0 21
|
||||
324 CLK_000_D_8_ 3 -1 6 1 2 -1 -1 1 0 21
|
||||
323 CLK_000_D_7_ 3 -1 5 1 6 -1 -1 1 0 21
|
||||
322 CLK_000_D_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
||||
321 CLK_000_D_5_ 3 -1 0 1 6 -1 -1 1 0 21
|
||||
319 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21
|
||||
318 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
||||
317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
||||
309 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
|
||||
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
|
||||
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
|
||||
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
67 IPL_2_ 1 -1 -1 2 1 5 67 -1
|
||||
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
2 RESET 1 -1 -1 2 1 2 2 -1
|
||||
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
||||
63 CLK_030 1 -1 -1 1 2 63 -1
|
||||
59 A_1_ 1 -1 -1 1 6 59 -1
|
||||
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
||||
35 VPA 1 -1 -1 1 6 35 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
10 CLK_000 1 -1 -1 1 6 10 -1
|
||||
127 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
81 AS_030 5 -1 7 7 0 1 3 4 5 6 7 81 -1 1 0 21
|
||||
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
||||
79 RW_000 5 350 7 3 2 4 6 79 -1 4 0 21
|
||||
70 RW 5 357 6 2 0 7 70 -1 2 0 21
|
||||
31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21
|
||||
78 SIZE_1_ 5 348 7 1 0 78 -1 3 0 21
|
||||
69 SIZE_0_ 5 358 6 1 0 69 -1 3 0 21
|
||||
68 A_0_ 5 351 6 1 0 68 -1 3 0 21
|
||||
40 BERR 5 -1 4 1 3 40 -1 1 0 21
|
||||
29 DTACK 5 -1 3 1 2 29 -1 1 0 21
|
||||
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
||||
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
||||
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
||||
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
||||
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
||||
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
||||
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
||||
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
||||
8 IPL_030_2_ 5 349 1 0 8 -1 10 0 21
|
||||
7 IPL_030_0_ 5 355 1 0 7 -1 10 0 21
|
||||
6 IPL_030_1_ 5 353 1 0 6 -1 10 0 21
|
||||
82 BGACK_030 5 354 7 0 82 -1 3 0 21
|
||||
34 VMA 5 356 3 0 34 -1 3 0 21
|
||||
65 E 0 6 0 65 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 352 3 0 28 -1 2 0 21
|
||||
97 DS_030 0 0 0 97 -1 1 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
80 DSACK1 0 7 0 80 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
354 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
||||
314 CLK_000_D_0_ 3 -1 2 6 0 1 3 5 6 7 -1 -1 1 0 21
|
||||
313 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21
|
||||
310 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21
|
||||
300 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 7 0 21
|
||||
302 inst_AS_000_DMA 3 -1 2 3 2 3 7 -1 -1 6 0 21
|
||||
345 SM_AMIGA_i_7_ 3 -1 0 3 0 5 7 -1 -1 3 1 21
|
||||
332 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 3 0 21
|
||||
330 SM_AMIGA_6_ 3 -1 0 3 0 6 7 -1 -1 3 0 21
|
||||
346 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21
|
||||
305 inst_CLK_OUT_PRE_D 3 -1 6 3 1 2 6 -1 -1 1 0 21
|
||||
301 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21
|
||||
299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21
|
||||
303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
||||
344 SM_AMIGA_2_ 3 -1 3 2 1 3 -1 -1 5 0 21
|
||||
339 inst_DSACK1_INT 3 -1 1 2 1 7 -1 -1 5 0 21
|
||||
333 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21
|
||||
295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21
|
||||
293 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21
|
||||
342 SM_AMIGA_5_ 3 -1 7 2 0 7 -1 -1 3 0 21
|
||||
341 SM_AMIGA_1_ 3 -1 1 2 1 5 -1 -1 3 0 21
|
||||
331 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21
|
||||
328 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21
|
||||
327 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
||||
294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 3 0 21
|
||||
340 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
|
||||
334 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 2 0 21
|
||||
329 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
||||
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21
|
||||
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
|
||||
315 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21
|
||||
306 CLK_000_D_3_ 3 -1 1 2 0 5 -1 -1 1 0 21
|
||||
296 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21
|
||||
355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
||||
353 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
||||
349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
||||
335 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21
|
||||
311 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21
|
||||
343 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21
|
||||
350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
||||
336 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
|
||||
358 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
|
||||
356 RN_VMA 3 34 3 1 3 34 -1 3 0 21
|
||||
351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
||||
348 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
|
||||
357 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
347 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
338 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
||||
337 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
|
||||
312 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21
|
||||
326 CLK_000_D_12_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
325 CLK_000_D_9_ 3 -1 5 1 2 -1 -1 1 0 21
|
||||
324 CLK_000_D_8_ 3 -1 2 1 5 -1 -1 1 0 21
|
||||
323 CLK_000_D_7_ 3 -1 1 1 2 -1 -1 1 0 21
|
||||
322 CLK_000_D_6_ 3 -1 6 1 1 -1 -1 1 0 21
|
||||
321 CLK_000_D_5_ 3 -1 0 1 6 -1 -1 1 0 21
|
||||
320 CLK_000_D_4_ 3 -1 5 1 0 -1 -1 1 0 21
|
||||
319 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21
|
||||
318 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
||||
317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
316 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21
|
||||
309 inst_DTACK_D0 3 -1 2 1 3 -1 -1 1 0 21
|
||||
308 CLK_000_D_11_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
307 CLK_000_D_10_ 3 -1 2 1 1 -1 -1 1 0 21
|
||||
304 inst_VPA_D 3 -1 3 1 3 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
||||
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
||||
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
|
||||
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
|
||||
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
|
||||
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
67 IPL_2_ 1 -1 -1 2 1 5 67 -1
|
||||
66 IPL_0_ 1 -1 -1 2 1 5 66 -1
|
||||
63 CLK_030 1 -1 -1 2 1 2 63 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
2 RESET 1 -1 -1 2 1 2 2 -1
|
||||
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
||||
59 A_1_ 1 -1 -1 1 5 59 -1
|
||||
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
||||
35 VPA 1 -1 -1 1 3 35 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
10 CLK_000 1 -1 -1 1 2 10 -1
|
||||
119 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
81 AS_030 5 -1 7 6 0 1 2 3 4 7 81 -1 1 0 21
|
||||
79 RW_000 5 345 7 3 0 4 6 79 -1 4 0 21
|
||||
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
||||
31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21
|
||||
70 RW 5 350 6 2 2 7 70 -1 2 0 21
|
||||
78 SIZE_1_ 5 341 7 1 5 78 -1 3 0 21
|
||||
69 SIZE_0_ 5 348 6 1 5 69 -1 3 0 21
|
||||
68 A_0_ 5 340 6 1 5 68 -1 3 0 21
|
||||
40 BERR 5 -1 4 1 2 40 -1 1 0 21
|
||||
29 DTACK 5 -1 3 1 1 29 -1 1 0 21
|
||||
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
||||
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
||||
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
||||
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
||||
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
||||
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
||||
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
||||
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
||||
8 IPL_030_2_ 5 344 1 0 8 -1 10 0 21
|
||||
7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21
|
||||
6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21
|
||||
82 BGACK_030 5 347 7 0 82 -1 3 0 21
|
||||
34 VMA 5 349 3 0 34 -1 3 0 21
|
||||
65 E 0 6 0 65 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 346 3 0 28 -1 2 0 21
|
||||
97 DS_030 0 0 0 97 -1 1 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
80 DSACK1 0 7 0 80 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
347 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
||||
311 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21
|
||||
310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21
|
||||
307 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21
|
||||
322 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21
|
||||
301 inst_BGACK_030_INT_D 3 -1 7 4 1 5 6 7 -1 -1 1 0 21
|
||||
300 inst_AS_030_000_SYNC 3 -1 1 3 1 3 5 -1 -1 7 0 21
|
||||
302 inst_AS_000_DMA 3 -1 0 3 0 3 7 -1 -1 6 0 21
|
||||
295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
||||
293 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
||||
337 SM_AMIGA_i_7_ 3 -1 5 3 1 5 7 -1 -1 3 1 21
|
||||
325 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 3 0 21
|
||||
296 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21
|
||||
338 CLK_OUT_INTreg 3 -1 3 3 0 1 6 -1 -1 1 0 21
|
||||
299 inst_AS_030_D0 3 -1 7 3 1 3 4 -1 -1 1 0 21
|
||||
294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21
|
||||
336 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 5 0 21
|
||||
349 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
||||
334 SM_AMIGA_5_ 3 -1 6 2 0 6 -1 -1 3 0 21
|
||||
324 SM_AMIGA_1_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
||||
323 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21
|
||||
320 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21
|
||||
319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
||||
333 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
||||
332 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21
|
||||
321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
|
||||
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21
|
||||
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
|
||||
313 inst_CLK_OUT_PRE_D 3 -1 4 2 0 3 -1 -1 1 0 21
|
||||
312 inst_CLK_OUT_PRE_50 3 -1 6 2 4 6 -1 -1 1 0 21
|
||||
305 CLK_000_D_3_ 3 -1 5 2 2 5 -1 -1 1 0 21
|
||||
304 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21
|
||||
344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
||||
343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
||||
342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
||||
328 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21
|
||||
303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
||||
308 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21
|
||||
335 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
|
||||
345 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
||||
329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
|
||||
326 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 4 0 21
|
||||
348 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
|
||||
341 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
|
||||
340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
||||
350 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
339 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
||||
330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
|
||||
327 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 2 0 21
|
||||
309 inst_AMIGA_DS 3 -1 2 1 0 -1 -1 2 0 21
|
||||
318 CLK_000_D_4_ 3 -1 2 1 5 -1 -1 1 0 21
|
||||
317 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21
|
||||
316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
314 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
306 inst_DTACK_D0 3 -1 1 1 2 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
; Source file 68030_tk.tt4
|
||||
; FITTER-generated Placements.
|
||||
; DEVICE mach447a
|
||||
; DATE Fri Nov 18 19:32:41 2016
|
||||
; DATE Thu Dec 29 16:02:00 2016
|
||||
|
||||
|
||||
Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@
|
|||
|--------------------------------------------|
|
||||
|
||||
|
||||
Start: Fri Nov 18 19:32:40 2016
|
||||
End : Fri Nov 18 19:32:41 2016 $$$ Elapsed time: 00:00:01
|
||||
Start: Thu Dec 29 16:02:00 2016
|
||||
End : Thu Dec 29 16:02:00 2016 $$$ Elapsed time: 00:00:00
|
||||
===========================================================================
|
||||
Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4]
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ Project_Summary
|
|||
|
||||
Project Name : 68030_tk
|
||||
Project Path : C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic
|
||||
Project Fitted on : Fri Nov 18 19:32:41 2016
|
||||
Project Fitted on : Thu Dec 29 16:02:00 2016
|
||||
|
||||
Device : M4A5-128/64
|
||||
Package : 100TQFP
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
|
||||
#$ DATE Fri Nov 18 19:32:36 2016
|
||||
#$ DATE Thu Dec 29 16:01:56 2016
|
||||
#$ MODULE 68030_tk
|
||||
#$ PINS 61 AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E AHIGH_30_ VPA AHIGH_29_ AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ AHIGH_25_ AMIGA_ADDR_ENABLE AHIGH_24_ AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_ AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ IPL_030_2_ RW_000 BG_000 BGACK_030 SIZE_0_ VMA RW
|
||||
#$ NODES 46 cpu_est_1_ cpu_est_2_ cpu_est_3_ cpu_est_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_030_PE_1_ inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ CLK_030_PE_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CLK_OUT_INTreg
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
|
||||
#$ DATE Fri Nov 18 19:32:36 2016
|
||||
#$ DATE Thu Dec 29 16:01:56 2016
|
||||
#$ MODULE 68030_tk
|
||||
#$ PINS 61 AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E AHIGH_30_ VPA AHIGH_29_ AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ AHIGH_25_ AMIGA_ADDR_ENABLE AHIGH_24_ AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_ AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ IPL_030_2_ RW_000 BG_000 BGACK_030 SIZE_0_ VMA RW
|
||||
#$ NODES 46 cpu_est_1_ cpu_est_2_ cpu_est_3_ cpu_est_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_030_PE_1_ inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ CLK_030_PE_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CLK_OUT_INTreg
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
|
||||
#$ DATE Fri Nov 18 19:32:36 2016
|
||||
#$ DATE Thu Dec 29 16:01:56 2016
|
||||
#$ MODULE BUS68030
|
||||
#$ PINS 61 AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_2_ FC_1_ AS_030
|
||||
AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
|
||||
#$ DATE Fri Nov 18 19:32:36 2016
|
||||
#$ DATE Thu Dec 29 16:01:56 2016
|
||||
#$ MODULE BUS68030
|
||||
#$ PINS 61 AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_2_ FC_1_ AS_030
|
||||
AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000
|
||||
|
|
|
|||
|
|
@ -17,8 +17,8 @@ Parent = m4a5.lci;
|
|||
SDS_file = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
Rev = 0.01;
|
||||
DATE = 11/18/16;
|
||||
TIME = 19:32:40;
|
||||
DATE = 12/29/16;
|
||||
TIME = 16:02:00;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
Source_Format = Pure_VHDL;
|
||||
|
|
|
|||
|
|
@ -17,8 +17,8 @@ Parent = m4a5.lci;
|
|||
SDS_file = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
Rev = 0.01;
|
||||
DATE = 11/18/16;
|
||||
TIME = 19:32:41;
|
||||
DATE = 12/29/16;
|
||||
TIME = 16:02:00;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
Source_Format = Pure_VHDL;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Signal Name Cross Reference File
|
|||
|
||||
ispLEVER Classic 2.0.00.17.20.15
|
||||
|
||||
Design '68030_tk' created Fri Nov 18 19:32:36 2016
|
||||
Design '68030_tk' created Thu Dec 29 16:01:56 2016
|
||||
|
||||
|
||||
LEGEND: '>' Functional Block Port Separator
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,4 +1,4 @@
|
|||
#$ DATE Fri Nov 18 19:32:36 2016
|
||||
#$ DATE Thu Dec 29 16:01:56 2016
|
||||
#$ TOOL EDIF2BLIF version IspLever 1.0
|
||||
#$ MODULE bus68030
|
||||
#$ PINS 75 A_DECODE_2_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC SIZE_0_ E AHIGH_30_ VPA AHIGH_29_ VMA AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ RW AHIGH_25_ AMIGA_ADDR_ENABLE AHIGH_24_ AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_ AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ A_DECODE_15_ A_DECODE_14_ A_DECODE_13_ A_DECODE_12_ A_DECODE_11_ A_DECODE_10_ A_DECODE_9_ A_DECODE_8_ A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ A_DECODE_3_
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
|
||||
#$ DATE Fri Nov 18 19:32:36 2016
|
||||
#$ DATE Thu Dec 29 16:01:56 2016
|
||||
#$ MODULE bus68030
|
||||
#$ PINS 75 A_DECODE_2_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ AHIGH_31_ IPL_1_ IPL_0_ \
|
||||
# A_DECODE_23_ FC_0_ A_1_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 \
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timeStamp 2016 11 18 19 32 31)
|
||||
(timeStamp 2016 12 29 16 1 51)
|
||||
(author "Synopsys, Inc.")
|
||||
(program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R"))
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#-- Lattice Semiconductor Corporation Ltd.
|
||||
#-- Synplify OEM project file c:/users/matze/amiga/hardwarehacks/68030-tk/github/logic\BUS68030.prj
|
||||
#-- Written on Fri Nov 18 19:32:22 2016
|
||||
#-- Written on Thu Dec 29 16:01:42 2016
|
||||
|
||||
|
||||
#device options
|
||||
|
|
|
|||
|
|
@ -188,8 +188,8 @@ RNP3ONsEDVHC;R(
|
|||
RNP38lFkVDCHRDC(N;
|
||||
P#R3$VM_lRNb"sIF "R\B\:\ks#C#l\\NC0x\l\NH\oN\sEN8sINCOEN \#\ndUjj -0\H\o0LEk\F\Do\HO\jnUdnj-Ujjj-#Lk38PE\M"\"N;
|
||||
POR3DMCNk#b_0.Cb_l0HC3Rjj.d46;jj
|
||||
RNP3CODNbMk_C#0b04_HRlCjj3jjjjj;P
|
||||
NR03#lH0D#H00ljCR36j4nj.6;P
|
||||
RNP3CODNbMk_C#0b04_HRlCj43j66n.jN;
|
||||
P#R30Dl0H0#0HRlCjj3jjjjj;P
|
||||
NRHFsoM_H#F0_VAR"zU1nj"dj;P
|
||||
NRs3FHNohl"CRAnz1Ujjd"N;
|
||||
P#R3$lM_#_s##HC08;Rj
|
||||
|
|
@ -202,7 +202,7 @@ j;}N;
|
|||
P$R#M#_HlCHG8MDNo;R4
|
||||
RNP3M#$_#lV_FoskHb_8;Rj
|
||||
RNP3M#$_lMkOsEN#4RU4
|
||||
.;N3PR#_$MD HMC8sHRj"{jnn(n-UUnjjj-Ucnwj-qnBj-c6j6gd Ag}(d"N;
|
||||
.;N3PR#_$MD HMC8sHR6"{jBw.7- qgcg6-(cg g-q 7j-(A476g(dd}Bc"N;
|
||||
POR38#L_NRPC{P
|
||||
NRM#$_VsCCMsCOOC_D FORN{
|
||||
P$R1#l0CRN{
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#Implementation: logic
|
||||
|
||||
$ Start of Compile
|
||||
#Fri Nov 18 19:32:29 2016
|
||||
#Thu Dec 29 16:01:49 2016
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
|
|
@ -49,7 +49,7 @@ State machine has 8 reachable states with original encodings of:
|
|||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Nov 18 19:32:29 2016
|
||||
# Thu Dec 29 16:01:49 2016
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
|
|
@ -59,7 +59,7 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c
|
|||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Nov 18 19:32:31 2016
|
||||
# Thu Dec 29 16:01:50 2016
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
|
@ -101,6 +101,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Nov 18 19:32:31 2016
|
||||
# Thu Dec 29 16:01:51 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,6 +1,6 @@
|
|||
<?xml version='1.0' encoding='utf-8' ?>
|
||||
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
|
||||
<ispXCF version="18.0.3">
|
||||
<ispXCF version="18.1">
|
||||
<Comment></Comment>
|
||||
<Chain>
|
||||
<Comm>JTAG</Comm>
|
||||
|
|
@ -19,14 +19,15 @@
|
|||
<BScanVal>0</BScanVal>
|
||||
</Bypass>
|
||||
<File>C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic\68030_tk.jed</File>
|
||||
<FileTime>10/15/16 23:48:29</FileTime>
|
||||
<JedecChecksum>0x1315</JedecChecksum>
|
||||
<FileTime>12/29/16 15:52:11</FileTime>
|
||||
<JedecChecksum>0x82ED</JedecChecksum>
|
||||
<Operation>Erase,Program,Verify</Operation>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
<IOState>HighZ</IOState>
|
||||
<PreloadLength>198</PreloadLength>
|
||||
<IOVectorData>0x00000000000000000000000000000000000000000000000000</IOVectorData>
|
||||
<Reinitialize value="TRUE"/>
|
||||
<OverideUES value="TRUE"/>
|
||||
<TCKFrequency>1.000000 MHz</TCKFrequency>
|
||||
<SVFProcessor>ispVM</SVFProcessor>
|
||||
|
|
@ -49,6 +50,7 @@
|
|||
TDO LOW;
|
||||
CableEN HIGH;
|
||||
ISPEN LOW;
|
||||
TRST HIGH;
|
||||
</PinSetting>
|
||||
</ProjectOptions>
|
||||
</ispXCF>
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ Section Member Rename Array-Notation Array Number
|
|||
Port FC_0_ FC[0] 3 1
|
||||
End
|
||||
Section Cross Reference File
|
||||
Design 'BUS68030' created Fri Nov 18 19:32:36 2016
|
||||
Design 'BUS68030' created Thu Dec 29 16:01:56 2016
|
||||
Type New Name Original Name
|
||||
// ----------------------------------------------------------------------
|
||||
Inst i_z3939 AS_030
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#Implementation: logic
|
||||
|
||||
$ Start of Compile
|
||||
#Fri Nov 18 19:32:29 2016
|
||||
#Thu Dec 29 16:01:49 2016
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
|
|
@ -49,7 +49,7 @@ State machine has 8 reachable states with original encodings of:
|
|||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Nov 18 19:32:29 2016
|
||||
# Thu Dec 29 16:01:49 2016
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
|
|
@ -59,6 +59,48 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c
|
|||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Nov 18 19:32:31 2016
|
||||
# Thu Dec 29 16:01:50 2016
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
|
||||
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
||||
Product Version I-2014.03LC
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N:"c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
|
||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||
original code -> new code
|
||||
000 -> 00000000
|
||||
001 -> 00000011
|
||||
010 -> 00000101
|
||||
011 -> 00001001
|
||||
100 -> 00010001
|
||||
101 -> 00100001
|
||||
110 -> 01000001
|
||||
111 -> 10000001
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
|
||||
Simple gate primitives:
|
||||
DFF 57 uses
|
||||
BI_DIR 19 uses
|
||||
BUFTH 3 uses
|
||||
IBUF 38 uses
|
||||
OBUF 15 uses
|
||||
AND2 277 uses
|
||||
INV 236 uses
|
||||
OR2 23 uses
|
||||
XOR2 8 uses
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
I-2014.03LC
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Dec 29 16:01:51 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -27,8 +27,8 @@ SR<WN(=""DRL=d"4"ORL=""(R=CD""4dR=CO""4cR
|
|||
/>SqS<R"M=3ONsEDVHCP"R=""(/S>
|
||||
SR<qM3="lkF8DHCVDRC"P(=""
|
||||
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jd3j4j.6"
|
||||
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=jj3jjjjj"
|
||||
/>SqS<R"M=3l#00#DH0l0HCP"R=3"jjn46./6">S
|
||||
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=j43j66n."
|
||||
/>SqS<R"M=3l#00#DH0l0HCP"R=3"jjjjjj/j">S
|
||||
S<MqR=s"FHHo_M_#0FRV"P&="J0kF;1AzndUjjk&JF"0;/S>
|
||||
SR<qM3="FosHhCNl"=RP"k&JFA0;zU1nj&djJ0kF;>"/
|
||||
/S<7>CV
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#-- Synopsys, Inc.
|
||||
#-- Version I-2014.03LC
|
||||
#-- Project file C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\run_options.txt
|
||||
#-- Written on Fri Nov 18 19:32:29 2016
|
||||
#-- Written on Thu Dec 29 16:01:49 2016
|
||||
|
||||
|
||||
#project files
|
||||
|
|
|
|||
|
|
@ -5,6 +5,6 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c
|
|||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Nov 18 19:32:31 2016
|
||||
# Thu Dec 29 16:01:50 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -35,6 +35,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Nov 18 19:32:31 2016
|
||||
# Thu Dec 29 16:01:51 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
<data>-</data>
|
||||
</info>
|
||||
<info name="Date &Time">
|
||||
<data type="timestamp">1479493949</data>
|
||||
<data type="timestamp">1483023709</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the
|
|||
<data>105MB</data>
|
||||
</info>
|
||||
<info name="Date & Time">
|
||||
<data type="timestamp">1479493951</data>
|
||||
<data type="timestamp">1483023711</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
<html><body><samp><pre>
|
||||
<!@TC:1479493949>
|
||||
<!@TC:1483023709>
|
||||
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
|
||||
#install: E:\ispLEVER_Classic2_0\synpbase
|
||||
#OS: Windows 7 6.2
|
||||
|
|
@ -8,32 +8,32 @@
|
|||
#Implementation: logic
|
||||
|
||||
<a name=compilerReport1>$ Start of Compile</a>
|
||||
#Fri Nov 18 19:32:29 2016
|
||||
#Thu Dec 29 16:01:49 2016
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N: : <!@TM:1479493949> | Running in 64-bit mode
|
||||
@N: : <!@TM:1483023709> | Running in 64-bit mode
|
||||
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
|
||||
|
||||
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1479493949> | Setting time resolution to ns
|
||||
@N: : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1479493949> | Top entity is set to BUS68030.
|
||||
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1483023709> | Setting time resolution to ns
|
||||
@N: : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1483023709> | Top entity is set to BUS68030.
|
||||
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
|
||||
VHDL syntax check successful!
|
||||
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1479493949> | Synthesizing work.bus68030.behavioral
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:70:10:70:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(70)</a><!@TM:1479493949> | Using sequential encoding for type sm_e
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:87:14:87:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(87)</a><!@TM:1479493949> | Using sequential encoding for type sm_68000
|
||||
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:129:7:129:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(129)</a><!@TM:1479493949> | Signal clk_out_pre is undriven </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:133:7:133:16:@W:CD638:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1479493949> | Signal clk_030_h is undriven </font>
|
||||
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1483023709> | Synthesizing work.bus68030.behavioral
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:70:10:70:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(70)</a><!@TM:1483023709> | Using sequential encoding for type sm_e
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:87:14:87:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(87)</a><!@TM:1483023709> | Using sequential encoding for type sm_68000
|
||||
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:129:7:129:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(129)</a><!@TM:1483023709> | Signal clk_out_pre is undriven </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:133:7:133:16:@W:CD638:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1483023709> | Signal clk_030_h is undriven </font>
|
||||
Post processing for work.bus68030.behavioral
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493949> | Pruning register AS_000_D0_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493949> | Pruning register DS_030_D0_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493949> | Pruning register nEXP_SPACE_D0_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493949> | Pruning register BGACK_030_INT_PRE_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1479493949> | Pruning register CLK_OUT_EXP_INT_1 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:127:36:127:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(127)</a><!@TM:1479493949> | Pruning register CLK_OUT_PRE_25_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:156:2:156:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(156)</a><!@TM:1479493949> | Pruning register CLK_030_D0_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL271:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493949> | Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ... </font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493949> | Trying to extract state machine for register SM_AMIGA
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1483023709> | Pruning register AS_000_D0_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1483023709> | Pruning register DS_030_D0_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1483023709> | Pruning register nEXP_SPACE_D0_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1483023709> | Pruning register BGACK_030_INT_PRE_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1483023709> | Pruning register CLK_OUT_EXP_INT_1 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:127:36:127:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(127)</a><!@TM:1483023709> | Pruning register CLK_OUT_PRE_25_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:156:2:156:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(156)</a><!@TM:1483023709> | Pruning register CLK_030_D0_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@W:CL271:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1483023709> | Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ... </font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1483023709> | Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
State machine has 8 reachable states with original encodings of:
|
||||
000
|
||||
|
|
@ -44,24 +44,24 @@ State machine has 8 reachable states with original encodings of:
|
|||
101
|
||||
110
|
||||
111
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493949> | Trying to extract state machine for register cpu_est
|
||||
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:24:1:24:9:@W:CL246:@XP_MSG">68030-68000-bus.vhd(24)</a><!@TM:1479493949> | Input port bits 15 to 2 of a_decode(23 downto 2) are unused </font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1483023709> | Trying to extract state machine for register cpu_est
|
||||
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:24:1:24:9:@W:CL246:@XP_MSG">68030-68000-bus.vhd(24)</a><!@TM:1483023709> | Input port bits 15 to 2 of a_decode(23 downto 2) are unused </font>
|
||||
@END
|
||||
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Nov 18 19:32:29 2016
|
||||
# Thu Dec 29 16:01:49 2016
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N: : <!@TM:1479493951> | Running in 64-bit mode
|
||||
@N: : <!@TM:1483023710> | Running in 64-bit mode
|
||||
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Nov 18 19:32:31 2016
|
||||
# Thu Dec 29 16:01:50 2016
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
|
@ -69,8 +69,8 @@ Map & Optimize Report
|
|||
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
|
||||
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
||||
Product Version I-2014.03LC
|
||||
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1479493951> | Running in 64-bit mode.
|
||||
@N: : <a href="c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@N::@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1479493951> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
|
||||
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1483023711> | Running in 64-bit mode.
|
||||
@N: : <a href="c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:132:38:132:41:@N::@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1483023711> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
|
||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||
original code -> new code
|
||||
000 -> 00000000
|
||||
|
|
@ -96,14 +96,14 @@ OR2 23 uses
|
|||
XOR2 8 uses
|
||||
|
||||
|
||||
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1479493951> | Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1483023711> | Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
I-2014.03LC
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Nov 18 19:32:31 2016
|
||||
# Thu Dec 29 16:01:51 2016
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
|
||||
<ul rel="open" >
|
||||
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
|
||||
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\stdout.log" target="srrFrame" title="">Session Log (19:32 18-Nov)</a>
|
||||
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\stdout.log" target="srrFrame" title="">Session Log (16:01 29-Dec)</a>
|
||||
<ul ></ul></li> </ul>
|
||||
</li>
|
||||
</ul>
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
Synopsys, Inc.
|
||||
Version I-2014.03LC
|
||||
Project file C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\run_option.xml
|
||||
Written on Fri Nov 18 19:32:29 2016
|
||||
Written on Thu Dec 29 16:01:49 2016
|
||||
|
||||
|
||||
-->
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
<td>-</td>
|
||||
<td>0m:00s</td>
|
||||
<td>-</td>
|
||||
<td><font size="-1">18.11.2016</font><br/><font size="-2">19:32:29</font></td>
|
||||
<td><font size="-1">29.12.2016</font><br/><font size="-2">16:01:49</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
|
|
@ -49,12 +49,12 @@
|
|||
<td>0m:00s</td>
|
||||
<td>0m:00s</td>
|
||||
<td>105MB</td>
|
||||
<td><font size="-1">18.11.2016</font><br/><font size="-2">19:32:31</font></td>
|
||||
<td><font size="-1">29.12.2016</font><br/><font size="-2">16:01:51</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td class="optionTitle">Multi-srs Generator</td>
|
||||
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:01s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">18.11.2016</font><br/><font size="-2">19:32:31</font></td> </tbody>
|
||||
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:01s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">29.12.2016</font><br/><font size="-2">16:01:50</font></td> </tbody>
|
||||
</table>
|
||||
</td></tr></table></body>
|
||||
</html>
|
||||
|
|
@ -9,7 +9,7 @@
|
|||
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401220368
|
||||
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401220122
|
||||
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401220122
|
||||
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1479493940
|
||||
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1483023695
|
||||
0 "C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401220368
|
||||
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401220122
|
||||
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401220122
|
||||
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1479493940
|
||||
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1483023695
|
||||
0 "C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
|
|
|||
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Loading…
Reference in New Issue