14 Commits

Author	SHA1	Message	Date
MHeinrichs	fecb45b004	Caching for mem enabled	2014-06-09 20:27:37 +02:00
MHeinrichs	8adc589599	PE/NE-Sync started	2014-06-09 10:29:32 +02:00
MHeinrichs	8a57db1209	New PCB and start for RW-Signal-Optimization	2014-06-01 22:50:01 +02:00
MHeinrichs	3060b6be03	minor clean up	2014-05-29 22:06:01 +02:00
MHeinrichs	99277e926b	dma-working and prework for turbo side	2014-05-28 21:34:35 +02:00
MHeinrichs	2bc1b94e91	DMA-TK-Side first non working version	2014-05-24 21:59:56 +02:00
MHeinrichs	d187b3fa35	33MHz @100MHz basis working	2014-05-24 16:03:26 +02:00
MHeinrichs	dd9d5e8c4e	better amiga timing	2014-05-24 15:17:08 +02:00
MHeinrichs	228e58b64e	sync	2014-05-22 15:00:48 +02:00
MHeinrichs	9643ce8642	50Mhz Clock working	2014-05-19 07:35:45 +02:00
MHeinrichs	3f0e99e010	Fixed external interface flaws	2014-05-16 20:18:55 +02:00
MHeinrichs	be14e6527f	Cleaned up version ... This version is the base for all future experiments.	2014-05-15 23:05:08 +02:00
MHeinrichs	dd8e1d7bac	Working!	2014-05-15 22:19:03 +02:00
MHeinrichs	473a4a745b	Initial push ... First VErsion after I decided to use version controll ;)	2014-05-15 21:16:29 +02:00