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204 Commits 9 Branches 13 Tags 42 MiB
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Author SHA1 Message Date
Eric Helgeson
f7799fb225 Replace magic numbers with constants - thanks Jokker 2022-04-23 16:08:30 -05:00
Eric Helgeson
845954edeb Remove unused SCSI_SELECT - upstream has moved to a different approch to 
support PC98/etc
 2022-04-23 16:08:30 -05:00
Eric Helgeson
7b7f19413c
Merge pull request #98 from mactcp/main 
Support for image files larger than 4GB
 2022-04-22 07:48:52 -05:00
Glenn Anderson
961ae0b8b7 Support for images larger than 4GB 2022-04-19 10:14:23 -07:00
Eric Helgeson
aa751dc3b8
Merge pull request #92 from erichelgeson/XCVR 
Code for Transceiver Hardware
 2022-04-18 21:19:08 -05:00
androda
fff520959e Merge branch 'main' into XCVR 2022-04-18 16:57:57 -06:00
androda
2f08b9fa73 Swap to #ifdef 2022-04-18 16:57:19 -06:00
Eric Helgeson
24e1612fc7 Add build env for xcvr 2022-04-17 16:39:59 -05:00
Eric Helgeson
a566c9bbb0
Merge pull request #94 from mactcp/Write-speed-tune 
Write speed tuning
 2022-04-17 14:51:46 -05:00
Eric Helgeson
9a4e3dc886
Merge pull request #96 from erichelgeson/eric/moveAssembly 
Point assembly to wiki
 2022-04-17 11:04:10 -05:00
Eric Helgeson
27c424d2f9
Update assembly.md 2022-04-17 11:01:44 -05:00
androda
3158391c86 Merge branch 'main' into XCVR 2022-04-15 06:29:02 -06:00
androda
ceb6da764b Boot tested 
Tested to boot beige G3 and Q700, both with XCVR mode on and off on appropriate hardware
 2022-04-15 06:14:59 -06:00
androda
b4b0ce711f Cleaning up changes 2022-04-15 05:34:47 -06:00
androda
77698d0a68 Disable by default 
Since this is new hardware, disable it by default
 2022-04-15 05:21:44 -06:00
androda
d593c0817c Seems to boot 2022-04-14 06:44:19 -06:00
Glenn Anderson
adca34aeb8 Write speed tuning 2022-04-13 16:47:48 -07:00
Eric Helgeson
693ab2a5c0
Merge pull request #88 from mactcp/Bus-settle-delay-cleanup 
Cleanup of SCSI phase change code, and adjustment of bus settle delays.
 2022-04-13 08:28:02 -05:00
androda
4d3ee87c56 Work in progress 2022-04-12 06:22:28 -06:00
Glenn Anderson
ba1b3df680 Cleanup of SCSI phase change code, and adjustment of bus settle delays. 2022-04-08 11:10:07 -07:00
Eric Helgeson
22eb2c8d3e Back to snapshot 2022-04-07 16:29:06 -05:00
Eric Helgeson
9290adb1d6 v1.1-20220404 2022-04-05 08:22:36 -05:00
Eric Helgeson
fc38371717 v1.1-BETA-20220330 2022-04-03 20:16:03 -05:00
Eric Helgeson
08f25847f2
Merge pull request #85 from erichelgeson/eric/init_blk1 
init blk1
 2022-04-03 19:59:13 -05:00
Eric Helgeson
e468bd6fef init blk1 
Thanks to @moof via discord
 2022-04-03 14:53:37 -05:00
Eric Helgeson
004eea5ace
Merge pull request #82 from erichelgeson/eric/rmLidoImgs 
Delete MacHD.zip
 2022-04-02 08:08:32 -05:00
Eric Helgeson
833cfd9384
Delete MacHD.zip 
LIDO is slow, don't offer them for download!
 2022-04-02 08:06:50 -05:00
Eric Helgeson
3b17788cc6
Merge pull request #81 from mactcp/main 
Remove obsolete initialization of sector data overrun byte.
 2022-03-31 20:35:00 -05:00
Glenn Anderson
de35be0dc2 Remove obsolete initialization of sector data overrun byte. 2022-03-31 14:18:35 -07:00
Eric Helgeson
30eccd413e
Merge pull request #80 from mactcp/AppleHDSCSetup 
Correct == to = for verify with bytchk of 3
 2022-03-31 13:10:48 -05:00
Glenn Anderson
5c357b578c Correct == to = for verify with bytchk of 3 2022-03-31 09:23:30 -07:00
Eric Helgeson
46fd192ede
Merge pull request #78 from mactcp/AppleHDSCSetup 
Code reordering for bus settle delays
 2022-03-30 11:17:17 -05:00
Glenn Anderson
79835832d1 Reorder bus phase change and file.seek() so that file.seek() acts as a bus settle delay. 2022-03-28 15:01:40 -07:00
Eric Helgeson
08a57174eb
Merge pull request #73 from erichelgeson/eric/ImageSelect 
Image set selection
 2022-03-27 14:53:35 -05:00
Eric Helgeson
8db8000db3 Image set selection 2022-03-26 09:02:11 -05:00
Eric Helgeson
13b8de7bfd
Merge pull request #69 from erichelgeson/eric/spiSpeed 
Try clock speeds from 50 -> 32mhz for SD communication
 2022-03-26 08:28:43 -05:00
Eric Helgeson
9732e90537
Merge pull request #71 from mactcp/AppleHDSCSetup 
Apple HD SC Setup support
 2022-03-25 08:23:39 -05:00
Glenn Anderson
7f68d9f808 Support for VERIFY (10). 
Support for MODE SELECT as a no-op.
Range checking on block commands.
Sense key and additional sense for no image file.
 2022-03-24 17:22:04 -07:00
Glenn Anderson
e42291e82f Support Apple mode sense page 0x30. 
Support for mode sense page control 01b (changeable values).
Change SYNCHRONIZE CACHE (10) to be a no-op rather than an error.
 2022-03-24 16:51:35 -07:00
Eric Helgeson
f904486ad9
Merge pull request #70 from erichelgeson/eric/pin_toolchain 
Explicitly pinning toolchain to 1.9031.200702 and updating to latest coordinates.
 2022-03-24 09:02:12 -05:00
Eric Helgeson
44ce53de04 Explicitly pinning toolchain to 1.9031.200702 and updating to latest 
coordinates.

Unpinned seemed to just grab the latest cached version.
 2022-03-24 08:58:41 -05:00
Eric Helgeson
551faf72b2 Try clock speeds from 50 -> 32mhz for SD communication 
Helps compatibility with SD and different STM32 chips.
Add warning if under 40mhz - testing showed 40-50mhz gave almost no change in speed

Thanks @marcelv-3 via https://github.com/erichelgeson/BlueSCSI/discussions/58
 2022-03-23 21:08:04 -05:00
Eric Helgeson
32219ce18b
Merge pull request #67 from mactcp/main 
Switch to latest toolchain
 2022-03-21 13:42:25 -05:00
Glenn Anderson
c9dbfec6be Change readDataLoop alignment to 16 2022-03-19 13:04:24 -07:00
Glenn Anderson
e0653d6647 Switch to latest toolchain. 
Tune the timing for the readDataLoop with the latest toolchain.
 2022-03-19 12:04:57 -07:00
Eric Helgeson
7eb1c0d250
Merge pull request #64 from mactcp/main 
Optimize handling of reset interrupt.
 2022-03-19 07:51:43 -05:00
Glenn Anderson
dd87235fc0 Pin down alignment for writeDataLoop and readDataLoop, and perform some additional timing adjustment. 2022-03-18 15:51:22 -07:00
Glenn Anderson
b797793340 Read timing adjustment, now getting 1216 KB/sec on LC III+. 
First pass at write speed optimization, now getting 825 KB/sec on LC III+.
Whitespace cleanup.
 2022-03-17 18:08:00 -07:00
Glenn Anderson
45f61a8346 Separate out writeDataLoop. Adjust the timing, and incorporate the loop overhead in to one of the desired delays. 2022-03-17 16:36:39 -07:00
Glenn Anderson
1f6410fdc2 Move the db_bsrr table to RAM for faster performance. 2022-03-16 13:21:10 -07:00