2018-03-05 17:40:43 +00:00
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# Specify root clocks
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2017-10-22 01:22:56 +00:00
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
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create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
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2019-09-27 17:11:21 +00:00
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create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
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2017-10-22 01:22:56 +00:00
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derive_pll_clocks
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derive_clock_uncertainty
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2018-03-05 17:40:43 +00:00
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# Decouple different clock groups (to simplify routing)
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2019-09-27 17:11:21 +00:00
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set_clock_groups -exclusive \
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2019-07-11 22:22:16 +00:00
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-group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] \
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-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \
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2018-03-05 17:40:43 +00:00
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-group [get_clocks { *|h2f_user0_clk}] \
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2019-09-27 17:11:21 +00:00
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-group [get_clocks { FPGA_CLK1_50 }] \
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-group [get_clocks { FPGA_CLK2_50 }] \
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-group [get_clocks { FPGA_CLK3_50 }]
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set_false_path -from [get_ports {KEY*}]
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set_false_path -from [get_ports {BTN_*}]
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set_false_path -to [get_ports {LED_*}]
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set_false_path -to [get_ports {VGA_*}]
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set_false_path -to [get_ports {AUDIO_SPDIF}]
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set_false_path -to [get_ports {AUDIO_L}]
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set_false_path -to [get_ports {AUDIO_R}]
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set_false_path -to {cfg[*]}
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set_false_path -from {cfg[*]}
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2020-01-21 16:55:46 +00:00
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set_false_path -from {VSET[*]}
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2019-09-27 17:11:21 +00:00
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set_false_path -to {wcalc[*] hcalc[*]}
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2020-01-21 16:55:46 +00:00
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set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
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set_multicycle_path -to {*_osd|osd_vcnt*} -hold 2
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set_false_path -to {*_osd|v_cnt*}
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set_false_path -to {*_osd|v_osd_start*}
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set_false_path -to {*_osd|h_osd_start*}
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set_false_path -from {*_osd|v_osd_start*}
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set_false_path -from {*_osd|h_osd_start*}
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set_false_path -from {*_osd|rot*}
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set_false_path -from {*_osd|dsp_width*}
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set_false_path -to {*_osd|half}
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set_false_path -to {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
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set_false_path -from {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
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set_false_path -to {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] FB_HMIN[*] FB_HMAX[*] FB_VMIN[*] FB_VMAX[*]}
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set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] FB_HMIN[*] FB_HMAX[*] FB_VMIN[*] FB_VMAX[*]}
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set_false_path -to {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
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set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
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