Romain Dolbeau 2d2cbdbafe update ioRange; it doesn't actually affect the cache, only the MMU which we don't use...

2022-06-12 13:46:58 +02:00

..

ConsoleTest

update to first tested version

2022-04-17 11:25:48 +02:00

DeclROM

use some custom RLE to initiliaze the RAM disk with a valid HFS FS. Still doesn't mount at boot though.

2022-06-12 13:45:41 +02:00

NuBusFPGAInit

draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel

2022-06-06 23:36:43 +02:00

.gitignore

accel in 16/32 ; includes adding MUL to Vex & fixing a FIFO overrun in NuBus in 32 bits mode

2022-06-04 14:55:40 +02:00

74fct245.v

push to github

2021-12-21 08:26:30 +01:00

blit.c

draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel

2022-06-06 23:36:43 +02:00

blit.lds

Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag)

2022-05-15 14:43:15 +02:00

blit.sh

new interface

2022-06-04 17:25:58 +02:00

CG6.scala

commit current Vex config

2022-06-05 18:04:00 +02:00

DepVideoEqu.a

update to first tested version

2022-04-17 11:25:48 +02:00

do

DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus

2022-06-04 09:53:09 +02:00

fb_dma.py

update to first tested version

2022-04-17 11:25:48 +02:00

fb_video.py

update to first tested version

2022-04-17 11:25:48 +02:00

GenGoblinAccel.scala

update ioRange; it doesn't actually affect the cache, only the MMU which we don't use...

2022-06-12 13:46:58 +02:00

goblin_accel.py

Move Vex to a 128-bit Wishbone, and add a bypass to access a dedicated memory port with a 128-bits datapath. Speeds up scrolling quite nicely.

2022-06-05 18:03:23 +02:00

goblin_fb.py

Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag)

2022-05-15 14:43:15 +02:00

MakeFile

push to github

2021-12-21 08:26:30 +01:00

nubus_arbiter.v

update to first tested version

2022-04-17 11:25:48 +02:00

nubus_cpld.ucf

update to first tested version

2022-04-17 11:25:48 +02:00

nubus_cpld.v

DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus

2022-06-04 09:53:09 +02:00

nubus_cpu_wb.py

Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag)

2022-05-15 14:43:15 +02:00

nubus_fpga_V1_0_timings.xdc

update to first tested version

2022-04-17 11:25:48 +02:00

nubus_full_sampling.py

in _sampling, map whole SDRAm in superslot and use the first 248 Mib as a RAM disk with driver in the DeclRom

2022-06-07 23:05:08 +02:00

nubus_full.py

draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel

2022-06-06 23:36:43 +02:00

nubus_master_tst.py

stat module

2022-06-04 18:56:41 +02:00

nubus_mem_wb.py

buffers (fifo) write from NuBus to Wishbone, to improve write BW

2022-05-30 13:15:20 +02:00

nubus_memfifo_wb.py

pingmaster sort-of-work

2022-05-30 19:06:33 +02:00

nubus_sampling.v

DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus

2022-06-04 09:53:09 +02:00

nubus_stat.py

stat module

2022-06-04 18:56:41 +02:00

nubus_to_fpga_export.py

more updates

2022-01-29 11:03:47 +01:00

nubus_to_fpga_soc.py

draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel

2022-06-06 23:36:43 +02:00

nubus-to-ztex-io-signal.xdc

push to github

2021-12-21 08:26:30 +01:00

nubus-to-ztex-pin-signal.xdc

push to github

2021-12-21 08:26:30 +01:00

nubus.py

DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus

2022-06-04 09:53:09 +02:00

nubus.v

DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus

2022-06-04 09:53:09 +02:00

NuBusFPGADrvr.a

update to first tested version

2022-04-17 11:25:48 +02:00

NuBusFPGAPrimaryInit.a

update to first tested version

2022-04-17 11:25:48 +02:00

NuBusFPGASecondaryInit.a

update to first tested version

2022-04-17 11:25:48 +02:00

post_process_timings.sh

update to first tested version

2022-04-17 11:25:48 +02:00

rom.a

update to first tested version

2022-04-17 11:25:48 +02:00

sdram_init.py

Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag)

2022-05-15 14:43:15 +02:00

slave_tb.sv

draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel

2022-06-06 23:36:43 +02:00

sn74lvt125.v

more updates

2022-01-29 11:03:47 +01:00

VexRiscv_FbAccel.v

update ioRange; it doesn't actually affect the cache, only the MMU which we don't use...

2022-06-12 13:46:58 +02:00

ztex213_nubus.py

update to first tested version

2022-04-17 11:25:48 +02:00