partial draft 2
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@ -45,8 +45,29 @@ module mux8x1 (
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input logic[2:0] select,
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output wire out
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);
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always_comb begin
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out <= in[select];
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assign out <= in[select];
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endmodule
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// basic 8-to-1 mux with transparent output latch
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module mux8x1latch (
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input logic[7:0] in,
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input logic[2:0] select,
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input wire clock,
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input wire nReset,
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output reg out
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);
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wire muxOut;
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mux8x1 mux (in,select,muxOut);
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// transparent latch -- when clock is low, output will
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// follow the output of the mux. When clock is high,
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// output will hold its last value.
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always @(clock or nReset or muxOut) begin
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if(nReset == 1'b0) begin
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out <= 1'b0;
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end else if(clock == 1'b0) begin
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out <= muxOut;
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end
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end
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endmodule
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59
se-vga.sv
59
se-vga.sv
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@ -33,15 +33,64 @@ logic [9:0] vCount;
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wire hActive;
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wire hSEActive;
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logic [7:0] vidVramData;
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//logic [7:0] vidVramData;
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logic [12:0] vidVramAddr;
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//logic [7:0] cpuVramData;
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logic [12:0] cpuVramAddr;
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// link module that generates all our timing signals
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vgagen vgatiming(nReset,pixClk,hCount,hActive,hSEActive,nhSync,vCount,vActive,vSEActive,nvSync);
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// link module that fetches & outputs video data
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vgaout vidvram(pixClock,nReset,hCount,vCount,hSEActive,vSEActive,vidVramData,vidVramAddr,nvramOE,vidOut);
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// link module that handles cpu writes
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vgagen vgatiming(
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.nReset(nReset),
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.pixClk(pixClk),
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.hCount(hCount),
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.hActive(hActive),
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.hSEActive(hSEActive),
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.nhSync(nhSync),
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.vCount(vCount),
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.vActive(vActive),
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.vSEActive(vSEActive),
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.nvSync(nvSync)
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);
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// link module that fetches & outputs video data
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vgaout vidvram(
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.pixClock(pixClk),
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.nReset(nReset),
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.hCount(hCount),
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.vCount(vCount),
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.hSEActive(hSEActive),
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.vSEActive(vSEActive),
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.vramData(vramData),
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.vramAddr(vidVramAddr),
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.nvramOE(nvramOE),
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.vidOut(vidOut)
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);
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// link module that handles cpu writes
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cpusnoop cpusnp(
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.nReset(nReset),
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.pixClock(pixClk),
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.sequence(hCount[2:0]),
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.cpuAddr(cpuAddr),
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.cpuData(cpuData),
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.ncpuAS(ncpuAS),
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.ncpuUDS(ncpuUDS),
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.ncpuLDS(ncpuLDS),
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.cpuRnW(cpuRnW),
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.cpuClk(cpuClk),
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.vramAddr(vramAddr),
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.vramData(cpuVramData),
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.nvramWE(nvramWE)
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);
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always_comb begin
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// vramAddr muxing
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if(.nvramWE == 1'b0) begin
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vramAddr <= cpuVramAddr;
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end else begin
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vramAddr <= vidVramData;
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end
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end
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endmodule
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19
vgaout.sv
19
vgaout.sv
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@ -25,8 +25,25 @@ module vgaout (
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reg [7:0] rVid;
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wire vidMuxOut;
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wire vidActive; // combined active video signal
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wire vidMuxClk; // latch mux output just before updating rVid
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mux8x1 vidOutMux(rVid[7:0],hCount[2:0],vidMuxOut);
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// select bits 0..7 from the vram data in rVid, and latch if
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// vidMuxClk goes high
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mux8x1latch vidOutMux(rVid,hCount[2:0],vidMuxClk,nReset,vidMuxOut);
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// vidMuxClk should be low during sequence 0..6, and high for 7
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// this may lead to a race condition trying to change the mux
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// before the output is latched. The alternative is to latch on
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// the rising edge of pixClock during sequence 7, but then we may
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// have a race condition with the data coming in from VRAM.
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// What we really need is a half clock delay :-/
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always_comb begin
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if(hCount[2:0] == 3'd7) begin
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vidMuxClk <= 1'b1;
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end else begin
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vidMuxClk <= 1'b0;
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end
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end
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// latch incoming vram data on rising clock and sequence 7
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always @(posedge pixClock or negedge nReset) begin
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