Refactor Video Out Sequence
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@ -118,7 +118,7 @@ module cpusnoop (
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S2 : begin
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// wait for sequence
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if(pendWriteHi == 1 && pendWriteLo == 1) begin
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if(seq < 5) begin
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if(seq < 6) begin
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// we have enough time to write both before the next VRAM read
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cycleState <= S3;
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end else begin
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@ -126,7 +126,7 @@ module cpusnoop (
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cycleState <= S2;
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end
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end else if(pendWriteHi == 1 || pendWriteLo == 1) begin
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if(seq < 6) begin
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if(seq < 7) begin
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// we have enough time for the pending write
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if(pendWriteLo == 0) begin
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// move on to write high byte
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32
sevga.vwf
32
sevga.vwf
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@ -1961,8 +1961,8 @@ TRANSITION_LIST("vramData[7]")
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LEVEL 0 FOR 80.0;
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LEVEL Z FOR 240.0;
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LEVEL 0 FOR 80.0;
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LEVEL Z FOR 280.0;
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LEVEL 0 FOR 640.0;
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LEVEL Z FOR 500.0;
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LEVEL 0 FOR 420.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 320.0;
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@ -2024,8 +2024,8 @@ TRANSITION_LIST("vramData[6]")
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LEVEL 1 FOR 80.0;
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LEVEL Z FOR 240.0;
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LEVEL 0 FOR 80.0;
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LEVEL Z FOR 280.0;
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LEVEL 0 FOR 960.0;
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LEVEL Z FOR 500.0;
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LEVEL 0 FOR 740.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 320.0;
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@ -2087,8 +2087,8 @@ TRANSITION_LIST("vramData[5]")
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LEVEL 0 FOR 80.0;
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LEVEL Z FOR 240.0;
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LEVEL 1 FOR 80.0;
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LEVEL Z FOR 280.0;
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LEVEL 0 FOR 320.0;
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LEVEL Z FOR 500.0;
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LEVEL 0 FOR 100.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 640.0;
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LEVEL 1 FOR 1600.0;
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@ -2152,8 +2152,8 @@ TRANSITION_LIST("vramData[4]")
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LEVEL 1 FOR 80.0;
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LEVEL Z FOR 240.0;
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LEVEL 1 FOR 80.0;
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LEVEL Z FOR 280.0;
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LEVEL 1 FOR 320.0;
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LEVEL Z FOR 500.0;
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LEVEL 1 FOR 100.0;
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LEVEL 0 FOR 1600.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 320.0;
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@ -2214,8 +2214,8 @@ TRANSITION_LIST("vramData[3]")
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LEVEL 0 FOR 80.0;
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LEVEL Z FOR 240.0;
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LEVEL 1 FOR 80.0;
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LEVEL Z FOR 280.0;
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LEVEL 0 FOR 640.0;
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LEVEL Z FOR 500.0;
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LEVEL 0 FOR 420.0;
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LEVEL 1 FOR 640.0;
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LEVEL 0 FOR 640.0;
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LEVEL 1 FOR 320.0;
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@ -2280,8 +2280,8 @@ TRANSITION_LIST("vramData[2]")
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LEVEL 1 FOR 80.0;
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LEVEL Z FOR 240.0;
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LEVEL 1 FOR 80.0;
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LEVEL Z FOR 280.0;
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LEVEL 1 FOR 960.0;
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LEVEL Z FOR 500.0;
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LEVEL 1 FOR 740.0;
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LEVEL 0 FOR 960.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 640.0;
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@ -2345,8 +2345,8 @@ TRANSITION_LIST("vramData[1]")
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LEVEL 0 FOR 80.0;
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LEVEL Z FOR 240.0;
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LEVEL 0 FOR 80.0;
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LEVEL Z FOR 280.0;
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LEVEL 1 FOR 640.0;
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LEVEL Z FOR 500.0;
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LEVEL 1 FOR 420.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 640.0;
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LEVEL 0 FOR 640.0;
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@ -2412,8 +2412,8 @@ TRANSITION_LIST("vramData[0]")
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LEVEL 1 FOR 80.0;
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LEVEL Z FOR 240.0;
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LEVEL 0 FOR 80.0;
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LEVEL Z FOR 280.0;
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LEVEL 0 FOR 640.0;
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LEVEL Z FOR 500.0;
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LEVEL 0 FOR 420.0;
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LEVEL 1 FOR 320.0;
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LEVEL 0 FOR 320.0;
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LEVEL 1 FOR 320.0;
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28
vgaout.sv
28
vgaout.sv
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@ -26,27 +26,33 @@ module vgaout (
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wire vidMuxOut;
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wire vidActive; // combined active video signal
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//wire vgaShiftEn; // Enable pixel shift out
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wire vgaShiftL1; // Load VRAM data into register
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wire vgaShiftL2; // Load VRAM data into shifter
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vgaShiftOut vOut(
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.nReset(nReset),
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.clk(pixClock),
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.vidActive(vidActive),
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.seq(hCount[2:0]),
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.shiftEn(vidActive),
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.nLoad1(vgaShiftL1),
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.nLoad2(vgaShiftL2),
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.parIn(vramData),
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.out(vidMuxOut)
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);
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always_comb begin
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// load VRAM data into register
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if(hCount[2:0] == 0) vgaShiftL1 <= !pixClock;
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else vgaShiftL1 <= 1;
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// load VRAM data into shifter
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if(hCount[2:0] == 0) vgaShiftL2 <= !pixClock;
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else if(hCount[2:0] == 1) vgaShiftL2 <= pixClock;
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else vgaShiftL2 <= 1;
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// combined video active signal
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if(hSEActive == 1'b1 && vSEActive == 1'b1) begin
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vidActive <= 1'b1;
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/*end else if(hCount == 799 && vCount == 524) begin
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// this is the exception to ensure the first byte of video is loaded
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// just before the new frame starts
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vidActive <= 1'b1;
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end else if(vSEActive == 1'b1 && hCount == 10'd799) begin
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// this is the exception to ensure the first byte of video is loaded
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// just before a new line starts
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vidActive <= 1'b1;*/
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end else begin
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vidActive <= 1'b0;
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end
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@ -59,7 +65,7 @@ always_comb begin
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end
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// vram read signal
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if(vidActive == 1'b1 && hCount[2:0] == 3'h7) begin
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if(vidActive == 1'b1 && hCount[2:0] == 0) begin
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nvramOE <= 1'b0;
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end else begin
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nvramOE <= 1'b1;
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@ -13,41 +13,26 @@
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module vgaShiftOut (
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input wire nReset,
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input wire clk,
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input wire vidActive,
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input logic [2:0] seq,
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input wire shiftEn,
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input wire nLoad1,
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input wire nLoad2,
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input logic [7:0] parIn,
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output wire out
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);
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/* Shift register functioning similar to a 74597, with 8-bit input latch
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* and 8-bit PISO shift register output stage.
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* In sequence 7 new data is loaded from VRAM into the input stage, and in
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* sequence 0 the input stage is copied to the output stage to be shifted.
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*/
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reg [7:0] inReg;
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reg [7:0] outReg;
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// to meet VRAM timing requirements, data from VRAM has to be clocked into
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// our input register on the rising edge of the pixel clock
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always @(posedge clk or negedge nReset) begin
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if(nReset == 0) begin
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inReg <= 0;
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end else begin
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if(seq == 7) begin
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inReg <= parIn;
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end
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end
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if(!nReset) inReg <= 0;
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else if(!nLoad1) inReg <= parIn;
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end
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// pixels are shifted out on the falling edge of the pixel clock
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always @(negedge clk or negedge nReset) begin
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if(nReset == 1'b0) begin
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//inReg <= 0;
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outReg <= 0;
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end else begin
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if(vidActive == 1'b1) begin
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if(seq == 0) begin
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outReg <= inReg;
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end else begin
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if(!nReset) outReg <= 0;
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else begin
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if(!nLoad2) outReg <= inReg;
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else if(shiftEn) begin
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outReg[7] <= outReg[6];
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outReg[6] <= outReg[5];
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outReg[5] <= outReg[4];
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@ -55,15 +40,65 @@ module vgaShiftOut (
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outReg[3] <= outReg[2];
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outReg[2] <= outReg[1];
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outReg[1] <= outReg[0];
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outReg[0] <= 1'b0;
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end
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/*if(seq == 7) begin
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inReg <= parIn;
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end*/
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outReg[0] <= 0;
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end
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end
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end
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assign out = outReg[7];
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endmodule
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// module vgaShiftOut (
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// input wire nReset,
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// input wire clk,
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// input wire vidActive,
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// input logic [2:0] seq,
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// input logic [7:0] parIn,
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// output wire out
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// );
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// /* Shift register functioning similar to a 74597, with 8-bit input latch
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// * and 8-bit PISO shift register output stage.
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// * In sequence 0 new data is loaded from VRAM into the input stage, and in
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// * sequence 1 the input stage is copied to the output stage to be shifted.
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// */
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// reg [7:0] inReg;
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// reg [7:0] outReg;
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// // to meet VRAM timing requirements, data from VRAM has to be clocked into
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// // our input register on the rising edge of the pixel clock
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// always @(posedge clk or negedge nReset) begin
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// if(nReset == 0) begin
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// inReg <= 0;
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// end else begin
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// if(seq == 0) begin
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// inReg <= parIn;
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// end
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// end
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// end
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// // pixels are shifted out on the falling edge of the pixel clock
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// always @(negedge clk or negedge nReset) begin
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// if(nReset == 1'b0) begin
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// //inReg <= 0;
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// outReg <= 0;
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// end else begin
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// if(vidActive == 1'b1) begin
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// if(seq == 0) begin
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// outReg <= inReg;
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// end else begin
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// outReg[7] <= outReg[6];
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// outReg[6] <= outReg[5];
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// outReg[5] <= outReg[4];
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// outReg[4] <= outReg[3];
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// outReg[3] <= outReg[2];
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// outReg[2] <= outReg[1];
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// outReg[1] <= outReg[0];
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// outReg[0] <= 1'b0;
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// end
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// end
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// end
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// end
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// assign out = outReg[7];
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// endmodule
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`endif
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