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83
cpusnoop.sv
83
cpusnoop.sv
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@ -11,34 +11,75 @@
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module cpusnoop (
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input wire nReset, // System Reset signal
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input wire pixClock, // 25.175MHz Pixel Clock
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input logic [2:0] sequence, // Sequence count (low 3 bits of hCount)
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input logic [23:1] cpuAddr, // CPU Address bus
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input logic [2:0] seq, // Sequence count (low 3 bits of hCount)
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input logic [22:0] cpuAddr, // CPU Address bus
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input logic [15:0] cpuData, // CPU Data bus
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input wire ncpuAS, // CPU Address Strobe signal
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input wire ncpuUDS, // CPU Upper Data Strobe signal
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input wire ncpuLDS, // CPU Lower Data Strobe signal
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input wire cpuRnW, // CPU Read/Write select signal
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input wire cpuClk, // CPU Clock
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output logic [12:0] vramAddr, // VRAM Address Bus
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inout logic [7:0] vramData, // VRAM Data Bus
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output logic [14:0] vramAddr, // VRAM Address Bus
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output logic [7:0] vramDataOut,// VRAM Data Bus Output
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output wire nvramWE, // VRAM Write strobe
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input logic [2:0] ramSize // CPU RAM size selection
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);
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// framebuffer address (with 4MB RAM installed): 0x3FA700 - 0x3FFFFF
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/* framebuffer starts $5900 below the top of RAM
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* ramSize is used to mask the cpuAddr bits [21:9] to select the amount
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* of memory installed in the computer. Not all possible ramSize selections
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* are valid memory sizes when using 30-pin SIMMs in the Mac SE.
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* They may be possible using PDS RAM expansion cards.
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* ramSize bufferStart ramTop+1 ramSize Valid? Installed SIMMs
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* $7 $3fa700 $400000 4.0MB Y [ 1MB 1MB ][ 1MB 1MB ]
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* $6 $37a700 $380000 3.5MB N
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* $5 $2fa700 $300000 3.0MB N
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* $4 $27a700 $280000 2.5MB Y [ 1MB 1MB ][256kB 256kB]
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* $3 $1fa700 $200000 2.0MB Y [ 1MB 1MB ][ --- --- ]
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* $2 $17a700 $180000 1.5MB N
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* $1 $0fa700 $100000 1.0MB Y [256kB 256kB][256kB 256kB]
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* $0 $07a700 $080000 0.5MB Y [256kB 256kB][ --- --- ]
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*/
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wire pendWriteLo; // low byte write to VRAM pending
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wire pendWriteHi; // high byte write to VRAM pending
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logic [12:1] addrCache; // store address for cpu writes to framebuffer
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logic [13:0] addrCache; // store address for cpu writes to framebuffer
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logic [7:0] dataCacheLo; // store data for cpu writes to low byte
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logic [7:0] dataCacheHi; // store data for cpu writes to high byte
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wire cpuBufSel; // is CPU accessing frame buffer?
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// when cpu addresses the framebuffer, set our enable signal
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always_comb begin
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if(ramSize == cpuAddr[20:18] && cpuAddr[22:21] == 2'b00 && cpuAddr[17:14] == 4'b1111) begin
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cpuBufSel <= 1'b1;
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end else begin
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cpuBufSel <= 1'b0;
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end
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end
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// when cpu addresses the framebuffer, save the address
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always @(negedge ncpuAS or negedge nReset) begin
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if(nReset == 1'b0) begin
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addrCache <= 16'h0;
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addrCache <= 0;
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end else begin
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if(cpuAddr >= 24'h3FA700 && cpuAddr < 24'h400000) begin
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addrCache[12:0] <= cpuAddr - 16'hA700;
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// here we match our ramSize jumpers and constants to confirm
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// the CPU is accessing the primary frame buffer
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if(cpuBufSel == 1'b1) begin
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// We have a match, so subtract constant $1380 from the
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// cpu address and store the result in addrCache register.
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// Constant $1380 corresponds to $2700 shifted right by 1.
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// Once the selection bits above are masked out, we're left
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// with buffer addresses starting with $2700
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// e.g. with 4MB of RAM, fram buffer starts at $3FA700
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// buffer address: 0011 1111 1010 0111 0000 0000 = $3FA700
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// vram addr mask: 0000 0000 0011 1111 1111 1111 - $003FFF
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// vram address: 0000 0000 0010 0111 0000 0000 = $002700
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// Since CPU is 16-bit and does not provide A0, our cpuAddr
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// signals are shifted right by one, so we need to do the same
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// to our offset before subtracting it from cpuAddr
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// offset: 0000 0000 0010 0111 0000 0000 = $002700
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// shifted offset: 0000 0000 0001 0011 1000 0000 = $001380
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addrCache <= cpuAddr[13:0] - 14'h1380;
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end
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end
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end
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@ -48,18 +89,18 @@ module cpusnoop (
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if(nReset == 1'b0) begin
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dataCacheHi <= 8'h0;
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end else begin
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if(cpuAddr >= 24'h3FA700 && cpuAddr < 24'h400000 && cpuRnW == 1'b0) begin
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if(cpuBufSel == 1'b1 && cpuRnW == 1'b0) begin
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dataCacheHi <= cpuData[15:8];
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end
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end
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end
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// when cpu addresses the framebuffer, save low byte
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always @(negedge ncpuUDS or negedge nReset) begin
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always @(negedge ncpuLDS or negedge nReset) begin
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if(nReset == 1'b0) begin
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dataCacheLo <= 8'h0;
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end else begin
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if(cpuAddr >= 24'h3FA700 && cpuAddr < 24'h400000 && cpuRnW == 1'b0) begin
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if(cpuBufSel == 1'b1 && cpuRnW == 1'b0) begin
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dataCacheLo <= cpuData[7:0];
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end
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end
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@ -71,7 +112,7 @@ module cpusnoop (
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pendWriteLo <= 1'b0;
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pendWriteHi <= 1'b0;
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end else begin
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if(cpuAddr >= 24'h3FA700 && cpuAddr < 24'h400000 && cpuRnW == 1'b0) begin
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if(cpuBufSel == 1'b1 && cpuRnW == 1'b0) begin
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if(ncpuUDS == 1'b0) begin
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pendWriteHi <= 1'b1;
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end
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@ -79,10 +120,10 @@ module cpusnoop (
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pendWriteLo <= 1'b1;
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end
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end else begin
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if(sequence == 3'h1) begin
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if(seq == 3'h1) begin
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pendWriteLo <= 1'b0;
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end
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if(sequence == 3'h2) begin
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if(seq == 3'h2) begin
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pendWriteHi <= 1'b0;
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end
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end
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@ -90,19 +131,19 @@ module cpusnoop (
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end
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always_comb begin
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vramAddr[12:1] <= addrCache[12:1];
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if(pendWriteLo == 1'b1 && sequence == 3'h1) begin
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vramAddr[14:1] <= addrCache[13:0];
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if(pendWriteLo == 1'b1 && seq == 3'h1) begin
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vramAddr[0] <= 1'b0;
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nvramWE <= 1'b0;
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vramData <= dataCacheLo;
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end else if(pendWriteHi == 1'b1 && sequence = 3'h2) begin
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vramDataOut <= dataCacheLo;
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end else if(pendWriteHi == 1'b1 && seq == 3'h2) begin
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vramAddr[0] <= 1'b1;
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nvramWE <= 1'b0;
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vramData <= dataCacheHi;
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vramDataOut <= dataCacheHi;
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end else begin
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vramAddr[0] <= 1'b0;
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nvramWE <= 1'b1;
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vramData <= 8'bZ;
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vramDataOut <= 8'h0;
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end
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end
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endmodule
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@ -7,14 +7,17 @@
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* Basic modules to be used elsewhere
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*****************************************************************************/
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`ifndef PRIMS
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`define PRIMS
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// basic d-flipflop
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module dff (
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module myDff (
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input wire nReset,
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input wire clk,
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input wire d,
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output reg q
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);
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always @(posedge clock or negedge nReset) begin
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always @(posedge clk or negedge nReset) begin
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if(nReset == 1'b0) begin
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q <= 1'b0;
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end else begin
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@ -45,7 +48,7 @@ module mux8x1 (
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input logic[2:0] select,
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output wire out
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);
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assign out <= in[select];
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assign out = in[select];
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endmodule
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// basic 8-to-1 mux with transparent output latch
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@ -62,11 +65,13 @@ module mux8x1latch (
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// transparent latch -- when clock is low, output will
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// follow the output of the mux. When clock is high,
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// output will hold its last value.
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always @(clock or nReset or muxOut) begin
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always @(clock or nReset or muxOut or out) begin
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if(nReset == 1'b0) begin
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out <= 1'b0;
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out = 1'b0;
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end else if(clock == 1'b0) begin
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out <= muxOut;
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out = muxOut;
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end else begin
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out = out;
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end
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end
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endmodule
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@ -84,14 +89,16 @@ module piso8 (
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logic [7:0] muxOuts;
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mux8 loader(muxIns[7:0],parIn[7:0],load,muxOuts[7:0]);
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dff u0(nReset,clk,muxOuts[0],muxIns[1]);
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dff u1(nReset,clk,muxOuts[1],muxIns[2]);
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dff u2(nReset,clk,muxOuts[2],muxIns[3]);
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dff u3(nReset,clk,muxOuts[3],muxIns[4]);
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dff u4(nReset,clk,muxOuts[4],muxIns[5]);
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dff u5(nReset,clk,muxOuts[5],muxIns[6]);
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dff u6(nReset,clk,muxOuts[6],muxIns[7]);
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dff u7(nReset,clk,muxOuts[7],muxIns[0]);
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myDff u0(nReset,clk,muxOuts[0],muxIns[1]);
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myDff u1(nReset,clk,muxOuts[1],muxIns[2]);
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myDff u2(nReset,clk,muxOuts[2],muxIns[3]);
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myDff u3(nReset,clk,muxOuts[3],muxIns[4]);
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myDff u4(nReset,clk,muxOuts[4],muxIns[5]);
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myDff u5(nReset,clk,muxOuts[5],muxIns[6]);
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myDff u6(nReset,clk,muxOuts[6],muxIns[7]);
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myDff u7(nReset,clk,muxOuts[7],muxIns[0]);
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out <= muxIns[0];
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endmodule
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assign out = muxIns[0];
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endmodule
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`endif
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42
se-vga.sv
42
se-vga.sv
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@ -7,14 +7,14 @@
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* Pulls together all the smaller modules to form the SE-VGA adapter
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*****************************************************************************/
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module design sevga (
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module sevga (
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input wire nReset, // System reset signal
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input wire pixClk, // 25.175MHz pixel clock
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output wire nhSync, // HSync signal
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output wire nvSync, // VSync signal
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output wire vidOut, // 1-bit Monochrome video signal
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output logic [12:0] vramAddr, // VRAM Address bus
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output logic [14:0] vramAddr, // VRAM Address bus
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inout logic [7:0] vramData, // VRAM Data bus
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output wire nvramOE, // VRAM Read strobe
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output wire nvramWE, // VRAM Write strobe
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@ -25,19 +25,21 @@ module design sevga (
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input wire ncpuUDS, // CPU Upper Data Strobe signal
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input wire ncpuLDS, // CPU Lower Data Strobe signal
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input wire cpuRnW, // CPU Read/Write select signal
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input wire cpuClk // CPU Clock
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//input wire cpuClk, // CPU Clock (probably not needed)
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input logic [2:0] ramSize // Select installed RAM size
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);
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logic [9:0] hCount;
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logic [9:0] vCount;
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wire hActive;
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wire hSEActive;
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wire vActive;
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wire vSEActive;
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//logic [7:0] vidVramData;
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logic [12:0] vidVramAddr;
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//logic [7:0] cpuVramData;
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logic [12:0] cpuVramAddr;
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logic [14:0] vidVramAddr;
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logic [14:0] cpuVramAddr;
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logic [7:0] vidVramData;
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wire [7:0] cpuVramData;
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// link module that generates all our timing signals
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vgagen vgatiming(
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@ -61,7 +63,7 @@ vgaout vidvram(
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.vCount(vCount),
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.hSEActive(hSEActive),
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.vSEActive(vSEActive),
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.vramData(vramData),
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.vramData(vidVramData),
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.vramAddr(vidVramAddr),
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.nvramOE(nvramOE),
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.vidOut(vidOut)
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@ -71,7 +73,7 @@ vgaout vidvram(
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cpusnoop cpusnp(
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.nReset(nReset),
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.pixClock(pixClk),
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.sequence(hCount[2:0]),
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.seq(hCount[2:0]),
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.cpuAddr(cpuAddr),
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.cpuData(cpuData),
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.ncpuAS(ncpuAS),
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@ -79,18 +81,28 @@ cpusnoop cpusnp(
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.ncpuLDS(ncpuLDS),
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.cpuRnW(cpuRnW),
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.cpuClk(cpuClk),
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.vramAddr(vramAddr),
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.vramData(cpuVramData),
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.nvramWE(nvramWE)
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.vramAddr(cpuVramAddr),
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.vramDataOut(cpuVramData),
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.nvramWE(nvramWE),
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.ramSize(ramSize)
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);
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always_comb begin
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// vramAddr muxing
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if(.nvramWE == 1'b0) begin
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if(nvramWE == 1'b0) begin
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vramAddr <= cpuVramAddr;
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end else begin
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vramAddr <= vidVramData;
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vramAddr <= vidVramAddr;
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end
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end
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always_comb begin
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if(nvramWE == 1'b0) begin
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vramData <= cpuVramData;
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end else begin
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vramData <= 8'bZZZZZZZZ;
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end
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vidVramData <= vramData;
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end
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endmodule
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27
vgacount.sv
27
vgacount.sv
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@ -7,10 +7,13 @@
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* Low-level VGA signal counter
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*****************************************************************************/
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`ifndef VGACOUNT
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`define VGACOUNT
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module vgacount (
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input wire nReset, // system reset signal
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input wire clock, // counter increment clock
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output logic [9:0] count, // count output
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output logic [9:0] count, // count output
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output wire nSync, // sync pulse
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output wire activeVid, // active video signal
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output wire activeSE // secondary active video signal (SE)
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@ -45,23 +48,25 @@ always_comb begin
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count <= counter;
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// Sync pulse
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if(hCount >= SYNCBEGIN && hCount < SYNCEND) begin
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nhSync <= 1'b0;
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if(count >= SYNCBEGIN && count < SYNCEND) begin
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nSync <= 1'b0;
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end else begin
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nhSync <= 1'b1;
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nSync <= 1'b1;
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end
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if(hCount >= ACTBEGIN && hCount < ACTEND) begin
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hActive <= 1'b0;
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if(count >= ACTBEGIN && count < ACTEND) begin
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activeVid <= 1'b0;
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end else begin
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hActive <= 1'b1;
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activeVid <= 1'b1;
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end
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if(hCount >= SEACTBEGIN) begin
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hSEActive <= 1'b0;
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if(count >= SEACTBEGIN) begin
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activeSE <= 1'b0;
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end else begin
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hSEActive <= 1'b1;
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activeSE <= 1'b1;
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end
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end
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endmodule
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endmodule
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`endif
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@ -7,6 +7,9 @@
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* Generates VGA timing signals & counters
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*****************************************************************************/
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`ifndef VGAGEN
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`define VGAGEN
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`include "vgacount.sv"
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module vgagen (
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@ -25,4 +28,6 @@ module vgagen (
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vgacount #(800,592,688,576,736,512) hoz(nReset,pixClk,hCount,nhSync,hActive,hSEActive);
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vgacount #(525,421,423,411,456,342) ver(nReset,nhSync,vCount,nvSync,vActive,vSEActive);
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endmodule
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endmodule
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`endif
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12
vgaout.sv
12
vgaout.sv
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@ -7,7 +7,7 @@
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* Fetches video data from VRAM and shifts out
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*****************************************************************************/
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`include "primitives.sv"
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`include "primitives/primitives.sv"
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module vgaout (
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input wire pixClock,
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@ -16,8 +16,8 @@ module vgaout (
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input logic [9:0] vCount,
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input wire hSEActive,
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input wire vSEActive,
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inout logic [7:0] vramData,
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output logic [12:0] vramAddr,
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input logic [7:0] vramData,
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output logic [14:0] vramAddr,
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output wire nvramOE,
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output wire vidOut
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);
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@ -50,7 +50,7 @@ always @(posedge pixClock or negedge nReset) begin
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if(nReset == 1'b0) begin
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rVid <= 8'h0;
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end else begin
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if(hCount[2:0] == 3'b7) begin
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if(hCount[2:0] == 3'h7) begin
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rVid <= vramData;
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end
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end
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@ -72,7 +72,7 @@ always_comb begin
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end
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// vram read signal
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if(vidActive == 1'b1 && hCount[2:0] == 3'b7) begin
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if(vidActive == 1'b1 && hCount[2:0] == 3'h7) begin
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nvramOE <= 1'b0;
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end else begin
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nvramOE <= 1'b1;
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@ -80,7 +80,7 @@ always_comb begin
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// vram address signals
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// these will be mux'd with cpu addresses externally
|
||||
vramAddr[12:6] <= vCount[6:0];
|
||||
vramAddr[14:6] <= vCount[8:0];
|
||||
vramAddr[5:0] <= hCount[8:3];
|
||||
end
|
||||
|
||||
|
|
Loading…
Reference in New Issue