2021-10-29 10:04:59 +00:00
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module IOBS(
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/* MC68HC000 interface */
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input CLK, input nWE, input nAS, input nLDS, input nUDS,
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/* AS cycle detection */
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input BACT,
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2023-03-30 15:50:05 +00:00
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/* Select signals */
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2024-09-22 12:13:18 +00:00
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input IOCS, input IORealCS, input IOPWCS,
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2023-03-30 15:50:05 +00:00
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/* FSB cycle termination outputs */
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2023-07-16 03:21:44 +00:00
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output reg IONPReady, output IOPWReady, output reg nBERR_FSB,
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2021-10-29 10:04:59 +00:00
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/* Read data OE control */
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output nDinOE,
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2023-04-07 03:11:11 +00:00
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/* IOB master controller interface */
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2024-10-03 09:51:10 +00:00
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output reg IORDREQ, output reg IOWRREQ,
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2023-04-07 03:11:11 +00:00
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input IOACT, input IODONEin, input IOBERR,
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2021-10-29 10:04:59 +00:00
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/* FIFO primary level control */
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2023-04-07 03:11:11 +00:00
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output reg ALE0, output reg IOL0, output reg IOU0,
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2021-10-29 10:04:59 +00:00
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/* FIFO secondary level control */
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output reg ALE1);
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/* IOACT input synchronization */
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2023-04-07 03:11:11 +00:00
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reg IOACTr = 0; always @(posedge CLK) IOACTr <= IOACT;
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/* IODTACK input synchronization */
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2023-04-07 06:33:04 +00:00
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reg IODONEr; always @(posedge CLK) IODONEr <= IODONEin;
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wire IODONE = IODONEr;
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2021-10-29 10:04:59 +00:00
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/* Read data OE control */
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2024-09-22 12:13:18 +00:00
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assign nDinOE = !(!nAS && IORealCS && nWE);
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2021-10-29 10:04:59 +00:00
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2023-03-30 15:50:05 +00:00
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/* I/O transfer state
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* TS0 - I/O bridge idle:
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* asserts IOREQ
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2023-04-01 08:46:47 +00:00
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* transitions to TS3 when BACT && IOCS && !ALE1 && !Sent
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2023-03-30 15:50:05 +00:00
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* TS3 - starting I/O transfer:
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latches LDS and UDS from FSB or FIFO secondary level
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transitions immediately to TS2
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* TS2 - waiting for IOBM to begin:
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transitions to TS1 when IOACT true
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* TS1 - waiting for IOBM to finish:
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* transitions to TS1 when IOACT false */
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reg [1:0] TS = 0;
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2023-03-31 10:17:08 +00:00
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reg Sent = 0;
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2021-10-29 10:04:59 +00:00
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2023-04-07 03:11:11 +00:00
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/* FIFO secondary level control */
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2023-04-10 03:26:05 +00:00
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reg Load1; reg Clear1;
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reg IORW1; reg IOL1; reg IOU1;
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2023-04-07 03:11:11 +00:00
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always @(posedge CLK) begin // ALE and R/W load control
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2023-03-30 15:50:05 +00:00
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// If write currently posting (TS!=0),
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// I/O selected, and FIFO secondary level empty
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2023-07-16 06:25:27 +00:00
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if (BACT && IOPWCS && !ALE1 && !Sent && TS!=0) begin
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2023-03-30 15:50:05 +00:00
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// Latch R/W now but latch address and LDS/UDS next cycle
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2021-10-29 10:04:59 +00:00
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IORW1 <= nWE;
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Load1 <= 1;
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2021-11-22 13:28:06 +00:00
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end else Load1 <= 0;
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end
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2023-04-07 03:11:11 +00:00
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always @(posedge CLK) begin // ALE clear control
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2023-03-30 15:50:05 +00:00
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// Make address latch transparent in cycle after TS3
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// (i.e. first TS2 cycle that's not part of current write)
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2024-10-03 09:51:10 +00:00
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if (TS==3) Clear1 <= 1;
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2021-11-22 13:28:06 +00:00
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else Clear1 <= 0;
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end
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2023-04-07 03:11:11 +00:00
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always @(posedge CLK) begin // LDS, UDS, ALE control
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if (Load1) begin // Latch address, LDS, UDS when Load1 true
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2023-04-01 08:46:47 +00:00
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ALE1 <= 1;
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2023-04-07 03:11:11 +00:00
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IOL1 <= !nLDS;
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IOU1 <= !nUDS;
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2023-03-30 15:50:05 +00:00
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end else if (Clear1) ALE1 <= 0;
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2021-10-29 10:04:59 +00:00
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end
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2023-04-07 03:11:11 +00:00
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/* FIFO primary level control */
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2021-10-29 10:04:59 +00:00
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always @(posedge CLK) begin
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2023-03-30 15:50:05 +00:00
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if (TS==0) begin
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2024-10-03 09:51:10 +00:00
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if (ALE1) begin // If FIFO secondary level occupied
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// Request transfer from IOBM and latch R/W from FIFO
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TS <= 3;
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IORDREQ <= IORW1;
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IOWRREQ <= !IORW1;
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2023-04-07 04:41:16 +00:00
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IOL0 <= IOL1;
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IOU0 <= IOU1;
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2024-10-03 09:51:10 +00:00
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end else if (BACT && IOCS && !ALE1 && !Sent) begin // FSB request
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// Request transfer from IOBM and latch R/W from FSB
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TS <= 3;
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IORDREQ <= nWE;
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IOWRREQ <= !nWE;
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2023-04-07 04:41:16 +00:00
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IOL0 <= !nLDS;
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IOU0 <= !nUDS;
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2024-10-03 09:51:10 +00:00
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end else begin // Otherwise stay in idle
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TS <= 0;
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IORDREQ <= 0;
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IOWRREQ <= 0;
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2021-10-29 10:04:59 +00:00
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end
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ALE0 <= 0;
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2024-10-03 09:51:10 +00:00
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end else if (TS==3) begin
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TS <= 2; // Always go to TS2. Keep IORDREQ/IOWRREQ active
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2023-04-07 03:11:11 +00:00
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ALE0 <= 1; // Latch address (and data)
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2024-10-03 09:51:10 +00:00
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// Latch data strobes from FIFO or FSB as appropriate
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2021-10-29 10:04:59 +00:00
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if (ALE1) begin
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IOL0 <= IOL1;
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IOU0 <= IOU1;
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end else begin
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2023-04-07 03:11:11 +00:00
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IOL0 <= !nLDS;
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IOU0 <= !nUDS;
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2021-10-29 10:04:59 +00:00
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end
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2023-03-30 15:50:05 +00:00
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end else if (TS==2) begin
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2024-10-03 09:51:10 +00:00
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// Wait for IOACT then withdraw IOREQ and enter TS1
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2021-10-29 10:04:59 +00:00
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if (IOACTr) begin
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2024-10-03 09:51:10 +00:00
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TS <= 1;
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IORDREQ <= 0;
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IOWRREQ <= 0;
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end else TS <= 2;
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2023-04-07 03:11:11 +00:00
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ALE0 <= 1; // Keep address latched
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2024-10-03 09:51:10 +00:00
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end else if (TS==1) begin
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2023-03-30 15:50:05 +00:00
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// Wait for IOACT low (transfer over) before going back to idle
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2023-04-07 03:11:11 +00:00
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if (!IOACTr) TS <= 0;
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2024-10-03 09:51:10 +00:00
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else TS <= 1;
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IORDREQ <= 0;
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IOWRREQ <= 0;
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2023-04-07 03:11:11 +00:00
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ALE0 <= 0; // Release addr latch since it's controlled by IOBM now
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2021-10-29 10:04:59 +00:00
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end
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end
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2023-04-07 03:11:11 +00:00
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/* Sent control */
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always @(posedge CLK) begin
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if (!BACT) Sent <= 0;
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2023-07-16 03:21:44 +00:00
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else if (BACT && IOCS && !ALE1 && (IOPWCS || TS==0)) Sent <= 1;
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2023-04-07 03:11:11 +00:00
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end
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2023-07-16 03:21:44 +00:00
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/* Nonposted and posted ready */
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2023-07-16 06:25:27 +00:00
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assign IOPWReady = !ALE1 || Sent; // Posted write reaedy
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2023-04-10 03:26:05 +00:00
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always @(posedge CLK) begin // Nonposted read/write ready
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2023-07-16 03:21:44 +00:00
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if (!BACT) IONPReady <= 0;
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else if (Sent && !IOPWCS && IODONE) IONPReady <= 1;
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2021-10-29 10:04:59 +00:00
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end
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2023-04-07 03:11:11 +00:00
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/* BERR control */
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2021-10-29 10:04:59 +00:00
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always @(posedge CLK) begin
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2023-04-07 03:11:11 +00:00
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if (!BACT) nBERR_FSB <= 1;
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else if (Sent && IOBERR) nBERR_FSB <= 0;
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2021-10-29 10:04:59 +00:00
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end
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endmodule
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