Merge branch 'dev-0.6c' into dev-0.6d

This commit is contained in:
Zane Kaminski 2024-10-03 12:06:59 -04:00
commit 76ec65a257
2 changed files with 3 additions and 3 deletions

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@ -12,7 +12,7 @@ module RAM(
input RefReqIn, input RefUrgIn, input RefReqIn, input RefUrgIn,
/* DRAM and NOR flash interface */ /* DRAM and NOR flash interface */
output [11:0] RA, output nRAS, output reg nCAS, output [11:0] RA, output nRAS, output reg nCAS,
output nLWE, output nUWE, output reg nOE, output nROMOE, output nROMWE); output nLWE, output nUWE, output nOE, output nROMOE, output nROMWE);
/* RAM control state */ /* RAM control state */
reg [2:0] RS; reg [2:0] RS;

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@ -69,7 +69,7 @@ module WarpSE(
wire IOCS, IORealCS, IOPWCS, IACS; wire IOCS, IORealCS, IOPWCS, IACS;
wire ROMCS, ROMCS4X; wire ROMCS, ROMCS4X;
wire RAMCS, RAMCS0X; wire RAMCS, RAMCS0X;
wire QoSCS, SndQoSCS; wire QoSCS, SndQoSCS, QoSEN;
CS cs( CS cs(
/* MC68HC000 interface */ /* MC68HC000 interface */
.A(A_FSB[23:08]), .A(A_FSB[23:08]),
@ -200,7 +200,7 @@ module WarpSE(
.IODONE(IODONE), .IODONE(IODONE),
.IOBERR(IOBERR)); .IOBERR(IOBERR));
wire QoSEN, SndQoSReady; wire SndQoSReady;
CNT cnt( CNT cnt(
/* FSB clock, 7.8336 MHz clock, and E clock inputs */ /* FSB clock, 7.8336 MHz clock, and E clock inputs */
.CLK(FCLK), .CLK(FCLK),