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https://github.com/garrettsworkshop/Warp-SE.git
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Merge branch 'dev-0.6c' into dev-0.6d
This commit is contained in:
commit
76ec65a257
@ -12,7 +12,7 @@ module RAM(
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input RefReqIn, input RefUrgIn,
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input RefReqIn, input RefUrgIn,
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/* DRAM and NOR flash interface */
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/* DRAM and NOR flash interface */
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output [11:0] RA, output nRAS, output reg nCAS,
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output [11:0] RA, output nRAS, output reg nCAS,
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output nLWE, output nUWE, output reg nOE, output nROMOE, output nROMWE);
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output nLWE, output nUWE, output nOE, output nROMOE, output nROMWE);
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/* RAM control state */
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/* RAM control state */
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reg [2:0] RS;
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reg [2:0] RS;
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@ -69,7 +69,7 @@ module WarpSE(
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wire IOCS, IORealCS, IOPWCS, IACS;
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wire IOCS, IORealCS, IOPWCS, IACS;
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wire ROMCS, ROMCS4X;
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wire ROMCS, ROMCS4X;
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wire RAMCS, RAMCS0X;
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wire RAMCS, RAMCS0X;
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wire QoSCS, SndQoSCS;
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wire QoSCS, SndQoSCS, QoSEN;
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CS cs(
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CS cs(
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/* MC68HC000 interface */
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/* MC68HC000 interface */
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.A(A_FSB[23:08]),
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.A(A_FSB[23:08]),
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@ -200,7 +200,7 @@ module WarpSE(
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.IODONE(IODONE),
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.IODONE(IODONE),
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.IOBERR(IOBERR));
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.IOBERR(IOBERR));
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wire QoSEN, SndQoSReady;
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wire SndQoSReady;
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CNT cnt(
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CNT cnt(
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/* FSB clock, 7.8336 MHz clock, and E clock inputs */
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/* FSB clock, 7.8336 MHz clock, and E clock inputs */
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.CLK(FCLK),
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.CLK(FCLK),
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