If it gets this far, the firmware is at least sort of running, so the
watchdog has served its purpose of resetting to the bootloader if
there's invalid firmware flashed to the device.
Provide the basic functionality for setting direction, turning on and
off, toggling, reading inputs, and enabling/disabling pullups.
This chip also provides pulldowns, so in the future I will also
implement pulldown control so we can detect shorts to 5V.
SPI isn't needed on this platform because we don't need an I/O expander.
So this can be a bunch of stub functions that do nothing. They will be
optimized out during the linking process anyway.
This implements a USB CDC serial port using the Nuvoton USBD driver. The
USB handling is based on Nuvoton's BSP sample code, especially the IRQ
handlers and descriptor buffer configuration. The descriptors have been
adapted to be similar to the AVR version, and RX/TX functions have been
written to implement an API closer to LUFA, which is what the SIMM
programmer common code needs.
I'm sure it's slightly more efficient as a static inline function, but
it results in less flash usage as a separate function. This is important
for the bootloader where every byte matters.
Nuvoton's sample startup_M251.S file handles enough initialization for
my purposes, so I can completely bypass _start and jump directly to
main. Note that I also had to add a define to enable clearing of BSS.
The default values for SystemCoreClock, CyclesPerUs, and PllClock work
fine for my purposes of running from the 48 MHz HIRC. Remove unnecessary
initialization code. This is especially useful for the bootloader where
flash space is at a premium.
Also strip out unneeded UART setup code.
This will be used during firmware updates so that the main firmware can
communicate to the bootloader that it should stay in the bootloader for
a firmware update rather than run the main firmware again.
The problem is that over time, the meaning of curChipType has changed.
It was originally meant to exactly map to chips (four SST39SF040 chips
or four M29F160FB5AN6E2 chips) but over time its meaning has shifted to
simply indicating whether the unlock address needs to be shifted or not.
When curChipType is ParallelFlash_SST39SF040_x4, sometimes the
programming size is 4 MB or 8 MB. So don't restrict it to 2 MB.
Note that the erase sector sizes are just plain wrong in this case. In
the future I should read the chip ID and keep a table of sector sizes
for each known chip ID.
This README contains an overall summary of the entire project, but it
was missing build instructions for the firmware. Add them now that cmake
is all set up.
This allows building with CMake instead of Eclipse. The reasoning behind
this is to make the code more easily portable to other architectures,
and to move away from being dependent on Eclipse.
The 646 and 1286 have different required USB PLL values when you have a
16 MHz crystal. Detect the chip at runtime to set up the PLL correctly.
This requires taking over control of the PLL from LUFA.
A whole bunch of files in this project had DOS line endings. This is due
to how I started working on it on a Windows machine with little Git
experience. Now it's inconsistent so I'm fixing it.
I noticed that after I implemented the SPI optimization of cycle
counting instead of polling on SPIF, the first "normal" SPI transaction
I tried would fail. This is because nothing was clearing the SPIF flag
anymore, and the normal SPI driver still looks at it. So it was thinking
that the latest transaction was already completed (it wasn't). Worked
around this by making sure we clear the flag in SPI_Assert. I'm not
concerned about performance impact here because the actual clean SPI
driver is not used in performance-bound situations.
Fixed an issue that identified the wrong pins as shorted to ground in
the electrical test functionality. Whoops!
If multiple read or write cycles are done in sequence, we'll no longer
needlessly update the data direction registers (which is a slow SPI
transaction). We can also skip updating the pullups on the AVR if
multiple read cycles occur in sequence.
