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dingusppc/devices/memctrl/mpc106.cpp

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Updating files with proper licensing header
2020-02-28 16:04:28 +00:00
/*
DingusPPC - The Experimental PowerPC Macintosh emulator
pcihost: pull common code from Grackle.
2022-01-16 20:30:43 +00:00
Copyright (C) 2018-22 divingkatae and maximum
Updating files with proper licensing header
2020-02-28 16:04:28 +00:00
(theweirdo) spatium
(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
Add files via upload The first attempt at uploading new files.
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pcihost: pull common code from Grackle.
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/** MPC106 (Grackle) emulation. */
Add files via upload The first attempt at uploading new files.
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Move devices into dedicated subdirectories.
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#include <devices/common/hwcomponent.h>
#include <devices/common/mmiodevice.h>
MPC106: self-registration with the device registry.
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#include <devices/deviceregistry.h>
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#include <devices/memctrl/memctrlbase.h>
#include <devices/memctrl/mpc106.h>
#include <memaccess.h>
Add files via upload The first attempt at uploading new files.
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#include <cinttypes>
clang-format everything
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#include <cstring>
#include <iostream>
Fix includes for loguru and SDL.
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#include <loguru.hpp>
MPC106: insert PCI devices using the CLI.
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#include <string>
#include <vector>
Worked more on Grackle, ESCC, and OpenPIC
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MPC106: use common PCI configuration code.
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MPC106::MPC106() : MemCtrlBase(), PCIDevice("Grackle"), PCIHost()
pcihost: pull common code from Grackle.
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{
Simplify registration of HW component types.
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supports_types(HWCompType::MEM_CTRL | HWCompType::MMIO_DEV |
HWCompType::PCI_HOST | HWCompType::PCI_DEV);
MPC106: use common PCI configuration code.
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// populate PCI config header
this->vendor_id = PCI_VENDOR_MOTOROLA;
this->device_id = 0x0002;
this->class_rev = 0x06000040;
this->cache_ln_sz = 8;
this->command = 6;
this->status = 0x80;
// add PCI/ISA I/O space, 64K for now
Add support for PCI I/O space.
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add_mmio_region(0xFE000000, 0x10000, this);
MPC106: use common PCI configuration code.
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// add memory mapped I/O region for MPC106 registers
Rewrite MPC106 emualation from scratch. From now on, ppcmemory delegates physical address translation to MPC106 on PowerMac Beige G3.
2019-08-21 06:33:01 +00:00
add_mmio_region(0xFEC00000, 0x300000, this);
}
Update for July 11, 2019 - Fixed the floating point operations dispatch table and filled in a lot of missing gaps - Started overhauling floating point emulation - Minor fixes for Grackle reading and writing, mostly writing - Handle integer division by zero cases
2019-07-12 05:27:14 +00:00
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int MPC106::device_postinit()
{
std::string pci_dev_name;
static const std::map<std::string, int> pci_slots = {
{"pci_A1", 0xD}, {"pci_B1", 0xE}, {"pci_C1", 0xF}
};
for (auto& slot : pci_slots) {
pci_dev_name = GET_STR_PROP(slot.first);
if (!pci_dev_name.empty()) {
this->attach_pci_device(pci_dev_name, slot.second);
}
}
return 0;
}
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
void MPC106::cfg_setup(uint32_t offset, int size, int &bus_num, int &dev_num, int &fun_num, uint8_t &reg_offs, AccessDetails &details, PCIDevice *&device)
{
device = NULL;
details.size = size;
details.offset = offset & 3;
bus_num = (this->config_addr >> 8) & 0xFF;
dev_num = (this->config_addr >> 19) & 0x1F;
fun_num = (this->config_addr >> 16) & 0x07;
reg_offs = (this->config_addr >> 24) & 0xFC;
if (bus_num) {
details.flags = PCI_CONFIG_TYPE_1;
device = pci_find_device(bus_num, dev_num, fun_num);
}
else {
details.flags = PCI_CONFIG_TYPE_0;
if (dev_num == 0 && fun_num == 0) {
device = this; // dev_num 0 is assigned to myself
}
else if (this->dev_map.count(dev_num)) {
device = this->dev_map[dev_num];
}
}
}
Fix read/write argument names base class uses reg_start so derived classes should do the same. Some derived class already uses reg_start for read method.
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uint32_t MPC106::read(uint32_t rgn_start, uint32_t offset, int size) {
Add support for PCI I/O space.
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uint32_t result;
Fix read/write argument names base class uses reg_start so derived classes should do the same. Some derived class already uses reg_start for read method.
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if (rgn_start == 0xFE000000) {
MPC106: use common PCI configuration code.
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// broadcast I/O request to devices that support I/O space
// until a device returns true that means "request accepted"
Add support for PCI I/O space.
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for (auto& dev : this->io_space_devs) {
if (dev->pci_io_read(offset, size, &result)) {
return result;
}
}
LOG_F(ERROR, "Attempt to read from unmapped PCI I/O space, offset=0x%X", offset);
clang-format everything
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} else {
Add support for PCI I/O space.
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if (offset >= 0x200000) {
clang-format everything
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if (this->config_addr & 0x80) // process only if bit E (enable) is set
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
return pci_read(offset, size);
Add support for PCI I/O space.
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}
Update for July 7, 2019 The following fixes and changes have been made - Better Grackle emulation (though far from perfect) - OpenPIC write/read fixes - DAVBus Stubs - Started splitting functionality from the main routine, to slowly make way for a GUI-based version - Added a new until command argument - Fixed an entry in the floating point instruction dispatch table - CMakeLists.txt added
2019-07-07 06:10:32 +00:00
}
MPC106: use common PCI configuration code.
2022-03-13 21:22:53 +00:00
// FIXME: reading from CONFIG_ADDR is ignored for now
Rewrite MPC106 emualation from scratch. From now on, ppcmemory delegates physical address translation to MPC106 on PowerMac Beige G3.
2019-08-21 06:33:01 +00:00
Update for July 7, 2019 The following fixes and changes have been made - Better Grackle emulation (though far from perfect) - OpenPIC write/read fixes - DAVBus Stubs - Started splitting functionality from the main routine, to slowly make way for a GUI-based version - Added a new until command argument - Fixed an entry in the floating point instruction dispatch table - CMakeLists.txt added
2019-07-07 06:10:32 +00:00
return 0;
Add files via upload The first attempt at uploading new files.
2019-07-02 02:15:33 +00:00
}
Fix read/write argument names base class uses reg_start so derived classes should do the same. Some derived class already uses reg_start for read method.
2022-08-22 10:16:31 +00:00
void MPC106::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) {
if (rgn_start == 0xFE000000) {
MPC106: use common PCI configuration code.
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// broadcast I/O request to devices that support I/O space
// until a device returns true that means "request accepted"
Add support for PCI I/O space.
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for (auto& dev : this->io_space_devs) {
if (dev->pci_io_write(offset, value, size)) {
return;
}
}
LOG_F(ERROR, "Attempt to write to unmapped PCI I/O space, offset=0x%X", offset);
clang-format everything
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} else {
Add support for PCI I/O space.
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if (offset < 0x200000) {
this->config_addr = value;
clang-format everything
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} else {
if (this->config_addr & 0x80) // process only if bit E (enable) is set
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
return pci_write(offset, value, size);
Add support for PCI I/O space.
2020-03-31 19:12:06 +00:00
}
Update for July 7, 2019 The following fixes and changes have been made - Better Grackle emulation (though far from perfect) - OpenPIC write/read fixes - DAVBus Stubs - Started splitting functionality from the main routine, to slowly make way for a GUI-based version - Added a new until command argument - Fixed an entry in the floating point instruction dispatch table - CMakeLists.txt added
2019-07-07 06:10:32 +00:00
}
Worked more on Grackle, ESCC, and OpenPIC
2019-07-15 00:05:10 +00:00
}
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
uint32_t MPC106::pci_read(uint32_t offset, uint32_t size) {
int bus_num, dev_num, fun_num;
uint8_t reg_offs;
AccessDetails details;
PCIDevice *device;
cfg_setup(offset, size, bus_num, dev_num, fun_num, reg_offs, details, device);
details.flags |= PCI_CONFIG_READ;
if (device) {
return pci_cfg_rev_read(device->pci_cfg_read(reg_offs, details), details);
Rewrite MPC106 emualation from scratch. From now on, ppcmemory delegates physical address translation to MPC106 on PowerMac Beige G3.
2019-08-21 06:33:01 +00:00
}
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
LOG_READ_NON_EXISTENT_PCI_DEVICE();
return 0xFFFFFFFFUL; // PCI spec §6.1
Worked more on Grackle, ESCC, and OpenPIC
2019-07-15 00:05:10 +00:00
}
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
void MPC106::pci_write(uint32_t offset, uint32_t value, uint32_t size) {
int bus_num, dev_num, fun_num;
uint8_t reg_offs;
AccessDetails details;
PCIDevice *device;
cfg_setup(offset, size, bus_num, dev_num, fun_num, reg_offs, details, device);
details.flags |= PCI_CONFIG_WRITE;
if (device) {
uint32_t oldvalue = details.size == 4 ? 0 : device->pci_cfg_read(reg_offs, details);
pcihost: refactor data access helpers.
2023-01-31 22:20:31 +00:00
value = pci_cfg_rev_write(oldvalue, value, details);
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
device->pci_cfg_write(reg_offs, value, details);
Rewrite MPC106 emualation from scratch. From now on, ppcmemory delegates physical address translation to MPC106 on PowerMac Beige G3.
2019-08-21 06:33:01 +00:00
return;
Worked more on Grackle, ESCC, and OpenPIC
2019-07-15 00:05:10 +00:00
}
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
LOG_WRITE_NON_EXISTENT_PCI_DEVICE();
Add files via upload The first attempt at uploading new files.
2019-07-02 02:15:33 +00:00
}
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
uint32_t MPC106::pci_cfg_read(uint32_t reg_offs, AccessDetails &details) {
Rewrite MPC106 emualation from scratch. From now on, ppcmemory delegates physical address translation to MPC106 on PowerMac Beige G3.
2019-08-21 06:33:01 +00:00
#ifdef MPC106_DEBUG
Remove unnecessary linefeeds from log To remove blank lines in the dingusppc.log file or in the console output when -d is used.
2022-08-14 12:26:56 +00:00
LOG_F(9, "read from Grackle register %08X", reg_offs);
Rewrite MPC106 emualation from scratch. From now on, ppcmemory delegates physical address translation to MPC106 on PowerMac Beige G3.
2019-08-21 06:33:01 +00:00
#endif
Add files via upload The first attempt at uploading new files.
2019-07-02 02:15:33 +00:00
MPC106: use common PCI configuration code.
2022-03-13 21:22:53 +00:00
if (reg_offs < 64) {
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
return PCIDevice::pci_cfg_read(reg_offs, details);
MPC106: use common PCI configuration code.
2022-03-13 21:22:53 +00:00
}
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
uint32_t value = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[reg_offs]);
if ((reg_offs >= 0x80 && reg_offs <= 0xA0) || reg_offs == 0xF0) {
return value;
}
LOG_READ_UNIMPLEMENTED_CONFIG_REGISTER_WITH_VALUE();
return value;
Worked more on Grackle, ESCC, and OpenPIC
2019-07-15 00:05:10 +00:00
}
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
void MPC106::pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details) {
Rewrite MPC106 emualation from scratch. From now on, ppcmemory delegates physical address translation to MPC106 on PowerMac Beige G3.
2019-08-21 06:33:01 +00:00
#ifdef MPC106_DEBUG
Remove unnecessary linefeeds from log To remove blank lines in the dingusppc.log file or in the console output when -d is used.
2022-08-14 12:26:56 +00:00
LOG_F(9, "write %08X to Grackle register %08X", value, reg_offs);
Rewrite MPC106 emualation from scratch. From now on, ppcmemory delegates physical address translation to MPC106 on PowerMac Beige G3.
2019-08-21 06:33:01 +00:00
#endif
MPC106: use common PCI configuration code.
2022-03-13 21:22:53 +00:00
if (reg_offs < 64) {
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
PCIDevice::pci_cfg_write(reg_offs, value, details);
MPC106: use common PCI configuration code.
2022-03-13 21:22:53 +00:00
return;
}
Rewrite MPC106 emualation from scratch. From now on, ppcmemory delegates physical address translation to MPC106 on PowerMac Beige G3.
2019-08-21 06:33:01 +00:00
// FIXME: implement write-protection for read-only registers
MPC106: use memaccess thoroughly.
2021-02-03 22:39:19 +00:00
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
uint32_t *addr = (uint32_t *)&this->my_pci_cfg_hdr[reg_offs];
WRITE_DWORD_LE_A(addr, value);
MPC106: allocate RAM after software setup. Software will setup MPC106 internal registers and finally set MCCR1[MEMGO] flag. This is the right time for initializing physical RAM.
2019-10-07 01:21:01 +00:00
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
if ((reg_offs >= 0x80 && reg_offs <= 0xA0) || reg_offs == 0xF0) {
if (this->my_pci_cfg_hdr[0xF2] & 8) {
MPC106: allocate RAM after software setup. Software will setup MPC106 internal registers and finally set MCCR1[MEMGO] flag. This is the right time for initializing physical RAM.
2019-10-07 01:21:01 +00:00
#ifdef MPC106_DEBUG
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
LOG_F(9, "MPC106: MCCR1[MEMGO] was set!");
MPC106: allocate RAM after software setup. Software will setup MPC106 internal registers and finally set MCCR1[MEMGO] flag. This is the right time for initializing physical RAM.
2019-10-07 01:21:01 +00:00
#endif
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
setup_ram();
}
return;
MPC106: allocate RAM after software setup. Software will setup MPC106 internal registers and finally set MCCR1[MEMGO] flag. This is the right time for initializing physical RAM.
2019-10-07 01:21:01 +00:00
}
Fix PCI config r/w of byte and word and unaligned. dingusppc could not read bytes from offset 1,2,3 or words from offset 2. dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3. This commit fixes those issues. - Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412) A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written. - Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified. Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev. read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106. write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106. pcidevice: - The logging macros should be used to handle all config register access logging. - Unaligned PCI config register accesses will be output as ERROR instead of WARNING. - The logging macros include the offset and size. They also include the value for named registers or for writes. - Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO. pcihost: - Added pci_find_device stub for handling PCI bridges in future commit. bandit and mpc106: - PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes. bandit: - Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class. - Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract. - Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device. - For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does). mpc106: - Common config space code is put in cfg_setup. It handles extracting the offset. - Added code to log access to unimplemented config registers of grackle. - Don't call setup_ram when writing to config registers that setup_ram doesn't use. - pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian. atirage: - The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2022-09-02 10:32:28 +00:00
LOG_WRITE_UNIMPLEMENTED_CONFIG_REGISTER();
Add files via upload The first attempt at uploading new files.
2019-07-02 02:15:33 +00:00
}
MPC106: add support for PCI devices.
2019-08-23 19:30:30 +00:00
clang-format everything
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void MPC106::setup_ram() {
MPC106: allocate RAM after software setup. Software will setup MPC106 internal registers and finally set MCCR1[MEMGO] flag. This is the right time for initializing physical RAM.
2019-10-07 01:21:01 +00:00
uint32_t mem_start, mem_end, ext_mem_start, ext_mem_end, bank_start, bank_end;
uint32_t ram_size = 0;
clang-format everything
2020-05-12 18:55:45 +00:00
uint8_t bank_en = this->my_pci_cfg_hdr[0xA0];
MPC106: allocate RAM after software setup. Software will setup MPC106 internal registers and finally set MCCR1[MEMGO] flag. This is the right time for initializing physical RAM.
2019-10-07 01:21:01 +00:00
for (int bank = 0; bank < 8; bank++) {
if (bank_en & (1 << bank)) {
if (bank < 4) {
clang-format everything
2020-05-12 18:55:45 +00:00
mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x80]);
Add aligned macros for reading ints from memory.
2020-01-13 02:04:06 +00:00
ext_mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x88]);
clang-format everything
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mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x90]);
ext_mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x98]);
MPC106: allocate RAM after software setup. Software will setup MPC106 internal registers and finally set MCCR1[MEMGO] flag. This is the right time for initializing physical RAM.
2019-10-07 01:21:01 +00:00
} else {
clang-format everything
2020-05-12 18:55:45 +00:00
mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x84]);
Add aligned macros for reading ints from memory.
2020-01-13 02:04:06 +00:00
ext_mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x8C]);
clang-format everything
2020-05-12 18:55:45 +00:00
mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x94]);
ext_mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x9C]);
MPC106: allocate RAM after software setup. Software will setup MPC106 internal registers and finally set MCCR1[MEMGO] flag. This is the right time for initializing physical RAM.
2019-10-07 01:21:01 +00:00
}
bank_start = (((ext_mem_start >> bank * 8) & 3) << 30) |
(((mem_start >> bank * 8) & 0xFF) << 20);
bank_end = (((ext_mem_end >> bank * 8) & 3) << 30) |
(((mem_end >> bank * 8) & 0xFF) << 20) | 0xFFFFFUL;
if (bank && bank_start != ram_size)
Remove unnecessary linefeeds from log To remove blank lines in the dingusppc.log file or in the console output when -d is used.
2022-08-14 12:26:56 +00:00
LOG_F(WARNING, "MPC106: RAM not contiguous!");
MPC106: fix RAM size calculation.
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ram_size += bank_end - bank_start + 1;
MPC106: allocate RAM after software setup. Software will setup MPC106 internal registers and finally set MCCR1[MEMGO] flag. This is the right time for initializing physical RAM.
2019-10-07 01:21:01 +00:00
}
}
if (!this->add_ram_region(0, ram_size)) {
Improve previous (cosmetics & code duplication).
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LOG_F(WARNING, "MPC106 RAM allocation 0x%X..0x%X failed (maybe already exists?)",
0, ram_size - 1);
MPC106: allocate RAM after software setup. Software will setup MPC106 internal registers and finally set MCCR1[MEMGO] flag. This is the right time for initializing physical RAM.
2019-10-07 01:21:01 +00:00
}
}
MPC106: self-registration with the device registry.
2022-07-17 03:33:06 +00:00
MPC106: insert PCI devices using the CLI.
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static const PropMap Grackle_Properties = {
{"pci_A1",
new StrProperty("")},
{"pci_B1",
new StrProperty("")},
{"pci_C1",
new StrProperty("")},
};
MPC106: self-registration with the device registry.
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static const DeviceDescription Grackle_Descriptor = {
MPC106: insert PCI devices using the CLI.
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MPC106::create, {}, Grackle_Properties
MPC106: self-registration with the device registry.
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};
REGISTER_DEVICE(Grackle, Grackle_Descriptor);