Commit Graph

915 Commits

Author SHA1 Message Date
Maxim Poliakovski
616d0728fd videoctrl: support guest rendered HW cursors. 2023-04-07 23:16:18 +02:00
Maxim Poliakovski
74a49d1568 atirage: major refactoring. 2023-04-07 23:16:18 +02:00
Maxim Poliakovski
3e545bdef9 Handling host events in video controllers. 2023-04-02 03:01:13 +02:00
Maxim Poliakovski
f1c898b17e Initial host event manager. 2023-04-02 03:01:13 +02:00
Maxim Poliakovski
49f47c5f3f bandit: attach devices from the CLI. 2023-04-02 03:01:13 +02:00
Maxim Poliakovski
888d919ae7 videoctrl: refactor palette access. 2023-04-02 03:01:13 +02:00
Maxim Poliakovski
e01fea87a9 More bitops. 2023-04-02 03:01:13 +02:00
dingusdev
f181e721b0 Fixed compilation for Visual Studio 2023-03-19 07:55:26 -07:00
Maxim Poliakovski
9fcf5ba51a ppcmmu: fix bug in mmu_change_mode(). 2023-02-15 02:18:31 +01:00
Maxim Poliakovski
094b3b5312 Fix Cuda response protocol. 2023-02-08 21:26:11 +01:00
Maxim Poliakovski
7e5451a97d Cosmetics: break long lines, fix indentation. 2023-02-08 11:41:37 +01:00
Maxim Poliakovski
8231ecd466
Merge pull request #43 from joevt/PCI-bridge-and-multi-function-support
Pci bridge and multi function support
2023-02-07 00:41:50 +01:00
joevt
1d33ea2beb Grackle: Update readme. 2023-02-05 07:17:29 -08:00
joevt
bee24b166d Add method to attach PCI device with new name.
- Added an overloaded version of attach_pci_device which takes a suffix string that can be used to make a device name unique so that multiple devices of the same class can be added to a machine. The method returns a PCIDevice which can be easily used to attach more PCI devices if it is a PCIHost.
2023-02-05 07:17:29 -08:00
joevt
f61854a0ae Add has_io_space flag.
PCIDevice
- supports_io_space method now uses a flag has_io_space which is automatically set for PCI bridges or PCI devices that have an I/O BAR.

atirage
- Devices that have I/O BARs don't need a supports_io_space method.

mpc106
- Devices that don't have I/O methods don't need a supports_io_space method.
2023-02-05 07:17:28 -08:00
joevt
99eb93f9e1 Add set_irq_pin method.
A multi-function device may have functions of the same class (e.g. a USB device with two OHCI functions) but each function should be initialized with a different interrupt pin.
2023-02-05 07:17:28 -08:00
joevt
be45a6a020 Add PCI bridge and multi-function device support.
Add PCI bridge and multi-function device support.
Overview:
- A multi-function device is two or more PCIDevices with the same device number but one device is function zero (as with currently implemented PCIDevices) and the other functions have function numbers between 1 and 7. The device number and function number are properties of the PCIDevice's parent PCIHost connection.
- A PCIBridge is a PCIHost (it can connect child PCI devices) and a PCIDevice (it has config space, BARs, and expansion ROM).
- A PCIDevice has Type 0 header. It has 6 BARs.
- A PCIBridge has Type 1 header. It has 2 BARs. The config space registers beginning from offset 0x18 differ from those of a PCIDevice.

Possible future modifications:
- Add a PCICardBus class. It is a PCIHost. It has Type 2 header. It has one BAR. The first 20 bytes match Type 0 and Type 1 headers. These exist in New World Macs. They allow hot-plug of PCI devices.
- Split base PCI registers (first 16 bytes) into a PCIBase class. Type 1 and 2 have two or one BAR but I think all 6 BARs belong in PCIBase class anyway.
- Split PCIHost into two classes: Currently existing PCIHosts (Bandit, Grackle) are PCIHost and PCIRoot (they have the broadcast I/O requests functionality) while PCIBridge is PCIHost only - it can propagate I/O requests but does not originate the broadcast.
- pci_register_mmio_region should maybe return a pointer to a region struct so that it can be used for unregistering or modifying the region's range. This may be useful for PCI bridges which have ranges that may constrain memory BARs of their downstream devices.

PCIDevice
- Moved expansion ROM BAR handling to a separate function pci_wr_exp_rom_bar so that it can be used by both PCI devices and PCI bridges which have the ROM BAR in different locations. It now supports unmapping expansion ROM. Also made exp_rom_bar not writable if there's no ROM.
- Added num_bars field which specifies the number of valid BARs since Type 0, 1, and 2 headers have different number of BARs.
- map_exp_rom_mem now properly unmaps expansion ROM (using new function unmap_exp_rom_mem) before mapping it again.
- Added function set_multi_function which modifies hdr_type to indicate if a device has other functions. This is to be applied only to devices with function number 0.

PCIHost
- When attaching a PCI device, it will check if it's a multi-function device (there exists an attached function that is not zero) and adjust hdr_type of function 0 of the device accordingly.
- Attached PCI bridges are added to a list of PCI bridges attached to the host.
- Added pci_io_read_loop and pci_io_write_loop which loop through attached PCI devices to find one that will perform the action for the given I/O address without logging an error (since some other device might perform the action).
- Added pci_io_read_broadcast and pci_io_write_broadcast which are used by a PCI root (bandit/grackle). They will log an error if the action is not performed. They should probably do a machine check exception to match real Power Macs.
- pci_find_device (used by PCI root) will recursively find a PCIDevice for type 1 config register accesses.
- Logging from PCIHost now includes the name of the PCIHost instead of just "PCIHost" because there can be multiple PCI hosts.

PCIBridge
- Sets num_bars to 2 and hdr_type to 1.
- I/O ranges set in the config registers are handled correctly by pci_io_read and pci_io_write.
- Memory ranges set in the config registers do not currently affect memory mmio regions. It is assumed that Open Firmware and the OS will set the ranges and BARs correctly to allow all BARs to be accessed fully.

bandit, mpc106
- Bandit and Grackle now call pci_io_read_broadcast and pci_io_read_broadcast to pass I/O accesses to downstream PCI devices.
- Chaos is modified to work like Bandit even though it will never have PCI bridges attached or devices that support I/O accesses. It's simpler this way.
2023-02-05 07:17:28 -08:00
joevt
b472123746 Standardize PCIDevice slot_id for PCIHost.
PCIHost
- PCIHosts (bandit and grackle) now use device number and function number for identifying attached PCIDevices. A macro DEV_FUN is added to calculate this new slot_id. Bandit no longer uses IDSEL. Grackle no longer uses only device number.

machinecatalyst, machinegossamer, machinetnt
- Use DEV_FUN to attach PCI devices by device number and function number.
2023-02-05 06:57:04 -08:00
joevt
fd2e6c5b09 Fix ATIRage I/O accesses.
- Don't log anything if the I/O access is not for this device. A different device might handle it.
- Don't return true for I/O access if an I/O access is not performed. Otherwise the I/O access won't be passed to other devices.
2023-02-05 01:22:01 -08:00
joevt
f7280c316b Fix 64 bit BAR.
A 64 bit BAR has least significant 32 bits first as in the original pull request.
2023-02-05 01:22:01 -08:00
Maxim Poliakovski
cc17035e67 pcidevice: improve BAR configuration. 2023-02-04 17:57:46 +01:00
Maxim Poliakovski
654ff0219c
Merge pull request #42 from joevt/64-bit-BARs
64 bit BAR support
2023-02-04 12:43:57 +01:00
joevt
8862a73ef1 Merge remote-tracking branch 'upstream/master' into 64-bit-BARs 2023-02-02 21:14:05 -08:00
Maxim Poliakovski
5e61b473f0 mpc106: support reading back CONFIG_ADDR. 2023-02-02 12:45:44 +01:00
joevt
2a64f547cc Add 64-bit BAR support.
While dingusppc only emulates 32-bit Macs (for now), it is possible for a 32-bit Power Mac to use a PCIe card that has 64-bit BARs.

finish_config_bars is added to scan the cfg values of the BARs and determine their type. The type is stored separately so that it does not need to be determined again.
The type can be I/O (16 or 32 bit) or Mem (20 or 32 or 64 bit). A 64 bit bar is two BARs, the second contains the most significant 32 bits.

set_bar_value uses the stored type instead of trying to determine the type itself. It is always called even when the firmware is doing sizing. For sizing, It does the job of setting the bar value so do_bar_sizing is now just a stub.

Every PCIDevice that has a BAR needs to call finish_config_bars after setting up the cfg values just as they need to setup the cfg values. Since they need to do both, maybe the cfg values should be arguments of finish_config_bars, then finish_config_bars() should be renamed config_bars().
2023-02-02 02:47:34 -08:00
joevt
fba2ff4231 Corrections for refactors.
- Macros need parenthesis to enforce operation order when expanded.
- Fix device and register numbers in log messages.
- Unmapped I/O space reads don't necessarily return 0xffffffff. That's only for config space reads. Just return 0. Unhandled I/O space read should probably cause a memory check (TEA - Transfer Error Acknowledge) exception as it does on a Power Mac 8600.
2023-02-02 02:47:34 -08:00
Maxim Poliakovski
e64aab1577 Rename data conversion helpers for PCI config.
Reword some descriptions for better understanding.
2023-02-02 02:22:47 +01:00
Maxim Poliakovski
36dee46e9b mpc106: refactor PCI read and write methods. 2023-02-02 02:22:47 +01:00
Maxim Poliakovski
99e92a5679 mpc106: rewrite control registers handling. 2023-02-02 00:21:55 +01:00
Maxim Poliakovski
ec97a671d8 bandit: refactor host read and write methods. 2023-02-01 16:21:49 +01:00
Maxim Poliakovski
31db015105 pcihost: refactor data access helpers. 2023-01-31 23:20:31 +01:00
Maxim Poliakovski
289ddf10b7 bandit: clean up PCI device connection. 2023-01-23 14:06:39 +01:00
Maxim Poliakovski
699b62373a
Merge pull request #41 from joevt/fix-pci-unaligned
Fix PCI config r/w of byte and word and unaligned.
2023-01-23 13:26:06 +01:00
joevt
4100a80f96 Fix PCI config r/w of byte and word and unaligned.
dingusppc could not read bytes from offset 1,2,3 or words from offset 2.
dingusppc did not read words from offset 1,3 and longs from offset 1,2,3 in the same way as a real Power Mac 8600 or B&W G3.
This commit fixes those issues.

- Added pci_cfg_rev_read. It takes a 32 bit value from offset 0 and returns a value of the specified size using bytes starting from the specified offset. Offsets 4,5, & 6 wrap around to 0,1, & 2 respectively. The result bytes are in flipped order as required by the read method (so a value of 0x12345678 is returned as 0x78563412)
A real Power Mac 8600 might return a random byte for offset 4, 5, 6 for vci0 but usually not for pci1. A B&W G3 seems to always wrap around correctly. We won't read random bytes, and we won't read a default such as 00 or FF. We'll do the wrap around which makes the most sense because writing 0x12345678 to any offset and reading from the same offset should produce the value that was written.

- Added pci_cfg_rev_write. It takes a 32 bit value from offset 0, and modifies a specified number of bytes starting at a specified offset with the offset wrapping around to 0 if it exceeds 3. The modified bytes take their new values from the flipped bytes passed to pci_cfg_write. When size is 4, the original value is not used since all bytes will be modified.

Basically, those two functions handle all the sizes and all the offsets and replace calls to BYTESWAP_32, read_mem or read_mem_rev, and write_mem or write_mem_rev.
read_mem_rev, as it was used by pcidevice and some other places, could read beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always read the wrong byte or word if they were not at offset 0. Same for read_mem as used by mpc106.
write_mem_rev, as it was used by pcidevice and some other places, could write beyond offset 3 if it were ever passed a reg_offs value that did not have offset as 0. Since the offset was always zero, it would always write the wrong byte or word if they were not at offset 0. Same for write_mem as used by mpc106.

pcidevice:
- The logging macros should be used to handle all config register access logging.
- Unaligned PCI config register accesses will be output as ERROR instead of WARNING.
- The logging macros include the offset and size. They also include the value for named registers or for writes.
- Added MMIODevice read and write methods so that PCIDevice is not abstract if a PCIDevice doesn't override the read and write method since some PCIDevices don't have MMIO.

pcihost:
- Added pci_find_device stub for handling PCI bridges in future commit.

bandit and mpc106:
- PCI host controllers will handle all PCI config access alignment and sizing. A PCIDevice will always access config registers as 32 bits on a 4 byte boundary. The AccessDetails passed to a PCIDevice config read or write method is there only for logging purposes.

bandit:
- Common MMIO code is moved to new BanditHost class so both Bandit and Chaos can use it. PCI related code is moved to new BanditPCI class.
- Simplify IDSEL to/from PCI device number conversion by removing the shift or subtract.
- Remove BANDIT_ID_SEL check. The IDSEL conversion to PCI device number can find the bandit PCI device.
- For logging, make best guess of PCI device number from invalid IDSEL - the result is always reasonable for device 0x00 to 0x0A when accessing config register 0x00 (as one would do when scanning for PCI devices like lspci does).

mpc106:
- Common config space code is put in cfg_setup. It handles extracting the offset.
- Added code to log access to unimplemented config registers of grackle.
- Don't call setup_ram when writing to config registers that setup_ram doesn't use.
- pci_cfg_read calls READ_DWORD_LE_A and pci_cfg_write calls WRITE_DWORD_LE_A. When reading or writing memory that is organized as little endian dwords, such as my_pci_cfg_hdr of mpc106, the function should explicitly state that it's little endian so that the emulator may be ported one day to a CPU architecture that is not little endian.

atirage:
- The changes correctly place user_cfg at byte 0x40 instead of 0x43 and writes the correct byte depending on size and offset.
2023-01-16 00:09:44 -08:00
Maxim Poliakovski
136aeca8f2 Fix Gossamer system register. 2023-01-11 23:49:20 +01:00
Maxim Poliakovski
8d01440558 Improve previous (cosmetics & code duplication). 2023-01-11 23:36:16 +01:00
Maxim Poliakovski
e510c11be2
Merge pull request #40 from joevt/master
Gazelle fixes, PCI changes and additions, MMIO changes, etc.
2023-01-11 23:05:15 +01:00
joevt
19adb54cd8 Fix compiler warnings.
These were detected by github Actions but not by Xcode.
2023-01-11 01:17:13 -08:00
joevt
f2db6bd066 Add missing header. 2023-01-11 01:17:13 -08:00
joevt
1b221bc0bd Fix compiler warnings: never executed. 2023-01-11 01:17:12 -08:00
joevt
85d0900d7d Fix compiler warnings: possible misuse of comma. 2023-01-11 01:17:12 -08:00
joevt
5294a8b71c Fix compiler warnings: unused variables. 2023-01-11 01:17:12 -08:00
joevt
46bc8567e9 Fix compiler warnings: uninitialized variables.
- mpc601_block_address_translation will now return 0 for prot and pa when bat_hit is false (when the if statement is not positive during the for loop). The calling function doesn't care what prot and pa are when bat_hit is false, but we do this to remove the compiler warining.
- For tlb_flush_entry, the compiler thinks m might not always be in the range 0 to 5 so tlb1 and tlb2 might not get initialized by the switch statement. Add default to get around this warning.
2023-01-11 01:17:12 -08:00
joevt
64fec88436 Fix compiler warnings: cast loses precision.
Use explicit cast when converting large integer types to smaller integer types when it is known that the most significant bytes are not required.
For pcidevice, check the ROM file size before casting to int. We'll allow expansion ROM sizes up to 4MB but usually they are 64K, sometimes 128K, rarely 256K.
for machinefactory, change the type to size_t so that it can correctly get the size of files that are larger than 4GB; it already checks the file size is 4MB before we need to cast to uint32_t.
For floppyimg, check the image size before casting to int. For raw images, only allow files up to 2MB. For DiskCopy42 images, it already checks the file size, so do the cast after that.
2023-01-11 01:17:12 -08:00
joevt
bd5a88f02f Ignore Xcode project files. 2023-01-11 01:17:12 -08:00
joevt
b61a7c4aea Log something from machine initialization.
The machine type and its corresponding source file name should appear once in the log output.
2023-01-11 01:17:12 -08:00
joevt
2f08a0b327 Fix Gossamer machineID allocation size.
When the allocation is logged, it will look appear like this:
Added mmio region 0xFF000004..0xFF000FFF (Machine-id)
instead of like this:
Added mmio region 0xFF000004..0xFF001003 (Machine-id)
2023-01-11 00:05:23 -08:00
joevt
52fa30b71d Add ability to unregister mmio region.
mmio regions are registered when a PCI BAR is set. Add the ability to reverse that - for when a PCI BAR is changed.
2023-01-11 00:05:23 -08:00
joevt
911acb4bc2 Remove MPC106 RAM allocation failed error.
It might not be an error - usually it just means that it was already allocated so demote this message to a warning.

Related memory allocation changes:
- Added find_range_exact which searches for an allocation that exactly matches a range.
- Added find_range_contains which searches for an allocation that is completely contained within a range.
- Added find_range_overlaps which searches for an allocation that overlaps any part of a range.
- Added is_range_free which is similar to the above three. It returns false if any allocated range overlaps a range. It reports the regions that it overlaps.
- Fix add_mem_region and add_memio_region so that they don't just check the first byte and last byte.
- Memory allocation logging should include the range (first byte..last byte) and device if possible.
- Log memory allocations.
2023-01-11 00:05:23 -08:00
joevt
0bd9d0e973 Fix HWComponent name initialization.
First, remove name override for subclasses of HWComponent (Chaos and ScsiBus) because HWComponent has its own name field.

HWComponent name should be set as early as possible in the constructor so it can be used in log messages.
PCIDevice should set name of HWComponent (through MMIODevice) in its constructor, using the name that is given to its constructor.
For Bandit and Grackle, they don't need to set the HWComponent name since its PCIDevice constructor will now do it.
Chaos is not a PCIDevice so it should set the MMIODevice name itself.
Why does PCIDevice have a name that is separate from the HWComponent name?
2023-01-11 00:05:23 -08:00