Commit Graph

1760 Commits

Author SHA1 Message Date
joevt
a5241d27c1 viacuda: Cleanup. 2024-04-21 06:03:32 -07:00
joevt
4479ecb1bb viacuda: One exit path for read. 2024-04-21 06:03:17 -07:00
joevt
b454ab45fe viacuda: Spelling. 2024-04-21 06:02:52 -07:00
joevt
d06d80619e viacuda: Add 1 Sec Timer, fix Get/Set Real Time.
GET_REAL_TIME was using the wrong offset and wasn't setting out_count.

May need to add time zone offset which could be different between host and guest.
get-time and set-time can be tested in Open Firmware.
SET_REAL_TIME is used by the Date/Time Control Panel when you change the date.
It is unknown what method Mac OS uses to get the time at boot. Mac OS 8.6 does not use GET_REAL_TIME during boot, so the time is left as 12:00 AM Jan 1, 1904.
2024-04-21 06:01:40 -07:00
Maxim Poliakovski
9a70c3bdb0
Remove bogus atirage128.cpp 2024-04-15 17:17:04 +02:00
dingusdev
103ef6169c Continued expanding zdocs 2024-04-15 07:52:09 -07:00
dingusdev
1a165ff64c Update manual.md 2024-04-15 07:28:30 -07:00
dingusdev
8cbbb2ed50 Initial preparation for a release 2024-04-15 07:01:51 -07:00
Maxim Poliakovski
781d9b46da athens: allow setting custom XTAL frequency. 2024-04-15 14:38:46 +02:00
Maxim Poliakovski
ffa221192d athens: use component's name in logging messages. 2024-04-15 14:21:08 +02:00
Maxim Poliakovski
751f964139 athens: clean up initialization. 2024-04-15 14:21:08 +02:00
joevt
14f75d834a macio: Add list of OHare/Heathrow bits. 2024-04-12 19:54:34 -07:00
Maxim Poliakovski
96efc99a00 control: clean up register bit definitions. 2024-04-11 17:50:50 +02:00
Maxim Poliakovski
45d2c8854d Revert "macio: Add fatman bits register."
This reverts commit 8aaf211c5b.
2024-04-11 17:18:20 +02:00
Maxim Poliakovski
c22843f238 appleramdac: vendor ID for AT&T fabbed RAMDACs. 2024-04-11 17:10:44 +02:00
joevt
1c5009fcb0 amic: Add more registers. 2024-04-10 20:59:34 -07:00
joevt
bd63d1dcda platinum: Validity check before enable display. 2024-04-10 20:56:51 -07:00
joevt
8aaf211c5b macio: Add fatman bits register.
This register is used in the control ndrv to detect presence of connected S-Video or composite video display.
2024-04-10 20:48:29 -07:00
joevt
8cc5838efe control: More register bits. 2024-04-10 20:48:12 -07:00
joevt
4b965c623b machinetnt: Add more Power Macs. 2024-04-10 20:36:59 -07:00
joevt
be27ceed00 machinetnt: Remove sixty6 and mesh properties.
Use the presence of the devices in the MachineDescription to determine these.
2024-04-10 20:19:43 -07:00
joevt
1d75730d44 dbdma: Do interrupt on main thread.
These may be triggered by other threads (such as for audio) so use the timer manager to handle them in the main thread.
2024-04-10 19:17:49 -07:00
joevt
95d74a6940 scsihd: Check Lun for INQUIRY.
INQUIRY now returns 0x7f for device type if LUN doesn't match. INQUIRY can get LUN from CDB or from IDENTIFY message.
2024-04-10 19:02:01 -07:00
joevt
c6ea3a374e control: Fix PAL/NTSC interlaced display. 2024-04-10 07:32:35 -07:00
joevt
e8ce805f2a poweropcodes: Remove power_setsoov.
None of the POWER opcodes uses it now, plus it is a duplicate of ppc_setsoov (though ppc_setsoov is inline so it would have to be moved to be able to use it in poweropcodes.cpp?
2024-04-10 07:30:06 -07:00
joevt
3d898ebdf3 poweropcodes: Cleanup power_rot_mask.
Use U instead of UL. U will use the smallest size that can fit all the unsigned bytes. Since 0xFFFFFFFF fits in 32 bits, the 0xFFFFFFFFU is a uint32_t.
2024-04-10 07:29:56 -07:00
joevt
f45b7c47c8 poweropcodes: Fix srq.
Test bit 26 of rB instead of testing for >= 0x20 to determine which operation to perform.
2024-04-10 07:29:46 -07:00
joevt
916cb47b9d poweropcodes: Fix srlq.
Test bit 26 of rB instead of testing for >= 0x20 to determine which operation to perform.
2024-04-10 07:29:37 -07:00
joevt
bce816139b poweropcodes: Fix sreq.
Including bits of rot_sh in the rA and MQ calculations is nonsensical since it is a rotation count and not a source of bits to be extracted or rotated.
The mask is not complicated, so we don't need to use power_rot_mask.
2024-04-10 07:29:28 -07:00
joevt
24bce16c4d poweropcodes: Fix srea.
Fix carry flag calculation. Anding with the rotation count (n = rB) is nonsensical.
(r & ~mask) is the rotated word ANDed with the complement of the generated mask of n zeros followed by 32 - n ones.
The manual says this 32-bit result is ORed together. This means all the bits are ORed together which is equivalent to saying 0 if all zeros and 1 if any ones. In other words: (r & ~mask) != 0.
This boolean is ANDed with bit 0 of rS to produce the carry. int32_t(rS) < 0 will test bit 0. The && operator will treat each side as a boolean so you can exclude "!= 0" tests.
2024-04-10 07:29:20 -07:00
joevt
a928c67913 poweropcodes: Fix sraq.
If bit 26 of rB is set then the mask should be all ones.
If bit 26 of rB is set then rA should be all ones or all zeros (depending on the sign bit of rA).
2024-04-10 07:29:11 -07:00
joevt
2b8f510603 poweropcodes: Fix slq.
Test bit 26 of rB instead of using >= 0x20 to determine which operation to perform.
The two operations need to be switched such that rA is cleared when bit 26 is set.
Don't forget to store the result in rA.
2024-04-10 07:28:58 -07:00
joevt
e8273ecc61 poweropcodes: Fix sllq.
Test bit 26 of rB instead of using >= 0x20 to determine which operation to perform.
Since the mask is not complicated, we don't need to use power_rot_mask.
2024-04-10 07:28:46 -07:00
joevt
e1f31a2da3 poweropcodes: Fix rrib.
It is redundant to test bit 0 of rS and then use bit 0 of rS in the case when bit 0 of rS is set.
In the case when bit 0 of rS is not set, using bit 0 or rS is incorrect since it results in no change of rA.
2024-04-10 07:26:52 -07:00
joevt
d897acfd3c poweropcodes: Fix nabs.
Calculate overflow first before calculating condition codes because the overflow condition is copied from XER.
2024-04-10 07:26:32 -07:00
joevt
1e57ac408a poweropcodes: Fix mul.
Operands are supposed to be twos complement numbers.
Calculate overflow first before calculating condition codes because the overflow condition is copied from XER.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations.
Fix CR calcalation. It's supposed to depend on the low order 32 bits that are placed into MQ.
2024-04-10 07:26:24 -07:00
joevt
ef8522e101 poweropcodes: Fix maskg.
The condition code register depends on rA, not rD since rA contains the result.
2024-04-10 07:26:16 -07:00
joevt
c71d856a08 poweropcodes: Fix lscbx.
- Fix CR calculation. It depends on whether a match occurred and only the EQ flag is affected.
- Remove bytes_copied. We can subtract bytes_remaining from bytes_to_load to calculate that.
- Initialize ppc_result_d to zero so that bitmask is not needed to add new bytes to it. This is ok since the manual says that bytes that are not loaded are undefined.
2024-04-10 07:26:07 -07:00
joevt
df7ff76404 poweropcodes: Fix doz.
Calculate overflow first before calculating condition codes because the overflow condition is copied from XER.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations. doz does a subtract but only if the result is supposed to be positive, therefore a negative result indicates an overflow.
2024-04-10 07:22:50 -07:00
joevt
0d1ce68d19 poweropcodes: Fix divs.
dividend and divisor are supposed to be a twos compliment numbers.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations.
Fix CR calculation. It depends on the remainder, not the quotient.
2024-04-10 07:22:41 -07:00
joevt
88aa249ce1 poweropcodes: Fix div.
dividend is supposed to be a twos compliment number.
Fix test for dividend = -0x80000000 and divisor = -1. Previously, the test was assuming dividend was a 32-bit value from rA.
Fix OV calculation. Previously, it was using power_setsoov which I think is only for add and subtract operations.
Fix CR calculation. It depends on the remainder, not the quotient.
2024-04-10 07:22:34 -07:00
joevt
ff626ae0b5 poweropcodes: Fix clcs.
For MPC601 CPUs, all values of rA return 64 though the manual says undefined values of rA produce undefined results.
For non-MPC601 CPUs, if this instruction is included (such as for risu DPPC) then return results that are obtained from a G4 running Mac OS 9.2.2.
2024-04-10 07:22:26 -07:00
joevt
529f23d836 poweropcodes: Fix abs.
Making a negative value positive requires unary negate operator rather than binary and operator since negative numbers are stored using twos compliment.
If ov is set then clear overflow when overflow doesn't happen.
2024-04-10 07:22:18 -07:00
joevt
cb88bab67d ppcopcodes: Fixes for SPRs.
- Rename DEC to DEC_S and add DEC_U.
- MQ, RTCL_U, RTCU_U, and DEC_U should cause an illegal instruction program exception for non-MPC601 CPUs. The exception handler of classic Mac OS uses this to emulate the instruction.
- For mtspr, the SPRs RTCL_U, RTCU_U, and DEC_U are treated as no-op on MPC601.
- For debugging, use the supervisor instead of the user SPR number as the index for storing the values for RTC, TB, and DEC.
- For debugging, RTC, TB, and DEC should be updated after each access. Previously, mfspr and mtspr would only update the half of RTC and TB that was being accessed instead of both halves.
2024-04-10 07:21:54 -07:00
joevt
67a5c39b1c ppcopcodes: Add Privileged exception for SPRs.
Accessing an SPR with bit 4 set (> 15) requires supervisor privilege and should cause a supervisor-level instruction exception (privileged instruction type program exception).
2024-04-10 07:21:23 -07:00
joevt
0273867c49 ppcopcodes: Cleanup ppc_changecrf0.
- Use one assignment to set ppc_state.cr.
- Use enums for CR and XER bits.
- Use < to check sign bit.
2024-04-10 06:47:10 -07:00
joevt
1e50d88183 ppcopcodes: Use macro to grab instruction fields. 2024-04-10 06:46:46 -07:00
joevt
29a832c68d ppcopcodes: Use < 0 instead of & 0x8000000. 2024-04-10 06:45:31 -07:00
joevt
cb05bd05eb cpu: Add ppc_grab_regssash macro.
This macro is like ppc_grab_regssa but includes rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
2024-04-10 06:43:34 -07:00
joevt
4f45d7de35 cpu: Add cpu options to ppc_cpu_init.
The first option is a flag that enables MPC601 (POWER) instructions for CPUs that are not MPC601.
This can be useful for the following reasons:
1) To produce results similar to classic Mac OS which emulates MPC601 instructions on CPUs that don't implement MPC601 instructions. This option is used to compare the risu traces produced in Mac OS 9 on a G3 or G4 with DPPC.
2) May increase performance in apps that use POWER instructions on emulated machines with CPUs that are not MPC601. It is not known if any such apps exist but there could be since Apple included MPC601 emulation in classic Mac OS.
2024-04-10 06:43:18 -07:00