Commit Graph

56 Commits

Author SHA1 Message Date
kanjitalk755
a51e030414 test alignas() 2020-10-03 12:22:23 +09:00
rakslice
d936e9938d SS: Fix JIT on minwg32
- add wrappers with default calling convention for powerpc_cpu member functions used through nv_mem_fun ptr()
** explicit wrappers for member functions that were used explicitly
** dynamic wrapper generator in nv_mem_fun1_t for member functions used dynamically via the instruction table
- add missing direct addressing (non-zero constant offset to Mac memory) support in lvx and stvx implementations
- fix mismatched parameter lists between powerpc_jit member functions and the calls they get through the jit_info table to fix problems at -O2
2020-03-17 17:45:38 -07:00
asvitkine
b2d58d423e Fix compile problem with --enable-jit=no 2010-09-24 00:36:34 +00:00
asvitkine
d6db773362 [patch from Darik Horn <dajhorn@vanadac.com> ]
Makes SheepShaver compatible with Ubuntu Intrepid and
other distros that bundle the gcc-4.3 compiler.

The patch changes two things:

1. Renames the block_cache where its name collides with its class
definition.

2. Fixes the "explicit template specialization cannot have a storage
class" error in the ppc-dyngen-ops.cpp file.
2009-01-15 23:25:08 +00:00
asvitkine
1002714623 Add frameskip 0 ("Dynamic") to MacOSX Prefs Editor, and fix line endings
and deprication warnings in the Objective-C code. Also, don't specify array
size with a macro in a header file.
2008-06-17 04:26:56 +00:00
gbeauche
9999881c78 Enable JIT in non-constructor so that a user-defined value can be set later 2007-01-21 13:44:27 +00:00
gbeauche
b9486d35e3 Rearrange powerpc_registers struct and nuke fp_result register which is
only needed for JIT (and to be handled differently in the future).
2007-01-17 07:05:19 +00:00
gbeauche
5b0b60da76 Remove specialised decoders. This will be done differently, if necessary. 2007-01-17 06:20:36 +00:00
gbeauche
e07e2196e3 Use new code generator. The gain is only 10%, bottlenecks are elsewhere.
Optimize Altivec vector splat instructions after Agner's guide.
2006-07-17 06:56:38 +00:00
gbeauche
cc12787047 Prepare for new code generator and mid-level optimizations. 2006-07-16 12:47:38 +00:00
gbeauche
7efab4276f Improve FPU emulation accurracy. However, PPC_ENABLE_FPU_EXCEPTIONS is still
set to 0 until generated code is optimized enough (current slow down factor
is 3x vs. previous core, expectations are about 50% slower FP code).

The main benefit is exception bits are accurate. All glibc test-fenv,
test-arith{,f}, test-double, test-float pass on ppc, and mostly on x86_64
with gcc 4.0.1. Yes, this is also compiler dependent.

FIXME: find a real Mac application that depends on precise FPSCR bits... I
think I don't want to care optimizing yet until someone shows me a real world
application.
2006-07-04 07:19:18 +00:00
gbeauche
dc3df920c5 Fix fctiw emulation (VEX's jm-ppc-test -f, handle current rounding mode) 2006-07-04 06:58:24 +00:00
gbeauche
3bd5d0c787 Instructions that trap are now an end-of-block condition. This should avoid
the compilation of illegal instructions and thus stopping execution earlier.
2006-05-06 07:19:39 +00:00
gbeauche
022d09375f Merge from KPX: new exit() handling code; make "syscall" illegal for MacOS
emulation (SheepShaver)
2006-01-28 21:57:52 +00:00
gbeauche
dd2b9a95d5 Align PowerPC registers struct manually, i.e. don't depend on non-portable
compiler extensions (e.g. GCC __attribute__((aligned(N)))).
2005-12-06 22:25:13 +00:00
gbeauche
b9b90fce11 fix last commit 2005-06-23 11:56:43 +00:00
gbeauche
2deca51ca4 Add code to gather some stats on register usage. 2005-06-23 11:37:01 +00:00
gbeauche
8db2a3ef62 implement lvsl/lvsr instructions 2005-04-15 17:03:49 +00:00
gbeauche
9019e71cfc Preserve all necessary registers on interrupt, thus also permitting nested
interrupts to occur. SheepShaver locks should now be reduced.
2005-03-05 15:25:10 +00:00
gbeauche
df0d5d2a41 Happy New Year 2005! 2005-01-30 21:48:22 +00:00
gbeauche
a8a235345c implement mcrxr instruction 2004-12-18 22:13:47 +00:00
gbeauche
c3f2342f47 Make NativeOp() handler a sheepshaver_cpu handler, thus getting rid of ugly
GPR macro definition.

Make the JIT engine somewhat reentrant. This brings a massive performance
boost for applications that cause many Execute68k(). e.g. audio in PlayerPRO.
2004-05-19 21:23:17 +00:00
gbeauche
08bcd2653d direct block chaining, aka faster block dispatcher 2004-05-11 20:53:25 +00:00
gbeauche
d10a3586f1 Year got increased "recently". ;-) 2004-02-16 10:57:07 +00:00
gbeauche
313cddeeb2 AltiVec emulation! ;-) 2004-02-15 17:17:37 +00:00
gbeauche
ea9553ee65 Optimize rlwinm further. Translate FP instructions if we don't need to
compute exceptions.
2004-01-25 23:21:06 +00:00
gbeauche
82808234fa Merge in FP exceptions support but disable it for now as it is incomplete
and slower. Implement mcrfs. Fix and optimize fctiw with native rounding.
2004-01-24 16:43:45 +00:00
gbeauche
60d371486b Propagate done_compile down to compile1() in case it needs to override
the end-of-block condition (e.g. sheep EmulOps)
2004-01-24 11:22:48 +00:00
gbeauche
07f0be19b5 Fix FP single operations. aka fix scrollbar & Graphing Calculator bugs. 2004-01-13 23:50:09 +00:00
gbeauche
5dca41d253 Add gen_invoke_CPU_im_im() to invoke do_record_step(pc, opcode). 2003-12-04 17:53:04 +00:00
gbeauche
7ebe0347bf Add "jit" prefs item. Fix PPC_DECODE_CACHE version to fill in new min_pc &
max_pc members of block info. Increase -finline-limit to 10000 for older gcc
2003-12-03 10:52:50 +00:00
gbeauche
04214f3820 Fix decrement the CTR, then branch conditional if decremented CTR != 0.
Remove CR cache for now. Remove BC & MODE_68K hacks for SheepShaver,
that was a colateral damage of wrong branch emulation of the former.
2003-12-02 22:49:18 +00:00
gbeauche
dd956c78db gather some stats on untranslated instructions 2003-12-01 13:07:26 +00:00
gbeauche
4a3cd024ed better handling of static translation cache allocation, handle nested
execution paths from the cpu core, cleanups for KPX_MAX_CPUS == 1.
2003-11-30 17:21:53 +00:00
gbeauche
73d51962f6 Merge in-progress PowerPC "JIT1" engine for AMD64, IA-32, PPC.
The merge probably got wrong as there are some problems probably due to the
experiment begining with CR deferred evaluation. With nbench/ppc, performance
improvement was around 2x. With nbench on x86, performance improvement was
around 4x on average.

Incompatible change: instr_info_t has a new field in the middle. But since
insertion of PPC_I(XXX) identifiers is auto-generated, there is no problem.
2003-11-24 23:45:52 +00:00
gbeauche
e9f3546539 Remove even more obsolete code. Drop TBL/TBU registers, they are manually
handled through the mftb instruction accessor.
2003-11-11 11:44:34 +00:00
gbeauche
cf0ed72f24 Remove obsolete code related to PPC_NO_FPSCR_UPDATE, PPC_LAZY_PC_UPDATE,
PPC_LAZY_CC_UPDATE, PPC_HAVE_SPLIT_CR defines.
2003-11-11 11:32:27 +00:00
gbeauche
42e1cabc94 Move variables for compile statistics to powerpc_cpu private data 2003-11-04 20:45:46 +00:00
gbeauche
30bd089279 PowerPC floating-point registers are now an union of uint64 & double. This
eases FP load/stores.
2003-11-04 15:03:15 +00:00
gbeauche
f0ea192460 Optimized pointers to non virtual member functions. This reduces space
and overhead since runtime checks are eliminated. Actually, it yields
up to 10% performance improvement with specialized decoders.
2003-11-02 14:48:20 +00:00
gbeauche
d956d3c4ca add specialized instruction decoders (disabled for now) 2003-11-01 17:07:17 +00:00
gbeauche
89d0f9ca29 Integrate spcflags handling code to kpx_cpu core. We can also remove
oldish EXEC_RETURN handling with a throw/catch mechanism since we
do have a dependency on extra conditions (invalidated cache) that
prevents fast execution loops.
2003-11-01 15:15:31 +00:00
gbeauche
9ce43c6cf3 Fix ASYNC_IRQ build but locks may still happen. Note that with a predecode
cache, checking for pending interrupts may not be the bottle neck nowadays.
2003-10-26 14:16:40 +00:00
gbeauche
60d34a6816 Rewrite interrupts handling code so that the emulator can work with a
predecode cache. This implies to run in interpreted mode only while
processing EmulOps or other native (nested) runs.

Note that the FLIGHT_RECORDER with a predecode cache gets slower than
without caching at all.
2003-10-26 13:59:04 +00:00
gbeauche
cb13fe3007 Log both r24 (m68k emulator PC) & stack pointer in SheepShaver mode only 2003-10-19 21:36:21 +00:00
gbeauche
9a05805a27 - Fix ADDME & ADDZE decoders, add RA==R0 testers
- Increase predecode cache size to 32K entries
- Enable PPC_EXECUTE_DUMP_STATE for predecode cache as well
2003-10-18 13:43:25 +00:00
gbeauche
1b9876889e - Record address range of block to invalidate. i.e. icbi records ranges
and isync actually invalidate caches
2003-10-12 06:44:04 +00:00
gbeauche
7e0dccc544 - Handle MakeExecutable() replacement
- Disable predecode cache in CVS for now
- Fix flight recorder ordering in predecode cache mode
2003-10-12 05:44:17 +00:00
gbeauche
a3036b0c9d Really enable flight_recorder with predecode cache on 2003-10-11 16:43:42 +00:00
gbeauche
7e20a8d205 - Add support for FLIGHT_RECORDER with predecode cache
- Always enable predecode cache & flight recorder for now
2003-10-11 09:57:52 +00:00