Commit Graph

10 Commits

Author SHA1 Message Date
gbeauche
b3f62598b7 More human readable instruction names (from e-uae). 2007-06-29 16:32:05 +00:00
gbeauche
c0cc43a87b Really make translation through constant jumps functional. This can be
disabled with the new prefs item "jitinline". Some rapid Speedometer 4
benchmarks showed only a 4% improvement.
2005-06-06 19:22:56 +00:00
gbeauche
2cda26edae Fix buffer overflow reported by Aranym people 2002-11-02 17:23:20 +00:00
gbeauche
8de7ad1091 - Turn on runtime detection of loop and jump alignment as Aranym people
reported they got some improvement with it and larger loops. Small
  loops are an issue for now until unrolling is implemented for DBcc.
- Const jumps are identified in readcpu. I don't want to duplicate code
  uselessly. Rather, it's the JIT job to know whether we are doing block
  inlining and un-marking those instructions as end-of-block.
2002-10-03 15:05:01 +00:00
gbeauche
94a9038826 - Remove dead code in readcpu.cpp concerning CONST_JUMP control flow.
- Replace unused fl_compiled with fl_const_jump
- Implement block inlining enabled with USE_INLINING && USE_CHECKSUM_INFO.
  However, this is currently disabled as it doesn't give much and exhibits
  even more a cache/code generation problem with FPU JIT compiled code.
- Actual checksum values are now integral part of a blockinfo regardless
  of USE_CHECKSUM_INFO is set or not. Reduce number of elements in that
  structure and speeds up a little calculation of checksum of chained blocks.
- Don't care about show_checksum() for now.
2002-10-02 15:55:10 +00:00
gbeauche
7972082c56 - Merge with Basilisk II/JIT cpu core, interpretive part for now
- Clean use of USE_PREFETCH_BUFFER macro and dependent bits
2002-09-01 15:17:13 +00:00
gbeauche
f93d1b483d - merge 680x0 emulation core with uae 0.8.17 2001-08-19 16:21:01 +00:00
gbeauche
7535a1042f Additions:
- MOVE16 (Ay)+,(xxx).L
- MOVE16 (xxx).L,(Ay)+
- MOVE16 (Ay),(xxx).L
- MOVE16 (xxx).L,(Ay)

Fixes:
- MOVE16 (Ax)+,(Ay)+ where x == y: address register shall be incremented
  only once
- CINV, CPUSH: 'p' field matches correctly the instruction 'cache field'
2001-03-19 13:11:40 +00:00
cebix
c31d1bd2af - added some 68040 instructions: CINV, CPUSH, MOVE16 (Ax)+,(Ay)+, MOVEC regs,
and FPU state frames; enough to boot MacOS
- CPU type can be selected in GTK prefs editor
1999-10-28 15:33:26 +00:00
cebix
8e491572ca Imported sources 1999-10-03 14:16:26 +00:00