Fixed some Z80 instruction timings
This commit is contained in:
transistor
parent
cbcfb26f49
commit
f9d613b3b9
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@ -8,6 +8,7 @@ pub struct Z80Decoder {
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pub clock: ClockTime,
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pub start: u16,
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pub end: u16,
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pub extra_instruction_bytes: u16,
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pub instruction: Instruction,
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}
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@ -17,6 +18,7 @@ impl Default for Z80Decoder {
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clock: ClockTime::START,
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start: 0,
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end: 0,
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extra_instruction_bytes: 0,
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instruction: Instruction::NOP,
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}
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}
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@ -27,16 +29,18 @@ impl Z80Decoder {
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self.clock = clock;
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self.start = start;
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self.end = start;
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self.extra_instruction_bytes = 0;
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self.instruction = self.decode_one(memory)?;
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Ok(())
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}
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pub fn decode_one(&mut self, memory: &mut dyn Addressable) -> Result<Instruction, Error> {
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let ins = self.read_instruction_byte(memory)?;
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self.decode_bare(memory, ins)
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self.decode_bare(memory, ins, 0)
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}
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pub fn decode_bare(&mut self, memory: &mut dyn Addressable, ins: u8) -> Result<Instruction, Error> {
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pub fn decode_bare(&mut self, memory: &mut dyn Addressable, ins: u8, extra_instruction_bytes: u16) -> Result<Instruction, Error> {
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self.extra_instruction_bytes = extra_instruction_bytes;
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match get_ins_x(ins) {
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0 => {
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match get_ins_z(ins) {
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@ -371,19 +375,22 @@ impl Z80Decoder {
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}
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},
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4 => {
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self.extra_instruction_bytes = 4;
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let half_target = Target::DirectRegHalf(get_index_register_half(index_reg, get_ins_q(ins)));
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Ok(Instruction::INC8(half_target))
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},
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5 => {
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self.extra_instruction_bytes = 4;
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let half_target = Target::DirectRegHalf(get_index_register_half(index_reg, get_ins_q(ins)));
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Ok(Instruction::DEC8(half_target))
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},
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6 => {
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self.extra_instruction_bytes = 4;
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let half_target = Target::DirectRegHalf(get_index_register_half(index_reg, get_ins_q(ins)));
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let data = self.read_instruction_byte(memory)?;
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Ok(Instruction::LD(to_load_target(half_target), LoadTarget::ImmediateByte(data)))
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},
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_ => self.decode_bare(memory, ins),
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_ => self.decode_bare(memory, ins, 4),
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}
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},
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3 => {
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@ -401,10 +408,10 @@ impl Z80Decoder {
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let immediate = self.read_instruction_byte(memory)?;
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Ok(Instruction::LD(LoadTarget::IndirectOffsetByte(index_reg, offset), LoadTarget::ImmediateByte(immediate)))
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},
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_ => self.decode_bare(memory, ins),
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_ => self.decode_bare(memory, ins, 4),
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}
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},
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_ => self.decode_bare(memory, ins),
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_ => self.decode_bare(memory, ins, 4),
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}
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},
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1 => {
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@ -412,7 +419,7 @@ impl Z80Decoder {
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0 | 1 => {
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let target = match self.decode_index_target(memory, index_reg, get_ins_z(ins))? {
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Some(target) => target,
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None => return self.decode_bare(memory, ins),
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None => return self.decode_bare(memory, ins, 4),
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};
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match (ins & 0x18) >> 3 {
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@ -450,7 +457,7 @@ impl Z80Decoder {
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3 => {
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if get_ins_q(ins) == 0 {
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if get_ins_z(ins) == 6 {
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return self.decode_bare(memory, ins);
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return self.decode_bare(memory, ins, 4);
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}
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let src = get_register(get_ins_z(ins));
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let offset = self.read_instruction_byte(memory)? as i8;
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@ -458,7 +465,7 @@ impl Z80Decoder {
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} else {
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let target = match self.decode_index_target(memory, index_reg, get_ins_z(ins))? {
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Some(target) => target,
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None => return self.decode_bare(memory, ins),
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None => return self.decode_bare(memory, ins, 4),
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};
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Ok(Instruction::LD(LoadTarget::DirectRegByte(Register::A), to_load_target(target)))
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@ -468,12 +475,13 @@ impl Z80Decoder {
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}
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},
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2 => {
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self.extra_instruction_bytes = 4;
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let target = match self.decode_index_target(memory, index_reg, get_ins_z(ins))? {
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Some(target) => target,
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None => return self.decode_bare(memory, ins),
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None => return self.decode_bare(memory, ins, 4),
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};
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match get_ins_y(ins) {
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0 => Ok(Instruction::ADDa(target)),
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1 => Ok(Instruction::ADCa(target)),
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@ -493,7 +501,7 @@ impl Z80Decoder {
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0xE5 => Ok(Instruction::PUSH(index_reg.into())),
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0xE9 => Ok(Instruction::JPIndirect(index_reg.into())),
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0xF9 => Ok(Instruction::LD(LoadTarget::DirectRegWord(RegisterPair::SP), LoadTarget::DirectRegWord(index_reg.into()))),
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_ => self.decode_bare(memory, ins),
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_ => self.decode_bare(memory, ins, 4),
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}
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},
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_ => panic!("InternalError: impossible value"),
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@ -103,7 +103,7 @@ impl Z80 {
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self.decode_next()?;
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self.execute_current()?;
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Ok(Z80InstructionCycles::from_instruction(&self.decoder.instruction)?
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Ok(Z80InstructionCycles::from_instruction(&self.decoder.instruction, self.decoder.extra_instruction_bytes)?
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.calculate_cycles(self.executor.took_branch))
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}
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@ -26,7 +26,7 @@ impl Z80InstructionCycles {
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}
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}
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pub fn from_instruction(instruction: &Instruction) -> Result<Z80InstructionCycles, Error> {
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pub fn from_instruction(instruction: &Instruction, extra: u16) -> Result<Z80InstructionCycles, Error> {
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let cycles = match instruction {
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Instruction::ADCa(target) |
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Instruction::ADDa(target) |
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@ -37,7 +37,6 @@ impl Z80InstructionCycles {
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Instruction::OR(target) |
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Instruction::XOR(target) => {
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match target {
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// TODO the undocumented DD version of this instruction is actually 8 cycles
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Target::DirectReg(_) |
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Target::DirectRegHalf(_) => 4,
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Target::IndirectReg(_) => 7,
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@ -70,8 +69,8 @@ impl Z80InstructionCycles {
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Instruction::CALLcc(_, _) => {
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return Ok(Z80InstructionCycles::Branch {
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taken: 17,
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not_taken: 10,
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taken: 17 + extra,
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not_taken: 10 + extra,
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});
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},
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@ -95,8 +94,8 @@ impl Z80InstructionCycles {
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Instruction::OTDR |
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Instruction::OTIR => {
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return Ok(Z80InstructionCycles::Repeating {
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repeating: 21,
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terminating: 16,
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repeating: 21 + extra,
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terminating: 16 + extra,
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})
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},
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@ -105,7 +104,6 @@ impl Z80InstructionCycles {
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Instruction::DEC8(target) |
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Instruction::INC8(target) => {
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// TODO the undocumented DD version of this instruction is actually 8 cycles
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match target {
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Target::DirectReg(_) |
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Target::DirectRegHalf(_) => 4,
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@ -129,8 +127,8 @@ impl Z80InstructionCycles {
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Instruction::DJNZ(_) => {
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return Ok(Z80InstructionCycles::Branch {
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taken: 13,
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not_taken: 8,
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taken: 13 + extra,
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not_taken: 8 + extra,
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});
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},
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@ -171,13 +169,12 @@ impl Z80InstructionCycles {
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Instruction::JRcc(_, _) => {
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return Ok(Z80InstructionCycles::Branch {
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taken: 12,
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not_taken: 7,
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taken: 12 + extra,
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not_taken: 7 + extra,
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});
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},
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Instruction::LD(dest, src) => {
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// TODO the undocumented DD version of this instruction is actually 8 cycles
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match (dest, src) {
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// 8-Bit Operations
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@ -265,8 +262,8 @@ impl Z80InstructionCycles {
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Instruction::RETcc(_) => {
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return Ok(Z80InstructionCycles::Branch {
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taken: 11,
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not_taken: 5,
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taken: 11 + extra,
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not_taken: 5 + extra,
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});
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},
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@ -298,7 +295,7 @@ impl Z80InstructionCycles {
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Instruction::SCF => 4,
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};
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Ok(Z80InstructionCycles::Single(cycles))
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Ok(Z80InstructionCycles::Single(cycles + extra))
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}
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}
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@ -1,4 +1,4 @@
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Last run on 2023-05-22 at commit 8c1a89a1fe788fc614c319e167372d47cb869417
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Last run on 2023-06-10 at commit cbcfb26f49c23414fe00317fddc65ffcbb087b18
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fe.json completed, all passed!
|
||||
ff.json completed, all passed!
|
||||
|
||||
passed: 1594638, failed: 15362, total 99%
|
||||
completed in 1m 39s
|
||||
passed: 1574638, failed: 35362, total 98%
|
||||
completed in 1m 19s
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -7,5 +7,5 @@ RESULTS=latest.txt
|
|||
cd $LOCATION
|
||||
echo "Last run on $DATE at commit $COMMIT" | tee $RESULTS
|
||||
echo "" | tee -a $RESULTS
|
||||
cargo run -- -q --testsuite "../jsmoo/misc/tests/GeneratedTests/z80/v1/" --check-undocumented | tee -a $RESULTS
|
||||
cargo run -- -q --testsuite "../jsmoo/misc/tests/GeneratedTests/z80/v1/" --check-undocumented --check-timings | tee -a $RESULTS
|
||||
}
|
||||
|
|
|
|||
8
todo.txt
8
todo.txt
|
|
@ -6,16 +6,19 @@
|
|||
the cost of having more events on the queue when re-scheduling. There needs to be a mechanism to avoid the event queue ballooning due to
|
||||
an error
|
||||
* can you somehow make devices have two step functions for running things at different times? (I'm thinking ym2612 audio gen vs timers)
|
||||
* the genesis coprocessor stuff will be a good reference point for things that make multiple devices, and how to add them correctly to the system
|
||||
|
||||
* address repeater on ym2612 doesn't seem to work the same, when it's on the 68000 device. The Z80 device doesn't have an affect, but maybe it's not being used
|
||||
* I like making address adapters like this (below)
|
||||
* you could have busport take a closure or something which translates the address, and returns an error that will be passed up if it occurs
|
||||
in order to implement the correct behaviour for address exceptions in 68k, transparently
|
||||
|
||||
* make Signal directional, by making SignalDriver and SignalInput or SignalReceiver
|
||||
|
||||
|
||||
* fix the m68k timings
|
||||
* add rust runtime checks for math to look for overflow errors
|
||||
* fix the watchers in the Bus, maybe make them manual
|
||||
* make Signal directional, by making SignalDriver and SignalInput or SignalReceiver
|
||||
* the genesis coprocessor stuff will be a good reference point for things that make multiple devices, and how to add them correctly to the system
|
||||
* make it possible to compile without audio support (minifb frontend requires it atm)
|
||||
* does Z80 need a customized Z80BusPort like the 68k?
|
||||
* can you make it so you don't need borrow_mut() so much?
|
||||
|
|
@ -49,7 +52,6 @@
|
|||
* get rustfmt, rustdoc, and clippy working in some kind of semi-automatic fashion
|
||||
|
||||
* you really need a full web-based debugger
|
||||
* test m68k cycle timing again
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue