Fixed some Z80 instruction timings

This commit is contained in:
transistor 2023-06-10 21:55:25 -07:00
parent cbcfb26f49
commit f9d613b3b9
7 changed files with 1676 additions and 54 deletions

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@ -8,6 +8,7 @@ pub struct Z80Decoder {
pub clock: ClockTime, pub clock: ClockTime,
pub start: u16, pub start: u16,
pub end: u16, pub end: u16,
pub extra_instruction_bytes: u16,
pub instruction: Instruction, pub instruction: Instruction,
} }
@ -17,6 +18,7 @@ impl Default for Z80Decoder {
clock: ClockTime::START, clock: ClockTime::START,
start: 0, start: 0,
end: 0, end: 0,
extra_instruction_bytes: 0,
instruction: Instruction::NOP, instruction: Instruction::NOP,
} }
} }
@ -27,16 +29,18 @@ impl Z80Decoder {
self.clock = clock; self.clock = clock;
self.start = start; self.start = start;
self.end = start; self.end = start;
self.extra_instruction_bytes = 0;
self.instruction = self.decode_one(memory)?; self.instruction = self.decode_one(memory)?;
Ok(()) Ok(())
} }
pub fn decode_one(&mut self, memory: &mut dyn Addressable) -> Result<Instruction, Error> { pub fn decode_one(&mut self, memory: &mut dyn Addressable) -> Result<Instruction, Error> {
let ins = self.read_instruction_byte(memory)?; let ins = self.read_instruction_byte(memory)?;
self.decode_bare(memory, ins) self.decode_bare(memory, ins, 0)
} }
pub fn decode_bare(&mut self, memory: &mut dyn Addressable, ins: u8) -> Result<Instruction, Error> { pub fn decode_bare(&mut self, memory: &mut dyn Addressable, ins: u8, extra_instruction_bytes: u16) -> Result<Instruction, Error> {
self.extra_instruction_bytes = extra_instruction_bytes;
match get_ins_x(ins) { match get_ins_x(ins) {
0 => { 0 => {
match get_ins_z(ins) { match get_ins_z(ins) {
@ -371,19 +375,22 @@ impl Z80Decoder {
} }
}, },
4 => { 4 => {
self.extra_instruction_bytes = 4;
let half_target = Target::DirectRegHalf(get_index_register_half(index_reg, get_ins_q(ins))); let half_target = Target::DirectRegHalf(get_index_register_half(index_reg, get_ins_q(ins)));
Ok(Instruction::INC8(half_target)) Ok(Instruction::INC8(half_target))
}, },
5 => { 5 => {
self.extra_instruction_bytes = 4;
let half_target = Target::DirectRegHalf(get_index_register_half(index_reg, get_ins_q(ins))); let half_target = Target::DirectRegHalf(get_index_register_half(index_reg, get_ins_q(ins)));
Ok(Instruction::DEC8(half_target)) Ok(Instruction::DEC8(half_target))
}, },
6 => { 6 => {
self.extra_instruction_bytes = 4;
let half_target = Target::DirectRegHalf(get_index_register_half(index_reg, get_ins_q(ins))); let half_target = Target::DirectRegHalf(get_index_register_half(index_reg, get_ins_q(ins)));
let data = self.read_instruction_byte(memory)?; let data = self.read_instruction_byte(memory)?;
Ok(Instruction::LD(to_load_target(half_target), LoadTarget::ImmediateByte(data))) Ok(Instruction::LD(to_load_target(half_target), LoadTarget::ImmediateByte(data)))
}, },
_ => self.decode_bare(memory, ins), _ => self.decode_bare(memory, ins, 4),
} }
}, },
3 => { 3 => {
@ -401,10 +408,10 @@ impl Z80Decoder {
let immediate = self.read_instruction_byte(memory)?; let immediate = self.read_instruction_byte(memory)?;
Ok(Instruction::LD(LoadTarget::IndirectOffsetByte(index_reg, offset), LoadTarget::ImmediateByte(immediate))) Ok(Instruction::LD(LoadTarget::IndirectOffsetByte(index_reg, offset), LoadTarget::ImmediateByte(immediate)))
}, },
_ => self.decode_bare(memory, ins), _ => self.decode_bare(memory, ins, 4),
} }
}, },
_ => self.decode_bare(memory, ins), _ => self.decode_bare(memory, ins, 4),
} }
}, },
1 => { 1 => {
@ -412,7 +419,7 @@ impl Z80Decoder {
0 | 1 => { 0 | 1 => {
let target = match self.decode_index_target(memory, index_reg, get_ins_z(ins))? { let target = match self.decode_index_target(memory, index_reg, get_ins_z(ins))? {
Some(target) => target, Some(target) => target,
None => return self.decode_bare(memory, ins), None => return self.decode_bare(memory, ins, 4),
}; };
match (ins & 0x18) >> 3 { match (ins & 0x18) >> 3 {
@ -450,7 +457,7 @@ impl Z80Decoder {
3 => { 3 => {
if get_ins_q(ins) == 0 { if get_ins_q(ins) == 0 {
if get_ins_z(ins) == 6 { if get_ins_z(ins) == 6 {
return self.decode_bare(memory, ins); return self.decode_bare(memory, ins, 4);
} }
let src = get_register(get_ins_z(ins)); let src = get_register(get_ins_z(ins));
let offset = self.read_instruction_byte(memory)? as i8; let offset = self.read_instruction_byte(memory)? as i8;
@ -458,7 +465,7 @@ impl Z80Decoder {
} else { } else {
let target = match self.decode_index_target(memory, index_reg, get_ins_z(ins))? { let target = match self.decode_index_target(memory, index_reg, get_ins_z(ins))? {
Some(target) => target, Some(target) => target,
None => return self.decode_bare(memory, ins), None => return self.decode_bare(memory, ins, 4),
}; };
Ok(Instruction::LD(LoadTarget::DirectRegByte(Register::A), to_load_target(target))) Ok(Instruction::LD(LoadTarget::DirectRegByte(Register::A), to_load_target(target)))
@ -468,12 +475,13 @@ impl Z80Decoder {
} }
}, },
2 => { 2 => {
self.extra_instruction_bytes = 4;
let target = match self.decode_index_target(memory, index_reg, get_ins_z(ins))? { let target = match self.decode_index_target(memory, index_reg, get_ins_z(ins))? {
Some(target) => target, Some(target) => target,
None => return self.decode_bare(memory, ins), None => return self.decode_bare(memory, ins, 4),
}; };
match get_ins_y(ins) { match get_ins_y(ins) {
0 => Ok(Instruction::ADDa(target)), 0 => Ok(Instruction::ADDa(target)),
1 => Ok(Instruction::ADCa(target)), 1 => Ok(Instruction::ADCa(target)),
@ -493,7 +501,7 @@ impl Z80Decoder {
0xE5 => Ok(Instruction::PUSH(index_reg.into())), 0xE5 => Ok(Instruction::PUSH(index_reg.into())),
0xE9 => Ok(Instruction::JPIndirect(index_reg.into())), 0xE9 => Ok(Instruction::JPIndirect(index_reg.into())),
0xF9 => Ok(Instruction::LD(LoadTarget::DirectRegWord(RegisterPair::SP), LoadTarget::DirectRegWord(index_reg.into()))), 0xF9 => Ok(Instruction::LD(LoadTarget::DirectRegWord(RegisterPair::SP), LoadTarget::DirectRegWord(index_reg.into()))),
_ => self.decode_bare(memory, ins), _ => self.decode_bare(memory, ins, 4),
} }
}, },
_ => panic!("InternalError: impossible value"), _ => panic!("InternalError: impossible value"),

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@ -103,7 +103,7 @@ impl Z80 {
self.decode_next()?; self.decode_next()?;
self.execute_current()?; self.execute_current()?;
Ok(Z80InstructionCycles::from_instruction(&self.decoder.instruction)? Ok(Z80InstructionCycles::from_instruction(&self.decoder.instruction, self.decoder.extra_instruction_bytes)?
.calculate_cycles(self.executor.took_branch)) .calculate_cycles(self.executor.took_branch))
} }

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@ -26,7 +26,7 @@ impl Z80InstructionCycles {
} }
} }
pub fn from_instruction(instruction: &Instruction) -> Result<Z80InstructionCycles, Error> { pub fn from_instruction(instruction: &Instruction, extra: u16) -> Result<Z80InstructionCycles, Error> {
let cycles = match instruction { let cycles = match instruction {
Instruction::ADCa(target) | Instruction::ADCa(target) |
Instruction::ADDa(target) | Instruction::ADDa(target) |
@ -37,7 +37,6 @@ impl Z80InstructionCycles {
Instruction::OR(target) | Instruction::OR(target) |
Instruction::XOR(target) => { Instruction::XOR(target) => {
match target { match target {
// TODO the undocumented DD version of this instruction is actually 8 cycles
Target::DirectReg(_) | Target::DirectReg(_) |
Target::DirectRegHalf(_) => 4, Target::DirectRegHalf(_) => 4,
Target::IndirectReg(_) => 7, Target::IndirectReg(_) => 7,
@ -70,8 +69,8 @@ impl Z80InstructionCycles {
Instruction::CALLcc(_, _) => { Instruction::CALLcc(_, _) => {
return Ok(Z80InstructionCycles::Branch { return Ok(Z80InstructionCycles::Branch {
taken: 17, taken: 17 + extra,
not_taken: 10, not_taken: 10 + extra,
}); });
}, },
@ -95,8 +94,8 @@ impl Z80InstructionCycles {
Instruction::OTDR | Instruction::OTDR |
Instruction::OTIR => { Instruction::OTIR => {
return Ok(Z80InstructionCycles::Repeating { return Ok(Z80InstructionCycles::Repeating {
repeating: 21, repeating: 21 + extra,
terminating: 16, terminating: 16 + extra,
}) })
}, },
@ -105,7 +104,6 @@ impl Z80InstructionCycles {
Instruction::DEC8(target) | Instruction::DEC8(target) |
Instruction::INC8(target) => { Instruction::INC8(target) => {
// TODO the undocumented DD version of this instruction is actually 8 cycles
match target { match target {
Target::DirectReg(_) | Target::DirectReg(_) |
Target::DirectRegHalf(_) => 4, Target::DirectRegHalf(_) => 4,
@ -129,8 +127,8 @@ impl Z80InstructionCycles {
Instruction::DJNZ(_) => { Instruction::DJNZ(_) => {
return Ok(Z80InstructionCycles::Branch { return Ok(Z80InstructionCycles::Branch {
taken: 13, taken: 13 + extra,
not_taken: 8, not_taken: 8 + extra,
}); });
}, },
@ -171,13 +169,12 @@ impl Z80InstructionCycles {
Instruction::JRcc(_, _) => { Instruction::JRcc(_, _) => {
return Ok(Z80InstructionCycles::Branch { return Ok(Z80InstructionCycles::Branch {
taken: 12, taken: 12 + extra,
not_taken: 7, not_taken: 7 + extra,
}); });
}, },
Instruction::LD(dest, src) => { Instruction::LD(dest, src) => {
// TODO the undocumented DD version of this instruction is actually 8 cycles
match (dest, src) { match (dest, src) {
// 8-Bit Operations // 8-Bit Operations
@ -265,8 +262,8 @@ impl Z80InstructionCycles {
Instruction::RETcc(_) => { Instruction::RETcc(_) => {
return Ok(Z80InstructionCycles::Branch { return Ok(Z80InstructionCycles::Branch {
taken: 11, taken: 11 + extra,
not_taken: 5, not_taken: 5 + extra,
}); });
}, },
@ -298,7 +295,7 @@ impl Z80InstructionCycles {
Instruction::SCF => 4, Instruction::SCF => 4,
}; };
Ok(Z80InstructionCycles::Single(cycles)) Ok(Z80InstructionCycles::Single(cycles + extra))
} }
} }

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@ -1,4 +1,4 @@
Last run on 2023-05-22 at commit 8c1a89a1fe788fc614c319e167372d47cb869417 Last run on 2023-06-10 at commit cbcfb26f49c23414fe00317fddc65ffcbb087b18
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passed: 1594638, failed: 15362, total 99% passed: 1574638, failed: 35362, total 98%
completed in 1m 39s completed in 1m 19s

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@ -7,5 +7,5 @@ RESULTS=latest.txt
cd $LOCATION cd $LOCATION
echo "Last run on $DATE at commit $COMMIT" | tee $RESULTS echo "Last run on $DATE at commit $COMMIT" | tee $RESULTS
echo "" | tee -a $RESULTS echo "" | tee -a $RESULTS
cargo run -- -q --testsuite "../jsmoo/misc/tests/GeneratedTests/z80/v1/" --check-undocumented | tee -a $RESULTS cargo run -- -q --testsuite "../jsmoo/misc/tests/GeneratedTests/z80/v1/" --check-undocumented --check-timings | tee -a $RESULTS
} }

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@ -6,16 +6,19 @@
the cost of having more events on the queue when re-scheduling. There needs to be a mechanism to avoid the event queue ballooning due to the cost of having more events on the queue when re-scheduling. There needs to be a mechanism to avoid the event queue ballooning due to
an error an error
* can you somehow make devices have two step functions for running things at different times? (I'm thinking ym2612 audio gen vs timers) * can you somehow make devices have two step functions for running things at different times? (I'm thinking ym2612 audio gen vs timers)
* the genesis coprocessor stuff will be a good reference point for things that make multiple devices, and how to add them correctly to the system
* address repeater on ym2612 doesn't seem to work the same, when it's on the 68000 device. The Z80 device doesn't have an affect, but maybe it's not being used * address repeater on ym2612 doesn't seem to work the same, when it's on the 68000 device. The Z80 device doesn't have an affect, but maybe it's not being used
* I like making address adapters like this (below) * I like making address adapters like this (below)
* you could have busport take a closure or something which translates the address, and returns an error that will be passed up if it occurs * you could have busport take a closure or something which translates the address, and returns an error that will be passed up if it occurs
in order to implement the correct behaviour for address exceptions in 68k, transparently in order to implement the correct behaviour for address exceptions in 68k, transparently
* make Signal directional, by making SignalDriver and SignalInput or SignalReceiver
* fix the m68k timings
* add rust runtime checks for math to look for overflow errors * add rust runtime checks for math to look for overflow errors
* fix the watchers in the Bus, maybe make them manual * fix the watchers in the Bus, maybe make them manual
* make Signal directional, by making SignalDriver and SignalInput or SignalReceiver
* the genesis coprocessor stuff will be a good reference point for things that make multiple devices, and how to add them correctly to the system
* make it possible to compile without audio support (minifb frontend requires it atm) * make it possible to compile without audio support (minifb frontend requires it atm)
* does Z80 need a customized Z80BusPort like the 68k? * does Z80 need a customized Z80BusPort like the 68k?
* can you make it so you don't need borrow_mut() so much? * can you make it so you don't need borrow_mut() so much?
@ -49,7 +52,6 @@
* get rustfmt, rustdoc, and clippy working in some kind of semi-automatic fashion * get rustfmt, rustdoc, and clippy working in some kind of semi-automatic fashion
* you really need a full web-based debugger * you really need a full web-based debugger
* test m68k cycle timing again