11 Commits

Author	SHA1	Message	Date
Zane Kaminski	fa08ca903a	Register Apple address bus on PHI0 rising edge	2021-04-21 20:06:56 -04:00
Zane Kaminski	a3517bf054	Revert "Updated slew rate/current strength assignments" ... This reverts commit 691c076b4d.	2021-04-20 05:50:09 -04:00
Zane Kaminski	691c076b4d	Updated slew rate/current strength assignments	2021-04-20 05:43:37 -04:00
Zane Kaminski	c4844b9646	idk	2021-04-11 15:39:19 -04:00
Zane Kaminski	b0b8b0dc6c	Works?	2021-04-03 03:44:42 -04:00
Zane Kaminski	e5da11855d	Remove old CPLD stuff	2021-03-15 13:40:41 -04:00
Zane Kaminski	f471e04244	New PLD revision ... For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.	2019-10-18 15:07:38 -04:00
Zane Kaminski	7ea556dd34	Clarified assignments	2019-09-06 17:26:42 -04:00
Zane Kaminski	f52c6e4781	Pipelined addition	2019-09-04 21:45:56 -04:00
Zane Kaminski	6b2378f99a	1MB CPLD design seems to work, fails Apple BIST	2019-09-01 21:18:44 -04:00
Zane Kaminski	396cc3c03c	CPLD firmware compiles	2019-08-31 22:55:04 -04:00