16 Commits

Author	SHA1	Message	Date
Steven Hugg	951088dd3b	added comments to verilog examples	2018-10-01 12:30:47 -04:00
Steven Hugg	4a82d341bc	make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes	2018-08-14 00:05:02 -04:00
Steven Hugg	2dbc60aa2e	updated presets; verilog code dup detect; need to handle local/ include files somehow	2018-07-31 23:03:53 -04:00
Steven Hugg	20ddb8a11f	moved around ALU ops, 16-bit cpu, reg/wire	2018-02-21 11:03:38 -06:00
Steven Hugg	1790ca1747	updated verilog presets and test makefile	2018-02-16 23:33:29 -06:00
Steven Hugg	661bbb0ced	fixed hsync generator to use assign	2018-02-09 10:59:52 -06:00
Steven Hugg	11992645d6	more presets	2018-02-09 00:11:36 -06:00
Steven Hugg	f0f6783f6b	more verilog presets	2018-02-03 20:37:12 -06:00
Steven Hugg	a456f3d9cf	updated presets	2018-01-13 19:38:20 -06:00
Steven Hugg	45756f682d	changed CRT timing	2018-01-08 10:30:10 -06:00
Steven Hugg	d732f320b0	work on simple CPU, paddle game, `include local files too, scope scrolling, hvsync reset	2017-11-30 12:28:25 -05:00
Steven Hugg	48baf73ecb	variable inspection, bitmaps for verilog, active high hsync/vsync, powerup vs reset	2017-11-21 14:12:02 -05:00
Steven Hugg	2525d6e585	start yosys profiling	2017-11-20 10:32:34 -05:00
Steven Hugg	27a9076cb5	verilog: 2d array; digits; score; reset w/ no init; more warnings	2017-11-19 13:26:21 -05:00
Steven Hugg	ff8784da33	more paddle/pong stuff; wider compiler msgs	2017-11-17 17:03:11 -05:00
Steven Hugg	4f73cde7cc	support `include statements in verilog; book link changes; paddle/switches; scope transitions	2017-11-16 10:30:47 -05:00