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8bitworkshop/presets/verilog
History
Steven Hugg aa7fe61a86 verilog: disabled v4 warnings, inline asm in non-main files
2021-07-12 12:39:57 -05:00
..
.gitignore
fixed multiplex issue in racing_game
2018-10-01 22:03:44 -04:00
7segment.v
added comments to verilog examples
2018-10-01 12:30:47 -04:00
alu.v
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
ball_absolute.v
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
ball_paddle.v
fixed ball_paddle.v
2018-10-09 19:37:38 -04:00
ball_slip_counter.v
added comments to verilog examples
2018-10-01 12:30:47 -04:00
binary_counter.v
more verilog updates
2018-12-15 11:25:22 -05:00
chardisplay.v
verilog: randomizeOnReset = true except for unit tests (only <=32 bit values reset)
2021-07-09 15:21:41 -05:00
clock_divider.v
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
copperbars.ice
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
cpu8.v
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
cpu16.v
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
cpu6502.v
verilog: test updates, source locations, labels, Silice
2021-07-07 15:43:35 -05:00
cpu_platform.v
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
digits10.v
verilog: randomizeOnReset = true except for unit tests (only <=32 bit values reset)
2021-07-09 15:21:41 -05:00
femto8.cfg
make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
2018-08-14 00:05:02 -04:00
femto8.json
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
femto16.cfg
make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
2018-08-14 00:05:02 -04:00
femto16.json
make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
2018-08-14 00:05:02 -04:00
font_cp437_8x8.ice
verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice
2020-12-28 10:06:50 -06:00
font_cp437_8x8.v
verilog: test updates, source locations, labels, Silice
2021-07-07 15:43:35 -05:00
framebuf_vpu.v
make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
2018-08-14 00:05:02 -04:00
framebuffer.v
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
gates.v
make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
2018-08-14 00:05:02 -04:00
hvsync_generator.v
added comments to verilog examples
2018-10-01 12:30:47 -04:00
icestick.pcf
fixed multiplex issue in racing_game
2018-10-01 22:03:44 -04:00
lfsr.v
added comments to verilog examples
2018-10-01 12:30:47 -04:00
life.ice
verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice
2020-12-28 10:06:50 -06:00
Makefile
dasm: fixed macro line parsing, breakpoints
2021-04-08 10:58:02 -05:00
music.v
make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
2018-08-14 00:05:02 -04:00
ntsc.ice
verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice
2020-12-28 10:06:50 -06:00
paddles.v
added comments to verilog examples
2018-10-01 12:30:47 -04:00
racing_game_cpu.v
verilog: added comments
2020-05-13 12:50:16 -05:00
racing_game.v
updated presets, changed array syntax, ice40 fpga examples
2018-10-08 20:38:39 -04:00
ram.v
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
riscv.json
verilog: disabled v4 warnings, inline asm in non-main files
2021-07-12 12:39:57 -05:00
rototexture.ice
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
scoreboard.v
added comments to verilog examples
2018-10-01 12:30:47 -04:00
sharedbuffer.v
make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
2018-08-14 00:05:02 -04:00
skeleton.silice
verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice
2020-12-28 10:06:50 -06:00
skeleton.verilator
make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
2018-08-14 00:05:02 -04:00
sound_generator.v
added comments to verilog examples
2018-10-01 12:30:47 -04:00
sprite_bitmap.v
added comments to verilog examples
2018-10-01 12:30:47 -04:00
sprite_renderer.v
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
sprite_rotation.v
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
sprite_scanline_renderer.v
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
starfield.v
minor scope tweaks, need phantomjs for wavedrom
2018-10-11 11:08:19 -04:00
switches.v
verilog/switches: Update Player 2 key documentation
2020-02-29 20:41:41 +13:00
tank.v
verilog tank example
2018-10-03 18:49:14 -04:00
test2.asm
nes runToVsync; debug info changes
2018-08-03 12:18:08 -04:00
test_hvsync.v
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00
test_pattern.ice
verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice
2020-12-28 10:06:50 -06:00
test.asm
make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
2018-08-14 00:05:02 -04:00
tile_renderer.v
verilog preset update
2018-12-13 18:25:54 -05:00
tile.tga
(WIP) new hdl package, verilator 4 (emscripten 2.0.6), hdlwasm
2021-06-30 18:07:55 -05:00