.. |
.gitignore
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fixed multiplex issue in racing_game
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2018-10-01 22:03:44 -04:00 |
7segment.v
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added comments to verilog examples
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2018-10-01 12:30:47 -04:00 |
alu.v
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verilog: added alu.v
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2021-05-07 09:50:04 -05:00 |
ball_absolute.v
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added comments to verilog examples
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2018-10-01 12:30:47 -04:00 |
ball_paddle.v
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fixed ball_paddle.v
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2018-10-09 19:37:38 -04:00 |
ball_slip_counter.v
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added comments to verilog examples
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2018-10-01 12:30:47 -04:00 |
binary_counter.v
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more verilog updates
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2018-12-15 11:25:22 -05:00 |
chardisplay.v
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verilog: fixed RAM Text Display example incrementing by +2
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2019-08-01 23:10:55 -04:00 |
clock_divider.v
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more verilog updates
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2018-12-15 11:25:22 -05:00 |
copperbars.ice
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verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice
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2020-12-28 10:06:50 -06:00 |
cpu8.v
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verilog presets; early exit from jsasm errors
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2018-09-08 19:14:51 -04:00 |
cpu16.v
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no more BOM on download files
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2018-12-08 10:15:02 -05:00 |
cpu6502.v
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fixed verilog 6502 CPU
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2019-09-04 21:06:59 -04:00 |
cpu_platform.v
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added comments to verilog examples
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2018-10-01 12:30:47 -04:00 |
digits10.v
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updated presets, changed array syntax, ice40 fpga examples
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2018-10-08 20:38:39 -04:00 |
femto8.cfg
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make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
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2018-08-14 00:05:02 -04:00 |
femto8.json
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make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
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2018-08-14 00:05:02 -04:00 |
femto16.cfg
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make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
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2018-08-14 00:05:02 -04:00 |
femto16.json
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make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
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2018-08-14 00:05:02 -04:00 |
font_cp437_8x8.ice
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verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice
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2020-12-28 10:06:50 -06:00 |
font_cp437_8x8.v
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make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
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2018-08-14 00:05:02 -04:00 |
framebuf_vpu.v
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make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
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2018-08-14 00:05:02 -04:00 |
framebuffer.v
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no more BOM on download files
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2018-12-08 10:15:02 -05:00 |
gates.v
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make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
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2018-08-14 00:05:02 -04:00 |
hvsync_generator.v
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added comments to verilog examples
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2018-10-01 12:30:47 -04:00 |
icestick.pcf
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fixed multiplex issue in racing_game
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2018-10-01 22:03:44 -04:00 |
lfsr.v
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added comments to verilog examples
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2018-10-01 12:30:47 -04:00 |
life.ice
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verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice
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2020-12-28 10:06:50 -06:00 |
Makefile
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dasm: fixed macro line parsing, breakpoints
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2021-04-08 10:58:02 -05:00 |
music.v
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make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
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2018-08-14 00:05:02 -04:00 |
ntsc.ice
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verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice
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2020-12-28 10:06:50 -06:00 |
paddles.v
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added comments to verilog examples
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2018-10-01 12:30:47 -04:00 |
racing_game_cpu.v
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verilog: added comments
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2020-05-13 12:50:16 -05:00 |
racing_game.v
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updated presets, changed array syntax, ice40 fpga examples
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2018-10-08 20:38:39 -04:00 |
ram.v
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updated presets, changed array syntax, ice40 fpga examples
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2018-10-08 20:38:39 -04:00 |
rototexture.ice
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verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice
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2020-12-28 10:06:50 -06:00 |
scoreboard.v
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added comments to verilog examples
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2018-10-01 12:30:47 -04:00 |
sharedbuffer.v
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make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
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2018-08-14 00:05:02 -04:00 |
skeleton.silice
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verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice
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2020-12-28 10:06:50 -06:00 |
skeleton.verilator
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make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
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2018-08-14 00:05:02 -04:00 |
sound_generator.v
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added comments to verilog examples
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2018-10-01 12:30:47 -04:00 |
sprite_bitmap.v
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added comments to verilog examples
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2018-10-01 12:30:47 -04:00 |
sprite_renderer.v
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added comments to verilog examples
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2018-10-01 12:30:47 -04:00 |
sprite_rotation.v
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fixed unit tests
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2018-10-03 15:06:48 -04:00 |
sprite_scanline_renderer.v
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updated presets, changed array syntax, ice40 fpga examples
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2018-10-08 20:38:39 -04:00 |
starfield.v
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minor scope tweaks, need phantomjs for wavedrom
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2018-10-11 11:08:19 -04:00 |
switches.v
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verilog/switches: Update Player 2 key documentation
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2020-02-29 20:41:41 +13:00 |
tank.v
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verilog tank example
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2018-10-03 18:49:14 -04:00 |
test2.asm
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nes runToVsync; debug info changes
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2018-08-03 12:18:08 -04:00 |
test_hvsync.v
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verilog: added comments
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2020-05-13 12:50:16 -05:00 |
test_pattern.ice
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verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice
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2020-12-28 10:06:50 -06:00 |
test.asm
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make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes
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2018-08-14 00:05:02 -04:00 |
tile_renderer.v
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verilog preset update
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2018-12-13 18:25:54 -05:00 |
tile.tga
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verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice
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2020-12-28 10:06:50 -06:00 |