1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-12-13 15:31:05 +00:00
CLK/InstructionSets/ARM/OperationMapper.hpp

554 lines
17 KiB
C++
Raw Normal View History

2024-02-17 02:35:49 +00:00
//
// OperationMapper.hpp
2024-02-17 02:35:49 +00:00
// Clock Signal
//
// Created by Thomas Harte on 16/02/2024.
// Copyright © 2024 Thomas Harte. All rights reserved.
//
#pragma once
#include "../../Reflection/Dispatcher.hpp"
#include "BarrelShifter.hpp"
2024-02-17 02:35:49 +00:00
namespace InstructionSet::ARM {
enum class Model {
2024-03-03 02:47:09 +00:00
ARMv2,
2024-03-11 01:45:56 +00:00
/// Like an ARMv2 but all non-PC addressing is 64-bit. Primarily useful for a particular set of test
/// cases that I want to apply retroactively; not a real iteration.
ARMv2with32bitAddressing,
};
enum class Condition {
EQ, NE, CS, CC,
MI, PL, VS, VC,
HI, LS, GE, LT,
GT, LE, AL, NV,
};
//
// Implementation details.
//
static constexpr int FlagsStartBit = 20;
using Flags = uint8_t;
template <int position>
constexpr bool flag_bit(const uint8_t flags) {
static_assert(position >= 20 && position < 28);
return flags & (1 << (position - FlagsStartBit));
}
2024-02-22 16:20:22 +00:00
//
// Methods common to data processing and data transfer.
//
2024-02-21 19:51:51 +00:00
struct WithShiftControlBits {
constexpr WithShiftControlBits(const uint32_t opcode) noexcept : opcode_(opcode) {}
2024-02-21 19:51:51 +00:00
/// The operand 2 register index if @c operand2_is_immediate() is @c false; meaningless otherwise.
2024-03-08 19:13:34 +00:00
uint32_t operand2() const { return opcode_ & 0xf; }
2024-02-21 19:51:51 +00:00
/// The type of shift to apply to operand 2 if @c operand2_is_immediate() is @c false; meaningless otherwise.
ShiftType shift_type() const { return ShiftType((opcode_ >> 5) & 3); }
/// @returns @c true if the amount to shift by should be taken from a register; @c false if it is an immediate value.
bool shift_count_is_register() const { return opcode_ & (1 << 4); }
/// The shift amount register index if @c shift_count_is_register() is @c true; meaningless otherwise.
2024-03-08 19:13:34 +00:00
uint32_t shift_register() const { return (opcode_ >> 8) & 0xf; }
2024-02-21 19:51:51 +00:00
/// The amount to shift by if @c shift_count_is_register() is @c false; meaningless otherwise.
2024-03-08 19:13:34 +00:00
uint32_t shift_amount() const { return (opcode_ >> 7) & 0x1f; }
2024-02-21 19:51:51 +00:00
protected:
uint32_t opcode_;
};
//
// Branch (i.e. B and BL).
//
2024-02-28 16:33:28 +00:00
struct BranchFlags {
constexpr BranchFlags(const uint8_t flags) noexcept : flags_(flags) {}
2024-02-28 16:33:28 +00:00
enum class Operation {
B, /// Add offset to PC; programmer allows for PC being two words ahead.
BL, /// Copy PC and PSR to R14, then branch. Copied PC points to next instruction.
};
2024-02-28 16:33:28 +00:00
/// @returns The operation to apply.
constexpr Operation operation() const {
return flag_bit<24>(flags_) ? Operation::BL : Operation::B;
2024-02-28 16:33:28 +00:00
}
private:
uint8_t flags_;
};
struct Branch {
constexpr Branch(const uint32_t opcode) noexcept : opcode_(opcode) {}
/// The 26-bit offset to add to the PC.
2024-03-04 18:53:46 +00:00
uint32_t offset() const { return (opcode_ & 0xff'ffff) << 2; }
private:
uint32_t opcode_;
};
//
// Data processing (i.e. AND to MVN).
//
enum class DataProcessingOperation {
AND, /// Rd = Op1 AND Op2.
EOR, /// Rd = Op1 EOR Op2.
SUB, /// Rd = Op1 - Op2.
RSB, /// Rd = Op2 - Op1.
ADD, /// Rd = Op1 + Op2.
ADC, /// Rd = Op1 + Ord2 + C.
SBC, /// Rd = Op1 - Op2 + C.
RSC, /// Rd = Op2 - Op1 + C.
TST, /// Set condition codes on Op1 AND Op2.
TEQ, /// Set condition codes on Op1 EOR Op2.
CMP, /// Set condition codes on Op1 - Op2.
CMN, /// Set condition codes on Op1 + Op2.
ORR, /// Rd = Op1 OR Op2.
MOV, /// Rd = Op2
BIC, /// Rd = Op1 AND NOT Op2.
MVN, /// Rd = NOT Op2.
};
constexpr bool is_logical(const DataProcessingOperation operation) {
switch(operation) {
case DataProcessingOperation::AND:
case DataProcessingOperation::EOR:
case DataProcessingOperation::TST:
case DataProcessingOperation::TEQ:
case DataProcessingOperation::ORR:
case DataProcessingOperation::MOV:
case DataProcessingOperation::BIC:
case DataProcessingOperation::MVN:
return true;
default: return false;
}
}
constexpr bool is_comparison(const DataProcessingOperation operation) {
switch(operation) {
case DataProcessingOperation::TST:
case DataProcessingOperation::TEQ:
case DataProcessingOperation::CMP:
case DataProcessingOperation::CMN:
return true;
default: return false;
}
}
struct DataProcessingFlags {
constexpr DataProcessingFlags(const uint8_t flags) noexcept : flags_(flags) {}
2024-02-26 19:30:26 +00:00
/// @returns The operation to apply.
constexpr DataProcessingOperation operation() const {
return DataProcessingOperation((flags_ >> (21 - FlagsStartBit)) & 0xf);
2024-02-26 19:30:26 +00:00
}
/// @returns @c true if operand 2 is defined by the @c rotate() and @c immediate() fields;
/// @c false if it is defined by the @c shift_*() and @c operand2() fields.
2024-02-26 19:30:26 +00:00
constexpr bool operand2_is_immediate() const { return flag_bit<25>(flags_); }
2024-02-22 16:20:22 +00:00
/// @c true if the status register should be updated; @c false otherwise.
2024-02-26 19:30:26 +00:00
constexpr bool set_condition_codes() const { return flag_bit<20>(flags_); }
private:
uint8_t flags_;
};
2024-02-21 19:51:51 +00:00
struct DataProcessing: public WithShiftControlBits {
using WithShiftControlBits::WithShiftControlBits;
/// The destination register index. i.e. Rd.
2024-03-08 19:13:34 +00:00
uint32_t destination() const { return (opcode_ >> 12) & 0xf; }
/// The operand 1 register index. i.e. Rn.
2024-03-08 19:13:34 +00:00
uint32_t operand1() const { return (opcode_ >> 16) & 0xf; }
//
// Immediate values for operand 2.
//
/// An 8-bit value to rotate right @c rotate() places if @c operand2_is_immediate() is @c true; meaningless otherwise.
2024-03-04 18:53:46 +00:00
uint32_t immediate() const { return opcode_ & 0xff; }
/// The number of bits to rotate @c immediate() by to the right if @c operand2_is_immediate() is @c true; meaningless otherwise.
2024-03-05 14:31:42 +00:00
uint32_t rotate() const { return (opcode_ >> 7) & 0x1e; }
};
//
// MUL and MLA.
//
struct MultiplyFlags {
constexpr MultiplyFlags(const uint8_t flags) noexcept : flags_(flags) {}
2024-02-22 16:20:22 +00:00
/// @c true if the status register should be updated; @c false otherwise.
2024-02-28 16:27:27 +00:00
constexpr bool set_condition_codes() const { return flag_bit<20>(flags_); }
enum class Operation {
MUL, /// Rd = Rm * Rs
MLA, /// Rd = Rm * Rs + Rn
};
2024-02-28 16:27:27 +00:00
/// @returns The operation to apply.
constexpr Operation operation() const {
return flag_bit<21>(flags_) ? Operation::MLA : Operation::MUL;
2024-02-28 16:27:27 +00:00
}
private:
uint8_t flags_;
};
struct Multiply {
constexpr Multiply(const uint32_t opcode) noexcept : opcode_(opcode) {}
/// The destination register index. i.e. 'Rd'.
2024-03-05 15:56:09 +00:00
uint32_t destination() const { return (opcode_ >> 16) & 0xf; }
/// The accumulator register index for multiply-add. i.e. 'Rn'.
2024-03-05 15:56:09 +00:00
uint32_t accumulator() const { return (opcode_ >> 12) & 0xf; }
/// The multiplicand register index. i.e. 'Rs'.
2024-03-05 15:56:09 +00:00
uint32_t multiplicand() const { return (opcode_ >> 8) & 0xf; }
/// The multiplier register index. i.e. 'Rm'.
2024-03-05 15:56:09 +00:00
uint32_t multiplier() const { return opcode_ & 0xf; }
private:
uint32_t opcode_;
};
2024-02-21 19:51:51 +00:00
//
// Single data transfer (LDR, STR).
//
struct SingleDataTransferFlags {
constexpr SingleDataTransferFlags(const uint8_t flags) noexcept : flags_(flags) {}
2024-02-21 19:51:51 +00:00
enum class Operation {
LDR, /// Read single byte or word from [base + offset], possibly mutating the base.
STR, /// Write a single byte or word to [base + offset], possibly mutating the base.
};
constexpr Operation operation() const {
return flag_bit<20>(flags_) ? Operation::LDR : Operation::STR;
2024-02-29 02:23:57 +00:00
}
2024-03-03 19:34:21 +00:00
constexpr bool offset_is_register() const { return flag_bit<25>(flags_); }
2024-02-28 19:43:31 +00:00
constexpr bool pre_index() const { return flag_bit<24>(flags_); }
constexpr bool add_offset() const { return flag_bit<23>(flags_); }
constexpr bool transfer_byte() const { return flag_bit<22>(flags_); }
constexpr bool write_back_address() const { return flag_bit<21>(flags_); }
2024-02-21 19:51:51 +00:00
private:
uint8_t flags_;
};
struct SingleDataTransfer: public WithShiftControlBits {
using WithShiftControlBits::WithShiftControlBits;
/// The destination register index. i.e. 'Rd' for LDR.
2024-03-08 19:13:34 +00:00
uint32_t destination() const { return (opcode_ >> 12) & 0xf; }
2024-02-21 19:51:51 +00:00
/// The destination register index. i.e. 'Rd' for STR.
2024-03-08 19:13:34 +00:00
uint32_t source() const { return (opcode_ >> 12) & 0xf; }
2024-02-21 19:51:51 +00:00
/// The base register index. i.e. 'Rn'.
2024-03-08 19:13:34 +00:00
uint32_t base() const { return (opcode_ >> 16) & 0xf; }
2024-02-21 19:51:51 +00:00
2024-03-03 19:40:05 +00:00
/// The immediate offset, if @c offset_is_register() was @c false; meaningless otherwise.
2024-03-04 18:53:46 +00:00
uint32_t immediate() const { return opcode_ & 0xfff; }
2024-02-21 19:51:51 +00:00
};
//
// Block data transfer (LDR, STR).
//
struct BlockDataTransferFlags {
constexpr BlockDataTransferFlags(const uint8_t flags) noexcept : flags_(flags) {}
enum class Operation {
LDM, /// Read 116 words from [base], possibly mutating it.
STM, /// Write 1-16 words to [base], possibly mutating it.
};
constexpr Operation operation() const {
return flag_bit<20>(flags_) ? Operation::LDM : Operation::STM;
2024-02-29 02:23:57 +00:00
}
2024-02-28 19:43:31 +00:00
constexpr bool pre_index() const { return flag_bit<24>(flags_); }
constexpr bool add_offset() const { return flag_bit<23>(flags_); }
constexpr bool load_psr() const { return flag_bit<22>(flags_); }
constexpr bool write_back_address() const { return flag_bit<21>(flags_); }
private:
uint8_t flags_;
};
struct BlockDataTransfer: public WithShiftControlBits {
using WithShiftControlBits::WithShiftControlBits;
/// The base register index. i.e. 'Rn'.
2024-03-05 15:56:09 +00:00
uint32_t base() const { return (opcode_ >> 16) & 0xf; }
/// A bitfield indicating which registers to load or store.
2024-03-04 18:53:46 +00:00
uint16_t register_list() const { return static_cast<uint16_t>(opcode_); }
2024-04-05 01:59:18 +00:00
uint32_t popcount() const {
const uint16_t list = register_list();
// TODO: just use std::popcount when adopting C++20.
uint32_t total = ((list & 0xaaaa) >> 1) + (list & 0x5555);
total = ((total & 0xcccc) >> 2) + (total & 0x3333);
total = ((total & 0xf0f0) >> 4) + (total & 0x0f0f);
total = ((total & 0xff00) >> 8) + (total & 0x00ff);
return total;
}
};
//
// Coprocessor data operation.
//
struct CoprocessorDataOperationFlags {
constexpr CoprocessorDataOperationFlags(const uint8_t flags) noexcept : flags_(flags) {}
2024-02-28 19:43:31 +00:00
constexpr int coprocessor_operation() const { return (flags_ >> (FlagsStartBit - 20)) & 0xf; }
private:
uint8_t flags_;
};
struct CoprocessorDataOperation {
constexpr CoprocessorDataOperation(const uint32_t opcode) noexcept : opcode_(opcode) {}
2024-03-08 19:13:34 +00:00
uint32_t operand1() const { return (opcode_ >> 16) & 0xf; }
2024-12-01 14:04:32 +00:00
uint32_t operand2() const { return opcode_ & 0xf; }
2024-03-08 19:13:34 +00:00
uint32_t destination() const { return (opcode_ >> 12) & 0xf; }
uint32_t coprocessor() const { return (opcode_ >> 8) & 0xf; }
uint32_t information() const { return (opcode_ >> 5) & 0x7; }
private:
uint32_t opcode_;
};
//
// Coprocessor register transfer.
//
struct CoprocessorRegisterTransferFlags {
constexpr CoprocessorRegisterTransferFlags(const uint8_t flags) noexcept : flags_(flags) {}
enum class Operation {
MRC, /// Move from coprocessor register to ARM register.
MCR, /// Move from ARM register to coprocessor register.
};
constexpr Operation operation() const {
return flag_bit<20>(flags_) ? Operation::MRC : Operation::MCR;
2024-02-28 19:43:31 +00:00
}
constexpr int coprocessor_operation() const { return (flags_ >> (FlagsStartBit - 20)) & 0x7; }
private:
uint8_t flags_;
};
struct CoprocessorRegisterTransfer {
constexpr CoprocessorRegisterTransfer(const uint32_t opcode) noexcept : opcode_(opcode) {}
2024-03-08 19:13:34 +00:00
uint32_t operand1() const { return (opcode_ >> 16) & 0xf; }
2024-12-01 14:04:32 +00:00
uint32_t operand2() const { return opcode_ & 0xf; }
2024-03-08 19:13:34 +00:00
uint32_t destination() const { return (opcode_ >> 12) & 0xf; }
uint32_t coprocessor() const { return (opcode_ >> 8) & 0xf; }
uint32_t information() const { return (opcode_ >> 5) & 0x7; }
private:
uint32_t opcode_;
};
//
// Coprocessor data transfer.
//
struct CoprocessorDataTransferFlags {
constexpr CoprocessorDataTransferFlags(const uint8_t flags) noexcept : flags_(flags) {}
enum class Operation {
LDC, /// Coprocessor data transfer load.
STC, /// Coprocessor data transfer store.
};
constexpr Operation operation() const {
return flag_bit<20>(flags_) ? Operation::LDC : Operation::STC;
2024-02-28 19:43:31 +00:00
}
constexpr bool pre_index() const { return flag_bit<24>(flags_); }
constexpr bool add_offset() const { return flag_bit<23>(flags_); }
constexpr bool transfer_length() const { return flag_bit<22>(flags_); }
constexpr bool write_back_address() const { return flag_bit<21>(flags_); }
private:
uint8_t flags_;
};
2024-04-19 02:13:58 +00:00
//
// Software interrupt.
//
struct SoftwareInterrupt {
constexpr SoftwareInterrupt(const uint32_t opcode) noexcept : opcode_(opcode) {}
2024-04-19 02:13:58 +00:00
/// The 24-bit comment field, often decoded by the receiver of an SWI.
uint32_t comment() const { return opcode_ & 0xff'ffff; }
private:
uint32_t opcode_;
};
struct CoprocessorDataTransfer {
constexpr CoprocessorDataTransfer(const uint32_t opcode) noexcept : opcode_(opcode) {}
2024-02-28 19:43:31 +00:00
int base() const { return (opcode_ >> 16) & 0xf; }
2024-02-28 19:43:31 +00:00
int source() const { return (opcode_ >> 12) & 0xf; }
int destination() const { return (opcode_ >> 12) & 0xf; }
2024-02-28 19:43:31 +00:00
int coprocessor() const { return (opcode_ >> 8) & 0xf; }
int offset() const { return opcode_ & 0xff; }
private:
uint32_t opcode_;
};
/// Operation mapper; use the free function @c dispatch as defined below.
2024-03-03 02:47:09 +00:00
template <Model>
struct OperationMapper {
static Condition condition(const uint32_t instruction) {
2024-02-27 02:36:23 +00:00
return Condition(instruction >> 28);
}
template <int i, typename SchedulerT>
static void dispatch(const uint32_t instruction, SchedulerT &scheduler) {
2024-02-27 02:36:23 +00:00
// Put the 8-bit segment of instruction back into its proper place;
// this allows all the tests below to be written so as to coordinate
// properly with the data sheet, and since it's all compile-time work
// it doesn't cost anything.
constexpr auto partial = uint32_t(i << 20);
2024-02-21 19:18:41 +00:00
// Cf. the ARM2 datasheet, p.45. Tests below match its ordering
// other than that 'undefined' is the fallthrough case. More specific
// page references are provided were more detailed versions of the
// decoding are depicted.
// Multiply and multiply-accumulate (MUL, MLA); cf. p.23.
2024-03-07 16:45:39 +00:00
//
// This usurps a potential data processing decoding, so needs priority.
2024-02-21 19:51:51 +00:00
if constexpr (((partial >> 22) & 0b111'111) == 0b000'000) {
// This implementation provides only eight bits baked into the template parameters so
// an additional dynamic test is required to check whether this is really, really MUL or MLA.
2024-03-14 14:43:51 +00:00
if((instruction & 0b1111'0000) == 0b1001'0000) {
2024-02-28 16:27:27 +00:00
scheduler.template perform<i>(Multiply(instruction));
return;
}
2024-02-21 19:51:51 +00:00
}
2024-03-07 16:45:39 +00:00
// Data processing; cf. p.17.
if constexpr (((partial >> 26) & 0b11) == 0b00) {
scheduler.template perform<i>(DataProcessing(instruction));
return;
}
2024-02-21 19:51:51 +00:00
// Single data transfer (LDR, STR); cf. p.25.
if constexpr (((partial >> 26) & 0b11) == 0b01) {
2024-02-29 02:23:57 +00:00
scheduler.template perform<i>(SingleDataTransfer(instruction));
return;
}
// Block data transfer (LDM, STM); cf. p.29.
if constexpr (((partial >> 25) & 0b111) == 0b100) {
2024-02-29 02:23:57 +00:00
scheduler.template perform<i>(BlockDataTransfer(instruction));
return;
}
// Branch and branch with link (B, BL); cf. p.15.
if constexpr (((partial >> 25) & 0b111) == 0b101) {
2024-02-28 16:33:28 +00:00
scheduler.template perform<i>(Branch(instruction));
return;
}
// Software interreupt; cf. p.35.
if constexpr (((partial >> 24) & 0b1111) == 0b1111) {
2024-04-19 02:13:58 +00:00
scheduler.software_interrupt(SoftwareInterrupt(instruction));
return;
}
// Both:
// Coprocessor data operation; cf. p. 37; and
// Coprocessor register transfers; cf. p. 42.
if constexpr (((partial >> 24) & 0b1111) == 0b1110) {
if(instruction & (1 << 4)) {
// Register transfer.
2024-02-28 19:43:31 +00:00
scheduler.template perform<i>(CoprocessorRegisterTransfer(instruction));
} else {
// Data operation.
2024-02-28 19:43:31 +00:00
scheduler.template perform<i>(CoprocessorDataOperation(instruction));
}
return;
}
// Coprocessor data transfers; cf. p.39.
if constexpr (((partial >> 25) & 0b111) == 0b110) {
2024-02-28 19:43:31 +00:00
scheduler.template perform<i>(CoprocessorDataTransfer(instruction));
return;
}
// Fallback position.
2024-02-28 19:43:31 +00:00
scheduler.unknown();
}
};
/// A brief documentation of the interface expected by @c dispatch below; will be a concept if/when this project adopts C++20.
struct SampleScheduler {
2024-02-29 02:23:57 +00:00
/// @returns @c true if the rest of the instruction should be decoded and supplied
/// to the scheduler as defined below; @c false otherwise.
bool should_schedule(Condition);
2024-02-29 02:23:57 +00:00
// Template argument:
//
2024-02-29 02:23:57 +00:00
// Flags, an opaque type which can be converted into a DataProcessingFlags, MultiplyFlags, etc,
// by simple construction, to provide all flags that can be baked into the template parameters.
//
2024-02-29 02:23:57 +00:00
// Function argument:
//
2024-02-29 02:23:57 +00:00
// An operation-specific encapsulation of the operation code for decoding of fields that didn't
// fit into the template parameters.
2024-02-29 02:23:57 +00:00
//
// Either or both may be omitted if unnecessary.
2024-02-27 02:36:23 +00:00
template <Flags> void perform(DataProcessing);
2024-02-28 16:42:33 +00:00
template <Flags> void perform(Multiply);
2024-02-29 02:23:57 +00:00
template <Flags> void perform(SingleDataTransfer);
template <Flags> void perform(BlockDataTransfer);
2024-02-28 16:42:33 +00:00
template <Flags> void perform(Branch);
2024-02-28 19:43:31 +00:00
template <Flags> void perform(CoprocessorRegisterTransfer);
template <Flags> void perform(CoprocessorDataOperation);
2024-02-29 02:23:57 +00:00
template <Flags> void perform(CoprocessorDataTransfer);
// Irregular operations.
2024-04-19 02:13:58 +00:00
void software_interrupt(SoftwareInterrupt);
2024-02-29 02:23:57 +00:00
void unknown();
};
2024-02-21 19:18:41 +00:00
/// Decodes @c instruction, making an appropriate call into @c scheduler.
///
2024-02-29 02:23:57 +00:00
/// In lieu of C++20, see the sample definition of SampleScheduler above for the expected interface.
template <Model model, typename SchedulerT> void dispatch(const uint32_t instruction, SchedulerT &scheduler) {
2024-03-03 02:47:09 +00:00
OperationMapper<model> mapper;
2024-02-27 02:36:23 +00:00
// Test condition.
const auto condition = mapper.condition(instruction);
if(!scheduler.should_schedule(condition)) {
return;
}
// Dispatch body.
2024-02-21 19:51:51 +00:00
Reflection::dispatch(mapper, (instruction >> FlagsStartBit) & 0xff, instruction, scheduler);
}
2024-02-17 02:35:49 +00:00
}