2022-04-11 19:00:55 +00:00
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//
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// Instruction.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 10/04/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef InstructionSets_68k_Instruction_hpp
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#define InstructionSets_68k_Instruction_hpp
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2022-04-15 13:40:37 +00:00
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#include "Model.hpp"
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2022-04-11 19:00:55 +00:00
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2022-05-03 15:09:57 +00:00
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#include <cassert>
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#include <cstdint>
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2022-04-11 19:00:55 +00:00
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namespace InstructionSet {
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namespace M68k {
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enum class Operation: uint8_t {
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Undefined,
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2022-04-12 11:49:08 +00:00
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NOP,
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2022-04-11 19:00:55 +00:00
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ABCD, SBCD, NBCD,
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ADDb, ADDw, ADDl,
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ADDAw, ADDAl,
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ADDXb, ADDXw, ADDXl,
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SUBb, SUBw, SUBl,
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SUBAw, SUBAl,
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SUBXb, SUBXw, SUBXl,
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2022-04-13 13:29:12 +00:00
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MOVEb, MOVEw, MOVEl,
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MOVEAw, MOVEAl,
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2022-04-19 23:36:21 +00:00
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LEA, PEA,
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MOVEtoSR, MOVEfromSR,
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MOVEtoCCR,
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MOVEtoUSP, MOVEfromUSP,
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ORItoSR, ORItoCCR,
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ANDItoSR, ANDItoCCR,
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EORItoSR, EORItoCCR,
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2022-04-15 19:33:54 +00:00
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BTST, BCLR,
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BCHG, BSET,
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CMPb, CMPw, CMPl,
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CMPAw, CMPAl,
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TSTb, TSTw, TSTl,
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2022-04-18 12:55:46 +00:00
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JMP,
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JSR, RTS,
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DBcc,
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Scc,
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2022-04-26 16:30:14 +00:00
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Bccb, Bccw, Bccl,
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BSRb, BSRw, BSRl,
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2022-04-18 12:55:46 +00:00
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2022-04-11 19:00:55 +00:00
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CLRb, CLRw, CLRl,
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NEGXb, NEGXw, NEGXl,
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NEGb, NEGw, NEGl,
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ASLb, ASLw, ASLl, ASLm,
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ASRb, ASRw, ASRl, ASRm,
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LSLb, LSLw, LSLl, LSLm,
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LSRb, LSRw, LSRl, LSRm,
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ROLb, ROLw, ROLl, ROLm,
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RORb, RORw, RORl, RORm,
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ROXLb, ROXLw, ROXLl, ROXLm,
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ROXRb, ROXRw, ROXRl, ROXRm,
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2022-04-12 20:17:30 +00:00
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MOVEMl, MOVEMw,
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MOVEPl, MOVEPw,
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ANDb, ANDw, ANDl,
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EORb, EORw, EORl,
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NOTb, NOTw, NOTl,
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ORb, ORw, ORl,
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MULU, MULS,
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DIVU, DIVS,
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2022-04-12 11:49:08 +00:00
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RTE, RTR,
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TRAP, TRAPV,
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CHK,
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EXG, SWAP,
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TAS,
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EXTbtow, EXTwtol,
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2022-04-15 13:40:37 +00:00
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LINKw, UNLINK,
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2022-04-12 11:49:08 +00:00
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STOP, RESET,
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Max = RESET
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};
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2022-04-15 13:40:37 +00:00
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template <Model model>
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constexpr bool requires_supervisor(Operation op) {
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switch(op) {
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2022-04-26 00:05:45 +00:00
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case Operation::MOVEfromSR:
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if constexpr (model == Model::M68000) {
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return false;
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}
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[[fallthrough]];
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case Operation::ORItoSR: case Operation::ANDItoSR:
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case Operation::EORItoSR: case Operation::RTE:
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case Operation::RESET: case Operation::STOP:
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case Operation::MOVEtoUSP: case Operation::MOVEfromUSP:
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return true;
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default:
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return false;
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}
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}
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2022-04-26 16:30:14 +00:00
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enum class DataSize {
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Byte = 0,
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Word = 1,
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LongWord = 2,
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};
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/// Classifies operations by the size of their memory accesses, if any.
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constexpr DataSize size(Operation operation) {
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switch(operation) {
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// These are given a value arbitrarily, to
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// complete the switch statement.
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case Operation::Undefined:
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case Operation::NOP:
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case Operation::STOP:
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case Operation::RESET:
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case Operation::RTE: case Operation::RTR:
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case Operation::TRAP:
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case Operation::TRAPV:
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case Operation::ABCD: case Operation::SBCD:
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case Operation::NBCD:
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2022-04-13 13:29:12 +00:00
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case Operation::ADDb: case Operation::ADDXb:
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case Operation::SUBb: case Operation::SUBXb:
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case Operation::MOVEb:
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case Operation::ORItoCCR:
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case Operation::ANDItoCCR:
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case Operation::EORItoCCR:
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2022-04-26 16:30:14 +00:00
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case Operation::BTST: case Operation::BCLR:
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case Operation::BCHG: case Operation::BSET:
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case Operation::CMPb: case Operation::TSTb:
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case Operation::Bccb: case Operation::BSRb:
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case Operation::CLRb:
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case Operation::Scc:
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case Operation::NEGXb: case Operation::NEGb:
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case Operation::ASLb: case Operation::ASRb:
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case Operation::LSLb: case Operation::LSRb:
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case Operation::ROLb: case Operation::RORb:
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case Operation::ROXLb: case Operation::ROXRb:
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case Operation::ANDb: case Operation::EORb:
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case Operation::NOTb: case Operation::ORb:
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case Operation::CHK:
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case Operation::TAS:
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return DataSize::Byte;
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case Operation::ADDw: case Operation::ADDAw:
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case Operation::ADDXw: case Operation::SUBw:
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case Operation::SUBAw: case Operation::SUBXw:
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case Operation::MOVEw: case Operation::MOVEAw:
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2022-04-15 13:40:37 +00:00
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case Operation::ORItoSR:
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case Operation::ANDItoSR:
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case Operation::EORItoSR:
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2022-04-26 16:30:14 +00:00
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case Operation::MOVEtoSR:
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case Operation::MOVEfromSR:
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case Operation::MOVEtoCCR:
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case Operation::CMPw: case Operation::CMPAw:
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case Operation::TSTw:
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2022-05-03 18:40:51 +00:00
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case Operation::DBcc:
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case Operation::Bccw: case Operation::BSRw:
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case Operation::CLRw:
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case Operation::NEGXw: case Operation::NEGw:
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case Operation::ASLw: case Operation::ASLm:
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case Operation::ASRw: case Operation::ASRm:
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case Operation::LSLw: case Operation::LSLm:
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case Operation::LSRw: case Operation::LSRm:
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case Operation::ROLw: case Operation::ROLm:
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case Operation::RORw: case Operation::RORm:
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case Operation::ROXLw: case Operation::ROXLm:
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case Operation::ROXRw: case Operation::ROXRm:
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case Operation::MOVEMw:
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case Operation::MOVEPw:
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case Operation::ANDw: case Operation::EORw:
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case Operation::NOTw: case Operation::ORw:
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case Operation::DIVU: case Operation::DIVS:
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case Operation::MULU: case Operation::MULS:
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case Operation::EXTbtow:
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case Operation::LINKw:
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return DataSize::Word;
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case Operation::ADDl: case Operation::ADDAl:
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case Operation::ADDXl: case Operation::SUBl:
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case Operation::SUBAl: case Operation::SUBXl:
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case Operation::MOVEl: case Operation::MOVEAl:
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case Operation::LEA: case Operation::PEA:
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case Operation::EXG: case Operation::SWAP:
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case Operation::MOVEtoUSP:
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case Operation::MOVEfromUSP:
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case Operation::CMPl: case Operation::CMPAl:
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case Operation::TSTl:
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case Operation::JMP: case Operation::JSR:
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case Operation::RTS:
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case Operation::Bccl: case Operation::BSRl:
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case Operation::CLRl:
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case Operation::NEGXl: case Operation::NEGl:
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case Operation::ASLl: case Operation::ASRl:
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case Operation::LSLl: case Operation::LSRl:
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case Operation::ROLl: case Operation::RORl:
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case Operation::ROXLl: case Operation::ROXRl:
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case Operation::MOVEMl:
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case Operation::MOVEPl:
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case Operation::ANDl: case Operation::EORl:
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case Operation::NOTl: case Operation::ORl:
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case Operation::EXTwtol:
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case Operation::UNLINK:
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return DataSize::LongWord;
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}
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}
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2022-05-03 15:09:57 +00:00
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template <Operation t_op = Operation::Undefined>
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constexpr uint32_t quick(uint16_t instruction, Operation r_op = Operation::Undefined) {
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switch((t_op != Operation::Undefined) ? t_op : r_op) {
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case Operation::Bccb:
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case Operation::BSRb:
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case Operation::MOVEl: return uint32_t(int8_t(instruction));
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case Operation::TRAP: return uint32_t(instruction & 15);
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default: {
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2022-04-26 16:30:14 +00:00
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uint32_t value = (instruction >> 9) & 7;
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2022-04-21 20:05:00 +00:00
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value |= (value - 1)&8;
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return value;
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}
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}
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}
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2022-05-03 15:09:57 +00:00
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static constexpr uint8_t FetchOp1 = (1 << 0);
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static constexpr uint8_t FetchOp2 = (1 << 1);
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static constexpr uint8_t StoreOp1 = (1 << 2);
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static constexpr uint8_t StoreOp2 = (1 << 3);
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/*!
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Provides a bitfield with a value in the range 0–15 indicating which of the provided operation's
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operands are accessed via standard fetch and store cycles.
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2022-04-22 14:06:39 +00:00
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2022-05-03 15:09:57 +00:00
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Unusual bus sequences, such as TAS or MOVEM, are not described here.
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*/
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template <Model model, Operation t_operation = Operation::Undefined> uint8_t operand_flags(Operation r_operation = Operation::Undefined) {
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switch((t_operation != Operation::Undefined) ? t_operation : r_operation) {
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2022-04-22 14:06:39 +00:00
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default:
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assert(false);
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//
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// No operands are fetched or stored.
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2022-05-03 19:49:55 +00:00
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// (which means that source and destination will appear as their effective addresses)
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2022-05-03 15:09:57 +00:00
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//
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2022-05-03 19:49:55 +00:00
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case Operation::LEA: case Operation::PEA:
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case Operation::JMP: case Operation::JSR:
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2022-05-03 15:09:57 +00:00
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return 0;
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//
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// Single-operand read.
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//
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case Operation::MOVEtoSR: case Operation::MOVEtoCCR: case Operation::MOVEtoUSP:
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case Operation::ORItoSR: case Operation::ORItoCCR:
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case Operation::ANDItoSR: case Operation::ANDItoCCR:
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case Operation::EORItoSR: case Operation::EORItoCCR:
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2022-05-03 18:45:49 +00:00
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case Operation::Bccb: case Operation::Bccw: case Operation::Bccl:
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2022-05-03 19:32:54 +00:00
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case Operation::BSRb: case Operation::BSRw: case Operation::BSRl:
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2022-05-03 15:09:57 +00:00
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return FetchOp1;
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//
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// Single-operand write.
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//
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case Operation::MOVEfromSR: case Operation::MOVEfromUSP:
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2022-05-03 18:23:57 +00:00
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case Operation::Scc:
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2022-05-03 15:09:57 +00:00
|
|
|
|
return StoreOp1;
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Single-operand read-modify-write.
|
|
|
|
|
//
|
|
|
|
|
case Operation::NBCD:
|
2022-05-03 19:40:04 +00:00
|
|
|
|
case Operation::NOTb: case Operation::NOTw: case Operation::NOTl:
|
|
|
|
|
case Operation::NEGb: case Operation::NEGw: case Operation::NEGl:
|
|
|
|
|
case Operation::NEGXb: case Operation::NEGXw: case Operation::NEGXl:
|
2022-05-03 15:09:57 +00:00
|
|
|
|
case Operation::EXTbtow: case Operation::EXTwtol:
|
2022-05-03 19:49:55 +00:00
|
|
|
|
case Operation::SWAP:
|
2022-05-03 15:09:57 +00:00
|
|
|
|
return FetchOp1 | StoreOp1;
|
|
|
|
|
|
2022-05-03 19:40:04 +00:00
|
|
|
|
//
|
|
|
|
|
// CLR, which is model-dependent.
|
|
|
|
|
//
|
|
|
|
|
case Operation::CLRb: case Operation::CLRw: case Operation::CLRl:
|
|
|
|
|
if constexpr (model == Model::M68000) {
|
|
|
|
|
return FetchOp1 | StoreOp1;
|
|
|
|
|
} else {
|
|
|
|
|
return StoreOp1;
|
|
|
|
|
}
|
|
|
|
|
|
2022-05-03 15:09:57 +00:00
|
|
|
|
//
|
|
|
|
|
// Two-operand; read both.
|
|
|
|
|
//
|
|
|
|
|
case Operation::CMPb: case Operation::CMPw: case Operation::CMPl:
|
|
|
|
|
case Operation::CMPAw: case Operation::CMPAl:
|
2022-05-03 19:40:04 +00:00
|
|
|
|
case Operation::CHK:
|
2022-05-03 15:09:57 +00:00
|
|
|
|
return FetchOp1 | FetchOp2;
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Two-operand; read source, write dest.
|
|
|
|
|
//
|
|
|
|
|
case Operation::MOVEb: case Operation::MOVEw: case Operation::MOVEl:
|
|
|
|
|
case Operation::MOVEAw: case Operation::MOVEAl:
|
|
|
|
|
return FetchOp1 | StoreOp2;
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Two-operand; read both, write dest.
|
|
|
|
|
//
|
|
|
|
|
case Operation::ABCD: case Operation::SBCD:
|
|
|
|
|
case Operation::ADDb: case Operation::ADDw: case Operation::ADDl:
|
|
|
|
|
case Operation::ADDAw: case Operation::ADDAl:
|
|
|
|
|
case Operation::ADDXb: case Operation::ADDXw: case Operation::ADDXl:
|
|
|
|
|
case Operation::SUBb: case Operation::SUBw: case Operation::SUBl:
|
|
|
|
|
case Operation::SUBAw: case Operation::SUBAl:
|
|
|
|
|
case Operation::SUBXb: case Operation::SUBXw: case Operation::SUBXl:
|
|
|
|
|
case Operation::ORb: case Operation::ORw: case Operation::ORl:
|
|
|
|
|
case Operation::ANDb: case Operation::ANDw: case Operation::ANDl:
|
|
|
|
|
case Operation::EORb: case Operation::EORw: case Operation::EORl:
|
2022-05-03 19:49:55 +00:00
|
|
|
|
case Operation::DIVU: case Operation::DIVS:
|
|
|
|
|
case Operation::MULU: case Operation::MULS:
|
2022-05-03 15:09:57 +00:00
|
|
|
|
return FetchOp1 | FetchOp2 | StoreOp2;
|
|
|
|
|
|
2022-05-03 19:40:04 +00:00
|
|
|
|
// case Operation::MOVEMw:
|
|
|
|
|
// case Operation::MOVEMl:
|
|
|
|
|
|
2022-05-03 18:40:51 +00:00
|
|
|
|
//
|
|
|
|
|
// Two-operand; read both, write source.
|
|
|
|
|
//
|
|
|
|
|
case Operation::DBcc:
|
|
|
|
|
return FetchOp1 | FetchOp2 | StoreOp1;
|
|
|
|
|
|
2022-05-03 15:09:57 +00:00
|
|
|
|
//
|
|
|
|
|
// Two-operand; read both, write both.
|
|
|
|
|
//
|
|
|
|
|
case Operation::EXG:
|
|
|
|
|
return FetchOp1 | FetchOp2 | StoreOp1 | StoreOp2;
|
2022-04-21 20:05:00 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2022-04-30 13:00:47 +00:00
|
|
|
|
enum class Condition {
|
|
|
|
|
True = 0x00, False = 0x01,
|
|
|
|
|
High = 0x02, LowOrSame = 0x03,
|
|
|
|
|
CarryClear = 0x04, CarrySet = 0x05,
|
|
|
|
|
NotEqual = 0x06, Equal = 0x07,
|
|
|
|
|
OverflowClear = 0x08, OverflowSet = 0x09,
|
|
|
|
|
Positive = 0x0a, Negative = 0x0b,
|
|
|
|
|
GreaterThanOrEqual = 0x0c, LessThan = 0x0d,
|
|
|
|
|
GreaterThan = 0x0e, LessThanOrEqual = 0x0f,
|
|
|
|
|
};
|
|
|
|
|
|
2022-04-11 19:00:55 +00:00
|
|
|
|
/// Indicates the addressing mode applicable to an operand.
|
|
|
|
|
///
|
|
|
|
|
/// Implementation notes:
|
|
|
|
|
///
|
|
|
|
|
/// Those entries starting 0b00 or 0b01 are mapped as per the 68000's native encoding;
|
|
|
|
|
/// those starting 0b00 are those which are indicated directly by a mode field and those starting
|
|
|
|
|
/// 0b01 are those which are indicated by a register field given a mode of 0b111. The only minor
|
|
|
|
|
/// exception is AddressRegisterDirect, which exists on a 68000 but isn't specifiable by a
|
|
|
|
|
/// mode and register, it's contextual based on the instruction.
|
|
|
|
|
///
|
|
|
|
|
/// Those modes starting in 0b10 are the various extended addressing modes introduced as
|
|
|
|
|
/// of the 68020, which can be detected only after interpreting an extension word. At the
|
|
|
|
|
/// Preinstruction stage:
|
|
|
|
|
///
|
|
|
|
|
/// * AddressRegisterIndirectWithIndexBaseDisplacement, MemoryIndirectPostindexed
|
|
|
|
|
/// and MemoryIndirectPreindexed will have been partially decoded as
|
|
|
|
|
/// AddressRegisterIndirectWithIndex8bitDisplacement; and
|
|
|
|
|
/// * ProgramCounterIndirectWithIndexBaseDisplacement,
|
|
|
|
|
/// ProgramCounterMemoryIndirectPostindexed and
|
|
|
|
|
/// ProgramCounterMemoryIndirectPreindexed will have been partially decoded
|
|
|
|
|
/// as ProgramCounterIndirectWithIndex8bitDisplacement.
|
|
|
|
|
enum class AddressingMode: uint8_t {
|
|
|
|
|
/// No adddressing mode; this operand doesn't exist.
|
2022-04-24 14:43:06 +00:00
|
|
|
|
None = 0b01'101,
|
2022-04-11 19:00:55 +00:00
|
|
|
|
|
|
|
|
|
/// Dn
|
|
|
|
|
DataRegisterDirect = 0b00'000,
|
|
|
|
|
|
|
|
|
|
/// An
|
2022-04-12 18:54:11 +00:00
|
|
|
|
AddressRegisterDirect = 0b00'001,
|
2022-04-11 19:00:55 +00:00
|
|
|
|
/// (An)
|
|
|
|
|
AddressRegisterIndirect = 0b00'010,
|
|
|
|
|
/// (An)+
|
|
|
|
|
AddressRegisterIndirectWithPostincrement = 0b00'011,
|
|
|
|
|
/// -(An)
|
|
|
|
|
AddressRegisterIndirectWithPredecrement = 0b00'100,
|
|
|
|
|
/// (d16, An)
|
|
|
|
|
AddressRegisterIndirectWithDisplacement = 0b00'101,
|
|
|
|
|
/// (d8, An, Xn)
|
|
|
|
|
AddressRegisterIndirectWithIndex8bitDisplacement = 0b00'110,
|
2022-05-01 19:10:54 +00:00
|
|
|
|
/// (bd, An, Xn) [68020+]
|
2022-04-11 19:00:55 +00:00
|
|
|
|
AddressRegisterIndirectWithIndexBaseDisplacement = 0b10'000,
|
|
|
|
|
|
2022-05-01 19:10:54 +00:00
|
|
|
|
/// ([bd, An, Xn], od) [68020+]
|
2022-04-11 19:00:55 +00:00
|
|
|
|
MemoryIndirectPostindexed = 0b10'001,
|
2022-05-01 19:10:54 +00:00
|
|
|
|
/// ([bd, An], Xn, od) [68020+]
|
2022-04-11 19:00:55 +00:00
|
|
|
|
MemoryIndirectPreindexed = 0b10'010,
|
|
|
|
|
|
|
|
|
|
/// (d16, PC)
|
|
|
|
|
ProgramCounterIndirectWithDisplacement = 0b01'010,
|
|
|
|
|
/// (d8, PC, Xn)
|
|
|
|
|
ProgramCounterIndirectWithIndex8bitDisplacement = 0b01'011,
|
2022-05-01 19:10:54 +00:00
|
|
|
|
/// (bd, PC, Xn) [68020+]
|
2022-04-11 19:00:55 +00:00
|
|
|
|
ProgramCounterIndirectWithIndexBaseDisplacement = 0b10'011,
|
2022-05-01 19:10:54 +00:00
|
|
|
|
/// ([bd, PC, Xn], od) [68020+]
|
2022-04-11 19:00:55 +00:00
|
|
|
|
ProgramCounterMemoryIndirectPostindexed = 0b10'100,
|
2022-05-01 19:10:54 +00:00
|
|
|
|
/// ([bc, PC], Xn, od) [68020+]
|
2022-04-11 19:00:55 +00:00
|
|
|
|
ProgramCounterMemoryIndirectPreindexed = 0b10'101,
|
|
|
|
|
|
|
|
|
|
/// (xxx).W
|
|
|
|
|
AbsoluteShort = 0b01'000,
|
|
|
|
|
/// (xxx).L
|
|
|
|
|
AbsoluteLong = 0b01'001,
|
|
|
|
|
|
|
|
|
|
/// #
|
|
|
|
|
ImmediateData = 0b01'100,
|
2022-04-13 13:29:12 +00:00
|
|
|
|
|
2022-04-19 12:37:35 +00:00
|
|
|
|
/// .q; value is embedded in the opcode.
|
2022-04-24 14:43:06 +00:00
|
|
|
|
Quick = 0b01'110,
|
2022-04-11 19:00:55 +00:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*!
|
|
|
|
|
A preinstruction is as much of an instruction as can be decoded with
|
|
|
|
|
only the first instruction word — i.e. an operation, and:
|
|
|
|
|
|
|
|
|
|
* on the 68000 and 68010, the complete addressing modes;
|
|
|
|
|
* on subsequent, a decent proportion of the addressing mode. See
|
|
|
|
|
the notes on @c AddressingMode for potential aliasing.
|
|
|
|
|
*/
|
|
|
|
|
class Preinstruction {
|
|
|
|
|
public:
|
|
|
|
|
Operation operation = Operation::Undefined;
|
|
|
|
|
|
2022-04-12 13:14:46 +00:00
|
|
|
|
// Instructions come with 0, 1 or 2 operands;
|
|
|
|
|
// the getters below act to provide a list of operands
|
|
|
|
|
// that is terminated by an AddressingMode::None.
|
|
|
|
|
//
|
|
|
|
|
// For two-operand instructions, argument 0 is a source
|
|
|
|
|
// and argument 1 is a destination.
|
|
|
|
|
//
|
|
|
|
|
// For one-operand instructions, only argument 0 will
|
|
|
|
|
// be provided, and will be a source and/or destination as
|
|
|
|
|
// per the semantics of the operation.
|
2022-05-01 17:00:20 +00:00
|
|
|
|
//
|
|
|
|
|
// The versions templated on index do a range check;
|
|
|
|
|
// if using the runtime versions then results for indices
|
|
|
|
|
// other than 0 and 1 are undefined.
|
2022-04-12 13:14:46 +00:00
|
|
|
|
|
2022-05-01 17:00:20 +00:00
|
|
|
|
AddressingMode mode(int index) const {
|
|
|
|
|
return AddressingMode(operands_[index] & 0x1f);
|
|
|
|
|
}
|
2022-04-19 18:35:40 +00:00
|
|
|
|
template <int index> AddressingMode mode() const {
|
2022-04-12 13:14:46 +00:00
|
|
|
|
if constexpr (index > 1) {
|
|
|
|
|
return AddressingMode::None;
|
|
|
|
|
}
|
2022-05-01 17:00:20 +00:00
|
|
|
|
return mode(index);
|
|
|
|
|
}
|
|
|
|
|
int reg(int index) const {
|
|
|
|
|
return operands_[index] >> 5;
|
2022-04-11 19:00:55 +00:00
|
|
|
|
}
|
2022-04-19 18:35:40 +00:00
|
|
|
|
template <int index> int reg() const {
|
2022-04-12 13:14:46 +00:00
|
|
|
|
if constexpr (index > 1) {
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2022-05-01 17:00:20 +00:00
|
|
|
|
return reg(index);
|
2022-04-11 19:00:55 +00:00
|
|
|
|
}
|
|
|
|
|
|
2022-05-01 17:00:20 +00:00
|
|
|
|
bool requires_supervisor() const {
|
2022-04-26 23:44:02 +00:00
|
|
|
|
return flags_ & 0x80;
|
|
|
|
|
}
|
2022-05-01 17:00:20 +00:00
|
|
|
|
DataSize size() const {
|
2022-04-30 13:00:47 +00:00
|
|
|
|
return DataSize(flags_ & 0x03);
|
|
|
|
|
}
|
2022-05-01 17:00:20 +00:00
|
|
|
|
Condition condition() const {
|
2022-04-30 13:00:47 +00:00
|
|
|
|
return Condition((flags_ >> 2) & 0x0f);
|
2022-04-26 23:44:02 +00:00
|
|
|
|
}
|
|
|
|
|
|
2022-04-11 19:00:55 +00:00
|
|
|
|
private:
|
2022-04-12 13:14:46 +00:00
|
|
|
|
uint8_t operands_[2] = { uint8_t(AddressingMode::None), uint8_t(AddressingMode::None)};
|
2022-04-26 23:44:02 +00:00
|
|
|
|
uint8_t flags_ = 0;
|
2022-04-11 19:00:55 +00:00
|
|
|
|
|
|
|
|
|
public:
|
|
|
|
|
Preinstruction(
|
|
|
|
|
Operation operation,
|
2022-04-12 13:14:46 +00:00
|
|
|
|
AddressingMode op1_mode, int op1_reg,
|
2022-04-12 18:54:11 +00:00
|
|
|
|
AddressingMode op2_mode, int op2_reg,
|
2022-04-26 23:44:02 +00:00
|
|
|
|
bool is_supervisor,
|
2022-04-30 13:00:47 +00:00
|
|
|
|
DataSize size,
|
|
|
|
|
Condition condition) : operation(operation)
|
2022-04-12 13:14:46 +00:00
|
|
|
|
{
|
|
|
|
|
operands_[0] = uint8_t(op1_mode) | uint8_t(op1_reg << 5);
|
|
|
|
|
operands_[1] = uint8_t(op2_mode) | uint8_t(op2_reg << 5);
|
2022-04-30 13:00:47 +00:00
|
|
|
|
flags_ = uint8_t(
|
|
|
|
|
(is_supervisor ? 0x80 : 0x00) |
|
|
|
|
|
(int(condition) << 2) |
|
|
|
|
|
int(size)
|
|
|
|
|
);
|
2022-04-11 19:00:55 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Preinstruction() {}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif /* InstructionSets_68k_Instruction_hpp */
|