 Thomas Harte
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105272630e
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Definitively eliminate per-logger state.
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2025-09-11 23:29:47 -04:00 |
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Thomas Harte
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5018d7d577
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Be more rigorous about static constexpr.
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2025-08-26 22:54:39 -04:00 |
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Thomas Harte
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0823fc32fe
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Eliminate file-relative paths.
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2025-02-28 12:30:25 -05:00 |
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Thomas Harte
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0c2a4f442e
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Resolve all commented-out old logging references.
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2024-01-19 22:17:35 -05:00 |
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Thomas Harte
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18814f7b2c
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Update use of logging.
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2024-01-19 22:14:24 -05:00 |
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Thomas Harte
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bfc77f1606
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Add workaround that further isolates whatever bug Spindizzy reveals.
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2022-08-19 16:38:42 -04:00 |
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Thomas Harte
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837acdcf60
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Experimentally decline immediate blits.
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2022-08-16 21:51:13 -04:00 |
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Thomas Harte
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bb54ac14b8
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Prove that new output errors are [probably] external to the Blitter.
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2022-08-15 11:10:17 -04:00 |
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Thomas Harte
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d4b7d73fc4
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Further reduces lines to one access per slot, max.
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2022-08-07 19:19:00 -04:00 |
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Thomas Harte
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867769f6e7
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Reduces line drawing to two accesses per slot.
Still a fiction, but a better one.
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2022-08-07 19:15:03 -04:00 |
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Thomas Harte
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45892f3584
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Add optional transaction records to the Blitter.
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2022-08-06 09:51:20 -04:00 |
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Thomas Harte
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612413cb1c
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Remove redundant state.
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2022-08-04 10:06:14 -04:00 |
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Thomas Harte
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511ec5a736
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Apply modulos at end of final line.
Possibly I need to rethink the sequence logic?
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2022-07-30 21:35:26 -04:00 |
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Thomas Harte
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4fb9dec381
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Fix use of bool.
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2022-07-30 21:02:44 -04:00 |
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Thomas Harte
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82476bdabe
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Avoid 'complete' repetition.
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2022-07-30 21:02:04 -04:00 |
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Thomas Harte
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58ee8e2460
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Minor tidy-up. No fixes.
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2022-07-30 21:00:50 -04:00 |
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Thomas Harte
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94a90b7a89
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Attempt a real slot-by-slot blit.
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2022-07-30 20:34:37 -04:00 |
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Thomas Harte
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27b8c29096
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Apply modulos at end of line, not beginning.
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2022-07-30 10:27:53 -04:00 |
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Thomas Harte
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93d2a612ee
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Add an explicit flush-pipeline step; some tests now pass.
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2022-07-29 16:33:46 -04:00 |
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Thomas Harte
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03d4960a03
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Begin a full-synchronous usage of the sequencer, at least exposing poor handling of the pipeline.
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2022-07-29 16:15:18 -04:00 |
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Thomas Harte
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2c95dea4db
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Introduce putative blitter sequencer.
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2022-07-26 17:05:05 -04:00 |
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Thomas Harte
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d0e3024bec
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Switch to nibble-oriented lookup tables for fill mode.
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2021-12-19 17:16:46 -05:00 |
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Thomas Harte
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d2ad149e56
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Fill mode always runs right to left.
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2021-12-19 16:43:18 -05:00 |
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Thomas Harte
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012084b37b
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Fix exclusive fill, sizing, eliminate ECS call-ins.
The clock test now proceeds further, but still doesn't seem to pass.
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2021-11-24 17:25:32 -05:00 |
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Thomas Harte
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47f36f08fb
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Switches to a synchronous audio state machine; renames advance -> advance_dma.
I can worry about how to just-in-time things once I better understand the hardware in general.
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2021-11-13 15:53:41 -05:00 |
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Thomas Harte
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8ef9a932aa
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Adds inclusive fill test; fixes inclusive fills.
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2021-11-07 14:26:13 -08:00 |
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Thomas Harte
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299d517449
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Performs a first implementation of fill mode.
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2021-10-31 14:36:31 -07:00 |
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Thomas Harte
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edb75e69cb
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Implement bitplane modulos.
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2021-10-29 11:29:22 -07:00 |
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Thomas Harte
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f3e895f17c
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Tag intended unused parameters.
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2021-10-29 06:21:02 -07:00 |
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Thomas Harte
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07facc0636
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Takes a stab at BZERO.
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2021-10-28 18:12:46 -07:00 |
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Thomas Harte
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b10f5ab110
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Apply A mask when loading into barrel shifter.
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2021-10-26 20:02:28 -07:00 |
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Thomas Harte
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b4286bb42b
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Modulos are subtracted in descending mode.
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2021-10-26 07:21:51 -07:00 |
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Thomas Harte
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7118a515e0
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Reduce logging in trustworthy areas.
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2021-10-23 20:36:41 -07:00 |
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Thomas Harte
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4917556a99
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The shift goes the other way in descending mode.
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2021-10-16 11:09:40 -07:00 |
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Thomas Harte
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aa6b0f07b7
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Correct filename.
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2021-10-16 05:37:46 -07:00 |
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Thomas Harte
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9be23ecc34
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Add end-of-Blit interrupt.
Along with a slightly easier path for posting interrupts, in C++ compilation unit terms.
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2021-10-13 15:09:19 -07:00 |
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Thomas Harte
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a282a51673
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Remove last of the direct printf'ing.
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2021-09-30 02:42:59 -04:00 |
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Thomas Harte
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b7b13e20d1
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Single column blits should use both masks.
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2021-09-29 22:49:35 -04:00 |
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Thomas Harte
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402fa41bc0
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Corrects initial error value.
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2021-09-29 22:19:17 -04:00 |
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Thomas Harte
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140e24ef15
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Grab further copy flags.
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2021-09-28 22:11:58 -04:00 |
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Thomas Harte
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ffcd2ea10c
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Attempts more properly to implement line mode.
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2021-09-28 21:39:09 -04:00 |
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Thomas Harte
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cb460de94d
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Makes bad first attempt at a Bresenham inner loop.
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2021-09-27 22:06:00 -04:00 |
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Thomas Harte
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f6624bf776
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Edges mildly closer to line output.
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2021-09-26 19:18:12 -04:00 |
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Thomas Harte
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b4b6c4d86f
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Attempts to support left and right masks.
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2021-09-26 18:42:08 -04:00 |
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Thomas Harte
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759689ff31
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Fix line mode flag, add busy status.
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2021-09-26 18:16:00 -04:00 |
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Thomas Harte
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42ef459e20
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Resolve resting values.
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2021-09-23 22:05:59 -04:00 |
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Thomas Harte
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cad1a9e0f1
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Correct bit test.
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2021-09-23 20:42:31 -04:00 |
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Thomas Harte
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9a7a54f22f
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Take alternative guess as to meaning of 'use' bits.
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2021-09-23 18:42:12 -04:00 |
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Thomas Harte
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137d1c61bd
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Allow for channel enables and blitting direction.
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2021-09-23 18:38:37 -04:00 |
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Thomas Harte
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adc071ed7a
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Fix: modulos are 15-bit signed, the minterms are also in regular BLTCON0.
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2021-09-23 18:30:35 -04:00 |
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