Thomas Harte
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0245b040b0
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Splits TOD storage by model.
TOD storage will probably end up being a full-on class.
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2021-08-03 18:50:58 -04:00 |
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Thomas Harte
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ef58ce6277
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Gets a bit more rigorous about the clocking stage.
Albeit without advancing relative to the test.
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2021-08-02 21:04:00 -04:00 |
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Thomas Harte
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15de5e98c4
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Adds [partial] test for whether counters are linked.
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2021-08-02 20:17:37 -04:00 |
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Thomas Harte
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38848ca2db
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Rationalises reload logic and cuts storage.
Failure point is now chaining, I think.
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2021-08-02 20:14:01 -04:00 |
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Thomas Harte
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77c627e822
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Ensure that reading the interrupt flags really clears the master bit.
Also makes some guesses on one-shot and reload timing. Alas the test isn't in itself specific enough to be more systematic here.
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2021-08-02 07:47:08 -04:00 |
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Thomas Harte
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c640132699
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Reinstates clocking.
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2021-08-01 21:35:08 -04:00 |
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Thomas Harte
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57dd38aef2
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Reintroduces reload-on-off, adds interrupt delay.
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2021-08-01 21:09:02 -04:00 |
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Thomas Harte
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460a6cb6fe
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Attempts a more literal implementation.
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2021-08-01 18:14:10 -04:00 |
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Thomas Harte
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3d160ce85f
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Add another potential warning.
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2021-07-30 18:21:38 -04:00 |
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Thomas Harte
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759007ffc1
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Attempts to route CIA interrupts.
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2021-07-28 19:36:30 -04:00 |
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Thomas Harte
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37a55c3a77
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Corrects 6526 interrupt control write.
This seems to imply that the 6526 should be interrupting too.
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2021-07-28 19:26:02 -04:00 |
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Thomas Harte
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bcb7bb5cce
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Improves logging further.
To investigate the new perpetual loop.
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2021-07-26 17:02:30 -04:00 |
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Thomas Harte
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34d4420e8c
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Correct reading of top byte of counter 2.
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2021-07-25 20:41:15 -04:00 |
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Thomas Harte
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fcd6b7b0ea
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Takes further aim at the conters.
I think test cases are needed, probably.
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2021-07-24 16:06:49 -04:00 |
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Thomas Harte
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ceca32ceb3
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Takes a guess at one-shot mode.
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2021-07-24 15:53:18 -04:00 |
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Thomas Harte
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77a8ddb95c
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Edges towards working counters.
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2021-07-23 22:43:47 -04:00 |
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Thomas Harte
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c733a4dbf8
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Beefs up interrupt awareness.
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2021-07-23 21:58:52 -04:00 |
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Thomas Harte
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d898a43dff
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Implements time-of-day counters, provisionally.
Interrupts to do.
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2021-07-23 21:24:07 -04:00 |
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Thomas Harte
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6123349b79
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Stubs in control registers and disables exit-on-miss.
I think I may be running up against the limits of stubbing now. Probably time to implement some stuff.
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2021-07-22 19:28:01 -04:00 |
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Thomas Harte
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56b62a5e49
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Adds a dummy interrupt control register.
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2021-07-22 16:09:32 -04:00 |
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Thomas Harte
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a030d9935e
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Adds port input.
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2021-07-18 20:25:04 -04:00 |
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Thomas Harte
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c425dec4d5
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Makes some attempt to get as far as the overlay being disabled.
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2021-07-18 17:17:41 -04:00 |
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Thomas Harte
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67d53601d5
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Latch and return data direction.
Albeit with no port-handling effect yet.
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2021-07-18 12:23:47 -04:00 |
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Thomas Harte
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622cca0acf
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Adds sufficient address decoding to print a more helpful exit message.
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2021-07-18 12:13:56 -04:00 |
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Thomas Harte
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48999c03a5
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Adds concept of time, captured port handler.
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2021-07-18 11:49:10 -04:00 |
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Thomas Harte
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377cc7bdcd
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Start to introduce a 6526/8250.
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2021-07-18 11:36:13 -04:00 |
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