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380 Commits

Author SHA1 Message Date
Thomas Harte
40339a12e1 Formalised the use of a cycles count with a divider, bringing a few additional plain-int users into the fold. 2017-07-25 07:15:31 -04:00
Thomas Harte
9be9bd9106 Neatened layout. 2017-07-24 22:52:35 -04:00
Thomas Harte
c1527cc9e2 Reduced back-and-forth between Cycles and ints within the Oric. 2017-07-24 22:46:31 -04:00
Thomas Harte
a1a3aab115 Fixed implicit sign conversion. 2017-07-24 22:40:15 -04:00
Thomas Harte
c77a83d86f The 6560 is now a ClockReceiver. This reduces to zero the number of remaining instances of the text run_for_cycles in this codebase. 2017-07-24 22:38:35 -04:00
Thomas Harte
efdac2ce8c The 6522 is now a ClockReceiver. 2017-07-24 22:29:09 -04:00
Thomas Harte
2912d7055b The 6532 is now a ClockReceiver. 2017-07-24 21:57:24 -04:00
Thomas Harte
b7f88e8f61 Filter is now a ClockReciever, affecting all sound output devices. 2017-07-24 21:29:13 -04:00
Thomas Harte
8a2bdb8d22 Converted the TimedEventLoop and the things that sit atop it into ClockReceivers. 2017-07-24 21:19:05 -04:00
Thomas Harte
b82bef95f3 Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion. 2017-07-24 20:10:05 -04:00
Thomas Harte
8a0b0cb3d7 Extended both classes to allow copy assignment, copy construction and implicit zero-length construction. 2017-07-23 22:13:41 -04:00
Thomas Harte
1ba3f262a2 Sketched out a template for clock-receiving components to allow them to be implemented in terms of either half or whole cycles. 2017-07-22 21:46:50 -04:00
Thomas Harte
8755824c64 Added some documentation. 2017-07-22 17:25:53 -04:00
Thomas Harte
64865b3f41 Signedness fixes. 2017-07-21 21:23:34 -04:00
Thomas Harte
53f0e1896b Made delay_time_ unsigned for safe comparison. 2017-07-21 21:21:23 -04:00
Thomas Harte
aaa60dab12 Fixed signedness of index. 2017-07-21 21:21:01 -04:00
Thomas Harte
12f7e1b804 Enshrined a default colour burst amplitude. Which now everybody relies on. The 102 figure is derived from the burst apparently being 40 IRE. 2017-07-07 23:35:14 -04:00
Thomas Harte
eb8a2de5d6 Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80. 2017-05-15 07:38:59 -04:00
Thomas Harte
e270b726b3 Tweaked blue, increased saturation. 2017-05-13 22:01:02 -04:00
Thomas Harte
44ce7fa54c Corrected luminances across the board, and PAL colours. 2017-05-13 21:50:09 -04:00
Thomas Harte
b0142cf050 Made an updated stab at NTSC colours. 2017-05-13 14:29:36 -04:00
Thomas Harte
a340331229 Introduced 1-bit of saturation, returning black and white as black and white. 2017-05-11 21:31:58 -04:00
Thomas Harte
15d17c12d5 Switched the 6560 to two bytes per pixel, since one isn't sufficient for precision and because mixing up the implementation might help me to figure out what's amiss. 2017-05-09 21:22:01 -04:00
Thomas Harte
5998123868 Added some consts, for a minor safety improvement. 2017-05-06 19:53:24 -04:00
Thomas Harte
e01f3f06c8 Completed curly bracket movement. 2017-03-26 14:34:47 -04:00
Thomas Harte
a4c5eebd1e The latest Atari Age-discovered numbers suggest this starts up in 1024T mode. 2017-03-21 18:22:50 -04:00
Thomas Harte
c445eaec3e Switched startup values, following a comment on AtariAge. May or may not be correct, the thread was speculative. 2017-03-19 17:38:26 -04:00
Thomas Harte
e0bca1e37b Reinstated the 16 and 32 kb Atari pagers, and ensured the 6532 always starts in a valid state. 2017-03-18 17:34:34 -04:00
Thomas Harte
d3257c345a Tested against public ROMs and corrected. Also moved the deferred adjustment into a more canonical place. 2017-03-04 17:00:28 -05:00
Thomas Harte
e09b76bf32 Fixed 'same value, then immediate increment, then proper counting increments' behaviour and ensured it takes one cycle to commit a value. Adjusted tests to match. 2017-03-04 15:57:54 -05:00
Thomas Harte
ced644b103 It seems likely that an AY divides its clock by 8, not 16. I had conflated wave frequency and counter clock. 2017-01-11 22:03:01 -05:00
Thomas Harte
eca3995481 Added a CRC check for read address, ensured CRC, lost data and record not found are initially reset. 2017-01-01 21:00:25 -05:00
Thomas Harte
044c920a5b Made it more explicit that there are no unhandled cases. 2017-01-01 20:56:52 -05:00
Thomas Harte
0df9ce5a76 Made an attempt at read address. So superficially that leaves only the force interrupts. 2017-01-01 20:55:09 -05:00
Thomas Harte
f94f34f053 Made an attempt at read track. Which means process_input_bit can't just swallow syncs any more; it now reports them as tokens of type ::Sync. 2017-01-01 20:39:19 -05:00
Thomas Harte
c994fa39f6 Ensured spin-up doesn't occur if there's no motor line. 2016-12-31 16:18:30 -05:00
Thomas Harte
1ea4f0d79d Made an attempt to implement 'write track' and ensure that 'write sector' can't end without announcing that it has ended writing. 2016-12-31 16:01:44 -05:00
Thomas Harte
8eb21c6702 The "MFM...Byte"s aren't MFM-specific, they're relevant to both FM and MFM encoding. So renamed them. Also slimmed syntax within MFM.cpp mostly where emigration from the Acorn disk analyser had left a residue of lengthy namespace specification. 2016-12-31 15:25:11 -05:00
Thomas Harte
a8bc9d830e Removed leftover very temporary debugging aid. 2016-12-28 23:03:05 -05:00
Thomas Harte
e4000bd060 Added some even more verbose logging; slightly simplified write loop logic, and decided it's definitely write_byte that's responsible for CRC generator feeding. 2016-12-28 21:24:19 -05:00
Thomas Harte
4adcb46665 Fixed FM-mode CRC generation. 2016-12-28 19:51:27 -05:00
Thomas Harte
1277a67f9a Introduced data_mode_ to replace is_reading_data_, representing that there are now three possible modes. When writing, any input from the read head won't affect the CRC generator. 2016-12-28 19:26:21 -05:00
Thomas Harte
7a627b782d Reintroduced writing of MFM sync marks when writing a sector. 2016-12-28 18:48:50 -05:00
Thomas Harte
a568172758 Made steps towards proper CRC generation. Am currently comparing against Oric disk images, as — amongst other things — they include precomputed CRCs. 2016-12-28 18:29:37 -05:00
Thomas Harte
9c0f622a2e Started working CRC checking into the 1770. Discovered immediately that my generated CRC does not match that built into the Oric disk images. So mine is pretty-much certainly wrong. An opportunity for learning! 2016-12-26 16:46:26 -05:00
Thomas Harte
0490a47058 Worked on the all-around framework for decoding sectors back from tracks when closing down a file. Hit the wall that the parser is more observant of CRCs than the WD. No, really. So I guess I have to stop avoiding that whole issue. 2016-12-26 14:24:33 -05:00
Thomas Harte
83c433c142 Deviated from the data sheet, which seems likely to be correct. Hence removed a whole load of the temporary logging. 2016-12-26 12:48:49 -05:00
Thomas Harte
742c5df367 With lots of logging arising temporarily, fixed bug whereby conversion to a patched track would lead to holding a track with a distinct measure of time, leading to improperly-placed patches. 2016-12-25 22:00:39 -05:00
Thomas Harte
acc35885cd Attempted to reduce track invalidations. 2016-12-25 20:38:25 -05:00
Thomas Harte
c0a1264ab0 Slightly improved legibility. 2016-12-25 20:19:47 -05:00
Thomas Harte
e2b829f68e Made an attempt to write the proper address mark. 2016-12-25 20:15:07 -05:00
Thomas Harte
beaa868079 Factored the MFM parser out into encodings. 2016-12-25 20:00:57 -05:00
Thomas Harte
74e98fd097 Made an attempt to write actual data (albeit that CRC calculation is still missing). 2016-12-25 19:18:45 -05:00
Thomas Harte
98be6ede45 Shuffled a little to reduce risk of overflow, ensured writing is a loop, still seem to be writing too quickly for some reason. 2016-12-25 16:13:05 -05:00
Thomas Harte
d2ad2c756e Added enough shovelling to write rubbish for an entire sector. 2016-12-25 15:46:49 -05:00
Thomas Harte
aceb7e3b6b Started implementing write sector on the 1770, immediately deciding it would be useful to have a callback for end-of-queued-data-written from disk controller. So had a go at implementing that, naively. More investigation required. 2016-12-25 12:31:38 -05:00
Thomas Harte
901f19f89c Added enough stuff that SSDs attached to a 1770 will now reach the entry point for writing. 2016-12-25 09:46:12 -05:00
Thomas Harte
c304db0f5a Deintegrated the busy flag and the interrupt request line, as the latter is reset by status reads. Which also means I can start reporting the WD INTRQ line status directly from the Microdisc. That appears to be correct, rather than honouring the Microdisc IRQ select there. 2016-12-06 21:16:29 -05:00
Thomas Harte
ca50606e1d Restored Vic audio. 2016-12-03 17:10:47 -05:00
Thomas Harte
36bc558798 Converted all 'Components' to postfix underscores. 2016-12-03 10:51:09 -05:00
Thomas Harte
81ee834530 As well as a bunch of logging, reinstated rotation position preservation across tracks. 2016-12-02 18:36:47 -05:00
Thomas Harte
93c573bfa9 Implemented missing status bits (other than the index hole), and a head loading delay for the Microdisc. 2016-12-01 21:13:16 -05:00
Thomas Harte
0a0775c3bd Removed earlier hacky solution. 2016-12-01 20:16:11 -05:00
Thomas Harte
442986ee2c Introduced a head loading path for 1793 machines. 2016-12-01 20:12:22 -05:00
Thomas Harte
82899f2f47 Ensured flag setting is atomic, removed duplication of interrupt request versus busy, found better names for the personality testers, unified delegate protocol. 2016-12-01 07:41:52 -05:00
Thomas Harte
b31fd11470 Fixed reporting of data request line, initial status values. 2016-11-30 22:39:55 -05:00
Thomas Harte
2222cb65d6 Split the status up into flags, assembled into a register upon demand. Attempted to implement some of the differences between the 1770/1772 and 1773/1793. Albeit with a motor fix still in place. 2016-11-30 22:26:02 -05:00
Thomas Harte
84cb07613d Checked some documentation more thoroughly; the 1793 has quite different spin-up (/head load) semantics. So it's another distinct personality. Grrr. 2016-11-27 20:39:08 -08:00
Thomas Harte
02ba1f220f The '72 seems to be a '70 with altered timing. So worth differentiating. 2016-11-27 21:06:17 +08:00
Thomas Harte
2c01f9dbed Added meaningful TODOs. 2016-11-27 08:42:39 +08:00
Thomas Harte
2f459690d4 It would appear the 1770 and 1773 actually differ in relation to the (non-sensical) ability not to spin-up for a Type 2, and whether a side compare can occur. So the WD1770 class now requires a personality to be specified. Which it singly fails to honour. 2016-11-26 23:29:30 +08:00
Thomas Harte
d8ecc52de8 Temporarily disabled spin-down as harmful to the status register if following anything other than a Type 1 command. 2016-11-26 22:27:20 +08:00
Thomas Harte
b9677c9927 Consolidated interrupt request setting. 2016-11-26 09:41:53 +08:00
Thomas Harte
d5f9e0aa3b Ensured there's no such thing as a zero-cycle operation, even if i don't yet know exactly what I should be doing. 2016-11-25 21:24:25 +08:00
Thomas Harte
4af678d2ed Gave the Microdisc a clock signal, added just enough of force interrupt to avoid a spurious belief that a type 3 command has started. 2016-11-25 20:51:39 +08:00
Thomas Harte
d4a1961378 Added getters for the IRQ and DRQ lines plus a delegate to receive changes; adjusted code so that the two lines signal. 2016-11-21 13:21:49 +08:00
Thomas Harte
7eeaac23e7 Reversed myself. I once again do not think the clock is divided by 256 for envelopes. 2016-11-11 20:31:48 -05:00
Thomas Harte
77987bf31e Decided to go with divide by 256 for the envelope counter after all. 2016-11-09 21:51:56 -05:00
Thomas Harte
77ce200fbb Simplified/corrected AY tone/noise mixer logic, and made a new guess at the effect of reading registers that are smaller than 8 bits. 2016-11-09 21:21:17 -05:00
Thomas Harte
fa65cc2058 Resolved type conversion error. 2016-11-05 12:57:01 -04:00
Thomas Harte
30c670f8de Ensured programmatic setting of the timers occurs during phase 2 _instead_ of counting. 2016-11-04 21:30:18 -04:00
Thomas Harte
21604376e6 Reintroduced clocking of the AY and boxed in the range of the master divider a little further. 2016-10-30 22:51:08 -04:00
Thomas Harte
ad00304e8a Fixed 6522 countdown. 2016-10-28 21:05:42 -04:00
Thomas Harte
4fab794747 Added a direct-to-two-cycles emulation path for 6522 owners. 2016-10-27 21:13:25 -04:00
Thomas Harte
2eda0b3c86 Attempted to simplify the logic behind the most common 6522 usage. 2016-10-27 21:06:31 -04:00
Thomas Harte
fd823dc222 Settled on terminology. 2016-10-23 20:42:49 -04:00
Thomas Harte
b12f2f2796 Switched to more straightforward version of two-step loop, dealing with my mistaken dealing of when _master_divider&15 == 0 upon entry without adding an extra sanity check. Am also temporarily on non-modulo logic for tone generation, for a profiling test. 2016-10-23 20:32:48 -04:00
Thomas Harte
583db88299 Added a dispatch queue-powered Apple implementation of the async task queue, removed any mention of skip_samples in the AY since it isn't implemented. 2016-10-22 21:58:45 -04:00
Thomas Harte
33e628a096 Made an attempt to eliminate what amounts to manual division. 2016-10-21 22:16:44 -04:00
Thomas Harte
46a3c0922f Slightly simplified code, fixed divider. 2016-10-21 22:12:44 -04:00
Thomas Harte
d7c0c49715 Might as well be consistent with divider loads. 2016-10-21 20:07:14 -04:00
Thomas Harte
782ef960e1 Sought both to [start to] optimise the AY and correct divider reloads. It turns out that conditionals aren't that troubling. But I can probably eliminate the counters. 2016-10-21 20:05:38 -04:00
Thomas Harte
cd59eb5f43 Implemented non-linear volume. 2016-10-19 23:07:51 -04:00
Thomas Harte
b59da7d4bc Added some documentation. 2016-10-19 22:47:44 -04:00
Thomas Harte
08275c6241 Fixed mixer IO bit usage. 2016-10-19 22:22:15 -04:00
Thomas Harte
59162228ef Reduced mask for clarity. 2016-10-19 22:14:05 -04:00
Thomas Harte
319d7c2b12 Fixed premature wrapping of the envelope, played about with whether that should be subject to a predivision by 256. It feels unlikely? 2016-10-19 22:12:51 -04:00
Thomas Harte
6073906c39 Commented and fixed mistake that would equate any noise divider > 32768 with 0. 2016-10-19 21:51:35 -04:00
Thomas Harte
101f168ea4 Made an attempt to tidy up. 2016-10-19 21:43:18 -04:00
Thomas Harte
ada37abe23 Made an attempt to implement noise and envelopes. Not quite right yet. 2016-10-19 21:13:22 -04:00
Thomas Harte
bd6e6674a0 Fixed signed shift assumption and noise-related register test. 2016-10-18 22:20:12 -04:00
Thomas Harte
9669a5ec9b Switched to a more authentic interfacing to the AY. 2016-10-18 19:32:15 -04:00
Thomas Harte
43612e1ca2 Made an attempt to eliminate conditionals (running before I can walk?) and started edging towards an envelope generator. 2016-10-17 08:03:38 -04:00
Thomas Harte
9730e8247f Ensured propagation of synchronise messages, added enough to do plain tone. Probably. So: noise and envelopes missing. And it's all far too quiet. 2016-10-15 21:04:21 -04:00
Thomas Harte
51bdac27ae Made some AY advances; it's now being polled for samples and collecting more information on what it needs to output. 2016-10-15 17:45:39 -04:00
Thomas Harte
288d10c253 Got some keyboard reaction. 2016-10-14 21:44:15 -04:00
Thomas Harte
138eabcff4 Continued in my effort to wire up a keyboard. Will need further to continue. 2016-10-14 21:35:15 -04:00
Thomas Harte
d8e4c488c2 Started iterating towards having an AY and a fully-working keyboard. 2016-10-14 21:18:03 -04:00
Thomas Harte
922dd6a586 Hit up the other two kinds of audio generator. 2016-10-07 17:10:00 -04:00
Thomas Harte
79412dc84d Upped MFM clock cycles, switched back to using the typer for the ADFS and adjusted ADFS ROM slots. 2016-09-28 21:28:34 -04:00
Thomas Harte
91235c7fd7 Fixed issue whereby parts of data that merely looked like index or ID address marks within tracks caused a resynchronisation of the tokeniser. 2016-09-27 07:36:37 -04:00
Thomas Harte
6330e5706c Fixed seek verify. First ADFS directory is visible. 2016-09-25 21:44:46 -04:00
Thomas Harte
4db086949a Made an attempt to add MFM decoding to the 1770; ensured something is returned when reading the Plus 3 status register again. 2016-09-25 21:38:52 -04:00
Thomas Harte
572d5587d9 Made a first stab at enabling multi-disk machines and thereby obeying (some of) the Plus 3's status register. 2016-09-25 21:24:16 -04:00
Thomas Harte
9bbcbd1001 Renamed class, intending to turn a Disk::Drive into literally just that, and have a thing with a PLL that consumes events be a Controller. 2016-09-25 20:05:56 -04:00
Thomas Harte
6084020ab3 Added shift-break as a better way to boot suitable disks. Continued attempting to clean the 1770. 2016-09-25 14:11:22 -04:00
Thomas Harte
a538b45213 Sought to implement the verify step of type 1 commands. 2016-09-25 09:54:49 -04:00
Thomas Harte
0918751802 Fixed stepping out. 2016-09-24 22:48:45 -04:00
Thomas Harte
9e1d4c8b01 Fixed an initial setup error with seek. 2016-09-24 22:43:12 -04:00
Thomas Harte
d50629e6aa This is clearly the winning solution. Edited down. 2016-09-24 22:36:38 -04:00
Thomas Harte
07ff5138b7 The catalogue now loads. 2016-09-24 22:35:34 -04:00
Thomas Harte
1b69ad0fd4 This attempts to implment sector reading. DFS reports an error. 2016-09-24 22:29:02 -04:00
Thomas Harte
ce4100e5b9 Fixed slots for DFS and ADFS to sideways RAM; continued working on the 1770 to get as far as trying to get the body of a sector. 2016-09-24 22:04:54 -04:00
Thomas Harte
7154e8986e Fixed stepping delay. 2016-09-24 20:16:23 -04:00
Thomas Harte
53522e28e2 Performed an about-face on how this should probably be implemented. Now forsaking the state machine in favour of a macro'd switch-for-cooperative-event-based-messaging implementation. Let's see how this ends up looking. 2016-09-24 20:12:45 -04:00
Thomas Harte
88bbeedad3 Set actual bit length. 2016-09-22 21:28:23 -04:00
Thomas Harte
75eb62b577 One painful step at a time, this now starts the disk rotating and gets as far as deciding whether it's about to head off on a read or a write. 2016-09-22 21:25:31 -04:00
Thomas Harte
8db0030068 Fixed ROM loading by the Electron, turned the WD1770 into a 'disk drive' (it'll do for now), persuaded it to get all the way through a very specifically convenient type 1 command. 2016-09-20 22:14:33 -04:00
Thomas Harte
7a34ae0da6 This is the start of my slog through type 1 commands. I kind of need to figure out what I'm doing about drives and PLLs now though. 2016-09-20 16:58:23 -04:00
Thomas Harte
3b97b038b9 Corrected and sketched out state machine far enough to get to a complaint about unhandled work. 2016-09-20 15:56:31 -04:00
Thomas Harte
a9e65e9b7a Tweaked disk side density, added call-outs to a WD1770 if the Electron had one (albeit without run_for_cycles yet as I need to figure out the clock rate), added a shell of the basic functions of the WD1770. No implementation yet. 2016-09-19 22:06:56 -04:00
Thomas Harte
bcf91de7e9 Declared support for the Acorn disk files, started hammering out an encoder. 2016-09-18 13:35:54 -04:00
Thomas Harte
e3daf80564 Added a file for the 1770, at least. 2016-09-17 18:01:00 -04:00
Thomas Harte
eeec516fa6 Implemented seeking on tapes, mucked about a bit more with the Commodore analyser, at least temporarily removed cropping from the Vic emulator. 2016-09-11 17:09:00 -04:00
Thomas Harte
1541273785 Moved responsibility for throwing in a low-pass filter up to the Vic, appropriately. 2016-08-21 18:13:31 -04:00
Thomas Harte
c783090980 It turns out that the Vic has a 1.6Khz low-pass filter. So added that. 2016-08-21 12:13:41 -04:00
Thomas Harte
8d839c5278 I think this is correct. And have explained why. 2016-08-20 16:54:43 -04:00
Thomas Harte
7c9455251d Fixed reload for the lower-frequency audio channels. 2016-08-19 17:34:01 -04:00
Thomas Harte
99157ad6b2 Ensured the 6560 knows its real audio clock on a PAL machine; removed some stray semicolons. 2016-08-19 13:35:34 -04:00
Thomas Harte
902c0f967a Implements known phase pattern for PAL output. 2016-08-17 08:09:48 -04:00
Thomas Harte
142774be37 Collapsed 6560 template to a more direct loop, albeit with quite a bit still left to fix. 2016-08-09 21:10:53 -04:00
Thomas Harte
12bad8f23f Turned the 6560 into an ordinary template, similar to the rest of the project, albeit right now with a fairly shonky internal implementation. Fixed a Mac-specific interface sizing issue. 2016-08-09 20:41:05 -04:00
Thomas Harte
3e65450a54 Converted the 6560 fully into a template; worked on allowing the typer to run at a much faster rate where hardware has some trigger by which it can request the next key. 2016-08-06 14:33:24 -04:00
Thomas Harte
c6e046253e Shunted code for the main part up into the header, in advance of turning it into a template so as to bring it inside the normal orthodoxy. 2016-08-05 19:13:49 -04:00
Thomas Harte
5d40d70c92 Fixed 6560 addressing error, added an autotyper for Vic disks (more work potentially needed), fixed semantics for testing whether a 6502 is about to reset. 2016-08-01 10:32:32 -04:00
Thomas Harte
b43a7381ae Fixed framing and first-byte-after-sync signalling. Hacked together as parts of it are, loading now appears to work! 2016-08-01 04:25:11 -04:00
Thomas Harte
11cd541786 Fixed accidental indentation. 2016-07-10 08:05:05 -04:00
Thomas Harte
c0ab45a73d Disabled a bunch of the caveman debug logging. 2016-07-09 22:29:11 -04:00
Thomas Harte
7cc4bf3fe7 Hit and hope is getting me nowhere. Time to unit test this thing. 2016-07-09 15:40:25 -04:00
Thomas Harte
1baf21827c Since the ROM is well disassembled, let's actually try to be a 1541 first. 2016-07-06 22:17:32 -04:00
Thomas Harte
8819711bc8 Threw in the second VIA as a currently clearly incorrect thing. 2016-07-05 22:22:09 -04:00
Thomas Harte
602e7f01c7 Control lines seem to have evolved to pure push. 2016-07-05 21:15:29 -04:00
Thomas Harte
93c2bb80a2 Improved a comment, added independent C[A/B]2 input mode. 2016-07-05 21:11:51 -04:00
Thomas Harte
1bb109a23b Made a quick attempt at basic C[A/B]2 interrupts. 2016-07-05 20:39:15 -04:00
Thomas Harte
c3b7d24293 It appears that the attention line is also wired to CB2. So the ball is back in the 6522's court. 2016-07-05 19:19:46 -04:00
Thomas Harte
97751a9d86 Took the preliminary steps necessary to wire up a serial port. 2016-07-05 10:55:47 -04:00
Thomas Harte
88964ceac0 Eliminated plain pointer passing for object types. 2016-07-04 19:33:55 -04:00
Thomas Harte
82b0bc9b58 Discovered that this is another meaningful usage of using. 2016-07-04 19:10:10 -04:00
Thomas Harte
7fa010a463 Attempted to add support for the most basic of control line output, and slightly to optimise the Vic. 2016-07-01 19:01:22 -04:00
Thomas Harte
5c85366de2 Made an attempt to prevent spurious border colour pushes. 2016-06-29 21:22:26 -04:00
Thomas Harte
ff53accca0 Demonstrated that issue is coloured borders, made a guess as to buffer exhaustion, upped limits as a temporary fix. 2016-06-29 21:16:34 -04:00
Thomas Harte
0182b0483a Added a 'power on' flag that is set automatically at construction but can be declined. Saves all that stuff of every machine having to set and then unset the RST line, and fixes an Electron bug related to that. 2016-06-29 19:13:24 -04:00
Thomas Harte
de5d2f1113 Ensured the line counter increments late on NTSC. 2016-06-27 22:12:55 -04:00
Thomas Harte
69d78dfdb3 Removed logging. 2016-06-26 21:36:26 -04:00
Thomas Harte
843d1fdca7 Added some extra logging while trying to determine what's going on; added interrupt clearing for the control lines. 2016-06-26 21:30:06 -04:00
Thomas Harte
c306d705e1 Made a quick first attempt at all-the-way-through tape wiring for the Vic. 2016-06-26 19:43:09 -04:00
Thomas Harte
37ba42a52f Factored out the stuff of playing a tape, started basic sketch of the Vic-related classes. 2016-06-26 19:03:57 -04:00
Thomas Harte
066db59773 Made a hasty attempt to implement CA1 and CB1 input as a potential source of interrupts. 2016-06-26 16:32:27 -04:00
Thomas Harte
d5e50f5ea0 Got a bit more explicit about how ports are identified on the 6522. 2016-06-26 12:30:01 -04:00
Thomas Harte
3c9183d034 Improved some commenting. 2016-06-23 20:43:29 -04:00
Thomas Harte
359ffb9aa7 Made some attempt to implement what appears to be the proper address generation logic. 2016-06-23 07:32:24 -04:00
Thomas Harte
b753690d5e Made an attempt to adjust the 6560 to a model compatible with that advocated by the available documentation. Exact decision timing may need further work. 2016-06-21 22:12:01 -04:00
Thomas Harte
106e56600d Added a DC offset for 6560 volume level, albeit one plucked from thin air. 2016-06-21 07:31:14 -04:00
Thomas Harte
fe17d1778c Expanded 6532 tests substantially, beefing up implementation to match. 2016-06-20 21:02:42 -04:00
Thomas Harte
88e2b382e5 Made an attempt at a full and thorough 6532 implementation (and got a bit more explicit about flag size in the 6502). 2016-06-20 18:57:35 -04:00
Thomas Harte
d4b9ff0ca4 Doubles up on register mirroring. Will do for now. More to come. 2016-06-20 07:27:38 -04:00
Thomas Harte
4db61d98f4 Killed the .cpp. 2016-06-19 20:21:38 -04:00
Thomas Harte
7cf6008e7c Started some very basic RIOT unit tests; corrected to pass. 2016-06-19 20:12:47 -04:00
Thomas Harte
65413f078c Factored out the 6532, eventually to make it testable. 2016-06-19 18:57:40 -04:00
Thomas Harte
ce2f5515c0 Made some minor documentation improvements, killed 6522.cpp as the 6522 is going to be a template only, attempting to promote good inlining behaviour. 2016-06-19 18:11:37 -04:00
Thomas Harte
f4915c5ad6 Fixed test and added basic implementation of data direction. 2016-06-18 17:17:03 -04:00
Thomas Harte
5d26cd85a3 Wrote test case for what appears to be correct timer behaviour if those were acting in isolation. Ensured implementation matches test case. 2016-06-18 14:30:23 -04:00
Thomas Harte
394902f409 Switched to clocking the 6522 by the half-cycle. Very trivial test now passes. 2016-06-18 13:57:10 -04:00
Thomas Harte
595791cee0 Made the base 6522 class more abstract: you must now opt-in if you want the IRQ line to be sent to a delegate. 2016-06-18 08:51:18 -04:00
Thomas Harte
ce7488dd30 Added support for _invertedCells. Treading water a little before making real changes. 2016-06-14 21:06:29 -04:00
Thomas Harte
926f819e3b Added some documentation, made the speaker private. 2016-06-14 20:00:16 -04:00
Thomas Harte
a2a6e3c818 Fixed phase offsets. 2016-06-14 18:19:06 -04:00
Thomas Harte
f4884a3481 Added the noise channel, albeit not very creatively. 2016-06-14 17:50:32 -04:00
Thomas Harte
c18cc4c8f5 It appears the Vic's output is sine-ish, after all. Also adjusted centre of display, simultaneously adding some validation on that. 2016-06-14 07:29:35 -04:00
Thomas Harte
fdc854c0c2 Fixed tone channels; made an attempt at loading PRGs that are supposed to go into RAM. 2016-06-13 21:49:59 -04:00
Thomas Harte
efcb196ef7 Made a complete attempt at the tone channels. 2016-06-13 20:59:01 -04:00
Thomas Harte
f1a45c1011 Merge branch 'VicAudio' into Vic-20 2016-06-13 19:34:13 -04:00
Thomas Harte
2d23bc46f2 Whoops; fixed line count target test. 2016-06-13 19:34:01 -04:00
Thomas Harte
5fc36b956c Attempted most basic sketching of a container for Vic audio. 2016-06-13 19:30:52 -04:00
Thomas Harte
91c406e065 Made an attempt to honour interlaced-frame line counts. 2016-06-13 18:21:21 -04:00
Thomas Harte
2e946e785f Settled on half-intensity colour for now, appears likely not to be too incorrect(?) 2016-06-13 18:20:21 -04:00
Thomas Harte
e10535181d Made an attempt to implement interlaced video. 2016-06-12 22:27:58 -04:00
Thomas Harte
4ad55a7f5e Trimmed the visible area. 2016-06-12 18:01:38 -04:00
Thomas Harte
a5efa7543a Added vertical sync, switching fully to the normal NTSC colour space. 2016-06-12 17:57:52 -04:00
Thomas Harte
4c2b964cd4 Added NTSC-VIC's switching of phase every field. 2016-06-12 17:45:25 -04:00