Thomas Harte
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4211389ac7
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Connected machine-supplied colour burst amplitude to shader, discarding hard-coded value. Net effect: the colour component is now discarded for the ZX80 and 81.
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2017-07-06 21:29:08 -04:00 |
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Thomas Harte
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c6d00ec7d1
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Switched phase and amplitude varying to a 3d vector; the third component is 1/amplitude if amplitude is non-zero, and zero otherwise. So you can multiply by that to get chrominance, rather than dividing by amplitude. With the direct effect that detected chrominance should automatically be zero if the colour burst didn't exist (i.e. had zero amplitude).
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2017-07-06 21:25:38 -04:00 |
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Thomas Harte
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212ae60622
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Typer fixes: the recipient no longer releases the caller, and a duplicate call to strlen and piece of arithmetic is corrected.
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2017-07-06 21:17:04 -04:00 |
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Thomas Harte
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a72a2e0a1a
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Ensured tape doesn't proceed of its own volition when in fast-loading mode.
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2017-06-23 20:21:37 -04:00 |
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Thomas Harte
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50375fb373
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Ensured tape position is unaffected if the attempt at loading quickly fails.
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2017-06-23 20:18:19 -04:00 |
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Thomas Harte
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2d02c23574
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Merge pull request #138 from TomHarte/ZX81Ports
Increases port decoding on the ZX81
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2017-06-23 08:32:21 -04:00 |
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Thomas Harte
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cb105fdeb4
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Took a first stab at high-res support.
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2017-06-22 22:48:17 -04:00 |
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Thomas Harte
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acfd4dde36
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Reduced port writes which can adjust programmatic sync, and prevented anything while NMI generation is active. Moved line counter increment from triggered by interrupt acknowledge to triggered by horizontal sync. In both cases, cribbing from my own earlier work. Initial results suggest that sync issues are resolved in third-party software.
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2017-06-22 22:44:06 -04:00 |
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Thomas Harte
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919fc48cc5
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Fixed dumb out-of-bounds access error.
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2017-06-22 22:28:50 -04:00 |
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Thomas Harte
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aec4fd066b
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I think I've definitively decided against this model of timing.
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2017-06-22 21:32:14 -04:00 |
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Thomas Harte
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73c7b18900
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Added a public declaration of ZX80/81 support to the readme.
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2017-06-22 21:14:43 -04:00 |
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Thomas Harte
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3dfe45d225
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Merge pull request #137 from TomHarte/NMIWaitTest
Introduces an NMI/wait interrupt timing test
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2017-06-22 21:11:54 -04:00 |
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Thomas Harte
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95a6b0f85c
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Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
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2017-06-22 21:09:26 -04:00 |
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Thomas Harte
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87ee8450fe
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Minor rejig: it's much more likely that something that can't be distinguished is a ZX81 program. TODO: some sort of BASIC token parsing, to be more confident.
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2017-06-22 20:23:14 -04:00 |
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Thomas Harte
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f2a6bcf2a8
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Merge pull request #136 from TomHarte/ZX8081Options
Finally adjusts ZX80/81 tape loading so that the fast loading hack is optional as per the GUI
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2017-06-22 20:21:28 -04:00 |
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Thomas Harte
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644ef13acd
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Connected up the fast-tape GUI option for the ZX80 and '81.
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2017-06-22 20:20:31 -04:00 |
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Thomas Harte
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342574761f
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Merge pull request #135 from TomHarte/InterruptWaitStates
Ensures wait states are observed during interrupt response
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2017-06-22 20:15:54 -04:00 |
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Thomas Harte
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b7c978e078
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Added getters for most of the input lines, and attempted to round out the ZX81's wait logic.
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2017-06-22 20:11:19 -04:00 |
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Thomas Harte
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f0398a6db8
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Added wait state hooks to the interrupt programs, and added an is_wait query on PartialMachineCycle.
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2017-06-22 20:07:47 -04:00 |
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Thomas Harte
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f3b1ef99cc
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Merge pull request #134 from TomHarte/BinaryTape
Switches the binary tape player to low = false, high = true
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2017-06-21 22:25:42 -04:00 |
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Thomas Harte
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52d9ddf9e5
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Gave the binary tape player a more logical assignment of wave level to output level. Which miraculously appears to have been the issue with the ZX80/81 tape loading — the inconsistency of silences seems to have been the issue.
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2017-06-21 22:13:24 -04:00 |
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Thomas Harte
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93f251dbcd
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Merge pull request #133 from TomHarte/ZX81Wait
Utilises the newly-working wait line in ZX81 emulation
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2017-06-21 21:46:08 -04:00 |
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Thomas Harte
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a6810fc3ef
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Removed some minor duplicity and ensured that hsync/NMI ends on the nominated cycle, not one afterwards.
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2017-06-21 21:44:42 -04:00 |
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Thomas Harte
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15f6c51062
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Added the most trivial implementation of the ZX81 wait line.
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2017-06-21 21:28:14 -04:00 |
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Thomas Harte
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5e21c706f3
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Merge pull request #132 from TomHarte/MachineCycles
Subdivides the Z80's machine cycles
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2017-06-21 21:19:48 -04:00 |
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Thomas Harte
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e1355d4b62
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Restored proper video output.
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2017-06-21 21:18:09 -04:00 |
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Thomas Harte
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7eeac3b586
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Switched R back to incrementing after the refresh cycle. It had snuck to before by virtue of subdivision of the M1 cycle. Which shortened the ZX80 line time, breaking synchronisation.
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2017-06-21 21:11:00 -04:00 |
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Thomas Harte
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4bf13610ce
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Reinstated interrupts by moving the refresh test back into the refresh cycle.
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2017-06-21 21:03:39 -04:00 |
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Thomas Harte
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0e0ce379b4
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Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
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2017-06-21 20:38:08 -04:00 |
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Thomas Harte
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36e8a11505
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Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
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2017-06-21 20:32:08 -04:00 |
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Thomas Harte
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45f442ea63
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Corrected interrupt mode 2: was both failing properly to load the vector address, and failing to read from it.
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2017-06-21 19:08:48 -04:00 |
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Thomas Harte
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db743c90d8
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Had neglected to count refresh time in my interrupt programs. Corrected. Mode 0 timing test succeeds again. Only Mode 2 is now at fault.
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2017-06-21 18:58:44 -04:00 |
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Thomas Harte
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10cc94f581
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Attempted to fix interrupt response timing; ensured initial interrupt mode is one that won't jump beyond the interrupt response program table's length, and that the conditionals other than CALL definitely have no alternative program attached.
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2017-06-21 18:47:00 -04:00 |
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Thomas Harte
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108da64562
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Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
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2017-06-20 22:25:00 -04:00 |
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Thomas Harte
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f85b46286e
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Resolved the timing disparity between LD (HL),n and LD (IX+d), n, hopefully having come up with a convincing theory of timing for the latter.
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2017-06-20 22:20:58 -04:00 |
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Thomas Harte
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184b371649
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Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
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2017-06-20 21:48:50 -04:00 |
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Thomas Harte
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b0375bb037
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Fixed the three LD rr, (nn) operations. Back down to four FUSE failures.
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2017-06-20 21:32:23 -04:00 |
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Thomas Harte
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48942848e7
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Fixed (Ix+d) read timing. I've put an extra wait cycle into the read, so no need to extend the refresh.
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2017-06-20 21:15:56 -04:00 |
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Thomas Harte
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27ac342928
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Corrected conditional call timing, and its test.
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2017-06-20 20:57:23 -04:00 |
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Thomas Harte
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25aba16ef8
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Quickly checking the FUSE tests, corrected a handful of instances where PC should be modified but isn't, correcting around 800 new failures.
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2017-06-19 22:20:23 -04:00 |
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Thomas Harte
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a0d0f383c8
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Corrected unconditional CALL timing. Conditional's going to require more work because once the wait state is put into the right place, it breaks the assumption under which the Z80 handles conditions — that they're either do something or else do nothing. So that can wait a day.
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2017-06-19 22:07:36 -04:00 |
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Thomas Harte
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6752f165db
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Added failing tests for both kinds of CALL.
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2017-06-19 22:03:29 -04:00 |
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Thomas Harte
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e05076b258
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Added tests for everything except CALL. All passing.
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2017-06-19 22:00:04 -04:00 |
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Thomas Harte
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fadbfdf801
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Added DJNZ test.
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2017-06-19 21:31:56 -04:00 |
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Thomas Harte
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cb277b8d1e
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Added JP and JR tests.
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2017-06-19 21:27:23 -04:00 |
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Thomas Harte
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234f14dbbe
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Tests were at fault; all passing now.
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2017-06-19 21:14:40 -04:00 |
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Thomas Harte
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99ede3a9ef
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BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).
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2017-06-19 21:04:14 -04:00 |
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Thomas Harte
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378233f53d
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Extended to BITs and SETs, accruing three new failures.
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2017-06-19 21:01:30 -04:00 |
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Thomas Harte
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f903408980
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Caught up on comments.
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2017-06-19 20:53:22 -04:00 |
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Thomas Harte
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cc8f316941
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Resolved read-modify-write (IX+d) timing, and therefore RLC (IX+d).
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2017-06-19 20:51:28 -04:00 |
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