Thomas Harte
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11d8f765b2
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Corrects divide-by-zero exception length, enables all other DIVS checks.
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2019-07-01 15:46:04 -04:00 |
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Thomas Harte
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514e57b3e9
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Corrects DIVU timing and flags, improves DIVS.
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2019-07-01 14:24:32 -04:00 |
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Thomas Harte
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d8fb6fb951
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Corrects MULU timing.
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2019-06-30 22:40:10 -04:00 |
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Thomas Harte
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255f0d4b2a
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Corrects MULS timing.
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2019-06-30 22:33:54 -04:00 |
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Thomas Harte
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8d0cd356fd
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Corrects TRAP, TRAPV and CHK timing.
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2019-06-29 21:25:22 -04:00 |
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Thomas Harte
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17666bc059
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Corrects CHK flags.
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2019-06-28 19:48:53 -04:00 |
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Thomas Harte
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241d29ff7c
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Imports SBCD and NBCD tests, and fixes corresponding operation.
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2019-06-28 19:39:08 -04:00 |
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Thomas Harte
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c5039a4719
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Imports ANDI, ORI and EORI to SR tests.
Hence corrects supervisor/user privileges for SR/CCR.
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2019-06-28 15:05:46 -04:00 |
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Thomas Harte
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6c588a1510
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Makes some further random swings at tracking the startup procedure.
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2019-06-28 13:03:47 -04:00 |
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Thomas Harte
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d81053ea38
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Invents some additional PEA tests, and further fixes PEA.
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2019-06-27 17:59:03 -04:00 |
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Thomas Harte
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8d39c3bc98
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Takes a shot at fixing PEA for A7-relative addresses.
Unit tests required. Tomorrow.
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2019-06-26 23:24:54 -04:00 |
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Thomas Harte
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c0591090f5
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Imports DIVU tests.
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2019-06-26 22:25:48 -04:00 |
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Thomas Harte
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538aecb46e
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Imports CMP tests, and fixes CMP.l timing.
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2019-06-26 22:02:04 -04:00 |
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Thomas Harte
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dbdbea85c2
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Imports CMPA tests, and fixes CMPA.w.
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2019-06-26 21:42:48 -04:00 |
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Thomas Harte
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ba2224dd06
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Imports NEGX tests and thereby fixes NEGX's zero flag.
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2019-06-26 19:39:04 -04:00 |
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Thomas Harte
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79066f8628
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Imports NOT tests, fixes NOT overflow and carry flags.
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2019-06-25 22:18:11 -04:00 |
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Thomas Harte
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2c813a2692
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Imports CMPM tests and fixes CMPM.bw source/destination order.
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2019-06-25 21:46:01 -04:00 |
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Thomas Harte
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d2cb595b83
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Proactively attempts to fix CMPM PostInc addressing.
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2019-06-25 21:24:03 -04:00 |
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Thomas Harte
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ecb5a0b8cc
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Incorporates ADDX tests and fixes ADDX PreDec.
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2019-06-25 19:18:07 -04:00 |
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Thomas Harte
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e12e8fc616
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Incorporates ASR tests, and fixes ASR (xxx).w.
... which was re-injecting the wrong bit to preserve sign.
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2019-06-25 18:44:31 -04:00 |
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Thomas Harte
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1fbbf32cd2
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Adds ASL tests, and corrects ASL (xxx).w.
Overflow is wrong on other ASLs though, I think.
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2019-06-25 18:09:01 -04:00 |
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Thomas Harte
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31edb15369
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Reduces 68000 startup costs a little further.
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2019-06-25 17:41:13 -04:00 |
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Thomas Harte
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e830d23533
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Incorporates TRAPV tests.
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2019-06-24 21:21:35 -04:00 |
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Thomas Harte
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9a666fb8cc
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Imports NEG tests and fixes NEG.l Dn timing.
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2019-06-24 19:43:30 -04:00 |
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Thomas Harte
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0e208ed432
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Fixes cycle counting in the test machine.
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2019-06-24 17:55:09 -04:00 |
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Thomas Harte
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c8b769de8a
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Completes import of LSL tests and fixes various LSL issues.
Including LSL (xxx).w actually being LSR, and the carry flag generally being questionable.
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2019-06-24 17:45:38 -04:00 |
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Thomas Harte
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c447655047
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Resolves assumption that shifts greater than the bit count of the relevant int are well-defined in C.
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2019-06-24 16:51:43 -04:00 |
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Thomas Harte
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3ec9a1d869
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Incorporates JMP tests, fixes JSR (xxx).l timing.
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2019-06-24 15:36:33 -04:00 |
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Thomas Harte
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faef917cbd
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Improves resizeable microcycle test.
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2019-06-24 10:55:22 -04:00 |
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Thomas Harte
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d27ba90c07
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Attempts to introduce more rigour to variable-length instruction handling.
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2019-06-24 10:43:28 -04:00 |
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Thomas Harte
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db4ca746e3
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Introduces BSET tests, fixes BSET timing.
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2019-06-23 22:53:37 -04:00 |
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Thomas Harte
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d50fbfb506
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Imports EXG and PEA tests, and fixes EXG timing.
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2019-06-23 22:21:25 -04:00 |
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Thomas Harte
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86fdc75feb
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Incorporates RTR test, adding a ProcessorState helper.
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2019-06-23 18:37:32 -04:00 |
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Thomas Harte
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b63231523a
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Completes import of ROL tests.
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2019-06-23 17:33:12 -04:00 |
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Thomas Harte
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70e296674d
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Starts import of ROL tests.
Including time tests, this time.
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2019-06-22 22:42:57 -04:00 |
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Thomas Harte
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8c8493bc9d
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Ensures proper loading of the SP at reset.
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2019-06-21 18:20:26 -04:00 |
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Thomas Harte
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ccfe1b13cb
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Imports DIVS, MULS and MOVE from SR tests.
Not all passing.
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2019-06-21 16:03:11 -04:00 |
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Thomas Harte
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0c1c10bc66
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Introduces a test that proves that DIVS' attempt to set proper timing isn't working.
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2019-06-20 19:29:02 -04:00 |
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Thomas Harte
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fafd1801fe
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Introduces first DIVS test, and associated fixes.
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2019-06-20 19:02:03 -04:00 |
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Thomas Harte
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79d8d27b4c
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Reintroduces use of locations_by_bus_step_ to decrease 68000 construction time.
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2019-06-20 15:10:11 -04:00 |
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Thomas Harte
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440f52c943
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Incorporates TRAP test.
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2019-06-19 21:18:30 -04:00 |
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Thomas Harte
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91ced056d2
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Adds tests for ADD. No failures.
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2019-06-19 18:56:21 -04:00 |
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Thomas Harte
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8dace34e63
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Imports third-party tests for ABCD, and thereby fixes ABCD.
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2019-06-19 18:13:06 -04:00 |
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Thomas Harte
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8182b0363f
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Adds enum to help with status decoding.
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2019-06-19 17:01:49 -04:00 |
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Thomas Harte
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c5b036fedf
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Ensures aborted decodes don't overwrite prior correct ones.
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2019-06-19 17:00:44 -04:00 |
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Thomas Harte
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e26ddd0ed5
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Corrects address fetches for CMPI.l #, (xxx).w.
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2019-06-19 13:52:56 -04:00 |
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Thomas Harte
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ca83431e54
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Fixed: Scc is a byte operation.
It was, until now, post-incrementing and pre-decrementing registers other than A7 incorrectly.
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2019-06-19 13:15:12 -04:00 |
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Thomas Harte
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00c32e4b59
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Further miscellaneous changes to debug logging. All temporary.
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2019-06-18 10:34:31 -04:00 |
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Thomas Harte
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877b46d2c1
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Advances IWM/drive emulation very close to the point of 'Welcome to Macintosh'.
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2019-06-15 16:08:54 -04:00 |
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Thomas Harte
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bde975a3b9
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Possibly mights the tiniest bit of headway with 'the IWM'.
I'm now pretty sure that my 3.5" drive, which for now is implemented in the IWM (yuck) is just responding to queries incorrectly.
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2019-06-13 22:38:09 -04:00 |
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