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Author SHA1 Message Date
Thomas Harte
ae56da2b0d
Merge pull request #1155 from TomHarte/Templates 
Show failing operations in human form.
 2023-08-19 15:58:15 -04:00
Thomas Harte
90f16026bc Merge branch 'master' into Templates 2023-08-19 15:57:37 -04:00
Thomas Harte
d0284917cf
Merge pull request #1154 from TomHarte/65816StackAgain 
Clarify SH=1 upon TCS.
 2023-08-19 15:56:30 -04:00
Thomas Harte
7815d18676 Merge branch 'master' into 65816StackAgain 2023-08-19 15:55:45 -04:00
Thomas Harte
222f6e92fb
Merge pull request #1153 from TomHarte/IIgsInterrupts 
IIgS: abstract VGC interrupt register; fix clearing bug.
 2023-08-18 22:14:13 -04:00
Thomas Harte
b34403164e Abstract out VGC interrupt register; fix clearing bug. 2023-08-18 14:30:40 -04:00
Thomas Harte
3bd931937f
Merge pull request #1152 from TomHarte/New6502TestGenerator 
Generalise 65816 test generator to handle all 6502esques.
 2023-08-18 11:28:57 -04:00
Thomas Harte
d207c13b6b
Merge pull request #1151 from TomHarte/STopByteAgain 
Fix S top byte overwrite.
 2023-08-18 11:28:51 -04:00
Thomas Harte
ca75822dbe Fix restart_operation_fetch. 2023-08-17 15:42:34 -04:00
Thomas Harte
d9df568dab Add faulty restart_operation_fetch. 2023-08-17 15:38:28 -04:00
Thomas Harte
26343148ae Use simplified control lines when appropriate. 2023-08-17 15:32:02 -04:00
Thomas Harte
fd0fe66851 Omit unsupported registers and flags. 2023-08-17 15:24:08 -04:00
Thomas Harte
c41ed191dc Fix S top byte overwrite. 2023-08-17 14:51:13 -04:00
Thomas Harte
833613b68a Fix S top byte overwrite. 2023-08-17 14:50:55 -04:00
Thomas Harte
0a336baae2 Perform minor generalisation. 2023-08-17 14:50:43 -04:00
Thomas Harte
b9bd3f9b8c
Merge pull request #1150 from TomHarte/65816Setter 
Don't allow setting of an invalid S.
 2023-08-07 09:19:59 -04:00
Thomas Harte
42024c1573 Don't allow setting of an invalid S. 2023-08-07 09:19:20 -04:00
Thomas Harte
0222dcf5ce
Merge pull request #1149 from TomHarte/65816StackAgain 
Add a between-instructions enforcement of SH = 1.
 2023-08-05 15:14:53 -04:00
Thomas Harte
54103f1f34 Fix SH=1 reset; appropriate TCS. 2023-08-05 15:06:18 -04:00
Thomas Harte
c0eb401d04 Add a between-instructions enforcement of SH = 1. 2023-08-05 14:57:43 -04:00
Thomas Harte
cdb86022a6
Merge pull request #1148 from TomHarte/NoEmulationStack 
Use full 16-bit stack pointer for all 'new' instructions.
 2023-07-31 20:41:10 -04:00
Thomas Harte
2262725010 Reveal 16-bit stack pointer when asked, regardless of mode. 2023-07-31 17:08:02 -04:00
Thomas Harte
e61a4eb5a9 Regularise PHD and PLD. 2023-07-30 16:36:29 -04:00
Thomas Harte
acd7f9f4cd Fix stack usage of JSL. 2023-07-30 16:34:42 -04:00
Thomas Harte
9f1a657cc4 Fix stack usage of PEA. 2023-07-30 16:33:44 -04:00
Thomas Harte
e52d1866ab Fix PEI stack usage. 2023-07-30 16:32:56 -04:00
Thomas Harte
a02b8222fa Fix stack usage of PER. 2023-07-30 16:29:56 -04:00
Thomas Harte
3762ee1a63 Fix stack usage of PHD. 2023-07-30 16:29:15 -04:00
Thomas Harte
3ec61e8770 Fix stack usage of RTL. 2023-07-30 16:27:13 -04:00
Thomas Harte
2f7dd0b01a Correct stack behaviour of PLD. 2023-07-30 16:26:29 -04:00
Thomas Harte
3a02c22072 Provide an always-16bit-address route to the stack. 2023-07-30 16:25:51 -04:00
Thomas Harte
6ae967de51
Merge pull request #1147 from TomHarte/ErrantDBR 
Remove DBR reset upon COP/BRK/IRQ/NMI; fix (d, x) addressing.
 2023-07-30 16:20:34 -04:00
Thomas Harte
5d45aa4a6a Fix seed per test. 2023-07-28 13:58:01 -04:00
Thomas Harte
0f1468adfd Correct wrapping behaviour for (d, x). 2023-07-28 13:39:21 -04:00
Thomas Harte
e9347168e6 Don't alter the data bank upon BRK, COP, IRQ, etc. 2023-07-28 10:53:02 -04:00
Thomas Harte
3e09afbb59
Remove errant square bracket. 2023-06-21 11:57:09 -04:00
Thomas Harte
f30637a773
Merge pull request #1144 from TomHarte/Base144 
Enhance mechanisms for display-style dispatch.
 2023-06-15 21:42:59 -04:00
Thomas Harte
1d8bc41724 Shift back to original name. 2023-06-13 15:25:51 -04:00
Thomas Harte
d36a88dd11 Collect up different dispatches. 2023-06-13 15:22:53 -04:00
Thomas Harte
de5ee8f0d0 Mildly extend test. 2023-06-13 13:26:39 -04:00
Thomas Harte
6261ac24b4 Reformat SubrangeDispatcher; test. 2023-06-13 12:46:21 -04:00
Thomas Harte
b00eac4a34 Get to building. 2023-06-12 23:16:45 -04:00
Thomas Harte
6e35d84a96 Merge branch 'Base144' of github.com:TomHarte/CLK into Base144 2023-06-12 17:39:16 -04:00
Thomas Harte
d028555361 Get code up on feet, fix most obvious transgressions. 2023-06-12 16:09:02 -04:00
Thomas Harte
1aa953dd4d Consolidate RangeDispatcher under Dispatcher's umbrella. 2023-06-12 15:52:10 -04:00
Thomas Harte
77c67ab59d Build max into the sequencer. 2023-06-12 15:35:33 -04:00
Thomas Harte
05d2e78f80 Conversion can be a separate step. 2023-06-12 15:34:44 -04:00
Thomas Harte
837d8d29ca Merge branch 'master' into Base144 2023-06-10 16:00:57 -04:00
Thomas Harte
8a831b1409 Import sketch for a potential range dispatcher. 2023-06-10 15:58:30 -04:00
Thomas Harte
c0547f6e14 Tidy up; forward construction arguments. 2023-06-10 15:58:13 -04:00