Thomas Harte
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23177df26a
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Added various tests of the basic ALU ops.
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2017-06-19 19:53:26 -04:00 |
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Thomas Harte
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ba15371948
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Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.
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2017-06-19 19:47:00 -04:00 |
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Thomas Harte
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73dbaebbc1
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Fixed timing of EX (SP), HL/IX.
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2017-06-19 19:25:53 -04:00 |
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Thomas Harte
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8d60734737
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Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.
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2017-06-19 19:17:54 -04:00 |
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Thomas Harte
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002098d496
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The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.
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2017-06-19 07:45:41 -04:00 |
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Thomas Harte
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e3244eb68e
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Rephrased internal operation machine cycles as having only an end. So they're now easy to count. Hence the test machine spots them, and a couple more of the current timing subset passes.
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2017-06-19 07:39:46 -04:00 |
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Thomas Harte
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85c6fb1430
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Explained refresh cycles to the all-RAM Z80.
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2017-06-19 07:36:11 -04:00 |
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Thomas Harte
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54e4643396
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Corrected non-default refresh cycle lengths. Reduces failures of the currently-tested timing subset from 10 to 4.
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2017-06-19 07:34:23 -04:00 |
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Thomas Harte
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85c5c4405a
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Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.
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2017-06-19 07:30:01 -04:00 |
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Thomas Harte
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d668879ba6
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Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
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2017-06-18 22:03:13 -04:00 |
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Thomas Harte
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cb140aa06e
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Managed to navigate back to building.
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2017-06-18 21:00:44 -04:00 |
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Thomas Harte
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6a769d3953
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Finally dipped below the 20 error threshold that the compiler tops out at.
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2017-06-18 20:34:46 -04:00 |
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Thomas Harte
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3be8ffd826
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Some correct timings have gone out the window for now, but only the final quarter of the base page now contains compiler errors.
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2017-06-18 20:31:12 -04:00 |
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Thomas Harte
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bb910e14a4
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Dealt with the CB page.
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2017-06-18 18:01:33 -04:00 |
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Thomas Harte
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69ebbe019a
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Completed ED page conversion. Rolling onwards...
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2017-06-18 17:56:48 -04:00 |
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Thomas Harte
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0d39672d32
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Fixing typos here and there, persuaded the first half of the ED table to compile.
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2017-06-18 17:48:54 -04:00 |
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Thomas Harte
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0d1231980a
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Advanced to getting specific warnings in the ed-page table. So that's progress.
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2017-06-18 17:25:15 -04:00 |
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Thomas Harte
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82a015892b
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Started adapting to the newly-segmented world.
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2017-06-18 17:18:01 -04:00 |
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Thomas Harte
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194b7f60c5
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Rephrased to allow non-conditional waits; expanded macros to cover all permitted lengths of read and write.
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2017-06-18 17:08:50 -04:00 |
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Thomas Harte
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ebc7356db5
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Reformulated the machine cycle slightly to support posting operation plus phase, thereby exposing the segue points at which waits might be inserted. So: to stick to the rule that CPUs expose the minimum amount of information sufficient completely to reconstruct bus activity. This breaks the Z80 for now.
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2017-06-18 12:21:27 -04:00 |
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Thomas Harte
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e1a2580b2a
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Renamed BusOperation to MachineCycle::Operation.
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2017-06-17 21:53:45 -04:00 |
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Thomas Harte
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b6f51474ff
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Ensured that -description can handle the newly-captured bus actions.
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2017-06-17 18:20:30 -04:00 |
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Thomas Harte
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0f18768091
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Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do.
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2017-06-17 18:19:25 -04:00 |
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Thomas Harte
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efc7f9df37
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Combined I and R into a register pair.
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2017-06-17 18:18:28 -04:00 |
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Thomas Harte
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50cd617bd9
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Ensured test raises only the intentional failure exceptions.
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2017-06-15 22:33:46 -04:00 |
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Thomas Harte
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838b818cd3
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Finished transcribing first page of machine cycle documentation; several failures contained.
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2017-06-15 22:19:49 -04:00 |
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Thomas Harte
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cf795562bf
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Continued filling in tests, fleshing out what the test machine captures as a result.
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2017-06-15 20:59:59 -04:00 |
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Thomas Harte
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ac37424878
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Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.
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2017-06-15 19:06:59 -04:00 |
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Thomas Harte
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a336048c98
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Merge branch 'ZX80FileFormats'
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2017-06-15 18:33:42 -04:00 |
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Thomas Harte
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87496f9978
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Merge pull request #131 from TomHarte/ZX80FileFormats
Adds very preliminary emulation of the ZX80.
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2017-06-15 18:32:38 -04:00 |
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Thomas Harte
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08a542a324
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Reenabled the fast-loading hack.
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2017-06-15 18:30:12 -04:00 |
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Thomas Harte
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9b3d05e05f
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Simplified decoding logic.
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2017-06-14 22:24:44 -04:00 |
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Thomas Harte
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d8e3103a2b
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Fixes: switched ZX80 and ZX81 timing to the correct way around, ensured that my wait takes effect if HALT **isn't** set, and made sure to recover from it.
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2017-06-13 21:48:17 -04:00 |
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Thomas Harte
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76a64d13a0
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Made a first attempt at ZX81 emulation.
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2017-06-13 21:25:55 -04:00 |
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Thomas Harte
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1e975859c2
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Started splitting ZX80 and ZX81 paths. Also the '80 fires its horizontal sync a little earlier than the '81, so pulled that back a little.
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2017-06-13 20:09:09 -04:00 |
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Thomas Harte
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4c5261bfa0
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Made first attempt to use the horizontal counter for something; here for sync timing only, even though I've gone exclusively with '81-style timing for now.
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2017-06-12 22:28:30 -04:00 |
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Thomas Harte
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aed2827e7b
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Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.
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2017-06-12 22:22:00 -04:00 |
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Thomas Harte
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e6e6e4e62b
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Adds an extra character for padding the ZX81 table.
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2017-06-12 22:08:11 -04:00 |
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Thomas Harte
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8b09b4180b
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This now at least remembers whether it is meant to be a ZX81 and has storage for a horizontal counter.
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2017-06-12 21:33:16 -04:00 |
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Thomas Harte
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626737b9fa
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Started mucking about with some string conversion routines. Not finished yet.
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2017-06-12 21:32:36 -04:00 |
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Thomas Harte
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22de481557
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Made an attempt to get .p/.80 checked and as far as the emulated machine.
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2017-06-12 19:41:59 -04:00 |
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Thomas Harte
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b9dbb6bcf8
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Discovered my timing error: the I/R <-> A loads should take an extra cycle. This means the ZX80 now finally takes the correct 207 cycles per line. Fixed the video output wave to be clocked at the appropriate rate.
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2017-06-12 18:55:04 -04:00 |
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Thomas Harte
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a48616a138
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Fixed reference to Swift-world MachineDocument for the ZX81 file type.
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2017-06-12 18:51:11 -04:00 |
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Thomas Harte
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8222aac9e3
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Added an official declaration of support for ZX81 files.
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2017-06-11 21:40:41 -04:00 |
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Thomas Harte
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77aa3c187e
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Rebranded ZX80O as ZX80O81P, with an eye to making it accept ZX81 .p files. Adjusted the initial selection part of the static analyser appropriately.
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2017-06-11 21:38:32 -04:00 |
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Thomas Harte
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ee0283c985
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Modified to use an in-memory buffer for file contents.
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2017-06-11 21:35:09 -04:00 |
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Thomas Harte
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302c2e94de
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Corrected lingering hard-coded mask. So titles for memory configurations above 1kb now load.
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2017-06-11 21:27:46 -04:00 |
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Thomas Harte
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06fe07932a
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While tidying up, killed an unused instance variable.
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2017-06-11 21:21:26 -04:00 |
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Thomas Harte
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6913c7a018
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This also can just use rom_mask_.
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2017-06-11 19:29:20 -04:00 |
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Thomas Harte
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6b602c74b7
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Made an attempt to support memory maps other than the unexpanded default of 1kb.
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2017-06-11 19:29:02 -04:00 |
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